if_ste.c revision 200808
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200808 2009-12-21 20:18:01Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56#include <net/if_vlan_var.h> 57 58#include <net/bpf.h> 59 60#include <vm/vm.h> /* for vtophys */ 61#include <vm/pmap.h> /* for vtophys */ 62#include <machine/bus.h> 63#include <machine/resource.h> 64#include <sys/bus.h> 65#include <sys/rman.h> 66 67#include <dev/mii/mii.h> 68#include <dev/mii/miivar.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73/* "device miibus" required. See GENERIC if you get errors here. */ 74#include "miibus_if.h" 75 76#define STE_USEIOSPACE 77 78#include <dev/ste/if_stereg.h> 79 80MODULE_DEPEND(ste, pci, 1, 1, 1); 81MODULE_DEPEND(ste, ether, 1, 1, 1); 82MODULE_DEPEND(ste, miibus, 1, 1, 1); 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92}; 93 94static int ste_probe(device_t); 95static int ste_attach(device_t); 96static int ste_detach(device_t); 97static void ste_init(void *); 98static void ste_init_locked(struct ste_softc *); 99static void ste_intr(void *); 100static void ste_rxeoc(struct ste_softc *); 101static int ste_rxeof(struct ste_softc *); 102static void ste_txeoc(struct ste_softc *); 103static void ste_txeof(struct ste_softc *); 104static void ste_stats_update(void *); 105static void ste_stop(struct ste_softc *); 106static void ste_reset(struct ste_softc *); 107static int ste_ioctl(struct ifnet *, u_long, caddr_t); 108static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 109static void ste_start(struct ifnet *); 110static void ste_start_locked(struct ifnet *); 111static void ste_watchdog(struct ste_softc *); 112static int ste_shutdown(device_t); 113static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 114 struct mbuf *); 115static int ste_ifmedia_upd(struct ifnet *); 116static void ste_ifmedia_upd_locked(struct ifnet *); 117static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 119static void ste_mii_sync(struct ste_softc *); 120static void ste_mii_send(struct ste_softc *, uint32_t, int); 121static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 122static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 123static int ste_miibus_readreg(device_t, int, int); 124static int ste_miibus_writereg(device_t, int, int, int); 125static void ste_miibus_statchg(device_t); 126 127static int ste_eeprom_wait(struct ste_softc *); 128static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 129static void ste_wait(struct ste_softc *); 130static void ste_setmulti(struct ste_softc *); 131static int ste_init_rx_list(struct ste_softc *); 132static void ste_init_tx_list(struct ste_softc *); 133 134#ifdef STE_USEIOSPACE 135#define STE_RES SYS_RES_IOPORT 136#define STE_RID STE_PCI_LOIO 137#else 138#define STE_RES SYS_RES_MEMORY 139#define STE_RID STE_PCI_LOMEM 140#endif 141 142static device_method_t ste_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, ste_probe), 145 DEVMETHOD(device_attach, ste_attach), 146 DEVMETHOD(device_detach, ste_detach), 147 DEVMETHOD(device_shutdown, ste_shutdown), 148 149 /* bus interface */ 150 DEVMETHOD(bus_print_child, bus_generic_print_child), 151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 152 153 /* MII interface */ 154 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 155 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 156 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 157 158 { 0, 0 } 159}; 160 161static driver_t ste_driver = { 162 "ste", 163 ste_methods, 164 sizeof(struct ste_softc) 165}; 166 167static devclass_t ste_devclass; 168 169DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 170DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 171 172SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 173 174static int ste_rxsyncs; 175SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 176 177#define STE_SETBIT4(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 179 180#define STE_CLRBIT4(sc, reg, x) \ 181 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 182 183#define STE_SETBIT2(sc, reg, x) \ 184 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 185 186#define STE_CLRBIT2(sc, reg, x) \ 187 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 188 189#define STE_SETBIT1(sc, reg, x) \ 190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 191 192#define STE_CLRBIT1(sc, reg, x) \ 193 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 194 195 196#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 197#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 198 199/* 200 * Sync the PHYs by setting data bit and strobing the clock 32 times. 201 */ 202static void 203ste_mii_sync(struct ste_softc *sc) 204{ 205 int i; 206 207 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 208 209 for (i = 0; i < 32; i++) { 210 MII_SET(STE_PHYCTL_MCLK); 211 DELAY(1); 212 MII_CLR(STE_PHYCTL_MCLK); 213 DELAY(1); 214 } 215} 216 217/* 218 * Clock a series of bits through the MII. 219 */ 220static void 221ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 222{ 223 int i; 224 225 MII_CLR(STE_PHYCTL_MCLK); 226 227 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 228 if (bits & i) { 229 MII_SET(STE_PHYCTL_MDATA); 230 } else { 231 MII_CLR(STE_PHYCTL_MDATA); 232 } 233 DELAY(1); 234 MII_CLR(STE_PHYCTL_MCLK); 235 DELAY(1); 236 MII_SET(STE_PHYCTL_MCLK); 237 } 238} 239 240/* 241 * Read an PHY register through the MII. 242 */ 243static int 244ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 245{ 246 int i, ack; 247 248 /* 249 * Set up frame for RX. 250 */ 251 frame->mii_stdelim = STE_MII_STARTDELIM; 252 frame->mii_opcode = STE_MII_READOP; 253 frame->mii_turnaround = 0; 254 frame->mii_data = 0; 255 256 CSR_WRITE_2(sc, STE_PHYCTL, 0); 257 /* 258 * Turn on data xmit. 259 */ 260 MII_SET(STE_PHYCTL_MDIR); 261 262 ste_mii_sync(sc); 263 264 /* 265 * Send command/address info. 266 */ 267 ste_mii_send(sc, frame->mii_stdelim, 2); 268 ste_mii_send(sc, frame->mii_opcode, 2); 269 ste_mii_send(sc, frame->mii_phyaddr, 5); 270 ste_mii_send(sc, frame->mii_regaddr, 5); 271 272 /* Turn off xmit. */ 273 MII_CLR(STE_PHYCTL_MDIR); 274 275 /* Idle bit */ 276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 277 DELAY(1); 278 MII_SET(STE_PHYCTL_MCLK); 279 DELAY(1); 280 281 /* Check for ack */ 282 MII_CLR(STE_PHYCTL_MCLK); 283 DELAY(1); 284 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 285 MII_SET(STE_PHYCTL_MCLK); 286 DELAY(1); 287 288 /* 289 * Now try reading data bits. If the ack failed, we still 290 * need to clock through 16 cycles to keep the PHY(s) in sync. 291 */ 292 if (ack) { 293 for (i = 0; i < 16; i++) { 294 MII_CLR(STE_PHYCTL_MCLK); 295 DELAY(1); 296 MII_SET(STE_PHYCTL_MCLK); 297 DELAY(1); 298 } 299 goto fail; 300 } 301 302 for (i = 0x8000; i; i >>= 1) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 if (!ack) { 306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 307 frame->mii_data |= i; 308 DELAY(1); 309 } 310 MII_SET(STE_PHYCTL_MCLK); 311 DELAY(1); 312 } 313 314fail: 315 316 MII_CLR(STE_PHYCTL_MCLK); 317 DELAY(1); 318 MII_SET(STE_PHYCTL_MCLK); 319 DELAY(1); 320 321 if (ack) 322 return (1); 323 return (0); 324} 325 326/* 327 * Write to a PHY register through the MII. 328 */ 329static int 330ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 331{ 332 333 /* 334 * Set up frame for TX. 335 */ 336 337 frame->mii_stdelim = STE_MII_STARTDELIM; 338 frame->mii_opcode = STE_MII_WRITEOP; 339 frame->mii_turnaround = STE_MII_TURNAROUND; 340 341 /* 342 * Turn on data output. 343 */ 344 MII_SET(STE_PHYCTL_MDIR); 345 346 ste_mii_sync(sc); 347 348 ste_mii_send(sc, frame->mii_stdelim, 2); 349 ste_mii_send(sc, frame->mii_opcode, 2); 350 ste_mii_send(sc, frame->mii_phyaddr, 5); 351 ste_mii_send(sc, frame->mii_regaddr, 5); 352 ste_mii_send(sc, frame->mii_turnaround, 2); 353 ste_mii_send(sc, frame->mii_data, 16); 354 355 /* Idle bit. */ 356 MII_SET(STE_PHYCTL_MCLK); 357 DELAY(1); 358 MII_CLR(STE_PHYCTL_MCLK); 359 DELAY(1); 360 361 /* 362 * Turn off xmit. 363 */ 364 MII_CLR(STE_PHYCTL_MDIR); 365 366 return (0); 367} 368 369static int 370ste_miibus_readreg(device_t dev, int phy, int reg) 371{ 372 struct ste_softc *sc; 373 struct ste_mii_frame frame; 374 375 sc = device_get_softc(dev); 376 377 if ( sc->ste_one_phy && phy != 0 ) 378 return (0); 379 380 bzero((char *)&frame, sizeof(frame)); 381 382 frame.mii_phyaddr = phy; 383 frame.mii_regaddr = reg; 384 ste_mii_readreg(sc, &frame); 385 386 return (frame.mii_data); 387} 388 389static int 390ste_miibus_writereg(device_t dev, int phy, int reg, int data) 391{ 392 struct ste_softc *sc; 393 struct ste_mii_frame frame; 394 395 sc = device_get_softc(dev); 396 bzero((char *)&frame, sizeof(frame)); 397 398 frame.mii_phyaddr = phy; 399 frame.mii_regaddr = reg; 400 frame.mii_data = data; 401 402 ste_mii_writereg(sc, &frame); 403 404 return (0); 405} 406 407static void 408ste_miibus_statchg(device_t dev) 409{ 410 struct ste_softc *sc; 411 struct mii_data *mii; 412 413 sc = device_get_softc(dev); 414 415 mii = device_get_softc(sc->ste_miibus); 416 417 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 418 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 419 } else { 420 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 421 } 422} 423 424static int 425ste_ifmedia_upd(struct ifnet *ifp) 426{ 427 struct ste_softc *sc; 428 429 sc = ifp->if_softc; 430 STE_LOCK(sc); 431 ste_ifmedia_upd_locked(ifp); 432 STE_UNLOCK(sc); 433 434 return (0); 435} 436 437static void 438ste_ifmedia_upd_locked(struct ifnet *ifp) 439{ 440 struct ste_softc *sc; 441 struct mii_data *mii; 442 443 sc = ifp->if_softc; 444 STE_LOCK_ASSERT(sc); 445 mii = device_get_softc(sc->ste_miibus); 446 sc->ste_link = 0; 447 if (mii->mii_instance) { 448 struct mii_softc *miisc; 449 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 450 mii_phy_reset(miisc); 451 } 452 mii_mediachg(mii); 453} 454 455static void 456ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 457{ 458 struct ste_softc *sc; 459 struct mii_data *mii; 460 461 sc = ifp->if_softc; 462 mii = device_get_softc(sc->ste_miibus); 463 464 STE_LOCK(sc); 465 mii_pollstat(mii); 466 ifmr->ifm_active = mii->mii_media_active; 467 ifmr->ifm_status = mii->mii_media_status; 468 STE_UNLOCK(sc); 469} 470 471static void 472ste_wait(struct ste_softc *sc) 473{ 474 int i; 475 476 for (i = 0; i < STE_TIMEOUT; i++) { 477 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 478 break; 479 } 480 481 if (i == STE_TIMEOUT) 482 device_printf(sc->ste_dev, "command never completed!\n"); 483} 484 485/* 486 * The EEPROM is slow: give it time to come ready after issuing 487 * it a command. 488 */ 489static int 490ste_eeprom_wait(struct ste_softc *sc) 491{ 492 int i; 493 494 DELAY(1000); 495 496 for (i = 0; i < 100; i++) { 497 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 498 DELAY(1000); 499 else 500 break; 501 } 502 503 if (i == 100) { 504 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 505 return (1); 506 } 507 508 return (0); 509} 510 511/* 512 * Read a sequence of words from the EEPROM. Note that ethernet address 513 * data is stored in the EEPROM in network byte order. 514 */ 515static int 516ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 517{ 518 uint16_t word, *ptr; 519 int err = 0, i; 520 521 if (ste_eeprom_wait(sc)) 522 return (1); 523 524 for (i = 0; i < cnt; i++) { 525 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 526 err = ste_eeprom_wait(sc); 527 if (err) 528 break; 529 word = CSR_READ_2(sc, STE_EEPROM_DATA); 530 ptr = (uint16_t *)(dest + (i * 2)); 531 if (swap) 532 *ptr = ntohs(word); 533 else 534 *ptr = word; 535 } 536 537 return (err ? 1 : 0); 538} 539 540static void 541ste_setmulti(struct ste_softc *sc) 542{ 543 struct ifnet *ifp; 544 struct ifmultiaddr *ifma; 545 uint32_t hashes[2] = { 0, 0 }; 546 int h; 547 548 ifp = sc->ste_ifp; 549 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 550 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 551 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 552 return; 553 } 554 555 /* first, zot all the existing hash bits */ 556 CSR_WRITE_2(sc, STE_MAR0, 0); 557 CSR_WRITE_2(sc, STE_MAR1, 0); 558 CSR_WRITE_2(sc, STE_MAR2, 0); 559 CSR_WRITE_2(sc, STE_MAR3, 0); 560 561 /* now program new ones */ 562 if_maddr_rlock(ifp); 563 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 564 if (ifma->ifma_addr->sa_family != AF_LINK) 565 continue; 566 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 567 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 568 if (h < 32) 569 hashes[0] |= (1 << h); 570 else 571 hashes[1] |= (1 << (h - 32)); 572 } 573 if_maddr_runlock(ifp); 574 575 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 576 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 577 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 578 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 579 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 580 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 581} 582 583#ifdef DEVICE_POLLING 584static poll_handler_t ste_poll, ste_poll_locked; 585 586static int 587ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 588{ 589 struct ste_softc *sc = ifp->if_softc; 590 int rx_npkts = 0; 591 592 STE_LOCK(sc); 593 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 594 rx_npkts = ste_poll_locked(ifp, cmd, count); 595 STE_UNLOCK(sc); 596 return (rx_npkts); 597} 598 599static int 600ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 601{ 602 struct ste_softc *sc = ifp->if_softc; 603 int rx_npkts; 604 605 STE_LOCK_ASSERT(sc); 606 607 sc->rxcycles = count; 608 if (cmd == POLL_AND_CHECK_STATUS) 609 ste_rxeoc(sc); 610 rx_npkts = ste_rxeof(sc); 611 ste_txeof(sc); 612 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 613 ste_start_locked(ifp); 614 615 if (cmd == POLL_AND_CHECK_STATUS) { 616 uint16_t status; 617 618 status = CSR_READ_2(sc, STE_ISR_ACK); 619 620 if (status & STE_ISR_TX_DONE) 621 ste_txeoc(sc); 622 623 if (status & STE_ISR_STATS_OFLOW) { 624 callout_stop(&sc->ste_stat_callout); 625 ste_stats_update(sc); 626 } 627 628 if (status & STE_ISR_LINKEVENT) 629 mii_pollstat(device_get_softc(sc->ste_miibus)); 630 631 if (status & STE_ISR_HOSTERR) { 632 ste_reset(sc); 633 ste_init_locked(sc); 634 } 635 } 636 return (rx_npkts); 637} 638#endif /* DEVICE_POLLING */ 639 640static void 641ste_intr(void *xsc) 642{ 643 struct ste_softc *sc; 644 struct ifnet *ifp; 645 uint16_t status; 646 647 sc = xsc; 648 STE_LOCK(sc); 649 ifp = sc->ste_ifp; 650 651#ifdef DEVICE_POLLING 652 if (ifp->if_capenable & IFCAP_POLLING) { 653 STE_UNLOCK(sc); 654 return; 655 } 656#endif 657 658 /* See if this is really our interrupt. */ 659 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 660 STE_UNLOCK(sc); 661 return; 662 } 663 664 for (;;) { 665 status = CSR_READ_2(sc, STE_ISR_ACK); 666 667 if (!(status & STE_INTRS)) 668 break; 669 670 if (status & STE_ISR_RX_DMADONE) { 671 ste_rxeoc(sc); 672 ste_rxeof(sc); 673 } 674 675 if (status & STE_ISR_TX_DMADONE) 676 ste_txeof(sc); 677 678 if (status & STE_ISR_TX_DONE) 679 ste_txeoc(sc); 680 681 if (status & STE_ISR_STATS_OFLOW) { 682 callout_stop(&sc->ste_stat_callout); 683 ste_stats_update(sc); 684 } 685 686 if (status & STE_ISR_LINKEVENT) 687 mii_pollstat(device_get_softc(sc->ste_miibus)); 688 689 690 if (status & STE_ISR_HOSTERR) { 691 ste_reset(sc); 692 ste_init_locked(sc); 693 } 694 } 695 696 /* Re-enable interrupts */ 697 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 698 699 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 700 ste_start_locked(ifp); 701 702 STE_UNLOCK(sc); 703} 704 705static void 706ste_rxeoc(struct ste_softc *sc) 707{ 708 struct ste_chain_onefrag *cur_rx; 709 710 STE_LOCK_ASSERT(sc); 711 712 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 713 cur_rx = sc->ste_cdata.ste_rx_head; 714 do { 715 cur_rx = cur_rx->ste_next; 716 /* If the ring is empty, just return. */ 717 if (cur_rx == sc->ste_cdata.ste_rx_head) 718 return; 719 } while (cur_rx->ste_ptr->ste_status == 0); 720 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 721 /* We've fallen behind the chip: catch it. */ 722 sc->ste_cdata.ste_rx_head = cur_rx; 723 ++ste_rxsyncs; 724 } 725 } 726} 727 728/* 729 * A frame has been uploaded: pass the resulting mbuf chain up to 730 * the higher level protocols. 731 */ 732static int 733ste_rxeof(struct ste_softc *sc) 734{ 735 struct mbuf *m; 736 struct ifnet *ifp; 737 struct ste_chain_onefrag *cur_rx; 738 uint32_t rxstat; 739 int total_len = 0, count = 0, rx_npkts = 0; 740 741 STE_LOCK_ASSERT(sc); 742 743 ifp = sc->ste_ifp; 744 745 while ((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 746 & STE_RXSTAT_DMADONE) { 747#ifdef DEVICE_POLLING 748 if (ifp->if_capenable & IFCAP_POLLING) { 749 if (sc->rxcycles <= 0) 750 break; 751 sc->rxcycles--; 752 } 753#endif 754 if ((STE_RX_LIST_CNT - count) < 3) { 755 break; 756 } 757 758 cur_rx = sc->ste_cdata.ste_rx_head; 759 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 760 761 /* 762 * If an error occurs, update stats, clear the 763 * status word and leave the mbuf cluster in place: 764 * it should simply get re-used next time this descriptor 765 * comes up in the ring. 766 */ 767 if (rxstat & STE_RXSTAT_FRAME_ERR) { 768 ifp->if_ierrors++; 769 cur_rx->ste_ptr->ste_status = 0; 770 continue; 771 } 772 773 /* 774 * If there error bit was not set, the upload complete 775 * bit should be set which means we have a valid packet. 776 * If not, something truly strange has happened. 777 */ 778 if (!(rxstat & STE_RXSTAT_DMADONE)) { 779 device_printf(sc->ste_dev, 780 "bad receive status -- packet dropped\n"); 781 ifp->if_ierrors++; 782 cur_rx->ste_ptr->ste_status = 0; 783 continue; 784 } 785 786 /* No errors; receive the packet. */ 787 m = cur_rx->ste_mbuf; 788 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 789 790 /* 791 * Try to conjure up a new mbuf cluster. If that 792 * fails, it means we have an out of memory condition and 793 * should leave the buffer in place and continue. This will 794 * result in a lost packet, but there's little else we 795 * can do in this situation. 796 */ 797 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 798 ifp->if_ierrors++; 799 cur_rx->ste_ptr->ste_status = 0; 800 continue; 801 } 802 803 m->m_pkthdr.rcvif = ifp; 804 m->m_pkthdr.len = m->m_len = total_len; 805 806 ifp->if_ipackets++; 807 STE_UNLOCK(sc); 808 (*ifp->if_input)(ifp, m); 809 STE_LOCK(sc); 810 811 cur_rx->ste_ptr->ste_status = 0; 812 count++; 813 rx_npkts++; 814 } 815 816 return (rx_npkts); 817} 818 819static void 820ste_txeoc(struct ste_softc *sc) 821{ 822 struct ifnet *ifp; 823 uint8_t txstat; 824 825 ifp = sc->ste_ifp; 826 827 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 828 STE_TXSTATUS_TXDONE) { 829 if (txstat & STE_TXSTATUS_UNDERRUN || 830 txstat & STE_TXSTATUS_EXCESSCOLLS || 831 txstat & STE_TXSTATUS_RECLAIMERR) { 832 ifp->if_oerrors++; 833 device_printf(sc->ste_dev, 834 "transmission error: %x\n", txstat); 835 836 ste_reset(sc); 837 ste_init_locked(sc); 838 839 if (txstat & STE_TXSTATUS_UNDERRUN && 840 sc->ste_tx_thresh < STE_PACKET_SIZE) { 841 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 842 device_printf(sc->ste_dev, 843 "tx underrun, increasing tx" 844 " start threshold to %d bytes\n", 845 sc->ste_tx_thresh); 846 } 847 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 848 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 849 (STE_PACKET_SIZE >> 4)); 850 } 851 ste_init_locked(sc); 852 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 853 } 854} 855 856static void 857ste_txeof(struct ste_softc *sc) 858{ 859 struct ifnet *ifp; 860 struct ste_chain *cur_tx; 861 int idx; 862 863 ifp = sc->ste_ifp; 864 865 idx = sc->ste_cdata.ste_tx_cons; 866 while (idx != sc->ste_cdata.ste_tx_prod) { 867 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 868 869 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 870 break; 871 872 m_freem(cur_tx->ste_mbuf); 873 cur_tx->ste_mbuf = NULL; 874 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 875 ifp->if_opackets++; 876 877 STE_INC(idx, STE_TX_LIST_CNT); 878 } 879 880 sc->ste_cdata.ste_tx_cons = idx; 881 if (idx == sc->ste_cdata.ste_tx_prod) 882 sc->ste_timer = 0; 883} 884 885static void 886ste_stats_update(void *xsc) 887{ 888 struct ste_softc *sc; 889 struct ifnet *ifp; 890 struct mii_data *mii; 891 892 sc = xsc; 893 STE_LOCK_ASSERT(sc); 894 895 ifp = sc->ste_ifp; 896 mii = device_get_softc(sc->ste_miibus); 897 898 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 899 + CSR_READ_1(sc, STE_MULTI_COLLS) 900 + CSR_READ_1(sc, STE_SINGLE_COLLS); 901 902 if (!sc->ste_link) { 903 mii_pollstat(mii); 904 if (mii->mii_media_status & IFM_ACTIVE && 905 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 906 sc->ste_link++; 907 /* 908 * we don't get a call-back on re-init so do it 909 * otherwise we get stuck in the wrong link state 910 */ 911 ste_miibus_statchg(sc->ste_dev); 912 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 913 ste_start_locked(ifp); 914 } 915 } 916 917 if (sc->ste_timer > 0 && --sc->ste_timer == 0) 918 ste_watchdog(sc); 919 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 920} 921 922 923/* 924 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 925 * IDs against our list and return a device name if we find a match. 926 */ 927static int 928ste_probe(device_t dev) 929{ 930 struct ste_type *t; 931 932 t = ste_devs; 933 934 while (t->ste_name != NULL) { 935 if ((pci_get_vendor(dev) == t->ste_vid) && 936 (pci_get_device(dev) == t->ste_did)) { 937 device_set_desc(dev, t->ste_name); 938 return (BUS_PROBE_DEFAULT); 939 } 940 t++; 941 } 942 943 return (ENXIO); 944} 945 946/* 947 * Attach the interface. Allocate softc structures, do ifmedia 948 * setup and ethernet/BPF attach. 949 */ 950static int 951ste_attach(device_t dev) 952{ 953 struct ste_softc *sc; 954 struct ifnet *ifp; 955 u_char eaddr[6]; 956 int error = 0, rid; 957 958 sc = device_get_softc(dev); 959 sc->ste_dev = dev; 960 961 /* 962 * Only use one PHY since this chip reports multiple 963 * Note on the DFE-550 the PHY is at 1 on the DFE-580 964 * it is at 0 & 1. It is rev 0x12. 965 */ 966 if (pci_get_vendor(dev) == DL_VENDORID && 967 pci_get_device(dev) == DL_DEVICEID_DL10050 && 968 pci_get_revid(dev) == 0x12 ) 969 sc->ste_one_phy = 1; 970 971 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 972 MTX_DEF); 973 /* 974 * Map control/status registers. 975 */ 976 pci_enable_busmaster(dev); 977 978 rid = STE_RID; 979 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 980 981 if (sc->ste_res == NULL) { 982 device_printf(dev, "couldn't map ports/memory\n"); 983 error = ENXIO; 984 goto fail; 985 } 986 987 sc->ste_btag = rman_get_bustag(sc->ste_res); 988 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 989 990 /* Allocate interrupt */ 991 rid = 0; 992 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 993 RF_SHAREABLE | RF_ACTIVE); 994 995 if (sc->ste_irq == NULL) { 996 device_printf(dev, "couldn't map interrupt\n"); 997 error = ENXIO; 998 goto fail; 999 } 1000 1001 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0); 1002 1003 /* Reset the adapter. */ 1004 ste_reset(sc); 1005 1006 /* 1007 * Get station address from the EEPROM. 1008 */ 1009 if (ste_read_eeprom(sc, eaddr, 1010 STE_EEADDR_NODE0, 3, 0)) { 1011 device_printf(dev, "failed to read station address\n"); 1012 error = ENXIO;; 1013 goto fail; 1014 } 1015 1016 /* Allocate the descriptor queues. */ 1017 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1018 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1019 1020 if (sc->ste_ldata == NULL) { 1021 device_printf(dev, "no memory for list buffers!\n"); 1022 error = ENXIO; 1023 goto fail; 1024 } 1025 1026 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1027 1028 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1029 if (ifp == NULL) { 1030 device_printf(dev, "can not if_alloc()\n"); 1031 error = ENOSPC; 1032 goto fail; 1033 } 1034 1035 /* Do MII setup. */ 1036 if (mii_phy_probe(dev, &sc->ste_miibus, 1037 ste_ifmedia_upd, ste_ifmedia_sts)) { 1038 device_printf(dev, "MII without any phy!\n"); 1039 error = ENXIO; 1040 goto fail; 1041 } 1042 1043 ifp->if_softc = sc; 1044 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1045 ifp->if_mtu = ETHERMTU; 1046 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1047 ifp->if_ioctl = ste_ioctl; 1048 ifp->if_start = ste_start; 1049 ifp->if_init = ste_init; 1050 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1051 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1052 IFQ_SET_READY(&ifp->if_snd); 1053 1054 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1055 1056 /* 1057 * Call MI attach routine. 1058 */ 1059 ether_ifattach(ifp, eaddr); 1060 1061 /* 1062 * Tell the upper layer(s) we support long frames. 1063 */ 1064 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1065 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1066 ifp->if_capenable = ifp->if_capabilities; 1067#ifdef DEVICE_POLLING 1068 ifp->if_capabilities |= IFCAP_POLLING; 1069#endif 1070 1071 /* Hook interrupt last to avoid having to lock softc */ 1072 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1073 NULL, ste_intr, sc, &sc->ste_intrhand); 1074 1075 if (error) { 1076 device_printf(dev, "couldn't set up irq\n"); 1077 ether_ifdetach(ifp); 1078 goto fail; 1079 } 1080 1081fail: 1082 if (error) 1083 ste_detach(dev); 1084 1085 return (error); 1086} 1087 1088/* 1089 * Shutdown hardware and free up resources. This can be called any 1090 * time after the mutex has been initialized. It is called in both 1091 * the error case in attach and the normal detach case so it needs 1092 * to be careful about only freeing resources that have actually been 1093 * allocated. 1094 */ 1095static int 1096ste_detach(device_t dev) 1097{ 1098 struct ste_softc *sc; 1099 struct ifnet *ifp; 1100 1101 sc = device_get_softc(dev); 1102 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1103 ifp = sc->ste_ifp; 1104 1105#ifdef DEVICE_POLLING 1106 if (ifp->if_capenable & IFCAP_POLLING) 1107 ether_poll_deregister(ifp); 1108#endif 1109 1110 /* These should only be active if attach succeeded */ 1111 if (device_is_attached(dev)) { 1112 ether_ifdetach(ifp); 1113 STE_LOCK(sc); 1114 ste_stop(sc); 1115 STE_UNLOCK(sc); 1116 callout_drain(&sc->ste_stat_callout); 1117 } 1118 if (sc->ste_miibus) 1119 device_delete_child(dev, sc->ste_miibus); 1120 bus_generic_detach(dev); 1121 1122 if (sc->ste_intrhand) 1123 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1124 if (sc->ste_irq) 1125 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1126 if (sc->ste_res) 1127 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1128 1129 if (ifp) 1130 if_free(ifp); 1131 1132 if (sc->ste_ldata) { 1133 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1134 M_DEVBUF); 1135 } 1136 1137 mtx_destroy(&sc->ste_mtx); 1138 1139 return (0); 1140} 1141 1142static int 1143ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *c, struct mbuf *m) 1144{ 1145 struct mbuf *m_new = NULL; 1146 1147 if (m == NULL) { 1148 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1149 if (m_new == NULL) 1150 return (ENOBUFS); 1151 MCLGET(m_new, M_DONTWAIT); 1152 if (!(m_new->m_flags & M_EXT)) { 1153 m_freem(m_new); 1154 return (ENOBUFS); 1155 } 1156 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1157 } else { 1158 m_new = m; 1159 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1160 m_new->m_data = m_new->m_ext.ext_buf; 1161 } 1162 1163 m_adj(m_new, ETHER_ALIGN); 1164 1165 c->ste_mbuf = m_new; 1166 c->ste_ptr->ste_status = 0; 1167 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1168 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1169 1170 return (0); 1171} 1172 1173static int 1174ste_init_rx_list(struct ste_softc *sc) 1175{ 1176 struct ste_chain_data *cd; 1177 struct ste_list_data *ld; 1178 int i; 1179 1180 cd = &sc->ste_cdata; 1181 ld = sc->ste_ldata; 1182 1183 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1184 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1185 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1186 return (ENOBUFS); 1187 if (i == (STE_RX_LIST_CNT - 1)) { 1188 cd->ste_rx_chain[i].ste_next = 1189 &cd->ste_rx_chain[0]; 1190 ld->ste_rx_list[i].ste_next = 1191 vtophys(&ld->ste_rx_list[0]); 1192 } else { 1193 cd->ste_rx_chain[i].ste_next = 1194 &cd->ste_rx_chain[i + 1]; 1195 ld->ste_rx_list[i].ste_next = 1196 vtophys(&ld->ste_rx_list[i + 1]); 1197 } 1198 ld->ste_rx_list[i].ste_status = 0; 1199 } 1200 1201 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1202 1203 return (0); 1204} 1205 1206static void 1207ste_init_tx_list(struct ste_softc *sc) 1208{ 1209 struct ste_chain_data *cd; 1210 struct ste_list_data *ld; 1211 int i; 1212 1213 cd = &sc->ste_cdata; 1214 ld = sc->ste_ldata; 1215 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1216 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1217 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1218 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1219 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1220 if (i == (STE_TX_LIST_CNT - 1)) 1221 cd->ste_tx_chain[i].ste_next = 1222 &cd->ste_tx_chain[0]; 1223 else 1224 cd->ste_tx_chain[i].ste_next = 1225 &cd->ste_tx_chain[i + 1]; 1226 } 1227 1228 cd->ste_tx_prod = 0; 1229 cd->ste_tx_cons = 0; 1230} 1231 1232static void 1233ste_init(void *xsc) 1234{ 1235 struct ste_softc *sc; 1236 1237 sc = xsc; 1238 STE_LOCK(sc); 1239 ste_init_locked(sc); 1240 STE_UNLOCK(sc); 1241} 1242 1243static void 1244ste_init_locked(struct ste_softc *sc) 1245{ 1246 struct ifnet *ifp; 1247 int i; 1248 1249 STE_LOCK_ASSERT(sc); 1250 ifp = sc->ste_ifp; 1251 1252 ste_stop(sc); 1253 1254 /* Init our MAC address */ 1255 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1256 CSR_WRITE_2(sc, STE_PAR0 + i, 1257 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1258 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1259 } 1260 1261 /* Init RX list */ 1262 if (ste_init_rx_list(sc) == ENOBUFS) { 1263 device_printf(sc->ste_dev, 1264 "initialization failed: no memory for RX buffers\n"); 1265 ste_stop(sc); 1266 return; 1267 } 1268 1269 /* Set RX polling interval */ 1270 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1271 1272 /* Init TX descriptors */ 1273 ste_init_tx_list(sc); 1274 1275 /* Set the TX freethresh value */ 1276 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1277 1278 /* Set the TX start threshold for best performance. */ 1279 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1280 1281 /* Set the TX reclaim threshold. */ 1282 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1283 1284 /* Set up the RX filter. */ 1285 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1286 1287 /* If we want promiscuous mode, set the allframes bit. */ 1288 if (ifp->if_flags & IFF_PROMISC) { 1289 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1290 } else { 1291 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1292 } 1293 1294 /* Set capture broadcast bit to accept broadcast frames. */ 1295 if (ifp->if_flags & IFF_BROADCAST) { 1296 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1297 } else { 1298 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1299 } 1300 1301 ste_setmulti(sc); 1302 1303 /* Load the address of the RX list. */ 1304 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1305 ste_wait(sc); 1306 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1307 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1308 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1309 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1310 1311 /* Set TX polling interval (defer until we TX first packet */ 1312 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1313 1314 /* Load address of the TX list */ 1315 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1316 ste_wait(sc); 1317 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1318 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1319 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1320 ste_wait(sc); 1321 sc->ste_tx_prev = NULL; 1322 1323 /* Enable receiver and transmitter */ 1324 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1325 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1326 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1327 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1328 1329 /* Enable stats counters. */ 1330 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1331 1332 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1333#ifdef DEVICE_POLLING 1334 /* Disable interrupts if we are polling. */ 1335 if (ifp->if_capenable & IFCAP_POLLING) 1336 CSR_WRITE_2(sc, STE_IMR, 0); 1337 else 1338#endif 1339 /* Enable interrupts. */ 1340 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1341 1342 /* Accept VLAN length packets */ 1343 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1344 1345 ste_ifmedia_upd_locked(ifp); 1346 1347 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1348 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1349 1350 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 1351} 1352 1353static void 1354ste_stop(struct ste_softc *sc) 1355{ 1356 struct ifnet *ifp; 1357 int i; 1358 1359 STE_LOCK_ASSERT(sc); 1360 ifp = sc->ste_ifp; 1361 1362 callout_stop(&sc->ste_stat_callout); 1363 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1364 1365 CSR_WRITE_2(sc, STE_IMR, 0); 1366 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1367 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1368 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1369 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1370 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1371 ste_wait(sc); 1372 /* 1373 * Try really hard to stop the RX engine or under heavy RX 1374 * data chip will write into de-allocated memory. 1375 */ 1376 ste_reset(sc); 1377 1378 sc->ste_link = 0; 1379 1380 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1381 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1382 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1383 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1384 } 1385 } 1386 1387 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1388 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1389 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1390 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1391 } 1392 } 1393 1394 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1395} 1396 1397static void 1398ste_reset(struct ste_softc *sc) 1399{ 1400 int i; 1401 1402 STE_SETBIT4(sc, STE_ASICCTL, 1403 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1404 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1405 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1406 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1407 STE_ASICCTL_EXTRESET_RESET); 1408 1409 DELAY(100000); 1410 1411 for (i = 0; i < STE_TIMEOUT; i++) { 1412 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1413 break; 1414 } 1415 1416 if (i == STE_TIMEOUT) 1417 device_printf(sc->ste_dev, "global reset never completed\n"); 1418} 1419 1420static int 1421ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1422{ 1423 struct ste_softc *sc; 1424 struct ifreq *ifr; 1425 struct mii_data *mii; 1426 int error = 0; 1427 1428 sc = ifp->if_softc; 1429 ifr = (struct ifreq *)data; 1430 1431 switch (command) { 1432 case SIOCSIFFLAGS: 1433 STE_LOCK(sc); 1434 if (ifp->if_flags & IFF_UP) { 1435 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1436 ifp->if_flags & IFF_PROMISC && 1437 !(sc->ste_if_flags & IFF_PROMISC)) { 1438 STE_SETBIT1(sc, STE_RX_MODE, 1439 STE_RXMODE_PROMISC); 1440 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1441 !(ifp->if_flags & IFF_PROMISC) && 1442 sc->ste_if_flags & IFF_PROMISC) { 1443 STE_CLRBIT1(sc, STE_RX_MODE, 1444 STE_RXMODE_PROMISC); 1445 } 1446 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1447 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1448 ste_setmulti(sc); 1449 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1450 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1451 ste_init_locked(sc); 1452 } 1453 } else { 1454 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1455 ste_stop(sc); 1456 } 1457 sc->ste_if_flags = ifp->if_flags; 1458 STE_UNLOCK(sc); 1459 error = 0; 1460 break; 1461 case SIOCADDMULTI: 1462 case SIOCDELMULTI: 1463 STE_LOCK(sc); 1464 ste_setmulti(sc); 1465 STE_UNLOCK(sc); 1466 error = 0; 1467 break; 1468 case SIOCGIFMEDIA: 1469 case SIOCSIFMEDIA: 1470 mii = device_get_softc(sc->ste_miibus); 1471 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1472 break; 1473 case SIOCSIFCAP: 1474#ifdef DEVICE_POLLING 1475 if (ifr->ifr_reqcap & IFCAP_POLLING && 1476 !(ifp->if_capenable & IFCAP_POLLING)) { 1477 error = ether_poll_register(ste_poll, ifp); 1478 if (error) 1479 return (error); 1480 STE_LOCK(sc); 1481 /* Disable interrupts */ 1482 CSR_WRITE_2(sc, STE_IMR, 0); 1483 ifp->if_capenable |= IFCAP_POLLING; 1484 STE_UNLOCK(sc); 1485 return (error); 1486 1487 } 1488 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1489 ifp->if_capenable & IFCAP_POLLING) { 1490 error = ether_poll_deregister(ifp); 1491 /* Enable interrupts. */ 1492 STE_LOCK(sc); 1493 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1494 ifp->if_capenable &= ~IFCAP_POLLING; 1495 STE_UNLOCK(sc); 1496 return (error); 1497 } 1498#endif /* DEVICE_POLLING */ 1499 break; 1500 default: 1501 error = ether_ioctl(ifp, command, data); 1502 break; 1503 } 1504 1505 return (error); 1506} 1507 1508static int 1509ste_encap(struct ste_softc *sc, struct ste_chain *c, struct mbuf *m_head) 1510{ 1511 struct mbuf *m; 1512 struct ste_desc *d; 1513 struct ste_frag *f = NULL; 1514 int frag = 0; 1515 1516 d = c->ste_ptr; 1517 d->ste_ctl = 0; 1518 1519encap_retry: 1520 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1521 if (m->m_len != 0) { 1522 if (frag == STE_MAXFRAGS) 1523 break; 1524 f = &d->ste_frags[frag]; 1525 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1526 f->ste_len = m->m_len; 1527 frag++; 1528 } 1529 } 1530 1531 if (m != NULL) { 1532 struct mbuf *mn; 1533 1534 /* 1535 * We ran out of segments. We have to recopy this 1536 * mbuf chain first. Bail out if we can't get the 1537 * new buffers. 1538 */ 1539 mn = m_defrag(m_head, M_DONTWAIT); 1540 if (mn == NULL) { 1541 m_freem(m_head); 1542 return ENOMEM; 1543 } 1544 m_head = mn; 1545 goto encap_retry; 1546 } 1547 1548 c->ste_mbuf = m_head; 1549 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1550 d->ste_ctl = 1; 1551 1552 return (0); 1553} 1554 1555static void 1556ste_start(struct ifnet *ifp) 1557{ 1558 struct ste_softc *sc; 1559 1560 sc = ifp->if_softc; 1561 STE_LOCK(sc); 1562 ste_start_locked(ifp); 1563 STE_UNLOCK(sc); 1564} 1565 1566static void 1567ste_start_locked(struct ifnet *ifp) 1568{ 1569 struct ste_softc *sc; 1570 struct ste_chain *cur_tx; 1571 struct mbuf *m_head = NULL; 1572 int idx; 1573 1574 sc = ifp->if_softc; 1575 STE_LOCK_ASSERT(sc); 1576 1577 if (!sc->ste_link) 1578 return; 1579 1580 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1581 return; 1582 1583 idx = sc->ste_cdata.ste_tx_prod; 1584 1585 while (sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1586 /* 1587 * We cannot re-use the last (free) descriptor; 1588 * the chip may not have read its ste_next yet. 1589 */ 1590 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1591 sc->ste_cdata.ste_tx_cons) { 1592 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1593 break; 1594 } 1595 1596 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1597 if (m_head == NULL) 1598 break; 1599 1600 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1601 1602 if (ste_encap(sc, cur_tx, m_head) != 0) 1603 break; 1604 1605 cur_tx->ste_ptr->ste_next = 0; 1606 1607 if (sc->ste_tx_prev == NULL) { 1608 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1609 /* Load address of the TX list */ 1610 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1611 ste_wait(sc); 1612 1613 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1614 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1615 1616 /* Set TX polling interval to start TX engine */ 1617 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1618 1619 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1620 ste_wait(sc); 1621 }else{ 1622 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1623 sc->ste_tx_prev->ste_ptr->ste_next 1624 = cur_tx->ste_phys; 1625 } 1626 1627 sc->ste_tx_prev = cur_tx; 1628 1629 /* 1630 * If there's a BPF listener, bounce a copy of this frame 1631 * to him. 1632 */ 1633 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1634 1635 STE_INC(idx, STE_TX_LIST_CNT); 1636 sc->ste_timer = 5; 1637 } 1638 sc->ste_cdata.ste_tx_prod = idx; 1639} 1640 1641static void 1642ste_watchdog(struct ste_softc *sc) 1643{ 1644 struct ifnet *ifp; 1645 1646 ifp = sc->ste_ifp; 1647 STE_LOCK_ASSERT(sc); 1648 1649 ifp->if_oerrors++; 1650 if_printf(ifp, "watchdog timeout\n"); 1651 1652 ste_txeoc(sc); 1653 ste_txeof(sc); 1654 ste_rxeoc(sc); 1655 ste_rxeof(sc); 1656 ste_reset(sc); 1657 ste_init_locked(sc); 1658 1659 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1660 ste_start_locked(ifp); 1661} 1662 1663static int 1664ste_shutdown(device_t dev) 1665{ 1666 struct ste_softc *sc; 1667 1668 sc = device_get_softc(dev); 1669 1670 STE_LOCK(sc); 1671 ste_stop(sc); 1672 STE_UNLOCK(sc); 1673 1674 return (0); 1675} 1676