if_ste.c revision 199559
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 199559 2009-11-19 22:06:40Z jhb $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56#include <net/if_vlan_var.h> 57 58#include <net/bpf.h> 59 60#include <vm/vm.h> /* for vtophys */ 61#include <vm/pmap.h> /* for vtophys */ 62#include <machine/bus.h> 63#include <machine/resource.h> 64#include <sys/bus.h> 65#include <sys/rman.h> 66 67#include <dev/mii/mii.h> 68#include <dev/mii/miivar.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73/* "device miibus" required. See GENERIC if you get errors here. */ 74#include "miibus_if.h" 75 76#define STE_USEIOSPACE 77 78#include <dev/ste/if_stereg.h> 79 80MODULE_DEPEND(ste, pci, 1, 1, 1); 81MODULE_DEPEND(ste, ether, 1, 1, 1); 82MODULE_DEPEND(ste, miibus, 1, 1, 1); 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92}; 93 94static int ste_probe(device_t); 95static int ste_attach(device_t); 96static int ste_detach(device_t); 97static void ste_init(void *); 98static void ste_init_locked(struct ste_softc *); 99static void ste_intr(void *); 100static void ste_rxeoc(struct ste_softc *); 101static int ste_rxeof(struct ste_softc *); 102static void ste_txeoc(struct ste_softc *); 103static void ste_txeof(struct ste_softc *); 104static void ste_stats_update(void *); 105static void ste_stop(struct ste_softc *); 106static void ste_reset(struct ste_softc *); 107static int ste_ioctl(struct ifnet *, u_long, caddr_t); 108static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 109static void ste_start(struct ifnet *); 110static void ste_start_locked(struct ifnet *); 111static void ste_watchdog(struct ste_softc *); 112static int ste_shutdown(device_t); 113static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 114 struct mbuf *); 115static int ste_ifmedia_upd(struct ifnet *); 116static void ste_ifmedia_upd_locked(struct ifnet *); 117static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 119static void ste_mii_sync(struct ste_softc *); 120static void ste_mii_send(struct ste_softc *, u_int32_t, int); 121static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 122static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 123static int ste_miibus_readreg(device_t, int, int); 124static int ste_miibus_writereg(device_t, int, int, int); 125static void ste_miibus_statchg(device_t); 126 127static int ste_eeprom_wait(struct ste_softc *); 128static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 129static void ste_wait(struct ste_softc *); 130static void ste_setmulti(struct ste_softc *); 131static int ste_init_rx_list(struct ste_softc *); 132static void ste_init_tx_list(struct ste_softc *); 133 134#ifdef STE_USEIOSPACE 135#define STE_RES SYS_RES_IOPORT 136#define STE_RID STE_PCI_LOIO 137#else 138#define STE_RES SYS_RES_MEMORY 139#define STE_RID STE_PCI_LOMEM 140#endif 141 142static device_method_t ste_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, ste_probe), 145 DEVMETHOD(device_attach, ste_attach), 146 DEVMETHOD(device_detach, ste_detach), 147 DEVMETHOD(device_shutdown, ste_shutdown), 148 149 /* bus interface */ 150 DEVMETHOD(bus_print_child, bus_generic_print_child), 151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 152 153 /* MII interface */ 154 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 155 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 156 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 157 158 { 0, 0 } 159}; 160 161static driver_t ste_driver = { 162 "ste", 163 ste_methods, 164 sizeof(struct ste_softc) 165}; 166 167static devclass_t ste_devclass; 168 169DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 170DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 171 172SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 173 174static int ste_rxsyncs; 175SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 176 177#define STE_SETBIT4(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 179 180#define STE_CLRBIT4(sc, reg, x) \ 181 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 182 183#define STE_SETBIT2(sc, reg, x) \ 184 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 185 186#define STE_CLRBIT2(sc, reg, x) \ 187 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 188 189#define STE_SETBIT1(sc, reg, x) \ 190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 191 192#define STE_CLRBIT1(sc, reg, x) \ 193 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 194 195 196#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 197#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 198 199/* 200 * Sync the PHYs by setting data bit and strobing the clock 32 times. 201 */ 202static void 203ste_mii_sync(sc) 204 struct ste_softc *sc; 205{ 206 register int i; 207 208 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 209 210 for (i = 0; i < 32; i++) { 211 MII_SET(STE_PHYCTL_MCLK); 212 DELAY(1); 213 MII_CLR(STE_PHYCTL_MCLK); 214 DELAY(1); 215 } 216 217 return; 218} 219 220/* 221 * Clock a series of bits through the MII. 222 */ 223static void 224ste_mii_send(sc, bits, cnt) 225 struct ste_softc *sc; 226 u_int32_t bits; 227 int cnt; 228{ 229 int i; 230 231 MII_CLR(STE_PHYCTL_MCLK); 232 233 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 234 if (bits & i) { 235 MII_SET(STE_PHYCTL_MDATA); 236 } else { 237 MII_CLR(STE_PHYCTL_MDATA); 238 } 239 DELAY(1); 240 MII_CLR(STE_PHYCTL_MCLK); 241 DELAY(1); 242 MII_SET(STE_PHYCTL_MCLK); 243 } 244} 245 246/* 247 * Read an PHY register through the MII. 248 */ 249static int 250ste_mii_readreg(sc, frame) 251 struct ste_softc *sc; 252 struct ste_mii_frame *frame; 253 254{ 255 int i, ack; 256 257 /* 258 * Set up frame for RX. 259 */ 260 frame->mii_stdelim = STE_MII_STARTDELIM; 261 frame->mii_opcode = STE_MII_READOP; 262 frame->mii_turnaround = 0; 263 frame->mii_data = 0; 264 265 CSR_WRITE_2(sc, STE_PHYCTL, 0); 266 /* 267 * Turn on data xmit. 268 */ 269 MII_SET(STE_PHYCTL_MDIR); 270 271 ste_mii_sync(sc); 272 273 /* 274 * Send command/address info. 275 */ 276 ste_mii_send(sc, frame->mii_stdelim, 2); 277 ste_mii_send(sc, frame->mii_opcode, 2); 278 ste_mii_send(sc, frame->mii_phyaddr, 5); 279 ste_mii_send(sc, frame->mii_regaddr, 5); 280 281 /* Turn off xmit. */ 282 MII_CLR(STE_PHYCTL_MDIR); 283 284 /* Idle bit */ 285 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 286 DELAY(1); 287 MII_SET(STE_PHYCTL_MCLK); 288 DELAY(1); 289 290 /* Check for ack */ 291 MII_CLR(STE_PHYCTL_MCLK); 292 DELAY(1); 293 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 297 /* 298 * Now try reading data bits. If the ack failed, we still 299 * need to clock through 16 cycles to keep the PHY(s) in sync. 300 */ 301 if (ack) { 302 for(i = 0; i < 16; i++) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 MII_SET(STE_PHYCTL_MCLK); 306 DELAY(1); 307 } 308 goto fail; 309 } 310 311 for (i = 0x8000; i; i >>= 1) { 312 MII_CLR(STE_PHYCTL_MCLK); 313 DELAY(1); 314 if (!ack) { 315 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 316 frame->mii_data |= i; 317 DELAY(1); 318 } 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 } 322 323fail: 324 325 MII_CLR(STE_PHYCTL_MCLK); 326 DELAY(1); 327 MII_SET(STE_PHYCTL_MCLK); 328 DELAY(1); 329 330 if (ack) 331 return(1); 332 return(0); 333} 334 335/* 336 * Write to a PHY register through the MII. 337 */ 338static int 339ste_mii_writereg(sc, frame) 340 struct ste_softc *sc; 341 struct ste_mii_frame *frame; 342 343{ 344 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 return(0); 379} 380 381static int 382ste_miibus_readreg(dev, phy, reg) 383 device_t dev; 384 int phy, reg; 385{ 386 struct ste_softc *sc; 387 struct ste_mii_frame frame; 388 389 sc = device_get_softc(dev); 390 391 if ( sc->ste_one_phy && phy != 0 ) 392 return (0); 393 394 bzero((char *)&frame, sizeof(frame)); 395 396 frame.mii_phyaddr = phy; 397 frame.mii_regaddr = reg; 398 ste_mii_readreg(sc, &frame); 399 400 return(frame.mii_data); 401} 402 403static int 404ste_miibus_writereg(dev, phy, reg, data) 405 device_t dev; 406 int phy, reg, data; 407{ 408 struct ste_softc *sc; 409 struct ste_mii_frame frame; 410 411 sc = device_get_softc(dev); 412 bzero((char *)&frame, sizeof(frame)); 413 414 frame.mii_phyaddr = phy; 415 frame.mii_regaddr = reg; 416 frame.mii_data = data; 417 418 ste_mii_writereg(sc, &frame); 419 420 return(0); 421} 422 423static void 424ste_miibus_statchg(dev) 425 device_t dev; 426{ 427 struct ste_softc *sc; 428 struct mii_data *mii; 429 430 sc = device_get_softc(dev); 431 432 mii = device_get_softc(sc->ste_miibus); 433 434 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 435 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 436 } else { 437 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } 439 440 return; 441} 442 443static int 444ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446{ 447 struct ste_softc *sc; 448 449 sc = ifp->if_softc; 450 STE_LOCK(sc); 451 ste_ifmedia_upd_locked(ifp); 452 STE_UNLOCK(sc); 453 454 return(0); 455} 456 457static void 458ste_ifmedia_upd_locked(ifp) 459 struct ifnet *ifp; 460{ 461 struct ste_softc *sc; 462 struct mii_data *mii; 463 464 sc = ifp->if_softc; 465 STE_LOCK_ASSERT(sc); 466 mii = device_get_softc(sc->ste_miibus); 467 sc->ste_link = 0; 468 if (mii->mii_instance) { 469 struct mii_softc *miisc; 470 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 471 mii_phy_reset(miisc); 472 } 473 mii_mediachg(mii); 474} 475 476static void 477ste_ifmedia_sts(ifp, ifmr) 478 struct ifnet *ifp; 479 struct ifmediareq *ifmr; 480{ 481 struct ste_softc *sc; 482 struct mii_data *mii; 483 484 sc = ifp->if_softc; 485 mii = device_get_softc(sc->ste_miibus); 486 487 STE_LOCK(sc); 488 mii_pollstat(mii); 489 ifmr->ifm_active = mii->mii_media_active; 490 ifmr->ifm_status = mii->mii_media_status; 491 STE_UNLOCK(sc); 492 493 return; 494} 495 496static void 497ste_wait(sc) 498 struct ste_softc *sc; 499{ 500 register int i; 501 502 for (i = 0; i < STE_TIMEOUT; i++) { 503 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 504 break; 505 } 506 507 if (i == STE_TIMEOUT) 508 device_printf(sc->ste_dev, "command never completed!\n"); 509 510 return; 511} 512 513/* 514 * The EEPROM is slow: give it time to come ready after issuing 515 * it a command. 516 */ 517static int 518ste_eeprom_wait(sc) 519 struct ste_softc *sc; 520{ 521 int i; 522 523 DELAY(1000); 524 525 for (i = 0; i < 100; i++) { 526 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 527 DELAY(1000); 528 else 529 break; 530 } 531 532 if (i == 100) { 533 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 534 return(1); 535 } 536 537 return(0); 538} 539 540/* 541 * Read a sequence of words from the EEPROM. Note that ethernet address 542 * data is stored in the EEPROM in network byte order. 543 */ 544static int 545ste_read_eeprom(sc, dest, off, cnt, swap) 546 struct ste_softc *sc; 547 caddr_t dest; 548 int off; 549 int cnt; 550 int swap; 551{ 552 int err = 0, i; 553 u_int16_t word = 0, *ptr; 554 555 if (ste_eeprom_wait(sc)) 556 return(1); 557 558 for (i = 0; i < cnt; i++) { 559 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 560 err = ste_eeprom_wait(sc); 561 if (err) 562 break; 563 word = CSR_READ_2(sc, STE_EEPROM_DATA); 564 ptr = (u_int16_t *)(dest + (i * 2)); 565 if (swap) 566 *ptr = ntohs(word); 567 else 568 *ptr = word; 569 } 570 571 return(err ? 1 : 0); 572} 573 574static void 575ste_setmulti(sc) 576 struct ste_softc *sc; 577{ 578 struct ifnet *ifp; 579 int h = 0; 580 u_int32_t hashes[2] = { 0, 0 }; 581 struct ifmultiaddr *ifma; 582 583 ifp = sc->ste_ifp; 584 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 585 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 586 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 587 return; 588 } 589 590 /* first, zot all the existing hash bits */ 591 CSR_WRITE_2(sc, STE_MAR0, 0); 592 CSR_WRITE_2(sc, STE_MAR1, 0); 593 CSR_WRITE_2(sc, STE_MAR2, 0); 594 CSR_WRITE_2(sc, STE_MAR3, 0); 595 596 /* now program new ones */ 597 if_maddr_rlock(ifp); 598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 599 if (ifma->ifma_addr->sa_family != AF_LINK) 600 continue; 601 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 602 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 603 if (h < 32) 604 hashes[0] |= (1 << h); 605 else 606 hashes[1] |= (1 << (h - 32)); 607 } 608 if_maddr_runlock(ifp); 609 610 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 611 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 612 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 613 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 614 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 615 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 616 617 return; 618} 619 620#ifdef DEVICE_POLLING 621static poll_handler_t ste_poll, ste_poll_locked; 622 623static int 624ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 625{ 626 struct ste_softc *sc = ifp->if_softc; 627 int rx_npkts = 0; 628 629 STE_LOCK(sc); 630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 631 rx_npkts = ste_poll_locked(ifp, cmd, count); 632 STE_UNLOCK(sc); 633 return (rx_npkts); 634} 635 636static int 637ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 638{ 639 struct ste_softc *sc = ifp->if_softc; 640 int rx_npkts; 641 642 STE_LOCK_ASSERT(sc); 643 644 sc->rxcycles = count; 645 if (cmd == POLL_AND_CHECK_STATUS) 646 ste_rxeoc(sc); 647 rx_npkts = ste_rxeof(sc); 648 ste_txeof(sc); 649 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 650 ste_start_locked(ifp); 651 652 if (cmd == POLL_AND_CHECK_STATUS) { 653 u_int16_t status; 654 655 status = CSR_READ_2(sc, STE_ISR_ACK); 656 657 if (status & STE_ISR_TX_DONE) 658 ste_txeoc(sc); 659 660 if (status & STE_ISR_STATS_OFLOW) { 661 callout_stop(&sc->ste_stat_callout); 662 ste_stats_update(sc); 663 } 664 665 if (status & STE_ISR_LINKEVENT) 666 mii_pollstat(device_get_softc(sc->ste_miibus)); 667 668 if (status & STE_ISR_HOSTERR) { 669 ste_reset(sc); 670 ste_init_locked(sc); 671 } 672 } 673 return (rx_npkts); 674} 675#endif /* DEVICE_POLLING */ 676 677static void 678ste_intr(xsc) 679 void *xsc; 680{ 681 struct ste_softc *sc; 682 struct ifnet *ifp; 683 u_int16_t status; 684 685 sc = xsc; 686 STE_LOCK(sc); 687 ifp = sc->ste_ifp; 688 689#ifdef DEVICE_POLLING 690 if (ifp->if_capenable & IFCAP_POLLING) { 691 STE_UNLOCK(sc); 692 return; 693 } 694#endif 695 696 /* See if this is really our interrupt. */ 697 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 698 STE_UNLOCK(sc); 699 return; 700 } 701 702 for (;;) { 703 status = CSR_READ_2(sc, STE_ISR_ACK); 704 705 if (!(status & STE_INTRS)) 706 break; 707 708 if (status & STE_ISR_RX_DMADONE) { 709 ste_rxeoc(sc); 710 ste_rxeof(sc); 711 } 712 713 if (status & STE_ISR_TX_DMADONE) 714 ste_txeof(sc); 715 716 if (status & STE_ISR_TX_DONE) 717 ste_txeoc(sc); 718 719 if (status & STE_ISR_STATS_OFLOW) { 720 callout_stop(&sc->ste_stat_callout); 721 ste_stats_update(sc); 722 } 723 724 if (status & STE_ISR_LINKEVENT) 725 mii_pollstat(device_get_softc(sc->ste_miibus)); 726 727 728 if (status & STE_ISR_HOSTERR) { 729 ste_reset(sc); 730 ste_init_locked(sc); 731 } 732 } 733 734 /* Re-enable interrupts */ 735 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 736 737 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 738 ste_start_locked(ifp); 739 740 STE_UNLOCK(sc); 741 742 return; 743} 744 745static void 746ste_rxeoc(struct ste_softc *sc) 747{ 748 struct ste_chain_onefrag *cur_rx; 749 750 STE_LOCK_ASSERT(sc); 751 752 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 753 cur_rx = sc->ste_cdata.ste_rx_head; 754 do { 755 cur_rx = cur_rx->ste_next; 756 /* If the ring is empty, just return. */ 757 if (cur_rx == sc->ste_cdata.ste_rx_head) 758 return; 759 } while (cur_rx->ste_ptr->ste_status == 0); 760 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 761 /* We've fallen behind the chip: catch it. */ 762 sc->ste_cdata.ste_rx_head = cur_rx; 763 ++ste_rxsyncs; 764 } 765 } 766} 767 768/* 769 * A frame has been uploaded: pass the resulting mbuf chain up to 770 * the higher level protocols. 771 */ 772static int 773ste_rxeof(sc) 774 struct ste_softc *sc; 775{ 776 struct mbuf *m; 777 struct ifnet *ifp; 778 struct ste_chain_onefrag *cur_rx; 779 int total_len = 0, count=0, rx_npkts = 0; 780 u_int32_t rxstat; 781 782 STE_LOCK_ASSERT(sc); 783 784 ifp = sc->ste_ifp; 785 786 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 787 & STE_RXSTAT_DMADONE) { 788#ifdef DEVICE_POLLING 789 if (ifp->if_capenable & IFCAP_POLLING) { 790 if (sc->rxcycles <= 0) 791 break; 792 sc->rxcycles--; 793 } 794#endif 795 if ((STE_RX_LIST_CNT - count) < 3) { 796 break; 797 } 798 799 cur_rx = sc->ste_cdata.ste_rx_head; 800 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 801 802 /* 803 * If an error occurs, update stats, clear the 804 * status word and leave the mbuf cluster in place: 805 * it should simply get re-used next time this descriptor 806 * comes up in the ring. 807 */ 808 if (rxstat & STE_RXSTAT_FRAME_ERR) { 809 ifp->if_ierrors++; 810 cur_rx->ste_ptr->ste_status = 0; 811 continue; 812 } 813 814 /* 815 * If there error bit was not set, the upload complete 816 * bit should be set which means we have a valid packet. 817 * If not, something truly strange has happened. 818 */ 819 if (!(rxstat & STE_RXSTAT_DMADONE)) { 820 device_printf(sc->ste_dev, 821 "bad receive status -- packet dropped\n"); 822 ifp->if_ierrors++; 823 cur_rx->ste_ptr->ste_status = 0; 824 continue; 825 } 826 827 /* No errors; receive the packet. */ 828 m = cur_rx->ste_mbuf; 829 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 830 831 /* 832 * Try to conjure up a new mbuf cluster. If that 833 * fails, it means we have an out of memory condition and 834 * should leave the buffer in place and continue. This will 835 * result in a lost packet, but there's little else we 836 * can do in this situation. 837 */ 838 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 839 ifp->if_ierrors++; 840 cur_rx->ste_ptr->ste_status = 0; 841 continue; 842 } 843 844 m->m_pkthdr.rcvif = ifp; 845 m->m_pkthdr.len = m->m_len = total_len; 846 847 ifp->if_ipackets++; 848 STE_UNLOCK(sc); 849 (*ifp->if_input)(ifp, m); 850 STE_LOCK(sc); 851 852 cur_rx->ste_ptr->ste_status = 0; 853 count++; 854 rx_npkts++; 855 } 856 857 return (rx_npkts); 858} 859 860static void 861ste_txeoc(sc) 862 struct ste_softc *sc; 863{ 864 u_int8_t txstat; 865 struct ifnet *ifp; 866 867 ifp = sc->ste_ifp; 868 869 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 870 STE_TXSTATUS_TXDONE) { 871 if (txstat & STE_TXSTATUS_UNDERRUN || 872 txstat & STE_TXSTATUS_EXCESSCOLLS || 873 txstat & STE_TXSTATUS_RECLAIMERR) { 874 ifp->if_oerrors++; 875 device_printf(sc->ste_dev, 876 "transmission error: %x\n", txstat); 877 878 ste_reset(sc); 879 ste_init_locked(sc); 880 881 if (txstat & STE_TXSTATUS_UNDERRUN && 882 sc->ste_tx_thresh < STE_PACKET_SIZE) { 883 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 884 device_printf(sc->ste_dev, 885 "tx underrun, increasing tx" 886 " start threshold to %d bytes\n", 887 sc->ste_tx_thresh); 888 } 889 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 890 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 891 (STE_PACKET_SIZE >> 4)); 892 } 893 ste_init_locked(sc); 894 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 895 } 896 897 return; 898} 899 900static void 901ste_txeof(sc) 902 struct ste_softc *sc; 903{ 904 struct ste_chain *cur_tx; 905 struct ifnet *ifp; 906 int idx; 907 908 ifp = sc->ste_ifp; 909 910 idx = sc->ste_cdata.ste_tx_cons; 911 while(idx != sc->ste_cdata.ste_tx_prod) { 912 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 913 914 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 915 break; 916 917 m_freem(cur_tx->ste_mbuf); 918 cur_tx->ste_mbuf = NULL; 919 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 920 ifp->if_opackets++; 921 922 STE_INC(idx, STE_TX_LIST_CNT); 923 } 924 925 sc->ste_cdata.ste_tx_cons = idx; 926 if (idx == sc->ste_cdata.ste_tx_prod) 927 sc->ste_timer = 0; 928} 929 930static void 931ste_stats_update(xsc) 932 void *xsc; 933{ 934 struct ste_softc *sc; 935 struct ifnet *ifp; 936 struct mii_data *mii; 937 938 sc = xsc; 939 STE_LOCK_ASSERT(sc); 940 941 ifp = sc->ste_ifp; 942 mii = device_get_softc(sc->ste_miibus); 943 944 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 945 + CSR_READ_1(sc, STE_MULTI_COLLS) 946 + CSR_READ_1(sc, STE_SINGLE_COLLS); 947 948 if (!sc->ste_link) { 949 mii_pollstat(mii); 950 if (mii->mii_media_status & IFM_ACTIVE && 951 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 952 sc->ste_link++; 953 /* 954 * we don't get a call-back on re-init so do it 955 * otherwise we get stuck in the wrong link state 956 */ 957 ste_miibus_statchg(sc->ste_dev); 958 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 959 ste_start_locked(ifp); 960 } 961 } 962 963 if (sc->ste_timer > 0 && --sc->ste_timer == 0) 964 ste_watchdog(sc); 965 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 966 967 return; 968} 969 970 971/* 972 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 973 * IDs against our list and return a device name if we find a match. 974 */ 975static int 976ste_probe(dev) 977 device_t dev; 978{ 979 struct ste_type *t; 980 981 t = ste_devs; 982 983 while(t->ste_name != NULL) { 984 if ((pci_get_vendor(dev) == t->ste_vid) && 985 (pci_get_device(dev) == t->ste_did)) { 986 device_set_desc(dev, t->ste_name); 987 return (BUS_PROBE_DEFAULT); 988 } 989 t++; 990 } 991 992 return(ENXIO); 993} 994 995/* 996 * Attach the interface. Allocate softc structures, do ifmedia 997 * setup and ethernet/BPF attach. 998 */ 999static int 1000ste_attach(dev) 1001 device_t dev; 1002{ 1003 struct ste_softc *sc; 1004 struct ifnet *ifp; 1005 int error = 0, rid; 1006 u_char eaddr[6]; 1007 1008 sc = device_get_softc(dev); 1009 sc->ste_dev = dev; 1010 1011 /* 1012 * Only use one PHY since this chip reports multiple 1013 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1014 * it is at 0 & 1. It is rev 0x12. 1015 */ 1016 if (pci_get_vendor(dev) == DL_VENDORID && 1017 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1018 pci_get_revid(dev) == 0x12 ) 1019 sc->ste_one_phy = 1; 1020 1021 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1022 MTX_DEF); 1023 /* 1024 * Map control/status registers. 1025 */ 1026 pci_enable_busmaster(dev); 1027 1028 rid = STE_RID; 1029 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1030 1031 if (sc->ste_res == NULL) { 1032 device_printf(dev, "couldn't map ports/memory\n"); 1033 error = ENXIO; 1034 goto fail; 1035 } 1036 1037 sc->ste_btag = rman_get_bustag(sc->ste_res); 1038 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1039 1040 /* Allocate interrupt */ 1041 rid = 0; 1042 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1043 RF_SHAREABLE | RF_ACTIVE); 1044 1045 if (sc->ste_irq == NULL) { 1046 device_printf(dev, "couldn't map interrupt\n"); 1047 error = ENXIO; 1048 goto fail; 1049 } 1050 1051 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0); 1052 1053 /* Reset the adapter. */ 1054 ste_reset(sc); 1055 1056 /* 1057 * Get station address from the EEPROM. 1058 */ 1059 if (ste_read_eeprom(sc, eaddr, 1060 STE_EEADDR_NODE0, 3, 0)) { 1061 device_printf(dev, "failed to read station address\n"); 1062 error = ENXIO;; 1063 goto fail; 1064 } 1065 1066 /* Allocate the descriptor queues. */ 1067 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1068 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1069 1070 if (sc->ste_ldata == NULL) { 1071 device_printf(dev, "no memory for list buffers!\n"); 1072 error = ENXIO; 1073 goto fail; 1074 } 1075 1076 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1077 1078 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1079 if (ifp == NULL) { 1080 device_printf(dev, "can not if_alloc()\n"); 1081 error = ENOSPC; 1082 goto fail; 1083 } 1084 1085 /* Do MII setup. */ 1086 if (mii_phy_probe(dev, &sc->ste_miibus, 1087 ste_ifmedia_upd, ste_ifmedia_sts)) { 1088 device_printf(dev, "MII without any phy!\n"); 1089 error = ENXIO; 1090 goto fail; 1091 } 1092 1093 ifp->if_softc = sc; 1094 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1095 ifp->if_mtu = ETHERMTU; 1096 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1097 ifp->if_ioctl = ste_ioctl; 1098 ifp->if_start = ste_start; 1099 ifp->if_init = ste_init; 1100 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1101 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1102 IFQ_SET_READY(&ifp->if_snd); 1103 1104 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1105 1106 /* 1107 * Call MI attach routine. 1108 */ 1109 ether_ifattach(ifp, eaddr); 1110 1111 /* 1112 * Tell the upper layer(s) we support long frames. 1113 */ 1114 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1115 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1116 ifp->if_capenable = ifp->if_capabilities; 1117#ifdef DEVICE_POLLING 1118 ifp->if_capabilities |= IFCAP_POLLING; 1119#endif 1120 1121 /* Hook interrupt last to avoid having to lock softc */ 1122 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1123 NULL, ste_intr, sc, &sc->ste_intrhand); 1124 1125 if (error) { 1126 device_printf(dev, "couldn't set up irq\n"); 1127 ether_ifdetach(ifp); 1128 goto fail; 1129 } 1130 1131fail: 1132 if (error) 1133 ste_detach(dev); 1134 1135 return(error); 1136} 1137 1138/* 1139 * Shutdown hardware and free up resources. This can be called any 1140 * time after the mutex has been initialized. It is called in both 1141 * the error case in attach and the normal detach case so it needs 1142 * to be careful about only freeing resources that have actually been 1143 * allocated. 1144 */ 1145static int 1146ste_detach(dev) 1147 device_t dev; 1148{ 1149 struct ste_softc *sc; 1150 struct ifnet *ifp; 1151 1152 sc = device_get_softc(dev); 1153 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1154 ifp = sc->ste_ifp; 1155 1156#ifdef DEVICE_POLLING 1157 if (ifp->if_capenable & IFCAP_POLLING) 1158 ether_poll_deregister(ifp); 1159#endif 1160 1161 /* These should only be active if attach succeeded */ 1162 if (device_is_attached(dev)) { 1163 ether_ifdetach(ifp); 1164 STE_LOCK(sc); 1165 ste_stop(sc); 1166 STE_UNLOCK(sc); 1167 callout_drain(&sc->ste_stat_callout); 1168 } 1169 if (sc->ste_miibus) 1170 device_delete_child(dev, sc->ste_miibus); 1171 bus_generic_detach(dev); 1172 1173 if (sc->ste_intrhand) 1174 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1175 if (sc->ste_irq) 1176 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1177 if (sc->ste_res) 1178 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1179 1180 if (ifp) 1181 if_free(ifp); 1182 1183 if (sc->ste_ldata) { 1184 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1185 M_DEVBUF); 1186 } 1187 1188 mtx_destroy(&sc->ste_mtx); 1189 1190 return(0); 1191} 1192 1193static int 1194ste_newbuf(sc, c, m) 1195 struct ste_softc *sc; 1196 struct ste_chain_onefrag *c; 1197 struct mbuf *m; 1198{ 1199 struct mbuf *m_new = NULL; 1200 1201 if (m == NULL) { 1202 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1203 if (m_new == NULL) 1204 return(ENOBUFS); 1205 MCLGET(m_new, M_DONTWAIT); 1206 if (!(m_new->m_flags & M_EXT)) { 1207 m_freem(m_new); 1208 return(ENOBUFS); 1209 } 1210 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1211 } else { 1212 m_new = m; 1213 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1214 m_new->m_data = m_new->m_ext.ext_buf; 1215 } 1216 1217 m_adj(m_new, ETHER_ALIGN); 1218 1219 c->ste_mbuf = m_new; 1220 c->ste_ptr->ste_status = 0; 1221 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1222 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1223 1224 return(0); 1225} 1226 1227static int 1228ste_init_rx_list(sc) 1229 struct ste_softc *sc; 1230{ 1231 struct ste_chain_data *cd; 1232 struct ste_list_data *ld; 1233 int i; 1234 1235 cd = &sc->ste_cdata; 1236 ld = sc->ste_ldata; 1237 1238 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1239 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1240 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1241 return(ENOBUFS); 1242 if (i == (STE_RX_LIST_CNT - 1)) { 1243 cd->ste_rx_chain[i].ste_next = 1244 &cd->ste_rx_chain[0]; 1245 ld->ste_rx_list[i].ste_next = 1246 vtophys(&ld->ste_rx_list[0]); 1247 } else { 1248 cd->ste_rx_chain[i].ste_next = 1249 &cd->ste_rx_chain[i + 1]; 1250 ld->ste_rx_list[i].ste_next = 1251 vtophys(&ld->ste_rx_list[i + 1]); 1252 } 1253 ld->ste_rx_list[i].ste_status = 0; 1254 } 1255 1256 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1257 1258 return(0); 1259} 1260 1261static void 1262ste_init_tx_list(sc) 1263 struct ste_softc *sc; 1264{ 1265 struct ste_chain_data *cd; 1266 struct ste_list_data *ld; 1267 int i; 1268 1269 cd = &sc->ste_cdata; 1270 ld = sc->ste_ldata; 1271 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1272 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1273 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1274 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1275 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1276 if (i == (STE_TX_LIST_CNT - 1)) 1277 cd->ste_tx_chain[i].ste_next = 1278 &cd->ste_tx_chain[0]; 1279 else 1280 cd->ste_tx_chain[i].ste_next = 1281 &cd->ste_tx_chain[i + 1]; 1282 } 1283 1284 cd->ste_tx_prod = 0; 1285 cd->ste_tx_cons = 0; 1286 1287 return; 1288} 1289 1290static void 1291ste_init(xsc) 1292 void *xsc; 1293{ 1294 struct ste_softc *sc; 1295 1296 sc = xsc; 1297 STE_LOCK(sc); 1298 ste_init_locked(sc); 1299 STE_UNLOCK(sc); 1300} 1301 1302static void 1303ste_init_locked(sc) 1304 struct ste_softc *sc; 1305{ 1306 int i; 1307 struct ifnet *ifp; 1308 1309 STE_LOCK_ASSERT(sc); 1310 ifp = sc->ste_ifp; 1311 1312 ste_stop(sc); 1313 1314 /* Init our MAC address */ 1315 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1316 CSR_WRITE_2(sc, STE_PAR0 + i, 1317 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1318 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1319 } 1320 1321 /* Init RX list */ 1322 if (ste_init_rx_list(sc) == ENOBUFS) { 1323 device_printf(sc->ste_dev, 1324 "initialization failed: no memory for RX buffers\n"); 1325 ste_stop(sc); 1326 return; 1327 } 1328 1329 /* Set RX polling interval */ 1330 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1331 1332 /* Init TX descriptors */ 1333 ste_init_tx_list(sc); 1334 1335 /* Set the TX freethresh value */ 1336 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1337 1338 /* Set the TX start threshold for best performance. */ 1339 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1340 1341 /* Set the TX reclaim threshold. */ 1342 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1343 1344 /* Set up the RX filter. */ 1345 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1346 1347 /* If we want promiscuous mode, set the allframes bit. */ 1348 if (ifp->if_flags & IFF_PROMISC) { 1349 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1350 } else { 1351 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1352 } 1353 1354 /* Set capture broadcast bit to accept broadcast frames. */ 1355 if (ifp->if_flags & IFF_BROADCAST) { 1356 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1357 } else { 1358 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1359 } 1360 1361 ste_setmulti(sc); 1362 1363 /* Load the address of the RX list. */ 1364 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1365 ste_wait(sc); 1366 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1367 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1368 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1369 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1370 1371 /* Set TX polling interval (defer until we TX first packet */ 1372 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1373 1374 /* Load address of the TX list */ 1375 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1376 ste_wait(sc); 1377 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1378 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1379 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1380 ste_wait(sc); 1381 sc->ste_tx_prev = NULL; 1382 1383 /* Enable receiver and transmitter */ 1384 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1385 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1386 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1387 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1388 1389 /* Enable stats counters. */ 1390 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1391 1392 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1393#ifdef DEVICE_POLLING 1394 /* Disable interrupts if we are polling. */ 1395 if (ifp->if_capenable & IFCAP_POLLING) 1396 CSR_WRITE_2(sc, STE_IMR, 0); 1397 else 1398#endif 1399 /* Enable interrupts. */ 1400 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1401 1402 /* Accept VLAN length packets */ 1403 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1404 1405 ste_ifmedia_upd_locked(ifp); 1406 1407 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1408 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1409 1410 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 1411 1412 return; 1413} 1414 1415static void 1416ste_stop(sc) 1417 struct ste_softc *sc; 1418{ 1419 int i; 1420 struct ifnet *ifp; 1421 1422 STE_LOCK_ASSERT(sc); 1423 ifp = sc->ste_ifp; 1424 1425 callout_stop(&sc->ste_stat_callout); 1426 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1427 1428 CSR_WRITE_2(sc, STE_IMR, 0); 1429 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1430 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1431 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1432 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1433 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1434 ste_wait(sc); 1435 /* 1436 * Try really hard to stop the RX engine or under heavy RX 1437 * data chip will write into de-allocated memory. 1438 */ 1439 ste_reset(sc); 1440 1441 sc->ste_link = 0; 1442 1443 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1444 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1445 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1446 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1447 } 1448 } 1449 1450 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1451 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1452 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1453 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1454 } 1455 } 1456 1457 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1458 1459 return; 1460} 1461 1462static void 1463ste_reset(sc) 1464 struct ste_softc *sc; 1465{ 1466 int i; 1467 1468 STE_SETBIT4(sc, STE_ASICCTL, 1469 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1470 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1471 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1472 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1473 STE_ASICCTL_EXTRESET_RESET); 1474 1475 DELAY(100000); 1476 1477 for (i = 0; i < STE_TIMEOUT; i++) { 1478 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1479 break; 1480 } 1481 1482 if (i == STE_TIMEOUT) 1483 device_printf(sc->ste_dev, "global reset never completed\n"); 1484 1485 return; 1486} 1487 1488static int 1489ste_ioctl(ifp, command, data) 1490 struct ifnet *ifp; 1491 u_long command; 1492 caddr_t data; 1493{ 1494 struct ste_softc *sc; 1495 struct ifreq *ifr; 1496 struct mii_data *mii; 1497 int error = 0; 1498 1499 sc = ifp->if_softc; 1500 ifr = (struct ifreq *)data; 1501 1502 switch(command) { 1503 case SIOCSIFFLAGS: 1504 STE_LOCK(sc); 1505 if (ifp->if_flags & IFF_UP) { 1506 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1507 ifp->if_flags & IFF_PROMISC && 1508 !(sc->ste_if_flags & IFF_PROMISC)) { 1509 STE_SETBIT1(sc, STE_RX_MODE, 1510 STE_RXMODE_PROMISC); 1511 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1512 !(ifp->if_flags & IFF_PROMISC) && 1513 sc->ste_if_flags & IFF_PROMISC) { 1514 STE_CLRBIT1(sc, STE_RX_MODE, 1515 STE_RXMODE_PROMISC); 1516 } 1517 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1518 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1519 ste_setmulti(sc); 1520 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1521 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1522 ste_init_locked(sc); 1523 } 1524 } else { 1525 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1526 ste_stop(sc); 1527 } 1528 sc->ste_if_flags = ifp->if_flags; 1529 STE_UNLOCK(sc); 1530 error = 0; 1531 break; 1532 case SIOCADDMULTI: 1533 case SIOCDELMULTI: 1534 STE_LOCK(sc); 1535 ste_setmulti(sc); 1536 STE_UNLOCK(sc); 1537 error = 0; 1538 break; 1539 case SIOCGIFMEDIA: 1540 case SIOCSIFMEDIA: 1541 mii = device_get_softc(sc->ste_miibus); 1542 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1543 break; 1544 case SIOCSIFCAP: 1545#ifdef DEVICE_POLLING 1546 if (ifr->ifr_reqcap & IFCAP_POLLING && 1547 !(ifp->if_capenable & IFCAP_POLLING)) { 1548 error = ether_poll_register(ste_poll, ifp); 1549 if (error) 1550 return(error); 1551 STE_LOCK(sc); 1552 /* Disable interrupts */ 1553 CSR_WRITE_2(sc, STE_IMR, 0); 1554 ifp->if_capenable |= IFCAP_POLLING; 1555 STE_UNLOCK(sc); 1556 return (error); 1557 1558 } 1559 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1560 ifp->if_capenable & IFCAP_POLLING) { 1561 error = ether_poll_deregister(ifp); 1562 /* Enable interrupts. */ 1563 STE_LOCK(sc); 1564 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1565 ifp->if_capenable &= ~IFCAP_POLLING; 1566 STE_UNLOCK(sc); 1567 return (error); 1568 } 1569#endif /* DEVICE_POLLING */ 1570 break; 1571 default: 1572 error = ether_ioctl(ifp, command, data); 1573 break; 1574 } 1575 1576 return(error); 1577} 1578 1579static int 1580ste_encap(sc, c, m_head) 1581 struct ste_softc *sc; 1582 struct ste_chain *c; 1583 struct mbuf *m_head; 1584{ 1585 int frag = 0; 1586 struct ste_frag *f = NULL; 1587 struct mbuf *m; 1588 struct ste_desc *d; 1589 1590 d = c->ste_ptr; 1591 d->ste_ctl = 0; 1592 1593encap_retry: 1594 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1595 if (m->m_len != 0) { 1596 if (frag == STE_MAXFRAGS) 1597 break; 1598 f = &d->ste_frags[frag]; 1599 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1600 f->ste_len = m->m_len; 1601 frag++; 1602 } 1603 } 1604 1605 if (m != NULL) { 1606 struct mbuf *mn; 1607 1608 /* 1609 * We ran out of segments. We have to recopy this 1610 * mbuf chain first. Bail out if we can't get the 1611 * new buffers. 1612 */ 1613 mn = m_defrag(m_head, M_DONTWAIT); 1614 if (mn == NULL) { 1615 m_freem(m_head); 1616 return ENOMEM; 1617 } 1618 m_head = mn; 1619 goto encap_retry; 1620 } 1621 1622 c->ste_mbuf = m_head; 1623 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1624 d->ste_ctl = 1; 1625 1626 return(0); 1627} 1628 1629static void 1630ste_start(ifp) 1631 struct ifnet *ifp; 1632{ 1633 struct ste_softc *sc; 1634 1635 sc = ifp->if_softc; 1636 STE_LOCK(sc); 1637 ste_start_locked(ifp); 1638 STE_UNLOCK(sc); 1639} 1640 1641static void 1642ste_start_locked(ifp) 1643 struct ifnet *ifp; 1644{ 1645 struct ste_softc *sc; 1646 struct mbuf *m_head = NULL; 1647 struct ste_chain *cur_tx; 1648 int idx; 1649 1650 sc = ifp->if_softc; 1651 STE_LOCK_ASSERT(sc); 1652 1653 if (!sc->ste_link) 1654 return; 1655 1656 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1657 return; 1658 1659 idx = sc->ste_cdata.ste_tx_prod; 1660 1661 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1662 /* 1663 * We cannot re-use the last (free) descriptor; 1664 * the chip may not have read its ste_next yet. 1665 */ 1666 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1667 sc->ste_cdata.ste_tx_cons) { 1668 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1669 break; 1670 } 1671 1672 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1673 if (m_head == NULL) 1674 break; 1675 1676 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1677 1678 if (ste_encap(sc, cur_tx, m_head) != 0) 1679 break; 1680 1681 cur_tx->ste_ptr->ste_next = 0; 1682 1683 if (sc->ste_tx_prev == NULL) { 1684 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1685 /* Load address of the TX list */ 1686 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1687 ste_wait(sc); 1688 1689 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1690 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1691 1692 /* Set TX polling interval to start TX engine */ 1693 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1694 1695 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1696 ste_wait(sc); 1697 }else{ 1698 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1699 sc->ste_tx_prev->ste_ptr->ste_next 1700 = cur_tx->ste_phys; 1701 } 1702 1703 sc->ste_tx_prev = cur_tx; 1704 1705 /* 1706 * If there's a BPF listener, bounce a copy of this frame 1707 * to him. 1708 */ 1709 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1710 1711 STE_INC(idx, STE_TX_LIST_CNT); 1712 sc->ste_timer = 5; 1713 } 1714 sc->ste_cdata.ste_tx_prod = idx; 1715 1716 return; 1717} 1718 1719static void 1720ste_watchdog(struct ste_softc *sc) 1721{ 1722 struct ifnet *ifp; 1723 1724 ifp = sc->ste_ifp; 1725 STE_LOCK_ASSERT(sc); 1726 1727 ifp->if_oerrors++; 1728 if_printf(ifp, "watchdog timeout\n"); 1729 1730 ste_txeoc(sc); 1731 ste_txeof(sc); 1732 ste_rxeoc(sc); 1733 ste_rxeof(sc); 1734 ste_reset(sc); 1735 ste_init_locked(sc); 1736 1737 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1738 ste_start_locked(ifp); 1739 1740 return; 1741} 1742 1743static int 1744ste_shutdown(dev) 1745 device_t dev; 1746{ 1747 struct ste_softc *sc; 1748 1749 sc = device_get_softc(dev); 1750 1751 STE_LOCK(sc); 1752 ste_stop(sc); 1753 STE_UNLOCK(sc); 1754 1755 return (0); 1756} 1757