if_ste.c revision 181739
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 181739 2008-08-14 20:09:58Z imp $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56#include <net/if_vlan_var.h> 57 58#include <net/bpf.h> 59 60#include <vm/vm.h> /* for vtophys */ 61#include <vm/pmap.h> /* for vtophys */ 62#include <machine/bus.h> 63#include <machine/resource.h> 64#include <sys/bus.h> 65#include <sys/rman.h> 66 67#include <dev/mii/mii.h> 68#include <dev/mii/miivar.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73/* "device miibus" required. See GENERIC if you get errors here. */ 74#include "miibus_if.h" 75 76#define STE_USEIOSPACE 77 78#include <dev/ste/if_stereg.h> 79 80MODULE_DEPEND(ste, pci, 1, 1, 1); 81MODULE_DEPEND(ste, ether, 1, 1, 1); 82MODULE_DEPEND(ste, miibus, 1, 1, 1); 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92}; 93 94static int ste_probe(device_t); 95static int ste_attach(device_t); 96static int ste_detach(device_t); 97static void ste_init(void *); 98static void ste_init_locked(struct ste_softc *); 99static void ste_intr(void *); 100static void ste_rxeoc(struct ste_softc *); 101static void ste_rxeof(struct ste_softc *); 102static void ste_txeoc(struct ste_softc *); 103static void ste_txeof(struct ste_softc *); 104static void ste_stats_update(void *); 105static void ste_stop(struct ste_softc *); 106static void ste_reset(struct ste_softc *); 107static int ste_ioctl(struct ifnet *, u_long, caddr_t); 108static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 109static void ste_start(struct ifnet *); 110static void ste_start_locked(struct ifnet *); 111static void ste_watchdog(struct ifnet *); 112static int ste_shutdown(device_t); 113static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 114 struct mbuf *); 115static int ste_ifmedia_upd(struct ifnet *); 116static void ste_ifmedia_upd_locked(struct ifnet *); 117static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 119static void ste_mii_sync(struct ste_softc *); 120static void ste_mii_send(struct ste_softc *, u_int32_t, int); 121static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 122static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 123static int ste_miibus_readreg(device_t, int, int); 124static int ste_miibus_writereg(device_t, int, int, int); 125static void ste_miibus_statchg(device_t); 126 127static int ste_eeprom_wait(struct ste_softc *); 128static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 129static void ste_wait(struct ste_softc *); 130static void ste_setmulti(struct ste_softc *); 131static int ste_init_rx_list(struct ste_softc *); 132static void ste_init_tx_list(struct ste_softc *); 133 134#ifdef STE_USEIOSPACE 135#define STE_RES SYS_RES_IOPORT 136#define STE_RID STE_PCI_LOIO 137#else 138#define STE_RES SYS_RES_MEMORY 139#define STE_RID STE_PCI_LOMEM 140#endif 141 142static device_method_t ste_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, ste_probe), 145 DEVMETHOD(device_attach, ste_attach), 146 DEVMETHOD(device_detach, ste_detach), 147 DEVMETHOD(device_shutdown, ste_shutdown), 148 149 /* bus interface */ 150 DEVMETHOD(bus_print_child, bus_generic_print_child), 151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 152 153 /* MII interface */ 154 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 155 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 156 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 157 158 { 0, 0 } 159}; 160 161static driver_t ste_driver = { 162 "ste", 163 ste_methods, 164 sizeof(struct ste_softc) 165}; 166 167static devclass_t ste_devclass; 168 169DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 170DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 171 172SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 173 174static int ste_rxsyncs; 175SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 176 177#define STE_SETBIT4(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 179 180#define STE_CLRBIT4(sc, reg, x) \ 181 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 182 183#define STE_SETBIT2(sc, reg, x) \ 184 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 185 186#define STE_CLRBIT2(sc, reg, x) \ 187 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 188 189#define STE_SETBIT1(sc, reg, x) \ 190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 191 192#define STE_CLRBIT1(sc, reg, x) \ 193 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 194 195 196#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 197#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 198 199/* 200 * Sync the PHYs by setting data bit and strobing the clock 32 times. 201 */ 202static void 203ste_mii_sync(sc) 204 struct ste_softc *sc; 205{ 206 register int i; 207 208 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 209 210 for (i = 0; i < 32; i++) { 211 MII_SET(STE_PHYCTL_MCLK); 212 DELAY(1); 213 MII_CLR(STE_PHYCTL_MCLK); 214 DELAY(1); 215 } 216 217 return; 218} 219 220/* 221 * Clock a series of bits through the MII. 222 */ 223static void 224ste_mii_send(sc, bits, cnt) 225 struct ste_softc *sc; 226 u_int32_t bits; 227 int cnt; 228{ 229 int i; 230 231 MII_CLR(STE_PHYCTL_MCLK); 232 233 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 234 if (bits & i) { 235 MII_SET(STE_PHYCTL_MDATA); 236 } else { 237 MII_CLR(STE_PHYCTL_MDATA); 238 } 239 DELAY(1); 240 MII_CLR(STE_PHYCTL_MCLK); 241 DELAY(1); 242 MII_SET(STE_PHYCTL_MCLK); 243 } 244} 245 246/* 247 * Read an PHY register through the MII. 248 */ 249static int 250ste_mii_readreg(sc, frame) 251 struct ste_softc *sc; 252 struct ste_mii_frame *frame; 253 254{ 255 int i, ack; 256 257 /* 258 * Set up frame for RX. 259 */ 260 frame->mii_stdelim = STE_MII_STARTDELIM; 261 frame->mii_opcode = STE_MII_READOP; 262 frame->mii_turnaround = 0; 263 frame->mii_data = 0; 264 265 CSR_WRITE_2(sc, STE_PHYCTL, 0); 266 /* 267 * Turn on data xmit. 268 */ 269 MII_SET(STE_PHYCTL_MDIR); 270 271 ste_mii_sync(sc); 272 273 /* 274 * Send command/address info. 275 */ 276 ste_mii_send(sc, frame->mii_stdelim, 2); 277 ste_mii_send(sc, frame->mii_opcode, 2); 278 ste_mii_send(sc, frame->mii_phyaddr, 5); 279 ste_mii_send(sc, frame->mii_regaddr, 5); 280 281 /* Turn off xmit. */ 282 MII_CLR(STE_PHYCTL_MDIR); 283 284 /* Idle bit */ 285 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 286 DELAY(1); 287 MII_SET(STE_PHYCTL_MCLK); 288 DELAY(1); 289 290 /* Check for ack */ 291 MII_CLR(STE_PHYCTL_MCLK); 292 DELAY(1); 293 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 297 /* 298 * Now try reading data bits. If the ack failed, we still 299 * need to clock through 16 cycles to keep the PHY(s) in sync. 300 */ 301 if (ack) { 302 for(i = 0; i < 16; i++) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 MII_SET(STE_PHYCTL_MCLK); 306 DELAY(1); 307 } 308 goto fail; 309 } 310 311 for (i = 0x8000; i; i >>= 1) { 312 MII_CLR(STE_PHYCTL_MCLK); 313 DELAY(1); 314 if (!ack) { 315 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 316 frame->mii_data |= i; 317 DELAY(1); 318 } 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 } 322 323fail: 324 325 MII_CLR(STE_PHYCTL_MCLK); 326 DELAY(1); 327 MII_SET(STE_PHYCTL_MCLK); 328 DELAY(1); 329 330 if (ack) 331 return(1); 332 return(0); 333} 334 335/* 336 * Write to a PHY register through the MII. 337 */ 338static int 339ste_mii_writereg(sc, frame) 340 struct ste_softc *sc; 341 struct ste_mii_frame *frame; 342 343{ 344 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 return(0); 379} 380 381static int 382ste_miibus_readreg(dev, phy, reg) 383 device_t dev; 384 int phy, reg; 385{ 386 struct ste_softc *sc; 387 struct ste_mii_frame frame; 388 389 sc = device_get_softc(dev); 390 391 if ( sc->ste_one_phy && phy != 0 ) 392 return (0); 393 394 bzero((char *)&frame, sizeof(frame)); 395 396 frame.mii_phyaddr = phy; 397 frame.mii_regaddr = reg; 398 ste_mii_readreg(sc, &frame); 399 400 return(frame.mii_data); 401} 402 403static int 404ste_miibus_writereg(dev, phy, reg, data) 405 device_t dev; 406 int phy, reg, data; 407{ 408 struct ste_softc *sc; 409 struct ste_mii_frame frame; 410 411 sc = device_get_softc(dev); 412 bzero((char *)&frame, sizeof(frame)); 413 414 frame.mii_phyaddr = phy; 415 frame.mii_regaddr = reg; 416 frame.mii_data = data; 417 418 ste_mii_writereg(sc, &frame); 419 420 return(0); 421} 422 423static void 424ste_miibus_statchg(dev) 425 device_t dev; 426{ 427 struct ste_softc *sc; 428 struct mii_data *mii; 429 430 sc = device_get_softc(dev); 431 432 mii = device_get_softc(sc->ste_miibus); 433 434 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 435 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 436 } else { 437 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } 439 440 return; 441} 442 443static int 444ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446{ 447 struct ste_softc *sc; 448 449 sc = ifp->if_softc; 450 STE_LOCK(sc); 451 ste_ifmedia_upd_locked(ifp); 452 STE_UNLOCK(sc); 453 454 return(0); 455} 456 457static void 458ste_ifmedia_upd_locked(ifp) 459 struct ifnet *ifp; 460{ 461 struct ste_softc *sc; 462 struct mii_data *mii; 463 464 sc = ifp->if_softc; 465 STE_LOCK_ASSERT(sc); 466 mii = device_get_softc(sc->ste_miibus); 467 sc->ste_link = 0; 468 if (mii->mii_instance) { 469 struct mii_softc *miisc; 470 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 471 mii_phy_reset(miisc); 472 } 473 mii_mediachg(mii); 474} 475 476static void 477ste_ifmedia_sts(ifp, ifmr) 478 struct ifnet *ifp; 479 struct ifmediareq *ifmr; 480{ 481 struct ste_softc *sc; 482 struct mii_data *mii; 483 484 sc = ifp->if_softc; 485 mii = device_get_softc(sc->ste_miibus); 486 487 STE_LOCK(sc); 488 mii_pollstat(mii); 489 ifmr->ifm_active = mii->mii_media_active; 490 ifmr->ifm_status = mii->mii_media_status; 491 STE_UNLOCK(sc); 492 493 return; 494} 495 496static void 497ste_wait(sc) 498 struct ste_softc *sc; 499{ 500 register int i; 501 502 for (i = 0; i < STE_TIMEOUT; i++) { 503 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 504 break; 505 } 506 507 if (i == STE_TIMEOUT) 508 device_printf(sc->ste_dev, "command never completed!\n"); 509 510 return; 511} 512 513/* 514 * The EEPROM is slow: give it time to come ready after issuing 515 * it a command. 516 */ 517static int 518ste_eeprom_wait(sc) 519 struct ste_softc *sc; 520{ 521 int i; 522 523 DELAY(1000); 524 525 for (i = 0; i < 100; i++) { 526 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 527 DELAY(1000); 528 else 529 break; 530 } 531 532 if (i == 100) { 533 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 534 return(1); 535 } 536 537 return(0); 538} 539 540/* 541 * Read a sequence of words from the EEPROM. Note that ethernet address 542 * data is stored in the EEPROM in network byte order. 543 */ 544static int 545ste_read_eeprom(sc, dest, off, cnt, swap) 546 struct ste_softc *sc; 547 caddr_t dest; 548 int off; 549 int cnt; 550 int swap; 551{ 552 int err = 0, i; 553 u_int16_t word = 0, *ptr; 554 555 if (ste_eeprom_wait(sc)) 556 return(1); 557 558 for (i = 0; i < cnt; i++) { 559 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 560 err = ste_eeprom_wait(sc); 561 if (err) 562 break; 563 word = CSR_READ_2(sc, STE_EEPROM_DATA); 564 ptr = (u_int16_t *)(dest + (i * 2)); 565 if (swap) 566 *ptr = ntohs(word); 567 else 568 *ptr = word; 569 } 570 571 return(err ? 1 : 0); 572} 573 574static void 575ste_setmulti(sc) 576 struct ste_softc *sc; 577{ 578 struct ifnet *ifp; 579 int h = 0; 580 u_int32_t hashes[2] = { 0, 0 }; 581 struct ifmultiaddr *ifma; 582 583 ifp = sc->ste_ifp; 584 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 585 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 586 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 587 return; 588 } 589 590 /* first, zot all the existing hash bits */ 591 CSR_WRITE_2(sc, STE_MAR0, 0); 592 CSR_WRITE_2(sc, STE_MAR1, 0); 593 CSR_WRITE_2(sc, STE_MAR2, 0); 594 CSR_WRITE_2(sc, STE_MAR3, 0); 595 596 /* now program new ones */ 597 IF_ADDR_LOCK(ifp); 598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 599 if (ifma->ifma_addr->sa_family != AF_LINK) 600 continue; 601 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 602 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 603 if (h < 32) 604 hashes[0] |= (1 << h); 605 else 606 hashes[1] |= (1 << (h - 32)); 607 } 608 IF_ADDR_UNLOCK(ifp); 609 610 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 611 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 612 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 613 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 614 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 615 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 616 617 return; 618} 619 620#ifdef DEVICE_POLLING 621static poll_handler_t ste_poll, ste_poll_locked; 622 623static void 624ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 625{ 626 struct ste_softc *sc = ifp->if_softc; 627 628 STE_LOCK(sc); 629 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 630 ste_poll_locked(ifp, cmd, count); 631 STE_UNLOCK(sc); 632} 633 634static void 635ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 636{ 637 struct ste_softc *sc = ifp->if_softc; 638 639 STE_LOCK_ASSERT(sc); 640 641 sc->rxcycles = count; 642 if (cmd == POLL_AND_CHECK_STATUS) 643 ste_rxeoc(sc); 644 ste_rxeof(sc); 645 ste_txeof(sc); 646 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 647 ste_start_locked(ifp); 648 649 if (cmd == POLL_AND_CHECK_STATUS) { 650 u_int16_t status; 651 652 status = CSR_READ_2(sc, STE_ISR_ACK); 653 654 if (status & STE_ISR_TX_DONE) 655 ste_txeoc(sc); 656 657 if (status & STE_ISR_STATS_OFLOW) { 658 callout_stop(&sc->ste_stat_callout); 659 ste_stats_update(sc); 660 } 661 662 if (status & STE_ISR_LINKEVENT) 663 mii_pollstat(device_get_softc(sc->ste_miibus)); 664 665 if (status & STE_ISR_HOSTERR) { 666 ste_reset(sc); 667 ste_init_locked(sc); 668 } 669 } 670} 671#endif /* DEVICE_POLLING */ 672 673static void 674ste_intr(xsc) 675 void *xsc; 676{ 677 struct ste_softc *sc; 678 struct ifnet *ifp; 679 u_int16_t status; 680 681 sc = xsc; 682 STE_LOCK(sc); 683 ifp = sc->ste_ifp; 684 685#ifdef DEVICE_POLLING 686 if (ifp->if_capenable & IFCAP_POLLING) { 687 STE_UNLOCK(sc); 688 return; 689 } 690#endif 691 692 /* See if this is really our interrupt. */ 693 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 694 STE_UNLOCK(sc); 695 return; 696 } 697 698 for (;;) { 699 status = CSR_READ_2(sc, STE_ISR_ACK); 700 701 if (!(status & STE_INTRS)) 702 break; 703 704 if (status & STE_ISR_RX_DMADONE) { 705 ste_rxeoc(sc); 706 ste_rxeof(sc); 707 } 708 709 if (status & STE_ISR_TX_DMADONE) 710 ste_txeof(sc); 711 712 if (status & STE_ISR_TX_DONE) 713 ste_txeoc(sc); 714 715 if (status & STE_ISR_STATS_OFLOW) { 716 callout_stop(&sc->ste_stat_callout); 717 ste_stats_update(sc); 718 } 719 720 if (status & STE_ISR_LINKEVENT) 721 mii_pollstat(device_get_softc(sc->ste_miibus)); 722 723 724 if (status & STE_ISR_HOSTERR) { 725 ste_reset(sc); 726 ste_init_locked(sc); 727 } 728 } 729 730 /* Re-enable interrupts */ 731 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 732 733 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 734 ste_start_locked(ifp); 735 736 STE_UNLOCK(sc); 737 738 return; 739} 740 741static void 742ste_rxeoc(struct ste_softc *sc) 743{ 744 struct ste_chain_onefrag *cur_rx; 745 746 STE_LOCK_ASSERT(sc); 747 748 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 749 cur_rx = sc->ste_cdata.ste_rx_head; 750 do { 751 cur_rx = cur_rx->ste_next; 752 /* If the ring is empty, just return. */ 753 if (cur_rx == sc->ste_cdata.ste_rx_head) 754 return; 755 } while (cur_rx->ste_ptr->ste_status == 0); 756 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 757 /* We've fallen behind the chip: catch it. */ 758 sc->ste_cdata.ste_rx_head = cur_rx; 759 ++ste_rxsyncs; 760 } 761 } 762} 763 764/* 765 * A frame has been uploaded: pass the resulting mbuf chain up to 766 * the higher level protocols. 767 */ 768static void 769ste_rxeof(sc) 770 struct ste_softc *sc; 771{ 772 struct mbuf *m; 773 struct ifnet *ifp; 774 struct ste_chain_onefrag *cur_rx; 775 int total_len = 0, count=0; 776 u_int32_t rxstat; 777 778 STE_LOCK_ASSERT(sc); 779 780 ifp = sc->ste_ifp; 781 782 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 783 & STE_RXSTAT_DMADONE) { 784#ifdef DEVICE_POLLING 785 if (ifp->if_capenable & IFCAP_POLLING) { 786 if (sc->rxcycles <= 0) 787 break; 788 sc->rxcycles--; 789 } 790#endif 791 if ((STE_RX_LIST_CNT - count) < 3) { 792 break; 793 } 794 795 cur_rx = sc->ste_cdata.ste_rx_head; 796 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 797 798 /* 799 * If an error occurs, update stats, clear the 800 * status word and leave the mbuf cluster in place: 801 * it should simply get re-used next time this descriptor 802 * comes up in the ring. 803 */ 804 if (rxstat & STE_RXSTAT_FRAME_ERR) { 805 ifp->if_ierrors++; 806 cur_rx->ste_ptr->ste_status = 0; 807 continue; 808 } 809 810 /* 811 * If there error bit was not set, the upload complete 812 * bit should be set which means we have a valid packet. 813 * If not, something truly strange has happened. 814 */ 815 if (!(rxstat & STE_RXSTAT_DMADONE)) { 816 device_printf(sc->ste_dev, 817 "bad receive status -- packet dropped\n"); 818 ifp->if_ierrors++; 819 cur_rx->ste_ptr->ste_status = 0; 820 continue; 821 } 822 823 /* No errors; receive the packet. */ 824 m = cur_rx->ste_mbuf; 825 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 826 827 /* 828 * Try to conjure up a new mbuf cluster. If that 829 * fails, it means we have an out of memory condition and 830 * should leave the buffer in place and continue. This will 831 * result in a lost packet, but there's little else we 832 * can do in this situation. 833 */ 834 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 835 ifp->if_ierrors++; 836 cur_rx->ste_ptr->ste_status = 0; 837 continue; 838 } 839 840 m->m_pkthdr.rcvif = ifp; 841 m->m_pkthdr.len = m->m_len = total_len; 842 843 ifp->if_ipackets++; 844 STE_UNLOCK(sc); 845 (*ifp->if_input)(ifp, m); 846 STE_LOCK(sc); 847 848 cur_rx->ste_ptr->ste_status = 0; 849 count++; 850 } 851 852 return; 853} 854 855static void 856ste_txeoc(sc) 857 struct ste_softc *sc; 858{ 859 u_int8_t txstat; 860 struct ifnet *ifp; 861 862 ifp = sc->ste_ifp; 863 864 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 865 STE_TXSTATUS_TXDONE) { 866 if (txstat & STE_TXSTATUS_UNDERRUN || 867 txstat & STE_TXSTATUS_EXCESSCOLLS || 868 txstat & STE_TXSTATUS_RECLAIMERR) { 869 ifp->if_oerrors++; 870 device_printf(sc->ste_dev, 871 "transmission error: %x\n", txstat); 872 873 ste_reset(sc); 874 ste_init_locked(sc); 875 876 if (txstat & STE_TXSTATUS_UNDERRUN && 877 sc->ste_tx_thresh < STE_PACKET_SIZE) { 878 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 879 device_printf(sc->ste_dev, 880 "tx underrun, increasing tx" 881 " start threshold to %d bytes\n", 882 sc->ste_tx_thresh); 883 } 884 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 885 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 886 (STE_PACKET_SIZE >> 4)); 887 } 888 ste_init_locked(sc); 889 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 890 } 891 892 return; 893} 894 895static void 896ste_txeof(sc) 897 struct ste_softc *sc; 898{ 899 struct ste_chain *cur_tx; 900 struct ifnet *ifp; 901 int idx; 902 903 ifp = sc->ste_ifp; 904 905 idx = sc->ste_cdata.ste_tx_cons; 906 while(idx != sc->ste_cdata.ste_tx_prod) { 907 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 908 909 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 910 break; 911 912 m_freem(cur_tx->ste_mbuf); 913 cur_tx->ste_mbuf = NULL; 914 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 915 ifp->if_opackets++; 916 917 STE_INC(idx, STE_TX_LIST_CNT); 918 } 919 920 sc->ste_cdata.ste_tx_cons = idx; 921 if (idx == sc->ste_cdata.ste_tx_prod) 922 ifp->if_timer = 0; 923} 924 925static void 926ste_stats_update(xsc) 927 void *xsc; 928{ 929 struct ste_softc *sc; 930 struct ifnet *ifp; 931 struct mii_data *mii; 932 933 sc = xsc; 934 STE_LOCK_ASSERT(sc); 935 936 ifp = sc->ste_ifp; 937 mii = device_get_softc(sc->ste_miibus); 938 939 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 940 + CSR_READ_1(sc, STE_MULTI_COLLS) 941 + CSR_READ_1(sc, STE_SINGLE_COLLS); 942 943 if (!sc->ste_link) { 944 mii_pollstat(mii); 945 if (mii->mii_media_status & IFM_ACTIVE && 946 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 947 sc->ste_link++; 948 /* 949 * we don't get a call-back on re-init so do it 950 * otherwise we get stuck in the wrong link state 951 */ 952 ste_miibus_statchg(sc->ste_dev); 953 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 954 ste_start_locked(ifp); 955 } 956 } 957 958 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 959 960 return; 961} 962 963 964/* 965 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 966 * IDs against our list and return a device name if we find a match. 967 */ 968static int 969ste_probe(dev) 970 device_t dev; 971{ 972 struct ste_type *t; 973 974 t = ste_devs; 975 976 while(t->ste_name != NULL) { 977 if ((pci_get_vendor(dev) == t->ste_vid) && 978 (pci_get_device(dev) == t->ste_did)) { 979 device_set_desc(dev, t->ste_name); 980 return (BUS_PROBE_DEFAULT); 981 } 982 t++; 983 } 984 985 return(ENXIO); 986} 987 988/* 989 * Attach the interface. Allocate softc structures, do ifmedia 990 * setup and ethernet/BPF attach. 991 */ 992static int 993ste_attach(dev) 994 device_t dev; 995{ 996 struct ste_softc *sc; 997 struct ifnet *ifp; 998 int error = 0, rid; 999 u_char eaddr[6]; 1000 1001 sc = device_get_softc(dev); 1002 sc->ste_dev = dev; 1003 1004 /* 1005 * Only use one PHY since this chip reports multiple 1006 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1007 * it is at 0 & 1. It is rev 0x12. 1008 */ 1009 if (pci_get_vendor(dev) == DL_VENDORID && 1010 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1011 pci_get_revid(dev) == 0x12 ) 1012 sc->ste_one_phy = 1; 1013 1014 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1015 MTX_DEF); 1016 /* 1017 * Map control/status registers. 1018 */ 1019 pci_enable_busmaster(dev); 1020 1021 rid = STE_RID; 1022 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1023 1024 if (sc->ste_res == NULL) { 1025 device_printf(dev, "couldn't map ports/memory\n"); 1026 error = ENXIO; 1027 goto fail; 1028 } 1029 1030 sc->ste_btag = rman_get_bustag(sc->ste_res); 1031 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1032 1033 /* Allocate interrupt */ 1034 rid = 0; 1035 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1036 RF_SHAREABLE | RF_ACTIVE); 1037 1038 if (sc->ste_irq == NULL) { 1039 device_printf(dev, "couldn't map interrupt\n"); 1040 error = ENXIO; 1041 goto fail; 1042 } 1043 1044 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0); 1045 1046 /* Reset the adapter. */ 1047 ste_reset(sc); 1048 1049 /* 1050 * Get station address from the EEPROM. 1051 */ 1052 if (ste_read_eeprom(sc, eaddr, 1053 STE_EEADDR_NODE0, 3, 0)) { 1054 device_printf(dev, "failed to read station address\n"); 1055 error = ENXIO;; 1056 goto fail; 1057 } 1058 1059 /* Allocate the descriptor queues. */ 1060 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1061 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1062 1063 if (sc->ste_ldata == NULL) { 1064 device_printf(dev, "no memory for list buffers!\n"); 1065 error = ENXIO; 1066 goto fail; 1067 } 1068 1069 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1070 1071 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1072 if (ifp == NULL) { 1073 device_printf(dev, "can not if_alloc()\n"); 1074 error = ENOSPC; 1075 goto fail; 1076 } 1077 1078 /* Do MII setup. */ 1079 if (mii_phy_probe(dev, &sc->ste_miibus, 1080 ste_ifmedia_upd, ste_ifmedia_sts)) { 1081 device_printf(dev, "MII without any phy!\n"); 1082 error = ENXIO; 1083 goto fail; 1084 } 1085 1086 ifp->if_softc = sc; 1087 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1088 ifp->if_mtu = ETHERMTU; 1089 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1090 ifp->if_ioctl = ste_ioctl; 1091 ifp->if_start = ste_start; 1092 ifp->if_watchdog = ste_watchdog; 1093 ifp->if_init = ste_init; 1094 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1095 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1096 IFQ_SET_READY(&ifp->if_snd); 1097 1098 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1099 1100 /* 1101 * Call MI attach routine. 1102 */ 1103 ether_ifattach(ifp, eaddr); 1104 1105 /* 1106 * Tell the upper layer(s) we support long frames. 1107 */ 1108 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1109 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1110 ifp->if_capenable = ifp->if_capabilities; 1111#ifdef DEVICE_POLLING 1112 ifp->if_capabilities |= IFCAP_POLLING; 1113#endif 1114 1115 /* Hook interrupt last to avoid having to lock softc */ 1116 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1117 NULL, ste_intr, sc, &sc->ste_intrhand); 1118 1119 if (error) { 1120 device_printf(dev, "couldn't set up irq\n"); 1121 ether_ifdetach(ifp); 1122 goto fail; 1123 } 1124 1125fail: 1126 if (error) 1127 ste_detach(dev); 1128 1129 return(error); 1130} 1131 1132/* 1133 * Shutdown hardware and free up resources. This can be called any 1134 * time after the mutex has been initialized. It is called in both 1135 * the error case in attach and the normal detach case so it needs 1136 * to be careful about only freeing resources that have actually been 1137 * allocated. 1138 */ 1139static int 1140ste_detach(dev) 1141 device_t dev; 1142{ 1143 struct ste_softc *sc; 1144 struct ifnet *ifp; 1145 1146 sc = device_get_softc(dev); 1147 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1148 ifp = sc->ste_ifp; 1149 1150#ifdef DEVICE_POLLING 1151 if (ifp->if_capenable & IFCAP_POLLING) 1152 ether_poll_deregister(ifp); 1153#endif 1154 1155 /* These should only be active if attach succeeded */ 1156 if (device_is_attached(dev)) { 1157 STE_LOCK(sc); 1158 ste_stop(sc); 1159 STE_UNLOCK(sc); 1160 callout_drain(&sc->ste_stat_callout); 1161 ether_ifdetach(ifp); 1162 } 1163 if (sc->ste_miibus) 1164 device_delete_child(dev, sc->ste_miibus); 1165 bus_generic_detach(dev); 1166 1167 if (sc->ste_intrhand) 1168 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1169 if (sc->ste_irq) 1170 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1171 if (sc->ste_res) 1172 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1173 1174 if (ifp) 1175 if_free(ifp); 1176 1177 if (sc->ste_ldata) { 1178 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1179 M_DEVBUF); 1180 } 1181 1182 mtx_destroy(&sc->ste_mtx); 1183 1184 return(0); 1185} 1186 1187static int 1188ste_newbuf(sc, c, m) 1189 struct ste_softc *sc; 1190 struct ste_chain_onefrag *c; 1191 struct mbuf *m; 1192{ 1193 struct mbuf *m_new = NULL; 1194 1195 if (m == NULL) { 1196 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1197 if (m_new == NULL) 1198 return(ENOBUFS); 1199 MCLGET(m_new, M_DONTWAIT); 1200 if (!(m_new->m_flags & M_EXT)) { 1201 m_freem(m_new); 1202 return(ENOBUFS); 1203 } 1204 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1205 } else { 1206 m_new = m; 1207 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1208 m_new->m_data = m_new->m_ext.ext_buf; 1209 } 1210 1211 m_adj(m_new, ETHER_ALIGN); 1212 1213 c->ste_mbuf = m_new; 1214 c->ste_ptr->ste_status = 0; 1215 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1216 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1217 1218 return(0); 1219} 1220 1221static int 1222ste_init_rx_list(sc) 1223 struct ste_softc *sc; 1224{ 1225 struct ste_chain_data *cd; 1226 struct ste_list_data *ld; 1227 int i; 1228 1229 cd = &sc->ste_cdata; 1230 ld = sc->ste_ldata; 1231 1232 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1233 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1234 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1235 return(ENOBUFS); 1236 if (i == (STE_RX_LIST_CNT - 1)) { 1237 cd->ste_rx_chain[i].ste_next = 1238 &cd->ste_rx_chain[0]; 1239 ld->ste_rx_list[i].ste_next = 1240 vtophys(&ld->ste_rx_list[0]); 1241 } else { 1242 cd->ste_rx_chain[i].ste_next = 1243 &cd->ste_rx_chain[i + 1]; 1244 ld->ste_rx_list[i].ste_next = 1245 vtophys(&ld->ste_rx_list[i + 1]); 1246 } 1247 ld->ste_rx_list[i].ste_status = 0; 1248 } 1249 1250 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1251 1252 return(0); 1253} 1254 1255static void 1256ste_init_tx_list(sc) 1257 struct ste_softc *sc; 1258{ 1259 struct ste_chain_data *cd; 1260 struct ste_list_data *ld; 1261 int i; 1262 1263 cd = &sc->ste_cdata; 1264 ld = sc->ste_ldata; 1265 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1266 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1267 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1268 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1269 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1270 if (i == (STE_TX_LIST_CNT - 1)) 1271 cd->ste_tx_chain[i].ste_next = 1272 &cd->ste_tx_chain[0]; 1273 else 1274 cd->ste_tx_chain[i].ste_next = 1275 &cd->ste_tx_chain[i + 1]; 1276 } 1277 1278 cd->ste_tx_prod = 0; 1279 cd->ste_tx_cons = 0; 1280 1281 return; 1282} 1283 1284static void 1285ste_init(xsc) 1286 void *xsc; 1287{ 1288 struct ste_softc *sc; 1289 1290 sc = xsc; 1291 STE_LOCK(sc); 1292 ste_init_locked(sc); 1293 STE_UNLOCK(sc); 1294} 1295 1296static void 1297ste_init_locked(sc) 1298 struct ste_softc *sc; 1299{ 1300 int i; 1301 struct ifnet *ifp; 1302 1303 STE_LOCK_ASSERT(sc); 1304 ifp = sc->ste_ifp; 1305 1306 ste_stop(sc); 1307 1308 /* Init our MAC address */ 1309 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1310 CSR_WRITE_2(sc, STE_PAR0 + i, 1311 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1312 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1313 } 1314 1315 /* Init RX list */ 1316 if (ste_init_rx_list(sc) == ENOBUFS) { 1317 device_printf(sc->ste_dev, 1318 "initialization failed: no memory for RX buffers\n"); 1319 ste_stop(sc); 1320 return; 1321 } 1322 1323 /* Set RX polling interval */ 1324 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1325 1326 /* Init TX descriptors */ 1327 ste_init_tx_list(sc); 1328 1329 /* Set the TX freethresh value */ 1330 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1331 1332 /* Set the TX start threshold for best performance. */ 1333 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1334 1335 /* Set the TX reclaim threshold. */ 1336 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1337 1338 /* Set up the RX filter. */ 1339 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1340 1341 /* If we want promiscuous mode, set the allframes bit. */ 1342 if (ifp->if_flags & IFF_PROMISC) { 1343 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1344 } else { 1345 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1346 } 1347 1348 /* Set capture broadcast bit to accept broadcast frames. */ 1349 if (ifp->if_flags & IFF_BROADCAST) { 1350 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1351 } else { 1352 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1353 } 1354 1355 ste_setmulti(sc); 1356 1357 /* Load the address of the RX list. */ 1358 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1359 ste_wait(sc); 1360 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1361 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1362 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1363 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1364 1365 /* Set TX polling interval (defer until we TX first packet */ 1366 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1367 1368 /* Load address of the TX list */ 1369 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1370 ste_wait(sc); 1371 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1372 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1373 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1374 ste_wait(sc); 1375 sc->ste_tx_prev = NULL; 1376 1377 /* Enable receiver and transmitter */ 1378 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1379 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1380 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1381 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1382 1383 /* Enable stats counters. */ 1384 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1385 1386 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1387#ifdef DEVICE_POLLING 1388 /* Disable interrupts if we are polling. */ 1389 if (ifp->if_capenable & IFCAP_POLLING) 1390 CSR_WRITE_2(sc, STE_IMR, 0); 1391 else 1392#endif 1393 /* Enable interrupts. */ 1394 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1395 1396 /* Accept VLAN length packets */ 1397 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1398 1399 ste_ifmedia_upd_locked(ifp); 1400 1401 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1402 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1403 1404 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 1405 1406 return; 1407} 1408 1409static void 1410ste_stop(sc) 1411 struct ste_softc *sc; 1412{ 1413 int i; 1414 struct ifnet *ifp; 1415 1416 STE_LOCK_ASSERT(sc); 1417 ifp = sc->ste_ifp; 1418 1419 callout_stop(&sc->ste_stat_callout); 1420 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1421 1422 CSR_WRITE_2(sc, STE_IMR, 0); 1423 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1424 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1425 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1426 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1427 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1428 ste_wait(sc); 1429 /* 1430 * Try really hard to stop the RX engine or under heavy RX 1431 * data chip will write into de-allocated memory. 1432 */ 1433 ste_reset(sc); 1434 1435 sc->ste_link = 0; 1436 1437 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1438 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1439 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1440 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1441 } 1442 } 1443 1444 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1445 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1446 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1447 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1448 } 1449 } 1450 1451 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1452 1453 return; 1454} 1455 1456static void 1457ste_reset(sc) 1458 struct ste_softc *sc; 1459{ 1460 int i; 1461 1462 STE_SETBIT4(sc, STE_ASICCTL, 1463 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1464 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1465 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1466 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1467 STE_ASICCTL_EXTRESET_RESET); 1468 1469 DELAY(100000); 1470 1471 for (i = 0; i < STE_TIMEOUT; i++) { 1472 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1473 break; 1474 } 1475 1476 if (i == STE_TIMEOUT) 1477 device_printf(sc->ste_dev, "global reset never completed\n"); 1478 1479 return; 1480} 1481 1482static int 1483ste_ioctl(ifp, command, data) 1484 struct ifnet *ifp; 1485 u_long command; 1486 caddr_t data; 1487{ 1488 struct ste_softc *sc; 1489 struct ifreq *ifr; 1490 struct mii_data *mii; 1491 int error = 0; 1492 1493 sc = ifp->if_softc; 1494 ifr = (struct ifreq *)data; 1495 1496 switch(command) { 1497 case SIOCSIFFLAGS: 1498 STE_LOCK(sc); 1499 if (ifp->if_flags & IFF_UP) { 1500 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1501 ifp->if_flags & IFF_PROMISC && 1502 !(sc->ste_if_flags & IFF_PROMISC)) { 1503 STE_SETBIT1(sc, STE_RX_MODE, 1504 STE_RXMODE_PROMISC); 1505 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1506 !(ifp->if_flags & IFF_PROMISC) && 1507 sc->ste_if_flags & IFF_PROMISC) { 1508 STE_CLRBIT1(sc, STE_RX_MODE, 1509 STE_RXMODE_PROMISC); 1510 } 1511 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1512 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1513 ste_setmulti(sc); 1514 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1515 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1516 ste_init_locked(sc); 1517 } 1518 } else { 1519 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1520 ste_stop(sc); 1521 } 1522 sc->ste_if_flags = ifp->if_flags; 1523 STE_UNLOCK(sc); 1524 error = 0; 1525 break; 1526 case SIOCADDMULTI: 1527 case SIOCDELMULTI: 1528 STE_LOCK(sc); 1529 ste_setmulti(sc); 1530 STE_UNLOCK(sc); 1531 error = 0; 1532 break; 1533 case SIOCGIFMEDIA: 1534 case SIOCSIFMEDIA: 1535 mii = device_get_softc(sc->ste_miibus); 1536 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1537 break; 1538 case SIOCSIFCAP: 1539#ifdef DEVICE_POLLING 1540 if (ifr->ifr_reqcap & IFCAP_POLLING && 1541 !(ifp->if_capenable & IFCAP_POLLING)) { 1542 error = ether_poll_register(ste_poll, ifp); 1543 if (error) 1544 return(error); 1545 STE_LOCK(sc); 1546 /* Disable interrupts */ 1547 CSR_WRITE_2(sc, STE_IMR, 0); 1548 ifp->if_capenable |= IFCAP_POLLING; 1549 STE_UNLOCK(sc); 1550 return (error); 1551 1552 } 1553 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1554 ifp->if_capenable & IFCAP_POLLING) { 1555 error = ether_poll_deregister(ifp); 1556 /* Enable interrupts. */ 1557 STE_LOCK(sc); 1558 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1559 ifp->if_capenable &= ~IFCAP_POLLING; 1560 STE_UNLOCK(sc); 1561 return (error); 1562 } 1563#endif /* DEVICE_POLLING */ 1564 break; 1565 default: 1566 error = ether_ioctl(ifp, command, data); 1567 break; 1568 } 1569 1570 return(error); 1571} 1572 1573static int 1574ste_encap(sc, c, m_head) 1575 struct ste_softc *sc; 1576 struct ste_chain *c; 1577 struct mbuf *m_head; 1578{ 1579 int frag = 0; 1580 struct ste_frag *f = NULL; 1581 struct mbuf *m; 1582 struct ste_desc *d; 1583 1584 d = c->ste_ptr; 1585 d->ste_ctl = 0; 1586 1587encap_retry: 1588 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1589 if (m->m_len != 0) { 1590 if (frag == STE_MAXFRAGS) 1591 break; 1592 f = &d->ste_frags[frag]; 1593 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1594 f->ste_len = m->m_len; 1595 frag++; 1596 } 1597 } 1598 1599 if (m != NULL) { 1600 struct mbuf *mn; 1601 1602 /* 1603 * We ran out of segments. We have to recopy this 1604 * mbuf chain first. Bail out if we can't get the 1605 * new buffers. 1606 */ 1607 mn = m_defrag(m_head, M_DONTWAIT); 1608 if (mn == NULL) { 1609 m_freem(m_head); 1610 return ENOMEM; 1611 } 1612 m_head = mn; 1613 goto encap_retry; 1614 } 1615 1616 c->ste_mbuf = m_head; 1617 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1618 d->ste_ctl = 1; 1619 1620 return(0); 1621} 1622 1623static void 1624ste_start(ifp) 1625 struct ifnet *ifp; 1626{ 1627 struct ste_softc *sc; 1628 1629 sc = ifp->if_softc; 1630 STE_LOCK(sc); 1631 ste_start_locked(ifp); 1632 STE_UNLOCK(sc); 1633} 1634 1635static void 1636ste_start_locked(ifp) 1637 struct ifnet *ifp; 1638{ 1639 struct ste_softc *sc; 1640 struct mbuf *m_head = NULL; 1641 struct ste_chain *cur_tx; 1642 int idx; 1643 1644 sc = ifp->if_softc; 1645 STE_LOCK_ASSERT(sc); 1646 1647 if (!sc->ste_link) 1648 return; 1649 1650 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1651 return; 1652 1653 idx = sc->ste_cdata.ste_tx_prod; 1654 1655 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1656 /* 1657 * We cannot re-use the last (free) descriptor; 1658 * the chip may not have read its ste_next yet. 1659 */ 1660 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1661 sc->ste_cdata.ste_tx_cons) { 1662 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1663 break; 1664 } 1665 1666 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1667 if (m_head == NULL) 1668 break; 1669 1670 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1671 1672 if (ste_encap(sc, cur_tx, m_head) != 0) 1673 break; 1674 1675 cur_tx->ste_ptr->ste_next = 0; 1676 1677 if (sc->ste_tx_prev == NULL) { 1678 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1679 /* Load address of the TX list */ 1680 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1681 ste_wait(sc); 1682 1683 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1684 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1685 1686 /* Set TX polling interval to start TX engine */ 1687 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1688 1689 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1690 ste_wait(sc); 1691 }else{ 1692 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1693 sc->ste_tx_prev->ste_ptr->ste_next 1694 = cur_tx->ste_phys; 1695 } 1696 1697 sc->ste_tx_prev = cur_tx; 1698 1699 /* 1700 * If there's a BPF listener, bounce a copy of this frame 1701 * to him. 1702 */ 1703 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1704 1705 STE_INC(idx, STE_TX_LIST_CNT); 1706 ifp->if_timer = 5; 1707 } 1708 sc->ste_cdata.ste_tx_prod = idx; 1709 1710 return; 1711} 1712 1713static void 1714ste_watchdog(ifp) 1715 struct ifnet *ifp; 1716{ 1717 struct ste_softc *sc; 1718 1719 sc = ifp->if_softc; 1720 STE_LOCK(sc); 1721 1722 ifp->if_oerrors++; 1723 if_printf(ifp, "watchdog timeout\n"); 1724 1725 ste_txeoc(sc); 1726 ste_txeof(sc); 1727 ste_rxeoc(sc); 1728 ste_rxeof(sc); 1729 ste_reset(sc); 1730 ste_init_locked(sc); 1731 1732 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1733 ste_start_locked(ifp); 1734 STE_UNLOCK(sc); 1735 1736 return; 1737} 1738 1739static int 1740ste_shutdown(dev) 1741 device_t dev; 1742{ 1743 struct ste_softc *sc; 1744 1745 sc = device_get_softc(dev); 1746 1747 STE_LOCK(sc); 1748 ste_stop(sc); 1749 STE_UNLOCK(sc); 1750 1751 return (0); 1752} 1753