if_ste.c revision 150789
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 150789 2005-10-01 18:56:19Z glebius $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_arp.h> 48#include <net/ethernet.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52#include <net/if_vlan_var.h> 53 54#include <net/bpf.h> 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69/* "controller miibus0" required. See GENERIC if you get errors here. */ 70#include "miibus_if.h" 71 72#define STE_USEIOSPACE 73 74#include <pci/if_stereg.h> 75 76MODULE_DEPEND(ste, pci, 1, 1, 1); 77MODULE_DEPEND(ste, ether, 1, 1, 1); 78MODULE_DEPEND(ste, miibus, 1, 1, 1); 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe(device_t); 90static int ste_attach(device_t); 91static int ste_detach(device_t); 92static void ste_init(void *); 93static void ste_init_locked(struct ste_softc *); 94static void ste_intr(void *); 95static void ste_rxeoc(struct ste_softc *); 96static void ste_rxeof(struct ste_softc *); 97static void ste_txeoc(struct ste_softc *); 98static void ste_txeof(struct ste_softc *); 99static void ste_stats_update(void *); 100static void ste_stop(struct ste_softc *); 101static void ste_reset(struct ste_softc *); 102static int ste_ioctl(struct ifnet *, u_long, caddr_t); 103static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 104static void ste_start(struct ifnet *); 105static void ste_start_locked(struct ifnet *); 106static void ste_watchdog(struct ifnet *); 107static void ste_shutdown(device_t); 108static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd(struct ifnet *); 111static void ste_ifmedia_upd_locked(struct ifnet *); 112static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113 114static void ste_mii_sync(struct ste_softc *); 115static void ste_mii_send(struct ste_softc *, u_int32_t, int); 116static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 117static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 118static int ste_miibus_readreg(device_t, int, int); 119static int ste_miibus_writereg(device_t, int, int, int); 120static void ste_miibus_statchg(device_t); 121 122static int ste_eeprom_wait(struct ste_softc *); 123static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 124static void ste_wait(struct ste_softc *); 125static void ste_setmulti(struct ste_softc *); 126static int ste_init_rx_list(struct ste_softc *); 127static void ste_init_tx_list(struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 168 169static int ste_rxsyncs; 170SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 171 172#define STE_SETBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 174 175#define STE_CLRBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 177 178#define STE_SETBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 180 181#define STE_CLRBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 183 184#define STE_SETBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186 187#define STE_CLRBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 189 190 191#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 192#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 193 194/* 195 * Sync the PHYs by setting data bit and strobing the clock 32 times. 196 */ 197static void 198ste_mii_sync(sc) 199 struct ste_softc *sc; 200{ 201 register int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211 212 return; 213} 214 215/* 216 * Clock a series of bits through the MII. 217 */ 218static void 219ste_mii_send(sc, bits, cnt) 220 struct ste_softc *sc; 221 u_int32_t bits; 222 int cnt; 223{ 224 int i; 225 226 MII_CLR(STE_PHYCTL_MCLK); 227 228 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 229 if (bits & i) { 230 MII_SET(STE_PHYCTL_MDATA); 231 } else { 232 MII_CLR(STE_PHYCTL_MDATA); 233 } 234 DELAY(1); 235 MII_CLR(STE_PHYCTL_MCLK); 236 DELAY(1); 237 MII_SET(STE_PHYCTL_MCLK); 238 } 239} 240 241/* 242 * Read an PHY register through the MII. 243 */ 244static int 245ste_mii_readreg(sc, frame) 246 struct ste_softc *sc; 247 struct ste_mii_frame *frame; 248 249{ 250 int i, ack; 251 252 /* 253 * Set up frame for RX. 254 */ 255 frame->mii_stdelim = STE_MII_STARTDELIM; 256 frame->mii_opcode = STE_MII_READOP; 257 frame->mii_turnaround = 0; 258 frame->mii_data = 0; 259 260 CSR_WRITE_2(sc, STE_PHYCTL, 0); 261 /* 262 * Turn on data xmit. 263 */ 264 MII_SET(STE_PHYCTL_MDIR); 265 266 ste_mii_sync(sc); 267 268 /* 269 * Send command/address info. 270 */ 271 ste_mii_send(sc, frame->mii_stdelim, 2); 272 ste_mii_send(sc, frame->mii_opcode, 2); 273 ste_mii_send(sc, frame->mii_phyaddr, 5); 274 ste_mii_send(sc, frame->mii_regaddr, 5); 275 276 /* Turn off xmit. */ 277 MII_CLR(STE_PHYCTL_MDIR); 278 279 /* Idle bit */ 280 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 285 /* Check for ack */ 286 MII_CLR(STE_PHYCTL_MCLK); 287 DELAY(1); 288 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 289 MII_SET(STE_PHYCTL_MCLK); 290 DELAY(1); 291 292 /* 293 * Now try reading data bits. If the ack failed, we still 294 * need to clock through 16 cycles to keep the PHY(s) in sync. 295 */ 296 if (ack) { 297 for(i = 0; i < 16; i++) { 298 MII_CLR(STE_PHYCTL_MCLK); 299 DELAY(1); 300 MII_SET(STE_PHYCTL_MCLK); 301 DELAY(1); 302 } 303 goto fail; 304 } 305 306 for (i = 0x8000; i; i >>= 1) { 307 MII_CLR(STE_PHYCTL_MCLK); 308 DELAY(1); 309 if (!ack) { 310 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 311 frame->mii_data |= i; 312 DELAY(1); 313 } 314 MII_SET(STE_PHYCTL_MCLK); 315 DELAY(1); 316 } 317 318fail: 319 320 MII_CLR(STE_PHYCTL_MCLK); 321 DELAY(1); 322 MII_SET(STE_PHYCTL_MCLK); 323 DELAY(1); 324 325 if (ack) 326 return(1); 327 return(0); 328} 329 330/* 331 * Write to a PHY register through the MII. 332 */ 333static int 334ste_mii_writereg(sc, frame) 335 struct ste_softc *sc; 336 struct ste_mii_frame *frame; 337 338{ 339 340 /* 341 * Set up frame for TX. 342 */ 343 344 frame->mii_stdelim = STE_MII_STARTDELIM; 345 frame->mii_opcode = STE_MII_WRITEOP; 346 frame->mii_turnaround = STE_MII_TURNAROUND; 347 348 /* 349 * Turn on data output. 350 */ 351 MII_SET(STE_PHYCTL_MDIR); 352 353 ste_mii_sync(sc); 354 355 ste_mii_send(sc, frame->mii_stdelim, 2); 356 ste_mii_send(sc, frame->mii_opcode, 2); 357 ste_mii_send(sc, frame->mii_phyaddr, 5); 358 ste_mii_send(sc, frame->mii_regaddr, 5); 359 ste_mii_send(sc, frame->mii_turnaround, 2); 360 ste_mii_send(sc, frame->mii_data, 16); 361 362 /* Idle bit. */ 363 MII_SET(STE_PHYCTL_MCLK); 364 DELAY(1); 365 MII_CLR(STE_PHYCTL_MCLK); 366 DELAY(1); 367 368 /* 369 * Turn off xmit. 370 */ 371 MII_CLR(STE_PHYCTL_MDIR); 372 373 return(0); 374} 375 376static int 377ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396} 397 398static int 399ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402{ 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416} 417 418static void 419ste_miibus_statchg(dev) 420 device_t dev; 421{ 422 struct ste_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 435 return; 436} 437 438static int 439ste_ifmedia_upd(ifp) 440 struct ifnet *ifp; 441{ 442 struct ste_softc *sc; 443 444 sc = ifp->if_softc; 445 STE_LOCK(sc); 446 ste_ifmedia_upd_locked(ifp); 447 STE_UNLOCK(sc); 448 449 return(0); 450} 451 452static void 453ste_ifmedia_upd_locked(ifp) 454 struct ifnet *ifp; 455{ 456 struct ste_softc *sc; 457 struct mii_data *mii; 458 459 sc = ifp->if_softc; 460 STE_LOCK_ASSERT(sc); 461 mii = device_get_softc(sc->ste_miibus); 462 sc->ste_link = 0; 463 if (mii->mii_instance) { 464 struct mii_softc *miisc; 465 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 466 mii_phy_reset(miisc); 467 } 468 mii_mediachg(mii); 469} 470 471static void 472ste_ifmedia_sts(ifp, ifmr) 473 struct ifnet *ifp; 474 struct ifmediareq *ifmr; 475{ 476 struct ste_softc *sc; 477 struct mii_data *mii; 478 479 sc = ifp->if_softc; 480 mii = device_get_softc(sc->ste_miibus); 481 482 STE_LOCK(sc); 483 mii_pollstat(mii); 484 ifmr->ifm_active = mii->mii_media_active; 485 ifmr->ifm_status = mii->mii_media_status; 486 STE_UNLOCK(sc); 487 488 return; 489} 490 491static void 492ste_wait(sc) 493 struct ste_softc *sc; 494{ 495 register int i; 496 497 for (i = 0; i < STE_TIMEOUT; i++) { 498 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 499 break; 500 } 501 502 if (i == STE_TIMEOUT) 503 if_printf(sc->ste_ifp, "command never completed!\n"); 504 505 return; 506} 507 508/* 509 * The EEPROM is slow: give it time to come ready after issuing 510 * it a command. 511 */ 512static int 513ste_eeprom_wait(sc) 514 struct ste_softc *sc; 515{ 516 int i; 517 518 DELAY(1000); 519 520 for (i = 0; i < 100; i++) { 521 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 522 DELAY(1000); 523 else 524 break; 525 } 526 527 if (i == 100) { 528 if_printf(sc->ste_ifp, "eeprom failed to come ready\n"); 529 return(1); 530 } 531 532 return(0); 533} 534 535/* 536 * Read a sequence of words from the EEPROM. Note that ethernet address 537 * data is stored in the EEPROM in network byte order. 538 */ 539static int 540ste_read_eeprom(sc, dest, off, cnt, swap) 541 struct ste_softc *sc; 542 caddr_t dest; 543 int off; 544 int cnt; 545 int swap; 546{ 547 int err = 0, i; 548 u_int16_t word = 0, *ptr; 549 550 if (ste_eeprom_wait(sc)) 551 return(1); 552 553 for (i = 0; i < cnt; i++) { 554 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 555 err = ste_eeprom_wait(sc); 556 if (err) 557 break; 558 word = CSR_READ_2(sc, STE_EEPROM_DATA); 559 ptr = (u_int16_t *)(dest + (i * 2)); 560 if (swap) 561 *ptr = ntohs(word); 562 else 563 *ptr = word; 564 } 565 566 return(err ? 1 : 0); 567} 568 569static void 570ste_setmulti(sc) 571 struct ste_softc *sc; 572{ 573 struct ifnet *ifp; 574 int h = 0; 575 u_int32_t hashes[2] = { 0, 0 }; 576 struct ifmultiaddr *ifma; 577 578 ifp = sc->ste_ifp; 579 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 580 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 581 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 582 return; 583 } 584 585 /* first, zot all the existing hash bits */ 586 CSR_WRITE_2(sc, STE_MAR0, 0); 587 CSR_WRITE_2(sc, STE_MAR1, 0); 588 CSR_WRITE_2(sc, STE_MAR2, 0); 589 CSR_WRITE_2(sc, STE_MAR3, 0); 590 591 /* now program new ones */ 592 IF_ADDR_LOCK(ifp); 593 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 594 if (ifma->ifma_addr->sa_family != AF_LINK) 595 continue; 596 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 597 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 598 if (h < 32) 599 hashes[0] |= (1 << h); 600 else 601 hashes[1] |= (1 << (h - 32)); 602 } 603 IF_ADDR_UNLOCK(ifp); 604 605 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 606 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 607 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 608 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 609 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 610 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 611 612 return; 613} 614 615#ifdef DEVICE_POLLING 616static poll_handler_t ste_poll, ste_poll_locked; 617 618static void 619ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 620{ 621 struct ste_softc *sc = ifp->if_softc; 622 623 STE_LOCK(sc); 624 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 625 ste_poll_locked(ifp, cmd, count); 626 STE_UNLOCK(sc); 627} 628 629static void 630ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 631{ 632 struct ste_softc *sc = ifp->if_softc; 633 634 STE_LOCK_ASSERT(sc); 635 636 sc->rxcycles = count; 637 if (cmd == POLL_AND_CHECK_STATUS) 638 ste_rxeoc(sc); 639 ste_rxeof(sc); 640 ste_txeof(sc); 641 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 642 ste_start_locked(ifp); 643 644 if (cmd == POLL_AND_CHECK_STATUS) { 645 u_int16_t status; 646 647 status = CSR_READ_2(sc, STE_ISR_ACK); 648 649 if (status & STE_ISR_TX_DONE) 650 ste_txeoc(sc); 651 652 if (status & STE_ISR_STATS_OFLOW) { 653 callout_stop(&sc->ste_stat_callout); 654 ste_stats_update(sc); 655 } 656 657 if (status & STE_ISR_LINKEVENT) 658 mii_pollstat(device_get_softc(sc->ste_miibus)); 659 660 if (status & STE_ISR_HOSTERR) { 661 ste_reset(sc); 662 ste_init_locked(sc); 663 } 664 } 665} 666#endif /* DEVICE_POLLING */ 667 668static void 669ste_intr(xsc) 670 void *xsc; 671{ 672 struct ste_softc *sc; 673 struct ifnet *ifp; 674 u_int16_t status; 675 676 sc = xsc; 677 STE_LOCK(sc); 678 ifp = sc->ste_ifp; 679 680#ifdef DEVICE_POLLING 681 if (ifp->if_capenable & IFCAP_POLLING) { 682 STE_UNLOCK(sc); 683 return; 684 } 685#endif 686 687 /* See if this is really our interrupt. */ 688 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 689 STE_UNLOCK(sc); 690 return; 691 } 692 693 for (;;) { 694 status = CSR_READ_2(sc, STE_ISR_ACK); 695 696 if (!(status & STE_INTRS)) 697 break; 698 699 if (status & STE_ISR_RX_DMADONE) { 700 ste_rxeoc(sc); 701 ste_rxeof(sc); 702 } 703 704 if (status & STE_ISR_TX_DMADONE) 705 ste_txeof(sc); 706 707 if (status & STE_ISR_TX_DONE) 708 ste_txeoc(sc); 709 710 if (status & STE_ISR_STATS_OFLOW) { 711 callout_stop(&sc->ste_stat_callout); 712 ste_stats_update(sc); 713 } 714 715 if (status & STE_ISR_LINKEVENT) 716 mii_pollstat(device_get_softc(sc->ste_miibus)); 717 718 719 if (status & STE_ISR_HOSTERR) { 720 ste_reset(sc); 721 ste_init_locked(sc); 722 } 723 } 724 725 /* Re-enable interrupts */ 726 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 727 728 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 729 ste_start_locked(ifp); 730 731 STE_UNLOCK(sc); 732 733 return; 734} 735 736static void 737ste_rxeoc(struct ste_softc *sc) 738{ 739 struct ste_chain_onefrag *cur_rx; 740 741 STE_LOCK_ASSERT(sc); 742 743 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 744 cur_rx = sc->ste_cdata.ste_rx_head; 745 do { 746 cur_rx = cur_rx->ste_next; 747 /* If the ring is empty, just return. */ 748 if (cur_rx == sc->ste_cdata.ste_rx_head) 749 return; 750 } while (cur_rx->ste_ptr->ste_status == 0); 751 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 752 /* We've fallen behind the chip: catch it. */ 753 sc->ste_cdata.ste_rx_head = cur_rx; 754 ++ste_rxsyncs; 755 } 756 } 757} 758 759/* 760 * A frame has been uploaded: pass the resulting mbuf chain up to 761 * the higher level protocols. 762 */ 763static void 764ste_rxeof(sc) 765 struct ste_softc *sc; 766{ 767 struct mbuf *m; 768 struct ifnet *ifp; 769 struct ste_chain_onefrag *cur_rx; 770 int total_len = 0, count=0; 771 u_int32_t rxstat; 772 773 STE_LOCK_ASSERT(sc); 774 775 ifp = sc->ste_ifp; 776 777 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 778 & STE_RXSTAT_DMADONE) { 779#ifdef DEVICE_POLLING 780 if (ifp->if_capenable & IFCAP_POLLING) { 781 if (sc->rxcycles <= 0) 782 break; 783 sc->rxcycles--; 784 } 785#endif 786 if ((STE_RX_LIST_CNT - count) < 3) { 787 break; 788 } 789 790 cur_rx = sc->ste_cdata.ste_rx_head; 791 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 792 793 /* 794 * If an error occurs, update stats, clear the 795 * status word and leave the mbuf cluster in place: 796 * it should simply get re-used next time this descriptor 797 * comes up in the ring. 798 */ 799 if (rxstat & STE_RXSTAT_FRAME_ERR) { 800 ifp->if_ierrors++; 801 cur_rx->ste_ptr->ste_status = 0; 802 continue; 803 } 804 805 /* 806 * If there error bit was not set, the upload complete 807 * bit should be set which means we have a valid packet. 808 * If not, something truly strange has happened. 809 */ 810 if (!(rxstat & STE_RXSTAT_DMADONE)) { 811 if_printf(ifp, 812 "bad receive status -- packet dropped\n"); 813 ifp->if_ierrors++; 814 cur_rx->ste_ptr->ste_status = 0; 815 continue; 816 } 817 818 /* No errors; receive the packet. */ 819 m = cur_rx->ste_mbuf; 820 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 821 822 /* 823 * Try to conjure up a new mbuf cluster. If that 824 * fails, it means we have an out of memory condition and 825 * should leave the buffer in place and continue. This will 826 * result in a lost packet, but there's little else we 827 * can do in this situation. 828 */ 829 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 830 ifp->if_ierrors++; 831 cur_rx->ste_ptr->ste_status = 0; 832 continue; 833 } 834 835 m->m_pkthdr.rcvif = ifp; 836 m->m_pkthdr.len = m->m_len = total_len; 837 838 ifp->if_ipackets++; 839 STE_UNLOCK(sc); 840 (*ifp->if_input)(ifp, m); 841 STE_LOCK(sc); 842 843 cur_rx->ste_ptr->ste_status = 0; 844 count++; 845 } 846 847 return; 848} 849 850static void 851ste_txeoc(sc) 852 struct ste_softc *sc; 853{ 854 u_int8_t txstat; 855 struct ifnet *ifp; 856 857 ifp = sc->ste_ifp; 858 859 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 860 STE_TXSTATUS_TXDONE) { 861 if (txstat & STE_TXSTATUS_UNDERRUN || 862 txstat & STE_TXSTATUS_EXCESSCOLLS || 863 txstat & STE_TXSTATUS_RECLAIMERR) { 864 ifp->if_oerrors++; 865 if_printf(ifp, "transmission error: %x\n", txstat); 866 867 ste_reset(sc); 868 ste_init_locked(sc); 869 870 if (txstat & STE_TXSTATUS_UNDERRUN && 871 sc->ste_tx_thresh < STE_PACKET_SIZE) { 872 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 873 if_printf(ifp, "tx underrun, increasing tx" 874 " start threshold to %d bytes\n", 875 sc->ste_tx_thresh); 876 } 877 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 878 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 879 (STE_PACKET_SIZE >> 4)); 880 } 881 ste_init_locked(sc); 882 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 883 } 884 885 return; 886} 887 888static void 889ste_txeof(sc) 890 struct ste_softc *sc; 891{ 892 struct ste_chain *cur_tx; 893 struct ifnet *ifp; 894 int idx; 895 896 ifp = sc->ste_ifp; 897 898 idx = sc->ste_cdata.ste_tx_cons; 899 while(idx != sc->ste_cdata.ste_tx_prod) { 900 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 901 902 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 903 break; 904 905 m_freem(cur_tx->ste_mbuf); 906 cur_tx->ste_mbuf = NULL; 907 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 908 ifp->if_opackets++; 909 910 STE_INC(idx, STE_TX_LIST_CNT); 911 } 912 913 sc->ste_cdata.ste_tx_cons = idx; 914 if (idx == sc->ste_cdata.ste_tx_prod) 915 ifp->if_timer = 0; 916} 917 918static void 919ste_stats_update(xsc) 920 void *xsc; 921{ 922 struct ste_softc *sc; 923 struct ifnet *ifp; 924 struct mii_data *mii; 925 926 sc = xsc; 927 STE_LOCK_ASSERT(sc); 928 929 ifp = sc->ste_ifp; 930 mii = device_get_softc(sc->ste_miibus); 931 932 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 933 + CSR_READ_1(sc, STE_MULTI_COLLS) 934 + CSR_READ_1(sc, STE_SINGLE_COLLS); 935 936 if (!sc->ste_link) { 937 mii_pollstat(mii); 938 if (mii->mii_media_status & IFM_ACTIVE && 939 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 940 sc->ste_link++; 941 /* 942 * we don't get a call-back on re-init so do it 943 * otherwise we get stuck in the wrong link state 944 */ 945 ste_miibus_statchg(sc->ste_dev); 946 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 947 ste_start_locked(ifp); 948 } 949 } 950 951 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 952 953 return; 954} 955 956 957/* 958 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 959 * IDs against our list and return a device name if we find a match. 960 */ 961static int 962ste_probe(dev) 963 device_t dev; 964{ 965 struct ste_type *t; 966 967 t = ste_devs; 968 969 while(t->ste_name != NULL) { 970 if ((pci_get_vendor(dev) == t->ste_vid) && 971 (pci_get_device(dev) == t->ste_did)) { 972 device_set_desc(dev, t->ste_name); 973 return (BUS_PROBE_DEFAULT); 974 } 975 t++; 976 } 977 978 return(ENXIO); 979} 980 981/* 982 * Attach the interface. Allocate softc structures, do ifmedia 983 * setup and ethernet/BPF attach. 984 */ 985static int 986ste_attach(dev) 987 device_t dev; 988{ 989 struct ste_softc *sc; 990 struct ifnet *ifp; 991 int error = 0, rid; 992 u_char eaddr[6]; 993 994 sc = device_get_softc(dev); 995 sc->ste_dev = dev; 996 997 /* 998 * Only use one PHY since this chip reports multiple 999 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1000 * it is at 0 & 1. It is rev 0x12. 1001 */ 1002 if (pci_get_vendor(dev) == DL_VENDORID && 1003 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1004 pci_get_revid(dev) == 0x12 ) 1005 sc->ste_one_phy = 1; 1006 1007 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1008 MTX_DEF); 1009 /* 1010 * Map control/status registers. 1011 */ 1012 pci_enable_busmaster(dev); 1013 1014 rid = STE_RID; 1015 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1016 1017 if (sc->ste_res == NULL) { 1018 device_printf(dev, "couldn't map ports/memory\n"); 1019 error = ENXIO; 1020 goto fail; 1021 } 1022 1023 sc->ste_btag = rman_get_bustag(sc->ste_res); 1024 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1025 1026 /* Allocate interrupt */ 1027 rid = 0; 1028 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1029 RF_SHAREABLE | RF_ACTIVE); 1030 1031 if (sc->ste_irq == NULL) { 1032 device_printf(dev, "couldn't map interrupt\n"); 1033 error = ENXIO; 1034 goto fail; 1035 } 1036 1037 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0); 1038 1039 /* Reset the adapter. */ 1040 ste_reset(sc); 1041 1042 /* 1043 * Get station address from the EEPROM. 1044 */ 1045 if (ste_read_eeprom(sc, eaddr, 1046 STE_EEADDR_NODE0, 3, 0)) { 1047 device_printf(dev, "failed to read station address\n"); 1048 error = ENXIO;; 1049 goto fail; 1050 } 1051 1052 /* Allocate the descriptor queues. */ 1053 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1054 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1055 1056 if (sc->ste_ldata == NULL) { 1057 device_printf(dev, "no memory for list buffers!\n"); 1058 error = ENXIO; 1059 goto fail; 1060 } 1061 1062 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1063 1064 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1065 if (ifp == NULL) { 1066 device_printf(dev, "can not if_alloc()\n"); 1067 error = ENOSPC; 1068 goto fail; 1069 } 1070 1071 /* Do MII setup. */ 1072 if (mii_phy_probe(dev, &sc->ste_miibus, 1073 ste_ifmedia_upd, ste_ifmedia_sts)) { 1074 device_printf(dev, "MII without any phy!\n"); 1075 error = ENXIO; 1076 goto fail; 1077 } 1078 1079 ifp->if_softc = sc; 1080 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1081 ifp->if_mtu = ETHERMTU; 1082 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1083 ifp->if_ioctl = ste_ioctl; 1084 ifp->if_start = ste_start; 1085 ifp->if_watchdog = ste_watchdog; 1086 ifp->if_init = ste_init; 1087 ifp->if_baudrate = 10000000; 1088 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1089 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1090 IFQ_SET_READY(&ifp->if_snd); 1091 1092 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1093 1094 /* 1095 * Call MI attach routine. 1096 */ 1097 ether_ifattach(ifp, eaddr); 1098 1099 /* 1100 * Tell the upper layer(s) we support long frames. 1101 */ 1102 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1103 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1104 ifp->if_capenable = ifp->if_capabilities; 1105#ifdef DEVICE_POLLING 1106 ifp->if_capabilities |= IFCAP_POLLING; 1107#endif 1108 1109 /* Hook interrupt last to avoid having to lock softc */ 1110 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1111 ste_intr, sc, &sc->ste_intrhand); 1112 1113 if (error) { 1114 device_printf(dev, "couldn't set up irq\n"); 1115 ether_ifdetach(ifp); 1116 goto fail; 1117 } 1118 1119fail: 1120 if (error) 1121 ste_detach(dev); 1122 1123 return(error); 1124} 1125 1126/* 1127 * Shutdown hardware and free up resources. This can be called any 1128 * time after the mutex has been initialized. It is called in both 1129 * the error case in attach and the normal detach case so it needs 1130 * to be careful about only freeing resources that have actually been 1131 * allocated. 1132 */ 1133static int 1134ste_detach(dev) 1135 device_t dev; 1136{ 1137 struct ste_softc *sc; 1138 struct ifnet *ifp; 1139 1140 sc = device_get_softc(dev); 1141 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1142 ifp = sc->ste_ifp; 1143 1144#ifdef DEVICE_POLLING 1145 if (ifp->if_capenable & IFCAP_POLLING) 1146 ether_poll_deregister(ifp); 1147#endif 1148 1149 /* These should only be active if attach succeeded */ 1150 if (device_is_attached(dev)) { 1151 STE_LOCK(sc); 1152 ste_stop(sc); 1153 STE_UNLOCK(sc); 1154 callout_drain(&sc->ste_stat_callout); 1155 ether_ifdetach(ifp); 1156 } 1157 if (ifp) 1158 if_free(ifp); 1159 if (sc->ste_miibus) 1160 device_delete_child(dev, sc->ste_miibus); 1161 bus_generic_detach(dev); 1162 1163 if (sc->ste_intrhand) 1164 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1165 if (sc->ste_irq) 1166 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1167 if (sc->ste_res) 1168 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1169 1170 if (sc->ste_ldata) { 1171 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1172 M_DEVBUF); 1173 } 1174 1175 mtx_destroy(&sc->ste_mtx); 1176 1177 return(0); 1178} 1179 1180static int 1181ste_newbuf(sc, c, m) 1182 struct ste_softc *sc; 1183 struct ste_chain_onefrag *c; 1184 struct mbuf *m; 1185{ 1186 struct mbuf *m_new = NULL; 1187 1188 if (m == NULL) { 1189 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1190 if (m_new == NULL) 1191 return(ENOBUFS); 1192 MCLGET(m_new, M_DONTWAIT); 1193 if (!(m_new->m_flags & M_EXT)) { 1194 m_freem(m_new); 1195 return(ENOBUFS); 1196 } 1197 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1198 } else { 1199 m_new = m; 1200 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1201 m_new->m_data = m_new->m_ext.ext_buf; 1202 } 1203 1204 m_adj(m_new, ETHER_ALIGN); 1205 1206 c->ste_mbuf = m_new; 1207 c->ste_ptr->ste_status = 0; 1208 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1209 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1210 1211 return(0); 1212} 1213 1214static int 1215ste_init_rx_list(sc) 1216 struct ste_softc *sc; 1217{ 1218 struct ste_chain_data *cd; 1219 struct ste_list_data *ld; 1220 int i; 1221 1222 cd = &sc->ste_cdata; 1223 ld = sc->ste_ldata; 1224 1225 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1226 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1227 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1228 return(ENOBUFS); 1229 if (i == (STE_RX_LIST_CNT - 1)) { 1230 cd->ste_rx_chain[i].ste_next = 1231 &cd->ste_rx_chain[0]; 1232 ld->ste_rx_list[i].ste_next = 1233 vtophys(&ld->ste_rx_list[0]); 1234 } else { 1235 cd->ste_rx_chain[i].ste_next = 1236 &cd->ste_rx_chain[i + 1]; 1237 ld->ste_rx_list[i].ste_next = 1238 vtophys(&ld->ste_rx_list[i + 1]); 1239 } 1240 ld->ste_rx_list[i].ste_status = 0; 1241 } 1242 1243 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1244 1245 return(0); 1246} 1247 1248static void 1249ste_init_tx_list(sc) 1250 struct ste_softc *sc; 1251{ 1252 struct ste_chain_data *cd; 1253 struct ste_list_data *ld; 1254 int i; 1255 1256 cd = &sc->ste_cdata; 1257 ld = sc->ste_ldata; 1258 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1259 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1260 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1261 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1262 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1263 if (i == (STE_TX_LIST_CNT - 1)) 1264 cd->ste_tx_chain[i].ste_next = 1265 &cd->ste_tx_chain[0]; 1266 else 1267 cd->ste_tx_chain[i].ste_next = 1268 &cd->ste_tx_chain[i + 1]; 1269 } 1270 1271 cd->ste_tx_prod = 0; 1272 cd->ste_tx_cons = 0; 1273 1274 return; 1275} 1276 1277static void 1278ste_init(xsc) 1279 void *xsc; 1280{ 1281 struct ste_softc *sc; 1282 1283 sc = xsc; 1284 STE_LOCK(sc); 1285 ste_init_locked(sc); 1286 STE_UNLOCK(sc); 1287} 1288 1289static void 1290ste_init_locked(sc) 1291 struct ste_softc *sc; 1292{ 1293 int i; 1294 struct ifnet *ifp; 1295 1296 STE_LOCK_ASSERT(sc); 1297 ifp = sc->ste_ifp; 1298 1299 ste_stop(sc); 1300 1301 /* Init our MAC address */ 1302 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1303 CSR_WRITE_1(sc, STE_PAR0 + i, IFP2ENADDR(sc->ste_ifp)[i]); 1304 } 1305 1306 /* Init RX list */ 1307 if (ste_init_rx_list(sc) == ENOBUFS) { 1308 if_printf(ifp, 1309 "initialization failed: no memory for RX buffers\n"); 1310 ste_stop(sc); 1311 return; 1312 } 1313 1314 /* Set RX polling interval */ 1315 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1316 1317 /* Init TX descriptors */ 1318 ste_init_tx_list(sc); 1319 1320 /* Set the TX freethresh value */ 1321 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1322 1323 /* Set the TX start threshold for best performance. */ 1324 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1325 1326 /* Set the TX reclaim threshold. */ 1327 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1328 1329 /* Set up the RX filter. */ 1330 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1331 1332 /* If we want promiscuous mode, set the allframes bit. */ 1333 if (ifp->if_flags & IFF_PROMISC) { 1334 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1335 } else { 1336 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1337 } 1338 1339 /* Set capture broadcast bit to accept broadcast frames. */ 1340 if (ifp->if_flags & IFF_BROADCAST) { 1341 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1342 } else { 1343 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1344 } 1345 1346 ste_setmulti(sc); 1347 1348 /* Load the address of the RX list. */ 1349 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1350 ste_wait(sc); 1351 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1352 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1353 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1354 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1355 1356 /* Set TX polling interval (defer until we TX first packet */ 1357 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1358 1359 /* Load address of the TX list */ 1360 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1361 ste_wait(sc); 1362 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1363 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1364 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1365 ste_wait(sc); 1366 sc->ste_tx_prev = NULL; 1367 1368 /* Enable receiver and transmitter */ 1369 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1370 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1371 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1372 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1373 1374 /* Enable stats counters. */ 1375 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1376 1377 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1378#ifdef DEVICE_POLLING 1379 /* Disable interrupts if we are polling. */ 1380 if (ifp->if_capenable & IFCAP_POLLING) 1381 CSR_WRITE_2(sc, STE_IMR, 0); 1382 else 1383#endif 1384 /* Enable interrupts. */ 1385 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1386 1387 /* Accept VLAN length packets */ 1388 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1389 1390 ste_ifmedia_upd_locked(ifp); 1391 1392 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1393 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1394 1395 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 1396 1397 return; 1398} 1399 1400static void 1401ste_stop(sc) 1402 struct ste_softc *sc; 1403{ 1404 int i; 1405 struct ifnet *ifp; 1406 1407 STE_LOCK_ASSERT(sc); 1408 ifp = sc->ste_ifp; 1409 1410 callout_stop(&sc->ste_stat_callout); 1411 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1412 1413 CSR_WRITE_2(sc, STE_IMR, 0); 1414 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1415 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1416 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1417 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1418 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1419 ste_wait(sc); 1420 /* 1421 * Try really hard to stop the RX engine or under heavy RX 1422 * data chip will write into de-allocated memory. 1423 */ 1424 ste_reset(sc); 1425 1426 sc->ste_link = 0; 1427 1428 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1429 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1430 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1431 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1432 } 1433 } 1434 1435 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1436 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1437 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1438 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1439 } 1440 } 1441 1442 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1443 1444 return; 1445} 1446 1447static void 1448ste_reset(sc) 1449 struct ste_softc *sc; 1450{ 1451 int i; 1452 1453 STE_SETBIT4(sc, STE_ASICCTL, 1454 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1455 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1456 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1457 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1458 STE_ASICCTL_EXTRESET_RESET); 1459 1460 DELAY(100000); 1461 1462 for (i = 0; i < STE_TIMEOUT; i++) { 1463 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1464 break; 1465 } 1466 1467 if (i == STE_TIMEOUT) 1468 if_printf(sc->ste_ifp, "global reset never completed\n"); 1469 1470 return; 1471} 1472 1473static int 1474ste_ioctl(ifp, command, data) 1475 struct ifnet *ifp; 1476 u_long command; 1477 caddr_t data; 1478{ 1479 struct ste_softc *sc; 1480 struct ifreq *ifr; 1481 struct mii_data *mii; 1482 int error = 0; 1483 1484 sc = ifp->if_softc; 1485 ifr = (struct ifreq *)data; 1486 1487 switch(command) { 1488 case SIOCSIFFLAGS: 1489 STE_LOCK(sc); 1490 if (ifp->if_flags & IFF_UP) { 1491 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1492 ifp->if_flags & IFF_PROMISC && 1493 !(sc->ste_if_flags & IFF_PROMISC)) { 1494 STE_SETBIT1(sc, STE_RX_MODE, 1495 STE_RXMODE_PROMISC); 1496 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1497 !(ifp->if_flags & IFF_PROMISC) && 1498 sc->ste_if_flags & IFF_PROMISC) { 1499 STE_CLRBIT1(sc, STE_RX_MODE, 1500 STE_RXMODE_PROMISC); 1501 } 1502 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1503 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1504 ste_setmulti(sc); 1505 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1506 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1507 ste_init_locked(sc); 1508 } 1509 } else { 1510 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1511 ste_stop(sc); 1512 } 1513 sc->ste_if_flags = ifp->if_flags; 1514 STE_UNLOCK(sc); 1515 error = 0; 1516 break; 1517 case SIOCADDMULTI: 1518 case SIOCDELMULTI: 1519 STE_LOCK(sc); 1520 ste_setmulti(sc); 1521 STE_UNLOCK(sc); 1522 error = 0; 1523 break; 1524 case SIOCGIFMEDIA: 1525 case SIOCSIFMEDIA: 1526 mii = device_get_softc(sc->ste_miibus); 1527 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1528 break; 1529 case SIOCSIFCAP: 1530#ifdef DEVICE_POLLING 1531 if (ifr->ifr_reqcap & IFCAP_POLLING && 1532 !(ifp->if_capenable & IFCAP_POLLING)) { 1533 error = ether_poll_register(ste_poll, ifp); 1534 if (error) 1535 return(error); 1536 STE_LOCK(sc); 1537 /* Disable interrupts */ 1538 CSR_WRITE_2(sc, STE_IMR, 0); 1539 ifp->if_capenable |= IFCAP_POLLING; 1540 STE_UNLOCK(sc); 1541 return (error); 1542 1543 } 1544 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1545 ifp->if_capenable & IFCAP_POLLING) { 1546 error = ether_poll_deregister(ifp); 1547 /* Enable interrupts. */ 1548 STE_LOCK(sc); 1549 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1550 ifp->if_capenable &= ~IFCAP_POLLING; 1551 STE_UNLOCK(sc); 1552 return (error); 1553 } 1554#endif /* DEVICE_POLLING */ 1555 break; 1556 default: 1557 error = ether_ioctl(ifp, command, data); 1558 break; 1559 } 1560 1561 return(error); 1562} 1563 1564static int 1565ste_encap(sc, c, m_head) 1566 struct ste_softc *sc; 1567 struct ste_chain *c; 1568 struct mbuf *m_head; 1569{ 1570 int frag = 0; 1571 struct ste_frag *f = NULL; 1572 struct mbuf *m; 1573 struct ste_desc *d; 1574 1575 d = c->ste_ptr; 1576 d->ste_ctl = 0; 1577 1578encap_retry: 1579 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1580 if (m->m_len != 0) { 1581 if (frag == STE_MAXFRAGS) 1582 break; 1583 f = &d->ste_frags[frag]; 1584 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1585 f->ste_len = m->m_len; 1586 frag++; 1587 } 1588 } 1589 1590 if (m != NULL) { 1591 struct mbuf *mn; 1592 1593 /* 1594 * We ran out of segments. We have to recopy this 1595 * mbuf chain first. Bail out if we can't get the 1596 * new buffers. 1597 */ 1598 mn = m_defrag(m_head, M_DONTWAIT); 1599 if (mn == NULL) { 1600 m_freem(m_head); 1601 return ENOMEM; 1602 } 1603 m_head = mn; 1604 goto encap_retry; 1605 } 1606 1607 c->ste_mbuf = m_head; 1608 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1609 d->ste_ctl = 1; 1610 1611 return(0); 1612} 1613 1614static void 1615ste_start(ifp) 1616 struct ifnet *ifp; 1617{ 1618 struct ste_softc *sc; 1619 1620 sc = ifp->if_softc; 1621 STE_LOCK(sc); 1622 ste_start_locked(ifp); 1623 STE_UNLOCK(sc); 1624} 1625 1626static void 1627ste_start_locked(ifp) 1628 struct ifnet *ifp; 1629{ 1630 struct ste_softc *sc; 1631 struct mbuf *m_head = NULL; 1632 struct ste_chain *cur_tx; 1633 int idx; 1634 1635 sc = ifp->if_softc; 1636 STE_LOCK_ASSERT(sc); 1637 1638 if (!sc->ste_link) 1639 return; 1640 1641 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1642 return; 1643 1644 idx = sc->ste_cdata.ste_tx_prod; 1645 1646 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1647 /* 1648 * We cannot re-use the last (free) descriptor; 1649 * the chip may not have read its ste_next yet. 1650 */ 1651 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1652 sc->ste_cdata.ste_tx_cons) { 1653 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1654 break; 1655 } 1656 1657 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1658 if (m_head == NULL) 1659 break; 1660 1661 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1662 1663 if (ste_encap(sc, cur_tx, m_head) != 0) 1664 break; 1665 1666 cur_tx->ste_ptr->ste_next = 0; 1667 1668 if (sc->ste_tx_prev == NULL) { 1669 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1670 /* Load address of the TX list */ 1671 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1672 ste_wait(sc); 1673 1674 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1675 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1676 1677 /* Set TX polling interval to start TX engine */ 1678 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1679 1680 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1681 ste_wait(sc); 1682 }else{ 1683 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1684 sc->ste_tx_prev->ste_ptr->ste_next 1685 = cur_tx->ste_phys; 1686 } 1687 1688 sc->ste_tx_prev = cur_tx; 1689 1690 /* 1691 * If there's a BPF listener, bounce a copy of this frame 1692 * to him. 1693 */ 1694 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1695 1696 STE_INC(idx, STE_TX_LIST_CNT); 1697 ifp->if_timer = 5; 1698 } 1699 sc->ste_cdata.ste_tx_prod = idx; 1700 1701 return; 1702} 1703 1704static void 1705ste_watchdog(ifp) 1706 struct ifnet *ifp; 1707{ 1708 struct ste_softc *sc; 1709 1710 sc = ifp->if_softc; 1711 STE_LOCK(sc); 1712 1713 ifp->if_oerrors++; 1714 if_printf(ifp, "watchdog timeout\n"); 1715 1716 ste_txeoc(sc); 1717 ste_txeof(sc); 1718 ste_rxeoc(sc); 1719 ste_rxeof(sc); 1720 ste_reset(sc); 1721 ste_init_locked(sc); 1722 1723 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1724 ste_start_locked(ifp); 1725 STE_UNLOCK(sc); 1726 1727 return; 1728} 1729 1730static void 1731ste_shutdown(dev) 1732 device_t dev; 1733{ 1734 struct ste_softc *sc; 1735 1736 sc = device_get_softc(dev); 1737 1738 STE_LOCK(sc); 1739 ste_stop(sc); 1740 STE_UNLOCK(sc); 1741 1742 return; 1743} 1744