if_ste.c revision 147256
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 147256 2005-06-10 16:49:24Z brooks $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_arp.h> 48#include <net/ethernet.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_types.h> 52#include <net/if_vlan_var.h> 53 54#include <net/bpf.h> 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69/* "controller miibus0" required. See GENERIC if you get errors here. */ 70#include "miibus_if.h" 71 72#define STE_USEIOSPACE 73 74#include <pci/if_stereg.h> 75 76MODULE_DEPEND(ste, pci, 1, 1, 1); 77MODULE_DEPEND(ste, ether, 1, 1, 1); 78MODULE_DEPEND(ste, miibus, 1, 1, 1); 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe(device_t); 90static int ste_attach(device_t); 91static int ste_detach(device_t); 92static void ste_init(void *); 93static void ste_intr(void *); 94static void ste_rxeoc(struct ste_softc *); 95static void ste_rxeof(struct ste_softc *); 96static void ste_txeoc(struct ste_softc *); 97static void ste_txeof(struct ste_softc *); 98static void ste_stats_update(void *); 99static void ste_stop(struct ste_softc *); 100static void ste_reset(struct ste_softc *); 101static int ste_ioctl(struct ifnet *, u_long, caddr_t); 102static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 103static void ste_start(struct ifnet *); 104static void ste_watchdog(struct ifnet *); 105static void ste_shutdown(device_t); 106static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 107 struct mbuf *); 108static int ste_ifmedia_upd(struct ifnet *); 109static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 110 111static void ste_mii_sync(struct ste_softc *); 112static void ste_mii_send(struct ste_softc *, u_int32_t, int); 113static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 114static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 115static int ste_miibus_readreg(device_t, int, int); 116static int ste_miibus_writereg(device_t, int, int, int); 117static void ste_miibus_statchg(device_t); 118 119static int ste_eeprom_wait(struct ste_softc *); 120static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 121static void ste_wait(struct ste_softc *); 122static void ste_setmulti(struct ste_softc *); 123static int ste_init_rx_list(struct ste_softc *); 124static void ste_init_tx_list(struct ste_softc *); 125 126#ifdef STE_USEIOSPACE 127#define STE_RES SYS_RES_IOPORT 128#define STE_RID STE_PCI_LOIO 129#else 130#define STE_RES SYS_RES_MEMORY 131#define STE_RID STE_PCI_LOMEM 132#endif 133 134static device_method_t ste_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, ste_probe), 137 DEVMETHOD(device_attach, ste_attach), 138 DEVMETHOD(device_detach, ste_detach), 139 DEVMETHOD(device_shutdown, ste_shutdown), 140 141 /* bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 144 145 /* MII interface */ 146 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 147 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 148 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 149 150 { 0, 0 } 151}; 152 153static driver_t ste_driver = { 154 "ste", 155 ste_methods, 156 sizeof(struct ste_softc) 157}; 158 159static devclass_t ste_devclass; 160 161DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 162DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 163 164SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 165 166static int ste_rxsyncs; 167SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 168 169#define STE_SETBIT4(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 171 172#define STE_CLRBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 174 175#define STE_SETBIT2(sc, reg, x) \ 176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 177 178#define STE_CLRBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 180 181#define STE_SETBIT1(sc, reg, x) \ 182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 183 184#define STE_CLRBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 186 187 188#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 189#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 190 191/* 192 * Sync the PHYs by setting data bit and strobing the clock 32 times. 193 */ 194static void 195ste_mii_sync(sc) 196 struct ste_softc *sc; 197{ 198 register int i; 199 200 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 201 202 for (i = 0; i < 32; i++) { 203 MII_SET(STE_PHYCTL_MCLK); 204 DELAY(1); 205 MII_CLR(STE_PHYCTL_MCLK); 206 DELAY(1); 207 } 208 209 return; 210} 211 212/* 213 * Clock a series of bits through the MII. 214 */ 215static void 216ste_mii_send(sc, bits, cnt) 217 struct ste_softc *sc; 218 u_int32_t bits; 219 int cnt; 220{ 221 int i; 222 223 MII_CLR(STE_PHYCTL_MCLK); 224 225 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 226 if (bits & i) { 227 MII_SET(STE_PHYCTL_MDATA); 228 } else { 229 MII_CLR(STE_PHYCTL_MDATA); 230 } 231 DELAY(1); 232 MII_CLR(STE_PHYCTL_MCLK); 233 DELAY(1); 234 MII_SET(STE_PHYCTL_MCLK); 235 } 236} 237 238/* 239 * Read an PHY register through the MII. 240 */ 241static int 242ste_mii_readreg(sc, frame) 243 struct ste_softc *sc; 244 struct ste_mii_frame *frame; 245 246{ 247 int i, ack; 248 249 STE_LOCK(sc); 250 251 /* 252 * Set up frame for RX. 253 */ 254 frame->mii_stdelim = STE_MII_STARTDELIM; 255 frame->mii_opcode = STE_MII_READOP; 256 frame->mii_turnaround = 0; 257 frame->mii_data = 0; 258 259 CSR_WRITE_2(sc, STE_PHYCTL, 0); 260 /* 261 * Turn on data xmit. 262 */ 263 MII_SET(STE_PHYCTL_MDIR); 264 265 ste_mii_sync(sc); 266 267 /* 268 * Send command/address info. 269 */ 270 ste_mii_send(sc, frame->mii_stdelim, 2); 271 ste_mii_send(sc, frame->mii_opcode, 2); 272 ste_mii_send(sc, frame->mii_phyaddr, 5); 273 ste_mii_send(sc, frame->mii_regaddr, 5); 274 275 /* Turn off xmit. */ 276 MII_CLR(STE_PHYCTL_MDIR); 277 278 /* Idle bit */ 279 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 280 DELAY(1); 281 MII_SET(STE_PHYCTL_MCLK); 282 DELAY(1); 283 284 /* Check for ack */ 285 MII_CLR(STE_PHYCTL_MCLK); 286 DELAY(1); 287 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 288 MII_SET(STE_PHYCTL_MCLK); 289 DELAY(1); 290 291 /* 292 * Now try reading data bits. If the ack failed, we still 293 * need to clock through 16 cycles to keep the PHY(s) in sync. 294 */ 295 if (ack) { 296 for(i = 0; i < 16; i++) { 297 MII_CLR(STE_PHYCTL_MCLK); 298 DELAY(1); 299 MII_SET(STE_PHYCTL_MCLK); 300 DELAY(1); 301 } 302 goto fail; 303 } 304 305 for (i = 0x8000; i; i >>= 1) { 306 MII_CLR(STE_PHYCTL_MCLK); 307 DELAY(1); 308 if (!ack) { 309 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 310 frame->mii_data |= i; 311 DELAY(1); 312 } 313 MII_SET(STE_PHYCTL_MCLK); 314 DELAY(1); 315 } 316 317fail: 318 319 MII_CLR(STE_PHYCTL_MCLK); 320 DELAY(1); 321 MII_SET(STE_PHYCTL_MCLK); 322 DELAY(1); 323 324 STE_UNLOCK(sc); 325 326 if (ack) 327 return(1); 328 return(0); 329} 330 331/* 332 * Write to a PHY register through the MII. 333 */ 334static int 335ste_mii_writereg(sc, frame) 336 struct ste_softc *sc; 337 struct ste_mii_frame *frame; 338 339{ 340 STE_LOCK(sc); 341 342 /* 343 * Set up frame for TX. 344 */ 345 346 frame->mii_stdelim = STE_MII_STARTDELIM; 347 frame->mii_opcode = STE_MII_WRITEOP; 348 frame->mii_turnaround = STE_MII_TURNAROUND; 349 350 /* 351 * Turn on data output. 352 */ 353 MII_SET(STE_PHYCTL_MDIR); 354 355 ste_mii_sync(sc); 356 357 ste_mii_send(sc, frame->mii_stdelim, 2); 358 ste_mii_send(sc, frame->mii_opcode, 2); 359 ste_mii_send(sc, frame->mii_phyaddr, 5); 360 ste_mii_send(sc, frame->mii_regaddr, 5); 361 ste_mii_send(sc, frame->mii_turnaround, 2); 362 ste_mii_send(sc, frame->mii_data, 16); 363 364 /* Idle bit. */ 365 MII_SET(STE_PHYCTL_MCLK); 366 DELAY(1); 367 MII_CLR(STE_PHYCTL_MCLK); 368 DELAY(1); 369 370 /* 371 * Turn off xmit. 372 */ 373 MII_CLR(STE_PHYCTL_MDIR); 374 375 STE_UNLOCK(sc); 376 377 return(0); 378} 379 380static int 381ste_miibus_readreg(dev, phy, reg) 382 device_t dev; 383 int phy, reg; 384{ 385 struct ste_softc *sc; 386 struct ste_mii_frame frame; 387 388 sc = device_get_softc(dev); 389 390 if ( sc->ste_one_phy && phy != 0 ) 391 return (0); 392 393 bzero((char *)&frame, sizeof(frame)); 394 395 frame.mii_phyaddr = phy; 396 frame.mii_regaddr = reg; 397 ste_mii_readreg(sc, &frame); 398 399 return(frame.mii_data); 400} 401 402static int 403ste_miibus_writereg(dev, phy, reg, data) 404 device_t dev; 405 int phy, reg, data; 406{ 407 struct ste_softc *sc; 408 struct ste_mii_frame frame; 409 410 sc = device_get_softc(dev); 411 bzero((char *)&frame, sizeof(frame)); 412 413 frame.mii_phyaddr = phy; 414 frame.mii_regaddr = reg; 415 frame.mii_data = data; 416 417 ste_mii_writereg(sc, &frame); 418 419 return(0); 420} 421 422static void 423ste_miibus_statchg(dev) 424 device_t dev; 425{ 426 struct ste_softc *sc; 427 struct mii_data *mii; 428 429 sc = device_get_softc(dev); 430 STE_LOCK(sc); 431 mii = device_get_softc(sc->ste_miibus); 432 433 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 434 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 435 } else { 436 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 437 } 438 STE_UNLOCK(sc); 439 440 return; 441} 442 443static int 444ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446{ 447 struct ste_softc *sc; 448 struct mii_data *mii; 449 450 sc = ifp->if_softc; 451 mii = device_get_softc(sc->ste_miibus); 452 sc->ste_link = 0; 453 if (mii->mii_instance) { 454 struct mii_softc *miisc; 455 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 456 mii_phy_reset(miisc); 457 } 458 mii_mediachg(mii); 459 460 return(0); 461} 462 463static void 464ste_ifmedia_sts(ifp, ifmr) 465 struct ifnet *ifp; 466 struct ifmediareq *ifmr; 467{ 468 struct ste_softc *sc; 469 struct mii_data *mii; 470 471 sc = ifp->if_softc; 472 mii = device_get_softc(sc->ste_miibus); 473 474 mii_pollstat(mii); 475 ifmr->ifm_active = mii->mii_media_active; 476 ifmr->ifm_status = mii->mii_media_status; 477 478 return; 479} 480 481static void 482ste_wait(sc) 483 struct ste_softc *sc; 484{ 485 register int i; 486 487 for (i = 0; i < STE_TIMEOUT; i++) { 488 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 489 break; 490 } 491 492 if (i == STE_TIMEOUT) 493 printf("ste%d: command never completed!\n", sc->ste_unit); 494 495 return; 496} 497 498/* 499 * The EEPROM is slow: give it time to come ready after issuing 500 * it a command. 501 */ 502static int 503ste_eeprom_wait(sc) 504 struct ste_softc *sc; 505{ 506 int i; 507 508 DELAY(1000); 509 510 for (i = 0; i < 100; i++) { 511 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 512 DELAY(1000); 513 else 514 break; 515 } 516 517 if (i == 100) { 518 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 519 return(1); 520 } 521 522 return(0); 523} 524 525/* 526 * Read a sequence of words from the EEPROM. Note that ethernet address 527 * data is stored in the EEPROM in network byte order. 528 */ 529static int 530ste_read_eeprom(sc, dest, off, cnt, swap) 531 struct ste_softc *sc; 532 caddr_t dest; 533 int off; 534 int cnt; 535 int swap; 536{ 537 int err = 0, i; 538 u_int16_t word = 0, *ptr; 539 540 if (ste_eeprom_wait(sc)) 541 return(1); 542 543 for (i = 0; i < cnt; i++) { 544 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 545 err = ste_eeprom_wait(sc); 546 if (err) 547 break; 548 word = CSR_READ_2(sc, STE_EEPROM_DATA); 549 ptr = (u_int16_t *)(dest + (i * 2)); 550 if (swap) 551 *ptr = ntohs(word); 552 else 553 *ptr = word; 554 } 555 556 return(err ? 1 : 0); 557} 558 559static void 560ste_setmulti(sc) 561 struct ste_softc *sc; 562{ 563 struct ifnet *ifp; 564 int h = 0; 565 u_int32_t hashes[2] = { 0, 0 }; 566 struct ifmultiaddr *ifma; 567 568 ifp = sc->ste_ifp; 569 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 570 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 571 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 572 return; 573 } 574 575 /* first, zot all the existing hash bits */ 576 CSR_WRITE_2(sc, STE_MAR0, 0); 577 CSR_WRITE_2(sc, STE_MAR1, 0); 578 CSR_WRITE_2(sc, STE_MAR2, 0); 579 CSR_WRITE_2(sc, STE_MAR3, 0); 580 581 /* now program new ones */ 582 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 583 if (ifma->ifma_addr->sa_family != AF_LINK) 584 continue; 585 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 586 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 587 if (h < 32) 588 hashes[0] |= (1 << h); 589 else 590 hashes[1] |= (1 << (h - 32)); 591 } 592 593 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 594 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 595 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 596 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 597 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 598 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 599 600 return; 601} 602 603#ifdef DEVICE_POLLING 604static poll_handler_t ste_poll; 605 606static void 607ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 608{ 609 struct ste_softc *sc = ifp->if_softc; 610 611 STE_LOCK(sc); 612 if (!(ifp->if_capenable & IFCAP_POLLING)) { 613 ether_poll_deregister(ifp); 614 cmd = POLL_DEREGISTER; 615 } 616 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 617 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 618 goto done; 619 } 620 621 sc->rxcycles = count; 622 if (cmd == POLL_AND_CHECK_STATUS) 623 ste_rxeoc(sc); 624 ste_rxeof(sc); 625 ste_txeof(sc); 626 if (ifp->if_snd.ifq_head != NULL) 627 ste_start(ifp); 628 629 if (cmd == POLL_AND_CHECK_STATUS) { 630 u_int16_t status; 631 632 status = CSR_READ_2(sc, STE_ISR_ACK); 633 634 if (status & STE_ISR_TX_DONE) 635 ste_txeoc(sc); 636 637 if (status & STE_ISR_STATS_OFLOW) { 638 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 639 ste_stats_update(sc); 640 } 641 642 if (status & STE_ISR_LINKEVENT) 643 mii_pollstat(device_get_softc(sc->ste_miibus)); 644 645 if (status & STE_ISR_HOSTERR) { 646 ste_reset(sc); 647 ste_init(sc); 648 } 649 } 650done: 651 STE_UNLOCK(sc); 652} 653#endif /* DEVICE_POLLING */ 654 655static void 656ste_intr(xsc) 657 void *xsc; 658{ 659 struct ste_softc *sc; 660 struct ifnet *ifp; 661 u_int16_t status; 662 663 sc = xsc; 664 STE_LOCK(sc); 665 ifp = sc->ste_ifp; 666 667#ifdef DEVICE_POLLING 668 if (ifp->if_flags & IFF_POLLING) 669 goto done; 670 if ((ifp->if_capenable & IFCAP_POLLING) && 671 ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 672 CSR_WRITE_2(sc, STE_IMR, 0); 673 ste_poll(ifp, 0, 1); 674 goto done; 675 } 676#endif /* DEVICE_POLLING */ 677 678 /* See if this is really our interrupt. */ 679 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 680 STE_UNLOCK(sc); 681 return; 682 } 683 684 for (;;) { 685 status = CSR_READ_2(sc, STE_ISR_ACK); 686 687 if (!(status & STE_INTRS)) 688 break; 689 690 if (status & STE_ISR_RX_DMADONE) { 691 ste_rxeoc(sc); 692 ste_rxeof(sc); 693 } 694 695 if (status & STE_ISR_TX_DMADONE) 696 ste_txeof(sc); 697 698 if (status & STE_ISR_TX_DONE) 699 ste_txeoc(sc); 700 701 if (status & STE_ISR_STATS_OFLOW) { 702 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 703 ste_stats_update(sc); 704 } 705 706 if (status & STE_ISR_LINKEVENT) 707 mii_pollstat(device_get_softc(sc->ste_miibus)); 708 709 710 if (status & STE_ISR_HOSTERR) { 711 ste_reset(sc); 712 ste_init(sc); 713 } 714 } 715 716 /* Re-enable interrupts */ 717 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 718 719 if (ifp->if_snd.ifq_head != NULL) 720 ste_start(ifp); 721 722#ifdef DEVICE_POLLING 723done: 724#endif /* DEVICE_POLLING */ 725 STE_UNLOCK(sc); 726 727 return; 728} 729 730static void 731ste_rxeoc(struct ste_softc *sc) 732{ 733 struct ste_chain_onefrag *cur_rx; 734 735 STE_LOCK_ASSERT(sc); 736 737 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 738 cur_rx = sc->ste_cdata.ste_rx_head; 739 do { 740 cur_rx = cur_rx->ste_next; 741 /* If the ring is empty, just return. */ 742 if (cur_rx == sc->ste_cdata.ste_rx_head) 743 return; 744 } while (cur_rx->ste_ptr->ste_status == 0); 745 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 746 /* We've fallen behind the chip: catch it. */ 747 sc->ste_cdata.ste_rx_head = cur_rx; 748 ++ste_rxsyncs; 749 } 750 } 751} 752 753/* 754 * A frame has been uploaded: pass the resulting mbuf chain up to 755 * the higher level protocols. 756 */ 757static void 758ste_rxeof(sc) 759 struct ste_softc *sc; 760{ 761 struct mbuf *m; 762 struct ifnet *ifp; 763 struct ste_chain_onefrag *cur_rx; 764 int total_len = 0, count=0; 765 u_int32_t rxstat; 766 767 STE_LOCK_ASSERT(sc); 768 769 ifp = sc->ste_ifp; 770 771 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 772 & STE_RXSTAT_DMADONE) { 773#ifdef DEVICE_POLLING 774 if (ifp->if_flags & IFF_POLLING) { 775 if (sc->rxcycles <= 0) 776 break; 777 sc->rxcycles--; 778 } 779#endif /* DEVICE_POLLING */ 780 if ((STE_RX_LIST_CNT - count) < 3) { 781 break; 782 } 783 784 cur_rx = sc->ste_cdata.ste_rx_head; 785 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 786 787 /* 788 * If an error occurs, update stats, clear the 789 * status word and leave the mbuf cluster in place: 790 * it should simply get re-used next time this descriptor 791 * comes up in the ring. 792 */ 793 if (rxstat & STE_RXSTAT_FRAME_ERR) { 794 ifp->if_ierrors++; 795 cur_rx->ste_ptr->ste_status = 0; 796 continue; 797 } 798 799 /* 800 * If there error bit was not set, the upload complete 801 * bit should be set which means we have a valid packet. 802 * If not, something truly strange has happened. 803 */ 804 if (!(rxstat & STE_RXSTAT_DMADONE)) { 805 printf("ste%d: bad receive status -- packet dropped\n", 806 sc->ste_unit); 807 ifp->if_ierrors++; 808 cur_rx->ste_ptr->ste_status = 0; 809 continue; 810 } 811 812 /* No errors; receive the packet. */ 813 m = cur_rx->ste_mbuf; 814 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 815 816 /* 817 * Try to conjure up a new mbuf cluster. If that 818 * fails, it means we have an out of memory condition and 819 * should leave the buffer in place and continue. This will 820 * result in a lost packet, but there's little else we 821 * can do in this situation. 822 */ 823 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 824 ifp->if_ierrors++; 825 cur_rx->ste_ptr->ste_status = 0; 826 continue; 827 } 828 829 m->m_pkthdr.rcvif = ifp; 830 m->m_pkthdr.len = m->m_len = total_len; 831 832 ifp->if_ipackets++; 833 STE_UNLOCK(sc); 834 (*ifp->if_input)(ifp, m); 835 STE_LOCK(sc); 836 837 cur_rx->ste_ptr->ste_status = 0; 838 count++; 839 } 840 841 return; 842} 843 844static void 845ste_txeoc(sc) 846 struct ste_softc *sc; 847{ 848 u_int8_t txstat; 849 struct ifnet *ifp; 850 851 ifp = sc->ste_ifp; 852 853 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 854 STE_TXSTATUS_TXDONE) { 855 if (txstat & STE_TXSTATUS_UNDERRUN || 856 txstat & STE_TXSTATUS_EXCESSCOLLS || 857 txstat & STE_TXSTATUS_RECLAIMERR) { 858 ifp->if_oerrors++; 859 printf("ste%d: transmission error: %x\n", 860 sc->ste_unit, txstat); 861 862 ste_reset(sc); 863 ste_init(sc); 864 865 if (txstat & STE_TXSTATUS_UNDERRUN && 866 sc->ste_tx_thresh < STE_PACKET_SIZE) { 867 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 868 printf("ste%d: tx underrun, increasing tx" 869 " start threshold to %d bytes\n", 870 sc->ste_unit, sc->ste_tx_thresh); 871 } 872 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 873 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 874 (STE_PACKET_SIZE >> 4)); 875 } 876 ste_init(sc); 877 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 878 } 879 880 return; 881} 882 883static void 884ste_txeof(sc) 885 struct ste_softc *sc; 886{ 887 struct ste_chain *cur_tx; 888 struct ifnet *ifp; 889 int idx; 890 891 ifp = sc->ste_ifp; 892 893 idx = sc->ste_cdata.ste_tx_cons; 894 while(idx != sc->ste_cdata.ste_tx_prod) { 895 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 896 897 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 898 break; 899 900 m_freem(cur_tx->ste_mbuf); 901 cur_tx->ste_mbuf = NULL; 902 ifp->if_flags &= ~IFF_OACTIVE; 903 ifp->if_opackets++; 904 905 STE_INC(idx, STE_TX_LIST_CNT); 906 } 907 908 sc->ste_cdata.ste_tx_cons = idx; 909 if (idx == sc->ste_cdata.ste_tx_prod) 910 ifp->if_timer = 0; 911} 912 913static void 914ste_stats_update(xsc) 915 void *xsc; 916{ 917 struct ste_softc *sc; 918 struct ifnet *ifp; 919 struct mii_data *mii; 920 921 sc = xsc; 922 STE_LOCK(sc); 923 924 ifp = sc->ste_ifp; 925 mii = device_get_softc(sc->ste_miibus); 926 927 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 928 + CSR_READ_1(sc, STE_MULTI_COLLS) 929 + CSR_READ_1(sc, STE_SINGLE_COLLS); 930 931 if (!sc->ste_link) { 932 mii_pollstat(mii); 933 if (mii->mii_media_status & IFM_ACTIVE && 934 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 935 sc->ste_link++; 936 /* 937 * we don't get a call-back on re-init so do it 938 * otherwise we get stuck in the wrong link state 939 */ 940 ste_miibus_statchg(sc->ste_dev); 941 if (ifp->if_snd.ifq_head != NULL) 942 ste_start(ifp); 943 } 944 } 945 946 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 947 STE_UNLOCK(sc); 948 949 return; 950} 951 952 953/* 954 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 955 * IDs against our list and return a device name if we find a match. 956 */ 957static int 958ste_probe(dev) 959 device_t dev; 960{ 961 struct ste_type *t; 962 963 t = ste_devs; 964 965 while(t->ste_name != NULL) { 966 if ((pci_get_vendor(dev) == t->ste_vid) && 967 (pci_get_device(dev) == t->ste_did)) { 968 device_set_desc(dev, t->ste_name); 969 return (BUS_PROBE_DEFAULT); 970 } 971 t++; 972 } 973 974 return(ENXIO); 975} 976 977/* 978 * Attach the interface. Allocate softc structures, do ifmedia 979 * setup and ethernet/BPF attach. 980 */ 981static int 982ste_attach(dev) 983 device_t dev; 984{ 985 struct ste_softc *sc; 986 struct ifnet *ifp; 987 int unit, error = 0, rid; 988 u_char eaddr[6]; 989 990 sc = device_get_softc(dev); 991 unit = device_get_unit(dev); 992 sc->ste_dev = dev; 993 994 /* 995 * Only use one PHY since this chip reports multiple 996 * Note on the DFE-550 the PHY is at 1 on the DFE-580 997 * it is at 0 & 1. It is rev 0x12. 998 */ 999 if (pci_get_vendor(dev) == DL_VENDORID && 1000 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1001 pci_get_revid(dev) == 0x12 ) 1002 sc->ste_one_phy = 1; 1003 1004 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1005 MTX_DEF | MTX_RECURSE); 1006 /* 1007 * Map control/status registers. 1008 */ 1009 pci_enable_busmaster(dev); 1010 1011 rid = STE_RID; 1012 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1013 1014 if (sc->ste_res == NULL) { 1015 printf ("ste%d: couldn't map ports/memory\n", unit); 1016 error = ENXIO; 1017 goto fail; 1018 } 1019 1020 sc->ste_btag = rman_get_bustag(sc->ste_res); 1021 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1022 1023 /* Allocate interrupt */ 1024 rid = 0; 1025 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1026 RF_SHAREABLE | RF_ACTIVE); 1027 1028 if (sc->ste_irq == NULL) { 1029 printf("ste%d: couldn't map interrupt\n", unit); 1030 error = ENXIO; 1031 goto fail; 1032 } 1033 1034 callout_handle_init(&sc->ste_stat_ch); 1035 1036 /* Reset the adapter. */ 1037 ste_reset(sc); 1038 1039 /* 1040 * Get station address from the EEPROM. 1041 */ 1042 if (ste_read_eeprom(sc, eaddr, 1043 STE_EEADDR_NODE0, 3, 0)) { 1044 printf("ste%d: failed to read station address\n", unit); 1045 error = ENXIO;; 1046 goto fail; 1047 } 1048 1049 sc->ste_unit = unit; 1050 1051 /* Allocate the descriptor queues. */ 1052 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1053 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1054 1055 if (sc->ste_ldata == NULL) { 1056 printf("ste%d: no memory for list buffers!\n", unit); 1057 error = ENXIO; 1058 goto fail; 1059 } 1060 1061 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1062 1063 /* Do MII setup. */ 1064 if (mii_phy_probe(dev, &sc->ste_miibus, 1065 ste_ifmedia_upd, ste_ifmedia_sts)) { 1066 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1067 error = ENXIO; 1068 goto fail; 1069 } 1070 1071 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1072 if (ifp == NULL) { 1073 printf("ste%d: can not if_alloc()\n", sc->ste_unit); 1074 error = ENOSPC; 1075 goto fail; 1076 } 1077 ifp->if_softc = sc; 1078 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1079 ifp->if_mtu = ETHERMTU; 1080 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 1081 IFF_NEEDSGIANT; 1082 ifp->if_ioctl = ste_ioctl; 1083 ifp->if_start = ste_start; 1084 ifp->if_watchdog = ste_watchdog; 1085 ifp->if_init = ste_init; 1086 ifp->if_baudrate = 10000000; 1087 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1088 1089 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1090 1091 /* 1092 * Call MI attach routine. 1093 */ 1094 ether_ifattach(ifp, eaddr); 1095 1096 /* 1097 * Tell the upper layer(s) we support long frames. 1098 */ 1099 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1100 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1101#ifdef DEVICE_POLLING 1102 ifp->if_capabilities |= IFCAP_POLLING; 1103#endif 1104 ifp->if_capenable = ifp->if_capabilities; 1105 1106 /* Hook interrupt last to avoid having to lock softc */ 1107 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1108 ste_intr, sc, &sc->ste_intrhand); 1109 1110 if (error) { 1111 printf("ste%d: couldn't set up irq\n", unit); 1112 ether_ifdetach(ifp); 1113 if_free(ifp); 1114 goto fail; 1115 } 1116 1117fail: 1118 if (error) 1119 ste_detach(dev); 1120 1121 return(error); 1122} 1123 1124/* 1125 * Shutdown hardware and free up resources. This can be called any 1126 * time after the mutex has been initialized. It is called in both 1127 * the error case in attach and the normal detach case so it needs 1128 * to be careful about only freeing resources that have actually been 1129 * allocated. 1130 */ 1131static int 1132ste_detach(dev) 1133 device_t dev; 1134{ 1135 struct ste_softc *sc; 1136 struct ifnet *ifp; 1137 1138 sc = device_get_softc(dev); 1139 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1140 STE_LOCK(sc); 1141 ifp = sc->ste_ifp; 1142 1143 /* These should only be active if attach succeeded */ 1144 if (device_is_attached(dev)) { 1145 ste_stop(sc); 1146 ether_ifdetach(ifp); 1147 if_free(ifp); 1148 } 1149 if (sc->ste_miibus) 1150 device_delete_child(dev, sc->ste_miibus); 1151 bus_generic_detach(dev); 1152 1153 if (sc->ste_intrhand) 1154 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1155 if (sc->ste_irq) 1156 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1157 if (sc->ste_res) 1158 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1159 1160 if (sc->ste_ldata) { 1161 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1162 M_DEVBUF); 1163 } 1164 1165 STE_UNLOCK(sc); 1166 mtx_destroy(&sc->ste_mtx); 1167 1168 return(0); 1169} 1170 1171static int 1172ste_newbuf(sc, c, m) 1173 struct ste_softc *sc; 1174 struct ste_chain_onefrag *c; 1175 struct mbuf *m; 1176{ 1177 struct mbuf *m_new = NULL; 1178 1179 if (m == NULL) { 1180 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1181 if (m_new == NULL) 1182 return(ENOBUFS); 1183 MCLGET(m_new, M_DONTWAIT); 1184 if (!(m_new->m_flags & M_EXT)) { 1185 m_freem(m_new); 1186 return(ENOBUFS); 1187 } 1188 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1189 } else { 1190 m_new = m; 1191 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1192 m_new->m_data = m_new->m_ext.ext_buf; 1193 } 1194 1195 m_adj(m_new, ETHER_ALIGN); 1196 1197 c->ste_mbuf = m_new; 1198 c->ste_ptr->ste_status = 0; 1199 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1200 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1201 1202 return(0); 1203} 1204 1205static int 1206ste_init_rx_list(sc) 1207 struct ste_softc *sc; 1208{ 1209 struct ste_chain_data *cd; 1210 struct ste_list_data *ld; 1211 int i; 1212 1213 cd = &sc->ste_cdata; 1214 ld = sc->ste_ldata; 1215 1216 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1217 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1218 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1219 return(ENOBUFS); 1220 if (i == (STE_RX_LIST_CNT - 1)) { 1221 cd->ste_rx_chain[i].ste_next = 1222 &cd->ste_rx_chain[0]; 1223 ld->ste_rx_list[i].ste_next = 1224 vtophys(&ld->ste_rx_list[0]); 1225 } else { 1226 cd->ste_rx_chain[i].ste_next = 1227 &cd->ste_rx_chain[i + 1]; 1228 ld->ste_rx_list[i].ste_next = 1229 vtophys(&ld->ste_rx_list[i + 1]); 1230 } 1231 ld->ste_rx_list[i].ste_status = 0; 1232 } 1233 1234 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1235 1236 return(0); 1237} 1238 1239static void 1240ste_init_tx_list(sc) 1241 struct ste_softc *sc; 1242{ 1243 struct ste_chain_data *cd; 1244 struct ste_list_data *ld; 1245 int i; 1246 1247 cd = &sc->ste_cdata; 1248 ld = sc->ste_ldata; 1249 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1250 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1251 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1252 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1253 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1254 if (i == (STE_TX_LIST_CNT - 1)) 1255 cd->ste_tx_chain[i].ste_next = 1256 &cd->ste_tx_chain[0]; 1257 else 1258 cd->ste_tx_chain[i].ste_next = 1259 &cd->ste_tx_chain[i + 1]; 1260 } 1261 1262 cd->ste_tx_prod = 0; 1263 cd->ste_tx_cons = 0; 1264 1265 return; 1266} 1267 1268static void 1269ste_init(xsc) 1270 void *xsc; 1271{ 1272 struct ste_softc *sc; 1273 int i; 1274 struct ifnet *ifp; 1275 1276 sc = xsc; 1277 STE_LOCK(sc); 1278 ifp = sc->ste_ifp; 1279 1280 ste_stop(sc); 1281 1282 /* Init our MAC address */ 1283 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1284 CSR_WRITE_1(sc, STE_PAR0 + i, IFP2ENADDR(sc->ste_ifp)[i]); 1285 } 1286 1287 /* Init RX list */ 1288 if (ste_init_rx_list(sc) == ENOBUFS) { 1289 printf("ste%d: initialization failed: no " 1290 "memory for RX buffers\n", sc->ste_unit); 1291 ste_stop(sc); 1292 STE_UNLOCK(sc); 1293 return; 1294 } 1295 1296 /* Set RX polling interval */ 1297 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1298 1299 /* Init TX descriptors */ 1300 ste_init_tx_list(sc); 1301 1302 /* Set the TX freethresh value */ 1303 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1304 1305 /* Set the TX start threshold for best performance. */ 1306 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1307 1308 /* Set the TX reclaim threshold. */ 1309 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1310 1311 /* Set up the RX filter. */ 1312 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1313 1314 /* If we want promiscuous mode, set the allframes bit. */ 1315 if (ifp->if_flags & IFF_PROMISC) { 1316 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1317 } else { 1318 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1319 } 1320 1321 /* Set capture broadcast bit to accept broadcast frames. */ 1322 if (ifp->if_flags & IFF_BROADCAST) { 1323 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1324 } else { 1325 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1326 } 1327 1328 ste_setmulti(sc); 1329 1330 /* Load the address of the RX list. */ 1331 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1332 ste_wait(sc); 1333 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1334 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1335 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1336 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1337 1338 /* Set TX polling interval (defer until we TX first packet */ 1339 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1340 1341 /* Load address of the TX list */ 1342 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1343 ste_wait(sc); 1344 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1345 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1346 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1347 ste_wait(sc); 1348 sc->ste_tx_prev = NULL; 1349 1350 /* Enable receiver and transmitter */ 1351 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1352 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1353 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1354 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1355 1356 /* Enable stats counters. */ 1357 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1358 1359 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1360#ifdef DEVICE_POLLING 1361 /* Disable interrupts if we are polling. */ 1362 if (ifp->if_flags & IFF_POLLING) 1363 CSR_WRITE_2(sc, STE_IMR, 0); 1364 else 1365#endif /* DEVICE_POLLING */ 1366 /* Enable interrupts. */ 1367 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1368 1369 /* Accept VLAN length packets */ 1370 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1371 1372 ste_ifmedia_upd(ifp); 1373 1374 ifp->if_flags |= IFF_RUNNING; 1375 ifp->if_flags &= ~IFF_OACTIVE; 1376 1377 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1378 STE_UNLOCK(sc); 1379 1380 return; 1381} 1382 1383static void 1384ste_stop(sc) 1385 struct ste_softc *sc; 1386{ 1387 int i; 1388 struct ifnet *ifp; 1389 1390 STE_LOCK(sc); 1391 ifp = sc->ste_ifp; 1392 1393 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1394 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1395#ifdef DEVICE_POLLING 1396 ether_poll_deregister(ifp); 1397#endif /* DEVICE_POLLING */ 1398 1399 CSR_WRITE_2(sc, STE_IMR, 0); 1400 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1401 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1402 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1403 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1404 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1405 ste_wait(sc); 1406 /* 1407 * Try really hard to stop the RX engine or under heavy RX 1408 * data chip will write into de-allocated memory. 1409 */ 1410 ste_reset(sc); 1411 1412 sc->ste_link = 0; 1413 1414 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1415 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1416 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1417 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1418 } 1419 } 1420 1421 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1422 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1423 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1424 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1425 } 1426 } 1427 1428 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1429 STE_UNLOCK(sc); 1430 1431 return; 1432} 1433 1434static void 1435ste_reset(sc) 1436 struct ste_softc *sc; 1437{ 1438 int i; 1439 1440 STE_SETBIT4(sc, STE_ASICCTL, 1441 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1442 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1443 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1444 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1445 STE_ASICCTL_EXTRESET_RESET); 1446 1447 DELAY(100000); 1448 1449 for (i = 0; i < STE_TIMEOUT; i++) { 1450 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1451 break; 1452 } 1453 1454 if (i == STE_TIMEOUT) 1455 printf("ste%d: global reset never completed\n", sc->ste_unit); 1456 1457 return; 1458} 1459 1460static int 1461ste_ioctl(ifp, command, data) 1462 struct ifnet *ifp; 1463 u_long command; 1464 caddr_t data; 1465{ 1466 struct ste_softc *sc; 1467 struct ifreq *ifr; 1468 struct mii_data *mii; 1469 int error = 0; 1470 1471 sc = ifp->if_softc; 1472 STE_LOCK(sc); 1473 ifr = (struct ifreq *)data; 1474 1475 switch(command) { 1476 case SIOCSIFFLAGS: 1477 if (ifp->if_flags & IFF_UP) { 1478 if (ifp->if_flags & IFF_RUNNING && 1479 ifp->if_flags & IFF_PROMISC && 1480 !(sc->ste_if_flags & IFF_PROMISC)) { 1481 STE_SETBIT1(sc, STE_RX_MODE, 1482 STE_RXMODE_PROMISC); 1483 } else if (ifp->if_flags & IFF_RUNNING && 1484 !(ifp->if_flags & IFF_PROMISC) && 1485 sc->ste_if_flags & IFF_PROMISC) { 1486 STE_CLRBIT1(sc, STE_RX_MODE, 1487 STE_RXMODE_PROMISC); 1488 } 1489 if (ifp->if_flags & IFF_RUNNING && 1490 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1491 ste_setmulti(sc); 1492 if (!(ifp->if_flags & IFF_RUNNING)) { 1493 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1494 ste_init(sc); 1495 } 1496 } else { 1497 if (ifp->if_flags & IFF_RUNNING) 1498 ste_stop(sc); 1499 } 1500 sc->ste_if_flags = ifp->if_flags; 1501 error = 0; 1502 break; 1503 case SIOCADDMULTI: 1504 case SIOCDELMULTI: 1505 ste_setmulti(sc); 1506 error = 0; 1507 break; 1508 case SIOCGIFMEDIA: 1509 case SIOCSIFMEDIA: 1510 mii = device_get_softc(sc->ste_miibus); 1511 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1512 break; 1513 case SIOCSIFCAP: 1514 ifp->if_capenable &= ~IFCAP_POLLING; 1515 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1516 break; 1517 default: 1518 error = ether_ioctl(ifp, command, data); 1519 break; 1520 } 1521 1522 STE_UNLOCK(sc); 1523 1524 return(error); 1525} 1526 1527static int 1528ste_encap(sc, c, m_head) 1529 struct ste_softc *sc; 1530 struct ste_chain *c; 1531 struct mbuf *m_head; 1532{ 1533 int frag = 0; 1534 struct ste_frag *f = NULL; 1535 struct mbuf *m; 1536 struct ste_desc *d; 1537 1538 d = c->ste_ptr; 1539 d->ste_ctl = 0; 1540 1541encap_retry: 1542 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1543 if (m->m_len != 0) { 1544 if (frag == STE_MAXFRAGS) 1545 break; 1546 f = &d->ste_frags[frag]; 1547 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1548 f->ste_len = m->m_len; 1549 frag++; 1550 } 1551 } 1552 1553 if (m != NULL) { 1554 struct mbuf *mn; 1555 1556 /* 1557 * We ran out of segments. We have to recopy this 1558 * mbuf chain first. Bail out if we can't get the 1559 * new buffers. 1560 */ 1561 mn = m_defrag(m_head, M_DONTWAIT); 1562 if (mn == NULL) { 1563 m_freem(m_head); 1564 return ENOMEM; 1565 } 1566 m_head = mn; 1567 goto encap_retry; 1568 } 1569 1570 c->ste_mbuf = m_head; 1571 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1572 d->ste_ctl = 1; 1573 1574 return(0); 1575} 1576 1577static void 1578ste_start(ifp) 1579 struct ifnet *ifp; 1580{ 1581 struct ste_softc *sc; 1582 struct mbuf *m_head = NULL; 1583 struct ste_chain *cur_tx; 1584 int idx; 1585 1586 sc = ifp->if_softc; 1587 STE_LOCK(sc); 1588 1589 if (!sc->ste_link) { 1590 STE_UNLOCK(sc); 1591 return; 1592 } 1593 1594 if (ifp->if_flags & IFF_OACTIVE) { 1595 STE_UNLOCK(sc); 1596 return; 1597 } 1598 1599 idx = sc->ste_cdata.ste_tx_prod; 1600 1601 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1602 /* 1603 * We cannot re-use the last (free) descriptor; 1604 * the chip may not have read its ste_next yet. 1605 */ 1606 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1607 sc->ste_cdata.ste_tx_cons) { 1608 ifp->if_flags |= IFF_OACTIVE; 1609 break; 1610 } 1611 1612 IF_DEQUEUE(&ifp->if_snd, m_head); 1613 if (m_head == NULL) 1614 break; 1615 1616 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1617 1618 if (ste_encap(sc, cur_tx, m_head) != 0) 1619 break; 1620 1621 cur_tx->ste_ptr->ste_next = 0; 1622 1623 if (sc->ste_tx_prev == NULL) { 1624 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1625 /* Load address of the TX list */ 1626 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1627 ste_wait(sc); 1628 1629 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1630 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1631 1632 /* Set TX polling interval to start TX engine */ 1633 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1634 1635 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1636 ste_wait(sc); 1637 }else{ 1638 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1639 sc->ste_tx_prev->ste_ptr->ste_next 1640 = cur_tx->ste_phys; 1641 } 1642 1643 sc->ste_tx_prev = cur_tx; 1644 1645 /* 1646 * If there's a BPF listener, bounce a copy of this frame 1647 * to him. 1648 */ 1649 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1650 1651 STE_INC(idx, STE_TX_LIST_CNT); 1652 ifp->if_timer = 5; 1653 } 1654 sc->ste_cdata.ste_tx_prod = idx; 1655 1656 STE_UNLOCK(sc); 1657 1658 return; 1659} 1660 1661static void 1662ste_watchdog(ifp) 1663 struct ifnet *ifp; 1664{ 1665 struct ste_softc *sc; 1666 1667 sc = ifp->if_softc; 1668 STE_LOCK(sc); 1669 1670 ifp->if_oerrors++; 1671 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1672 1673 ste_txeoc(sc); 1674 ste_txeof(sc); 1675 ste_rxeoc(sc); 1676 ste_rxeof(sc); 1677 ste_reset(sc); 1678 ste_init(sc); 1679 1680 if (ifp->if_snd.ifq_head != NULL) 1681 ste_start(ifp); 1682 STE_UNLOCK(sc); 1683 1684 return; 1685} 1686 1687static void 1688ste_shutdown(dev) 1689 device_t dev; 1690{ 1691 struct ste_softc *sc; 1692 1693 sc = device_get_softc(dev); 1694 1695 ste_stop(sc); 1696 1697 return; 1698} 1699