if_ste.c revision 146734
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 146734 2005-05-29 04:42:30Z nyan $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_arp.h> 48#include <net/ethernet.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_vlan_var.h> 52 53#include <net/bpf.h> 54 55#include <vm/vm.h> /* for vtophys */ 56#include <vm/pmap.h> /* for vtophys */ 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/bus.h> 60#include <sys/rman.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68/* "controller miibus0" required. See GENERIC if you get errors here. */ 69#include "miibus_if.h" 70 71#define STE_USEIOSPACE 72 73#include <pci/if_stereg.h> 74 75MODULE_DEPEND(ste, pci, 1, 1, 1); 76MODULE_DEPEND(ste, ether, 1, 1, 1); 77MODULE_DEPEND(ste, miibus, 1, 1, 1); 78 79/* 80 * Various supported device vendors/types and their names. 81 */ 82static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 85 { 0, 0, NULL } 86}; 87 88static int ste_probe(device_t); 89static int ste_attach(device_t); 90static int ste_detach(device_t); 91static void ste_init(void *); 92static void ste_intr(void *); 93static void ste_rxeoc(struct ste_softc *); 94static void ste_rxeof(struct ste_softc *); 95static void ste_txeoc(struct ste_softc *); 96static void ste_txeof(struct ste_softc *); 97static void ste_stats_update(void *); 98static void ste_stop(struct ste_softc *); 99static void ste_reset(struct ste_softc *); 100static int ste_ioctl(struct ifnet *, u_long, caddr_t); 101static int ste_encap(struct ste_softc *, struct ste_chain *, struct mbuf *); 102static void ste_start(struct ifnet *); 103static void ste_watchdog(struct ifnet *); 104static void ste_shutdown(device_t); 105static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *, 106 struct mbuf *); 107static int ste_ifmedia_upd(struct ifnet *); 108static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 110static void ste_mii_sync(struct ste_softc *); 111static void ste_mii_send(struct ste_softc *, u_int32_t, int); 112static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 113static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 114static int ste_miibus_readreg(device_t, int, int); 115static int ste_miibus_writereg(device_t, int, int, int); 116static void ste_miibus_statchg(device_t); 117 118static int ste_eeprom_wait(struct ste_softc *); 119static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 120static void ste_wait(struct ste_softc *); 121static void ste_setmulti(struct ste_softc *); 122static int ste_init_rx_list(struct ste_softc *); 123static void ste_init_tx_list(struct ste_softc *); 124 125#ifdef STE_USEIOSPACE 126#define STE_RES SYS_RES_IOPORT 127#define STE_RID STE_PCI_LOIO 128#else 129#define STE_RES SYS_RES_MEMORY 130#define STE_RID STE_PCI_LOMEM 131#endif 132 133static device_method_t ste_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, ste_probe), 136 DEVMETHOD(device_attach, ste_attach), 137 DEVMETHOD(device_detach, ste_detach), 138 DEVMETHOD(device_shutdown, ste_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 146 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 147 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 148 149 { 0, 0 } 150}; 151 152static driver_t ste_driver = { 153 "ste", 154 ste_methods, 155 sizeof(struct ste_softc) 156}; 157 158static devclass_t ste_devclass; 159 160DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 161DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 162 163SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 164 165static int ste_rxsyncs; 166SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 167 168#define STE_SETBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 170 171#define STE_CLRBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 173 174#define STE_SETBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 176 177#define STE_CLRBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 179 180#define STE_SETBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 182 183#define STE_CLRBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 185 186 187#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 188#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 189 190/* 191 * Sync the PHYs by setting data bit and strobing the clock 32 times. 192 */ 193static void 194ste_mii_sync(sc) 195 struct ste_softc *sc; 196{ 197 register int i; 198 199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 200 201 for (i = 0; i < 32; i++) { 202 MII_SET(STE_PHYCTL_MCLK); 203 DELAY(1); 204 MII_CLR(STE_PHYCTL_MCLK); 205 DELAY(1); 206 } 207 208 return; 209} 210 211/* 212 * Clock a series of bits through the MII. 213 */ 214static void 215ste_mii_send(sc, bits, cnt) 216 struct ste_softc *sc; 217 u_int32_t bits; 218 int cnt; 219{ 220 int i; 221 222 MII_CLR(STE_PHYCTL_MCLK); 223 224 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 225 if (bits & i) { 226 MII_SET(STE_PHYCTL_MDATA); 227 } else { 228 MII_CLR(STE_PHYCTL_MDATA); 229 } 230 DELAY(1); 231 MII_CLR(STE_PHYCTL_MCLK); 232 DELAY(1); 233 MII_SET(STE_PHYCTL_MCLK); 234 } 235} 236 237/* 238 * Read an PHY register through the MII. 239 */ 240static int 241ste_mii_readreg(sc, frame) 242 struct ste_softc *sc; 243 struct ste_mii_frame *frame; 244 245{ 246 int i, ack; 247 248 STE_LOCK(sc); 249 250 /* 251 * Set up frame for RX. 252 */ 253 frame->mii_stdelim = STE_MII_STARTDELIM; 254 frame->mii_opcode = STE_MII_READOP; 255 frame->mii_turnaround = 0; 256 frame->mii_data = 0; 257 258 CSR_WRITE_2(sc, STE_PHYCTL, 0); 259 /* 260 * Turn on data xmit. 261 */ 262 MII_SET(STE_PHYCTL_MDIR); 263 264 ste_mii_sync(sc); 265 266 /* 267 * Send command/address info. 268 */ 269 ste_mii_send(sc, frame->mii_stdelim, 2); 270 ste_mii_send(sc, frame->mii_opcode, 2); 271 ste_mii_send(sc, frame->mii_phyaddr, 5); 272 ste_mii_send(sc, frame->mii_regaddr, 5); 273 274 /* Turn off xmit. */ 275 MII_CLR(STE_PHYCTL_MDIR); 276 277 /* Idle bit */ 278 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 279 DELAY(1); 280 MII_SET(STE_PHYCTL_MCLK); 281 DELAY(1); 282 283 /* Check for ack */ 284 MII_CLR(STE_PHYCTL_MCLK); 285 DELAY(1); 286 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 287 MII_SET(STE_PHYCTL_MCLK); 288 DELAY(1); 289 290 /* 291 * Now try reading data bits. If the ack failed, we still 292 * need to clock through 16 cycles to keep the PHY(s) in sync. 293 */ 294 if (ack) { 295 for(i = 0; i < 16; i++) { 296 MII_CLR(STE_PHYCTL_MCLK); 297 DELAY(1); 298 MII_SET(STE_PHYCTL_MCLK); 299 DELAY(1); 300 } 301 goto fail; 302 } 303 304 for (i = 0x8000; i; i >>= 1) { 305 MII_CLR(STE_PHYCTL_MCLK); 306 DELAY(1); 307 if (!ack) { 308 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 309 frame->mii_data |= i; 310 DELAY(1); 311 } 312 MII_SET(STE_PHYCTL_MCLK); 313 DELAY(1); 314 } 315 316fail: 317 318 MII_CLR(STE_PHYCTL_MCLK); 319 DELAY(1); 320 MII_SET(STE_PHYCTL_MCLK); 321 DELAY(1); 322 323 STE_UNLOCK(sc); 324 325 if (ack) 326 return(1); 327 return(0); 328} 329 330/* 331 * Write to a PHY register through the MII. 332 */ 333static int 334ste_mii_writereg(sc, frame) 335 struct ste_softc *sc; 336 struct ste_mii_frame *frame; 337 338{ 339 STE_LOCK(sc); 340 341 /* 342 * Set up frame for TX. 343 */ 344 345 frame->mii_stdelim = STE_MII_STARTDELIM; 346 frame->mii_opcode = STE_MII_WRITEOP; 347 frame->mii_turnaround = STE_MII_TURNAROUND; 348 349 /* 350 * Turn on data output. 351 */ 352 MII_SET(STE_PHYCTL_MDIR); 353 354 ste_mii_sync(sc); 355 356 ste_mii_send(sc, frame->mii_stdelim, 2); 357 ste_mii_send(sc, frame->mii_opcode, 2); 358 ste_mii_send(sc, frame->mii_phyaddr, 5); 359 ste_mii_send(sc, frame->mii_regaddr, 5); 360 ste_mii_send(sc, frame->mii_turnaround, 2); 361 ste_mii_send(sc, frame->mii_data, 16); 362 363 /* Idle bit. */ 364 MII_SET(STE_PHYCTL_MCLK); 365 DELAY(1); 366 MII_CLR(STE_PHYCTL_MCLK); 367 DELAY(1); 368 369 /* 370 * Turn off xmit. 371 */ 372 MII_CLR(STE_PHYCTL_MDIR); 373 374 STE_UNLOCK(sc); 375 376 return(0); 377} 378 379static int 380ste_miibus_readreg(dev, phy, reg) 381 device_t dev; 382 int phy, reg; 383{ 384 struct ste_softc *sc; 385 struct ste_mii_frame frame; 386 387 sc = device_get_softc(dev); 388 389 if ( sc->ste_one_phy && phy != 0 ) 390 return (0); 391 392 bzero((char *)&frame, sizeof(frame)); 393 394 frame.mii_phyaddr = phy; 395 frame.mii_regaddr = reg; 396 ste_mii_readreg(sc, &frame); 397 398 return(frame.mii_data); 399} 400 401static int 402ste_miibus_writereg(dev, phy, reg, data) 403 device_t dev; 404 int phy, reg, data; 405{ 406 struct ste_softc *sc; 407 struct ste_mii_frame frame; 408 409 sc = device_get_softc(dev); 410 bzero((char *)&frame, sizeof(frame)); 411 412 frame.mii_phyaddr = phy; 413 frame.mii_regaddr = reg; 414 frame.mii_data = data; 415 416 ste_mii_writereg(sc, &frame); 417 418 return(0); 419} 420 421static void 422ste_miibus_statchg(dev) 423 device_t dev; 424{ 425 struct ste_softc *sc; 426 struct mii_data *mii; 427 428 sc = device_get_softc(dev); 429 STE_LOCK(sc); 430 mii = device_get_softc(sc->ste_miibus); 431 432 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 433 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 434 } else { 435 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 436 } 437 STE_UNLOCK(sc); 438 439 return; 440} 441 442static int 443ste_ifmedia_upd(ifp) 444 struct ifnet *ifp; 445{ 446 struct ste_softc *sc; 447 struct mii_data *mii; 448 449 sc = ifp->if_softc; 450 mii = device_get_softc(sc->ste_miibus); 451 sc->ste_link = 0; 452 if (mii->mii_instance) { 453 struct mii_softc *miisc; 454 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 455 mii_phy_reset(miisc); 456 } 457 mii_mediachg(mii); 458 459 return(0); 460} 461 462static void 463ste_ifmedia_sts(ifp, ifmr) 464 struct ifnet *ifp; 465 struct ifmediareq *ifmr; 466{ 467 struct ste_softc *sc; 468 struct mii_data *mii; 469 470 sc = ifp->if_softc; 471 mii = device_get_softc(sc->ste_miibus); 472 473 mii_pollstat(mii); 474 ifmr->ifm_active = mii->mii_media_active; 475 ifmr->ifm_status = mii->mii_media_status; 476 477 return; 478} 479 480static void 481ste_wait(sc) 482 struct ste_softc *sc; 483{ 484 register int i; 485 486 for (i = 0; i < STE_TIMEOUT; i++) { 487 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 488 break; 489 } 490 491 if (i == STE_TIMEOUT) 492 printf("ste%d: command never completed!\n", sc->ste_unit); 493 494 return; 495} 496 497/* 498 * The EEPROM is slow: give it time to come ready after issuing 499 * it a command. 500 */ 501static int 502ste_eeprom_wait(sc) 503 struct ste_softc *sc; 504{ 505 int i; 506 507 DELAY(1000); 508 509 for (i = 0; i < 100; i++) { 510 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 511 DELAY(1000); 512 else 513 break; 514 } 515 516 if (i == 100) { 517 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 518 return(1); 519 } 520 521 return(0); 522} 523 524/* 525 * Read a sequence of words from the EEPROM. Note that ethernet address 526 * data is stored in the EEPROM in network byte order. 527 */ 528static int 529ste_read_eeprom(sc, dest, off, cnt, swap) 530 struct ste_softc *sc; 531 caddr_t dest; 532 int off; 533 int cnt; 534 int swap; 535{ 536 int err = 0, i; 537 u_int16_t word = 0, *ptr; 538 539 if (ste_eeprom_wait(sc)) 540 return(1); 541 542 for (i = 0; i < cnt; i++) { 543 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 544 err = ste_eeprom_wait(sc); 545 if (err) 546 break; 547 word = CSR_READ_2(sc, STE_EEPROM_DATA); 548 ptr = (u_int16_t *)(dest + (i * 2)); 549 if (swap) 550 *ptr = ntohs(word); 551 else 552 *ptr = word; 553 } 554 555 return(err ? 1 : 0); 556} 557 558static void 559ste_setmulti(sc) 560 struct ste_softc *sc; 561{ 562 struct ifnet *ifp; 563 int h = 0; 564 u_int32_t hashes[2] = { 0, 0 }; 565 struct ifmultiaddr *ifma; 566 567 ifp = &sc->arpcom.ac_if; 568 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 569 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 570 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 571 return; 572 } 573 574 /* first, zot all the existing hash bits */ 575 CSR_WRITE_2(sc, STE_MAR0, 0); 576 CSR_WRITE_2(sc, STE_MAR1, 0); 577 CSR_WRITE_2(sc, STE_MAR2, 0); 578 CSR_WRITE_2(sc, STE_MAR3, 0); 579 580 /* now program new ones */ 581 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 582 if (ifma->ifma_addr->sa_family != AF_LINK) 583 continue; 584 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 585 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 586 if (h < 32) 587 hashes[0] |= (1 << h); 588 else 589 hashes[1] |= (1 << (h - 32)); 590 } 591 592 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 593 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 594 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 595 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 596 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 597 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 598 599 return; 600} 601 602#ifdef DEVICE_POLLING 603static poll_handler_t ste_poll; 604 605static void 606ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 607{ 608 struct ste_softc *sc = ifp->if_softc; 609 610 STE_LOCK(sc); 611 if (!(ifp->if_capenable & IFCAP_POLLING)) { 612 ether_poll_deregister(ifp); 613 cmd = POLL_DEREGISTER; 614 } 615 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 616 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 617 goto done; 618 } 619 620 sc->rxcycles = count; 621 if (cmd == POLL_AND_CHECK_STATUS) 622 ste_rxeoc(sc); 623 ste_rxeof(sc); 624 ste_txeof(sc); 625 if (ifp->if_snd.ifq_head != NULL) 626 ste_start(ifp); 627 628 if (cmd == POLL_AND_CHECK_STATUS) { 629 u_int16_t status; 630 631 status = CSR_READ_2(sc, STE_ISR_ACK); 632 633 if (status & STE_ISR_TX_DONE) 634 ste_txeoc(sc); 635 636 if (status & STE_ISR_STATS_OFLOW) { 637 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 638 ste_stats_update(sc); 639 } 640 641 if (status & STE_ISR_LINKEVENT) 642 mii_pollstat(device_get_softc(sc->ste_miibus)); 643 644 if (status & STE_ISR_HOSTERR) { 645 ste_reset(sc); 646 ste_init(sc); 647 } 648 } 649done: 650 STE_UNLOCK(sc); 651} 652#endif /* DEVICE_POLLING */ 653 654static void 655ste_intr(xsc) 656 void *xsc; 657{ 658 struct ste_softc *sc; 659 struct ifnet *ifp; 660 u_int16_t status; 661 662 sc = xsc; 663 STE_LOCK(sc); 664 ifp = &sc->arpcom.ac_if; 665 666#ifdef DEVICE_POLLING 667 if (ifp->if_flags & IFF_POLLING) 668 goto done; 669 if ((ifp->if_capenable & IFCAP_POLLING) && 670 ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 671 CSR_WRITE_2(sc, STE_IMR, 0); 672 ste_poll(ifp, 0, 1); 673 goto done; 674 } 675#endif /* DEVICE_POLLING */ 676 677 /* See if this is really our interrupt. */ 678 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 679 STE_UNLOCK(sc); 680 return; 681 } 682 683 for (;;) { 684 status = CSR_READ_2(sc, STE_ISR_ACK); 685 686 if (!(status & STE_INTRS)) 687 break; 688 689 if (status & STE_ISR_RX_DMADONE) { 690 ste_rxeoc(sc); 691 ste_rxeof(sc); 692 } 693 694 if (status & STE_ISR_TX_DMADONE) 695 ste_txeof(sc); 696 697 if (status & STE_ISR_TX_DONE) 698 ste_txeoc(sc); 699 700 if (status & STE_ISR_STATS_OFLOW) { 701 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 702 ste_stats_update(sc); 703 } 704 705 if (status & STE_ISR_LINKEVENT) 706 mii_pollstat(device_get_softc(sc->ste_miibus)); 707 708 709 if (status & STE_ISR_HOSTERR) { 710 ste_reset(sc); 711 ste_init(sc); 712 } 713 } 714 715 /* Re-enable interrupts */ 716 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 717 718 if (ifp->if_snd.ifq_head != NULL) 719 ste_start(ifp); 720 721#ifdef DEVICE_POLLING 722done: 723#endif /* DEVICE_POLLING */ 724 STE_UNLOCK(sc); 725 726 return; 727} 728 729static void 730ste_rxeoc(struct ste_softc *sc) 731{ 732 struct ste_chain_onefrag *cur_rx; 733 734 STE_LOCK_ASSERT(sc); 735 736 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 737 cur_rx = sc->ste_cdata.ste_rx_head; 738 do { 739 cur_rx = cur_rx->ste_next; 740 /* If the ring is empty, just return. */ 741 if (cur_rx == sc->ste_cdata.ste_rx_head) 742 return; 743 } while (cur_rx->ste_ptr->ste_status == 0); 744 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 745 /* We've fallen behind the chip: catch it. */ 746 sc->ste_cdata.ste_rx_head = cur_rx; 747 ++ste_rxsyncs; 748 } 749 } 750} 751 752/* 753 * A frame has been uploaded: pass the resulting mbuf chain up to 754 * the higher level protocols. 755 */ 756static void 757ste_rxeof(sc) 758 struct ste_softc *sc; 759{ 760 struct mbuf *m; 761 struct ifnet *ifp; 762 struct ste_chain_onefrag *cur_rx; 763 int total_len = 0, count=0; 764 u_int32_t rxstat; 765 766 STE_LOCK_ASSERT(sc); 767 768 ifp = &sc->arpcom.ac_if; 769 770 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 771 & STE_RXSTAT_DMADONE) { 772#ifdef DEVICE_POLLING 773 if (ifp->if_flags & IFF_POLLING) { 774 if (sc->rxcycles <= 0) 775 break; 776 sc->rxcycles--; 777 } 778#endif /* DEVICE_POLLING */ 779 if ((STE_RX_LIST_CNT - count) < 3) { 780 break; 781 } 782 783 cur_rx = sc->ste_cdata.ste_rx_head; 784 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 785 786 /* 787 * If an error occurs, update stats, clear the 788 * status word and leave the mbuf cluster in place: 789 * it should simply get re-used next time this descriptor 790 * comes up in the ring. 791 */ 792 if (rxstat & STE_RXSTAT_FRAME_ERR) { 793 ifp->if_ierrors++; 794 cur_rx->ste_ptr->ste_status = 0; 795 continue; 796 } 797 798 /* 799 * If there error bit was not set, the upload complete 800 * bit should be set which means we have a valid packet. 801 * If not, something truly strange has happened. 802 */ 803 if (!(rxstat & STE_RXSTAT_DMADONE)) { 804 printf("ste%d: bad receive status -- packet dropped\n", 805 sc->ste_unit); 806 ifp->if_ierrors++; 807 cur_rx->ste_ptr->ste_status = 0; 808 continue; 809 } 810 811 /* No errors; receive the packet. */ 812 m = cur_rx->ste_mbuf; 813 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 814 815 /* 816 * Try to conjure up a new mbuf cluster. If that 817 * fails, it means we have an out of memory condition and 818 * should leave the buffer in place and continue. This will 819 * result in a lost packet, but there's little else we 820 * can do in this situation. 821 */ 822 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 823 ifp->if_ierrors++; 824 cur_rx->ste_ptr->ste_status = 0; 825 continue; 826 } 827 828 m->m_pkthdr.rcvif = ifp; 829 m->m_pkthdr.len = m->m_len = total_len; 830 831 ifp->if_ipackets++; 832 STE_UNLOCK(sc); 833 (*ifp->if_input)(ifp, m); 834 STE_LOCK(sc); 835 836 cur_rx->ste_ptr->ste_status = 0; 837 count++; 838 } 839 840 return; 841} 842 843static void 844ste_txeoc(sc) 845 struct ste_softc *sc; 846{ 847 u_int8_t txstat; 848 struct ifnet *ifp; 849 850 ifp = &sc->arpcom.ac_if; 851 852 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 853 STE_TXSTATUS_TXDONE) { 854 if (txstat & STE_TXSTATUS_UNDERRUN || 855 txstat & STE_TXSTATUS_EXCESSCOLLS || 856 txstat & STE_TXSTATUS_RECLAIMERR) { 857 ifp->if_oerrors++; 858 printf("ste%d: transmission error: %x\n", 859 sc->ste_unit, txstat); 860 861 ste_reset(sc); 862 ste_init(sc); 863 864 if (txstat & STE_TXSTATUS_UNDERRUN && 865 sc->ste_tx_thresh < STE_PACKET_SIZE) { 866 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 867 printf("ste%d: tx underrun, increasing tx" 868 " start threshold to %d bytes\n", 869 sc->ste_unit, sc->ste_tx_thresh); 870 } 871 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 872 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 873 (STE_PACKET_SIZE >> 4)); 874 } 875 ste_init(sc); 876 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 877 } 878 879 return; 880} 881 882static void 883ste_txeof(sc) 884 struct ste_softc *sc; 885{ 886 struct ste_chain *cur_tx; 887 struct ifnet *ifp; 888 int idx; 889 890 ifp = &sc->arpcom.ac_if; 891 892 idx = sc->ste_cdata.ste_tx_cons; 893 while(idx != sc->ste_cdata.ste_tx_prod) { 894 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 895 896 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 897 break; 898 899 m_freem(cur_tx->ste_mbuf); 900 cur_tx->ste_mbuf = NULL; 901 ifp->if_flags &= ~IFF_OACTIVE; 902 ifp->if_opackets++; 903 904 STE_INC(idx, STE_TX_LIST_CNT); 905 } 906 907 sc->ste_cdata.ste_tx_cons = idx; 908 if (idx == sc->ste_cdata.ste_tx_prod) 909 ifp->if_timer = 0; 910} 911 912static void 913ste_stats_update(xsc) 914 void *xsc; 915{ 916 struct ste_softc *sc; 917 struct ifnet *ifp; 918 struct mii_data *mii; 919 920 sc = xsc; 921 STE_LOCK(sc); 922 923 ifp = &sc->arpcom.ac_if; 924 mii = device_get_softc(sc->ste_miibus); 925 926 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 927 + CSR_READ_1(sc, STE_MULTI_COLLS) 928 + CSR_READ_1(sc, STE_SINGLE_COLLS); 929 930 if (!sc->ste_link) { 931 mii_pollstat(mii); 932 if (mii->mii_media_status & IFM_ACTIVE && 933 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 934 sc->ste_link++; 935 /* 936 * we don't get a call-back on re-init so do it 937 * otherwise we get stuck in the wrong link state 938 */ 939 ste_miibus_statchg(sc->ste_dev); 940 if (ifp->if_snd.ifq_head != NULL) 941 ste_start(ifp); 942 } 943 } 944 945 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 946 STE_UNLOCK(sc); 947 948 return; 949} 950 951 952/* 953 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 954 * IDs against our list and return a device name if we find a match. 955 */ 956static int 957ste_probe(dev) 958 device_t dev; 959{ 960 struct ste_type *t; 961 962 t = ste_devs; 963 964 while(t->ste_name != NULL) { 965 if ((pci_get_vendor(dev) == t->ste_vid) && 966 (pci_get_device(dev) == t->ste_did)) { 967 device_set_desc(dev, t->ste_name); 968 return (BUS_PROBE_DEFAULT); 969 } 970 t++; 971 } 972 973 return(ENXIO); 974} 975 976/* 977 * Attach the interface. Allocate softc structures, do ifmedia 978 * setup and ethernet/BPF attach. 979 */ 980static int 981ste_attach(dev) 982 device_t dev; 983{ 984 struct ste_softc *sc; 985 struct ifnet *ifp; 986 int unit, error = 0, rid; 987 988 sc = device_get_softc(dev); 989 unit = device_get_unit(dev); 990 sc->ste_dev = dev; 991 992 /* 993 * Only use one PHY since this chip reports multiple 994 * Note on the DFE-550 the PHY is at 1 on the DFE-580 995 * it is at 0 & 1. It is rev 0x12. 996 */ 997 if (pci_get_vendor(dev) == DL_VENDORID && 998 pci_get_device(dev) == DL_DEVICEID_DL10050 && 999 pci_get_revid(dev) == 0x12 ) 1000 sc->ste_one_phy = 1; 1001 1002 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1003 MTX_DEF | MTX_RECURSE); 1004 /* 1005 * Map control/status registers. 1006 */ 1007 pci_enable_busmaster(dev); 1008 1009 rid = STE_RID; 1010 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1011 1012 if (sc->ste_res == NULL) { 1013 printf ("ste%d: couldn't map ports/memory\n", unit); 1014 error = ENXIO; 1015 goto fail; 1016 } 1017 1018 sc->ste_btag = rman_get_bustag(sc->ste_res); 1019 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1020 1021 /* Allocate interrupt */ 1022 rid = 0; 1023 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1024 RF_SHAREABLE | RF_ACTIVE); 1025 1026 if (sc->ste_irq == NULL) { 1027 printf("ste%d: couldn't map interrupt\n", unit); 1028 error = ENXIO; 1029 goto fail; 1030 } 1031 1032 callout_handle_init(&sc->ste_stat_ch); 1033 1034 /* Reset the adapter. */ 1035 ste_reset(sc); 1036 1037 /* 1038 * Get station address from the EEPROM. 1039 */ 1040 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1041 STE_EEADDR_NODE0, 3, 0)) { 1042 printf("ste%d: failed to read station address\n", unit); 1043 error = ENXIO;; 1044 goto fail; 1045 } 1046 1047 sc->ste_unit = unit; 1048 1049 /* Allocate the descriptor queues. */ 1050 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1051 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1052 1053 if (sc->ste_ldata == NULL) { 1054 printf("ste%d: no memory for list buffers!\n", unit); 1055 error = ENXIO; 1056 goto fail; 1057 } 1058 1059 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1060 1061 /* Do MII setup. */ 1062 if (mii_phy_probe(dev, &sc->ste_miibus, 1063 ste_ifmedia_upd, ste_ifmedia_sts)) { 1064 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1065 error = ENXIO; 1066 goto fail; 1067 } 1068 1069 ifp = &sc->arpcom.ac_if; 1070 ifp->if_softc = sc; 1071 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1072 ifp->if_mtu = ETHERMTU; 1073 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 1074 IFF_NEEDSGIANT; 1075 ifp->if_ioctl = ste_ioctl; 1076 ifp->if_start = ste_start; 1077 ifp->if_watchdog = ste_watchdog; 1078 ifp->if_init = ste_init; 1079 ifp->if_baudrate = 10000000; 1080 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1081 1082 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1083 1084 /* 1085 * Call MI attach routine. 1086 */ 1087 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1088 1089 /* 1090 * Tell the upper layer(s) we support long frames. 1091 */ 1092 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1093 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1094#ifdef DEVICE_POLLING 1095 ifp->if_capabilities |= IFCAP_POLLING; 1096#endif 1097 ifp->if_capenable = ifp->if_capabilities; 1098 1099 /* Hook interrupt last to avoid having to lock softc */ 1100 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1101 ste_intr, sc, &sc->ste_intrhand); 1102 1103 if (error) { 1104 printf("ste%d: couldn't set up irq\n", unit); 1105 ether_ifdetach(ifp); 1106 goto fail; 1107 } 1108 1109fail: 1110 if (error) 1111 ste_detach(dev); 1112 1113 return(error); 1114} 1115 1116/* 1117 * Shutdown hardware and free up resources. This can be called any 1118 * time after the mutex has been initialized. It is called in both 1119 * the error case in attach and the normal detach case so it needs 1120 * to be careful about only freeing resources that have actually been 1121 * allocated. 1122 */ 1123static int 1124ste_detach(dev) 1125 device_t dev; 1126{ 1127 struct ste_softc *sc; 1128 struct ifnet *ifp; 1129 1130 sc = device_get_softc(dev); 1131 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1132 STE_LOCK(sc); 1133 ifp = &sc->arpcom.ac_if; 1134 1135 /* These should only be active if attach succeeded */ 1136 if (device_is_attached(dev)) { 1137 ste_stop(sc); 1138 ether_ifdetach(ifp); 1139 } 1140 if (sc->ste_miibus) 1141 device_delete_child(dev, sc->ste_miibus); 1142 bus_generic_detach(dev); 1143 1144 if (sc->ste_intrhand) 1145 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1146 if (sc->ste_irq) 1147 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1148 if (sc->ste_res) 1149 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1150 1151 if (sc->ste_ldata) { 1152 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1153 M_DEVBUF); 1154 } 1155 1156 STE_UNLOCK(sc); 1157 mtx_destroy(&sc->ste_mtx); 1158 1159 return(0); 1160} 1161 1162static int 1163ste_newbuf(sc, c, m) 1164 struct ste_softc *sc; 1165 struct ste_chain_onefrag *c; 1166 struct mbuf *m; 1167{ 1168 struct mbuf *m_new = NULL; 1169 1170 if (m == NULL) { 1171 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1172 if (m_new == NULL) 1173 return(ENOBUFS); 1174 MCLGET(m_new, M_DONTWAIT); 1175 if (!(m_new->m_flags & M_EXT)) { 1176 m_freem(m_new); 1177 return(ENOBUFS); 1178 } 1179 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1180 } else { 1181 m_new = m; 1182 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1183 m_new->m_data = m_new->m_ext.ext_buf; 1184 } 1185 1186 m_adj(m_new, ETHER_ALIGN); 1187 1188 c->ste_mbuf = m_new; 1189 c->ste_ptr->ste_status = 0; 1190 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1191 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1192 1193 return(0); 1194} 1195 1196static int 1197ste_init_rx_list(sc) 1198 struct ste_softc *sc; 1199{ 1200 struct ste_chain_data *cd; 1201 struct ste_list_data *ld; 1202 int i; 1203 1204 cd = &sc->ste_cdata; 1205 ld = sc->ste_ldata; 1206 1207 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1208 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1209 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1210 return(ENOBUFS); 1211 if (i == (STE_RX_LIST_CNT - 1)) { 1212 cd->ste_rx_chain[i].ste_next = 1213 &cd->ste_rx_chain[0]; 1214 ld->ste_rx_list[i].ste_next = 1215 vtophys(&ld->ste_rx_list[0]); 1216 } else { 1217 cd->ste_rx_chain[i].ste_next = 1218 &cd->ste_rx_chain[i + 1]; 1219 ld->ste_rx_list[i].ste_next = 1220 vtophys(&ld->ste_rx_list[i + 1]); 1221 } 1222 ld->ste_rx_list[i].ste_status = 0; 1223 } 1224 1225 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1226 1227 return(0); 1228} 1229 1230static void 1231ste_init_tx_list(sc) 1232 struct ste_softc *sc; 1233{ 1234 struct ste_chain_data *cd; 1235 struct ste_list_data *ld; 1236 int i; 1237 1238 cd = &sc->ste_cdata; 1239 ld = sc->ste_ldata; 1240 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1241 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1242 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1243 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1244 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1245 if (i == (STE_TX_LIST_CNT - 1)) 1246 cd->ste_tx_chain[i].ste_next = 1247 &cd->ste_tx_chain[0]; 1248 else 1249 cd->ste_tx_chain[i].ste_next = 1250 &cd->ste_tx_chain[i + 1]; 1251 } 1252 1253 cd->ste_tx_prod = 0; 1254 cd->ste_tx_cons = 0; 1255 1256 return; 1257} 1258 1259static void 1260ste_init(xsc) 1261 void *xsc; 1262{ 1263 struct ste_softc *sc; 1264 int i; 1265 struct ifnet *ifp; 1266 1267 sc = xsc; 1268 STE_LOCK(sc); 1269 ifp = &sc->arpcom.ac_if; 1270 1271 ste_stop(sc); 1272 1273 /* Init our MAC address */ 1274 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1275 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1276 } 1277 1278 /* Init RX list */ 1279 if (ste_init_rx_list(sc) == ENOBUFS) { 1280 printf("ste%d: initialization failed: no " 1281 "memory for RX buffers\n", sc->ste_unit); 1282 ste_stop(sc); 1283 STE_UNLOCK(sc); 1284 return; 1285 } 1286 1287 /* Set RX polling interval */ 1288 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1289 1290 /* Init TX descriptors */ 1291 ste_init_tx_list(sc); 1292 1293 /* Set the TX freethresh value */ 1294 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1295 1296 /* Set the TX start threshold for best performance. */ 1297 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1298 1299 /* Set the TX reclaim threshold. */ 1300 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1301 1302 /* Set up the RX filter. */ 1303 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1304 1305 /* If we want promiscuous mode, set the allframes bit. */ 1306 if (ifp->if_flags & IFF_PROMISC) { 1307 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1308 } else { 1309 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1310 } 1311 1312 /* Set capture broadcast bit to accept broadcast frames. */ 1313 if (ifp->if_flags & IFF_BROADCAST) { 1314 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1315 } else { 1316 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1317 } 1318 1319 ste_setmulti(sc); 1320 1321 /* Load the address of the RX list. */ 1322 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1323 ste_wait(sc); 1324 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1325 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1326 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1327 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1328 1329 /* Set TX polling interval (defer until we TX first packet */ 1330 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1331 1332 /* Load address of the TX list */ 1333 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1334 ste_wait(sc); 1335 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1336 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1337 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1338 ste_wait(sc); 1339 sc->ste_tx_prev = NULL; 1340 1341 /* Enable receiver and transmitter */ 1342 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1343 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1344 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1345 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1346 1347 /* Enable stats counters. */ 1348 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1349 1350 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1351#ifdef DEVICE_POLLING 1352 /* Disable interrupts if we are polling. */ 1353 if (ifp->if_flags & IFF_POLLING) 1354 CSR_WRITE_2(sc, STE_IMR, 0); 1355 else 1356#endif /* DEVICE_POLLING */ 1357 /* Enable interrupts. */ 1358 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1359 1360 /* Accept VLAN length packets */ 1361 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1362 1363 ste_ifmedia_upd(ifp); 1364 1365 ifp->if_flags |= IFF_RUNNING; 1366 ifp->if_flags &= ~IFF_OACTIVE; 1367 1368 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1369 STE_UNLOCK(sc); 1370 1371 return; 1372} 1373 1374static void 1375ste_stop(sc) 1376 struct ste_softc *sc; 1377{ 1378 int i; 1379 struct ifnet *ifp; 1380 1381 STE_LOCK(sc); 1382 ifp = &sc->arpcom.ac_if; 1383 1384 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1385 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1386#ifdef DEVICE_POLLING 1387 ether_poll_deregister(ifp); 1388#endif /* DEVICE_POLLING */ 1389 1390 CSR_WRITE_2(sc, STE_IMR, 0); 1391 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1392 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1393 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1394 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1395 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1396 ste_wait(sc); 1397 /* 1398 * Try really hard to stop the RX engine or under heavy RX 1399 * data chip will write into de-allocated memory. 1400 */ 1401 ste_reset(sc); 1402 1403 sc->ste_link = 0; 1404 1405 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1406 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1407 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1408 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1409 } 1410 } 1411 1412 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1413 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1414 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1415 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1416 } 1417 } 1418 1419 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1420 STE_UNLOCK(sc); 1421 1422 return; 1423} 1424 1425static void 1426ste_reset(sc) 1427 struct ste_softc *sc; 1428{ 1429 int i; 1430 1431 STE_SETBIT4(sc, STE_ASICCTL, 1432 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1433 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1434 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1435 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1436 STE_ASICCTL_EXTRESET_RESET); 1437 1438 DELAY(100000); 1439 1440 for (i = 0; i < STE_TIMEOUT; i++) { 1441 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1442 break; 1443 } 1444 1445 if (i == STE_TIMEOUT) 1446 printf("ste%d: global reset never completed\n", sc->ste_unit); 1447 1448 return; 1449} 1450 1451static int 1452ste_ioctl(ifp, command, data) 1453 struct ifnet *ifp; 1454 u_long command; 1455 caddr_t data; 1456{ 1457 struct ste_softc *sc; 1458 struct ifreq *ifr; 1459 struct mii_data *mii; 1460 int error = 0; 1461 1462 sc = ifp->if_softc; 1463 STE_LOCK(sc); 1464 ifr = (struct ifreq *)data; 1465 1466 switch(command) { 1467 case SIOCSIFFLAGS: 1468 if (ifp->if_flags & IFF_UP) { 1469 if (ifp->if_flags & IFF_RUNNING && 1470 ifp->if_flags & IFF_PROMISC && 1471 !(sc->ste_if_flags & IFF_PROMISC)) { 1472 STE_SETBIT1(sc, STE_RX_MODE, 1473 STE_RXMODE_PROMISC); 1474 } else if (ifp->if_flags & IFF_RUNNING && 1475 !(ifp->if_flags & IFF_PROMISC) && 1476 sc->ste_if_flags & IFF_PROMISC) { 1477 STE_CLRBIT1(sc, STE_RX_MODE, 1478 STE_RXMODE_PROMISC); 1479 } 1480 if (ifp->if_flags & IFF_RUNNING && 1481 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1482 ste_setmulti(sc); 1483 if (!(ifp->if_flags & IFF_RUNNING)) { 1484 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1485 ste_init(sc); 1486 } 1487 } else { 1488 if (ifp->if_flags & IFF_RUNNING) 1489 ste_stop(sc); 1490 } 1491 sc->ste_if_flags = ifp->if_flags; 1492 error = 0; 1493 break; 1494 case SIOCADDMULTI: 1495 case SIOCDELMULTI: 1496 ste_setmulti(sc); 1497 error = 0; 1498 break; 1499 case SIOCGIFMEDIA: 1500 case SIOCSIFMEDIA: 1501 mii = device_get_softc(sc->ste_miibus); 1502 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1503 break; 1504 case SIOCSIFCAP: 1505 ifp->if_capenable &= ~IFCAP_POLLING; 1506 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1507 break; 1508 default: 1509 error = ether_ioctl(ifp, command, data); 1510 break; 1511 } 1512 1513 STE_UNLOCK(sc); 1514 1515 return(error); 1516} 1517 1518static int 1519ste_encap(sc, c, m_head) 1520 struct ste_softc *sc; 1521 struct ste_chain *c; 1522 struct mbuf *m_head; 1523{ 1524 int frag = 0; 1525 struct ste_frag *f = NULL; 1526 struct mbuf *m; 1527 struct ste_desc *d; 1528 1529 d = c->ste_ptr; 1530 d->ste_ctl = 0; 1531 1532encap_retry: 1533 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1534 if (m->m_len != 0) { 1535 if (frag == STE_MAXFRAGS) 1536 break; 1537 f = &d->ste_frags[frag]; 1538 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1539 f->ste_len = m->m_len; 1540 frag++; 1541 } 1542 } 1543 1544 if (m != NULL) { 1545 struct mbuf *mn; 1546 1547 /* 1548 * We ran out of segments. We have to recopy this 1549 * mbuf chain first. Bail out if we can't get the 1550 * new buffers. 1551 */ 1552 mn = m_defrag(m_head, M_DONTWAIT); 1553 if (mn == NULL) { 1554 m_freem(m_head); 1555 return ENOMEM; 1556 } 1557 m_head = mn; 1558 goto encap_retry; 1559 } 1560 1561 c->ste_mbuf = m_head; 1562 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1563 d->ste_ctl = 1; 1564 1565 return(0); 1566} 1567 1568static void 1569ste_start(ifp) 1570 struct ifnet *ifp; 1571{ 1572 struct ste_softc *sc; 1573 struct mbuf *m_head = NULL; 1574 struct ste_chain *cur_tx; 1575 int idx; 1576 1577 sc = ifp->if_softc; 1578 STE_LOCK(sc); 1579 1580 if (!sc->ste_link) { 1581 STE_UNLOCK(sc); 1582 return; 1583 } 1584 1585 if (ifp->if_flags & IFF_OACTIVE) { 1586 STE_UNLOCK(sc); 1587 return; 1588 } 1589 1590 idx = sc->ste_cdata.ste_tx_prod; 1591 1592 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1593 /* 1594 * We cannot re-use the last (free) descriptor; 1595 * the chip may not have read its ste_next yet. 1596 */ 1597 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1598 sc->ste_cdata.ste_tx_cons) { 1599 ifp->if_flags |= IFF_OACTIVE; 1600 break; 1601 } 1602 1603 IF_DEQUEUE(&ifp->if_snd, m_head); 1604 if (m_head == NULL) 1605 break; 1606 1607 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1608 1609 if (ste_encap(sc, cur_tx, m_head) != 0) 1610 break; 1611 1612 cur_tx->ste_ptr->ste_next = 0; 1613 1614 if (sc->ste_tx_prev == NULL) { 1615 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1616 /* Load address of the TX list */ 1617 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1618 ste_wait(sc); 1619 1620 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1621 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1622 1623 /* Set TX polling interval to start TX engine */ 1624 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1625 1626 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1627 ste_wait(sc); 1628 }else{ 1629 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1630 sc->ste_tx_prev->ste_ptr->ste_next 1631 = cur_tx->ste_phys; 1632 } 1633 1634 sc->ste_tx_prev = cur_tx; 1635 1636 /* 1637 * If there's a BPF listener, bounce a copy of this frame 1638 * to him. 1639 */ 1640 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1641 1642 STE_INC(idx, STE_TX_LIST_CNT); 1643 ifp->if_timer = 5; 1644 } 1645 sc->ste_cdata.ste_tx_prod = idx; 1646 1647 STE_UNLOCK(sc); 1648 1649 return; 1650} 1651 1652static void 1653ste_watchdog(ifp) 1654 struct ifnet *ifp; 1655{ 1656 struct ste_softc *sc; 1657 1658 sc = ifp->if_softc; 1659 STE_LOCK(sc); 1660 1661 ifp->if_oerrors++; 1662 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1663 1664 ste_txeoc(sc); 1665 ste_txeof(sc); 1666 ste_rxeoc(sc); 1667 ste_rxeof(sc); 1668 ste_reset(sc); 1669 ste_init(sc); 1670 1671 if (ifp->if_snd.ifq_head != NULL) 1672 ste_start(ifp); 1673 STE_UNLOCK(sc); 1674 1675 return; 1676} 1677 1678static void 1679ste_shutdown(dev) 1680 device_t dev; 1681{ 1682 struct ste_softc *sc; 1683 1684 sc = device_get_softc(dev); 1685 1686 ste_stop(sc); 1687 1688 return; 1689} 1690