if_ste.c revision 139825
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 139825 2005-01-07 02:29:27Z imp $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/socket.h> 44#include <sys/sysctl.h> 45 46#include <net/if.h> 47#include <net/if_arp.h> 48#include <net/ethernet.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51#include <net/if_vlan_var.h> 52 53#include <net/bpf.h> 54 55#include <vm/vm.h> /* for vtophys */ 56#include <vm/pmap.h> /* for vtophys */ 57#include <machine/bus_memio.h> 58#include <machine/bus_pio.h> 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/bus.h> 62#include <sys/rman.h> 63 64#include <dev/mii/mii.h> 65#include <dev/mii/miivar.h> 66 67#include <dev/pci/pcireg.h> 68#include <dev/pci/pcivar.h> 69 70/* "controller miibus0" required. See GENERIC if you get errors here. */ 71#include "miibus_if.h" 72 73#define STE_USEIOSPACE 74 75#include <pci/if_stereg.h> 76 77MODULE_DEPEND(ste, pci, 1, 1, 1); 78MODULE_DEPEND(ste, ether, 1, 1, 1); 79MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 87 { 0, 0, NULL } 88}; 89 90static int ste_probe (device_t); 91static int ste_attach (device_t); 92static int ste_detach (device_t); 93static void ste_init (void *); 94static void ste_intr (void *); 95static void ste_rxeoc (struct ste_softc *); 96static void ste_rxeof (struct ste_softc *); 97static void ste_txeoc (struct ste_softc *); 98static void ste_txeof (struct ste_softc *); 99static void ste_stats_update (void *); 100static void ste_stop (struct ste_softc *); 101static void ste_reset (struct ste_softc *); 102static int ste_ioctl (struct ifnet *, u_long, caddr_t); 103static int ste_encap (struct ste_softc *, struct ste_chain *, 104 struct mbuf *); 105static void ste_start (struct ifnet *); 106static void ste_watchdog (struct ifnet *); 107static void ste_shutdown (device_t); 108static int ste_newbuf (struct ste_softc *, 109 struct ste_chain_onefrag *, 110 struct mbuf *); 111static int ste_ifmedia_upd (struct ifnet *); 112static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 113 114static void ste_mii_sync (struct ste_softc *); 115static void ste_mii_send (struct ste_softc *, u_int32_t, int); 116static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 118static int ste_miibus_readreg (device_t, int, int); 119static int ste_miibus_writereg (device_t, int, int, int); 120static void ste_miibus_statchg (device_t); 121 122static int ste_eeprom_wait (struct ste_softc *); 123static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 124static void ste_wait (struct ste_softc *); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 168 169static int ste_rxsyncs; 170SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 171 172#define STE_SETBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 174 175#define STE_CLRBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 177 178#define STE_SETBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 180 181#define STE_CLRBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 183 184#define STE_SETBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186 187#define STE_CLRBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 189 190 191#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 192#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 193 194/* 195 * Sync the PHYs by setting data bit and strobing the clock 32 times. 196 */ 197static void 198ste_mii_sync(sc) 199 struct ste_softc *sc; 200{ 201 register int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211 212 return; 213} 214 215/* 216 * Clock a series of bits through the MII. 217 */ 218static void 219ste_mii_send(sc, bits, cnt) 220 struct ste_softc *sc; 221 u_int32_t bits; 222 int cnt; 223{ 224 int i; 225 226 MII_CLR(STE_PHYCTL_MCLK); 227 228 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 229 if (bits & i) { 230 MII_SET(STE_PHYCTL_MDATA); 231 } else { 232 MII_CLR(STE_PHYCTL_MDATA); 233 } 234 DELAY(1); 235 MII_CLR(STE_PHYCTL_MCLK); 236 DELAY(1); 237 MII_SET(STE_PHYCTL_MCLK); 238 } 239} 240 241/* 242 * Read an PHY register through the MII. 243 */ 244static int 245ste_mii_readreg(sc, frame) 246 struct ste_softc *sc; 247 struct ste_mii_frame *frame; 248 249{ 250 int i, ack; 251 252 STE_LOCK(sc); 253 254 /* 255 * Set up frame for RX. 256 */ 257 frame->mii_stdelim = STE_MII_STARTDELIM; 258 frame->mii_opcode = STE_MII_READOP; 259 frame->mii_turnaround = 0; 260 frame->mii_data = 0; 261 262 CSR_WRITE_2(sc, STE_PHYCTL, 0); 263 /* 264 * Turn on data xmit. 265 */ 266 MII_SET(STE_PHYCTL_MDIR); 267 268 ste_mii_sync(sc); 269 270 /* 271 * Send command/address info. 272 */ 273 ste_mii_send(sc, frame->mii_stdelim, 2); 274 ste_mii_send(sc, frame->mii_opcode, 2); 275 ste_mii_send(sc, frame->mii_phyaddr, 5); 276 ste_mii_send(sc, frame->mii_regaddr, 5); 277 278 /* Turn off xmit. */ 279 MII_CLR(STE_PHYCTL_MDIR); 280 281 /* Idle bit */ 282 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 283 DELAY(1); 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* Check for ack */ 288 MII_CLR(STE_PHYCTL_MCLK); 289 DELAY(1); 290 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 291 MII_SET(STE_PHYCTL_MCLK); 292 DELAY(1); 293 294 /* 295 * Now try reading data bits. If the ack failed, we still 296 * need to clock through 16 cycles to keep the PHY(s) in sync. 297 */ 298 if (ack) { 299 for(i = 0; i < 16; i++) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 MII_SET(STE_PHYCTL_MCLK); 303 DELAY(1); 304 } 305 goto fail; 306 } 307 308 for (i = 0x8000; i; i >>= 1) { 309 MII_CLR(STE_PHYCTL_MCLK); 310 DELAY(1); 311 if (!ack) { 312 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 313 frame->mii_data |= i; 314 DELAY(1); 315 } 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 } 319 320fail: 321 322 MII_CLR(STE_PHYCTL_MCLK); 323 DELAY(1); 324 MII_SET(STE_PHYCTL_MCLK); 325 DELAY(1); 326 327 STE_UNLOCK(sc); 328 329 if (ack) 330 return(1); 331 return(0); 332} 333 334/* 335 * Write to a PHY register through the MII. 336 */ 337static int 338ste_mii_writereg(sc, frame) 339 struct ste_softc *sc; 340 struct ste_mii_frame *frame; 341 342{ 343 STE_LOCK(sc); 344 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 STE_UNLOCK(sc); 379 380 return(0); 381} 382 383static int 384ste_miibus_readreg(dev, phy, reg) 385 device_t dev; 386 int phy, reg; 387{ 388 struct ste_softc *sc; 389 struct ste_mii_frame frame; 390 391 sc = device_get_softc(dev); 392 393 if ( sc->ste_one_phy && phy != 0 ) 394 return (0); 395 396 bzero((char *)&frame, sizeof(frame)); 397 398 frame.mii_phyaddr = phy; 399 frame.mii_regaddr = reg; 400 ste_mii_readreg(sc, &frame); 401 402 return(frame.mii_data); 403} 404 405static int 406ste_miibus_writereg(dev, phy, reg, data) 407 device_t dev; 408 int phy, reg, data; 409{ 410 struct ste_softc *sc; 411 struct ste_mii_frame frame; 412 413 sc = device_get_softc(dev); 414 bzero((char *)&frame, sizeof(frame)); 415 416 frame.mii_phyaddr = phy; 417 frame.mii_regaddr = reg; 418 frame.mii_data = data; 419 420 ste_mii_writereg(sc, &frame); 421 422 return(0); 423} 424 425static void 426ste_miibus_statchg(dev) 427 device_t dev; 428{ 429 struct ste_softc *sc; 430 struct mii_data *mii; 431 432 sc = device_get_softc(dev); 433 STE_LOCK(sc); 434 mii = device_get_softc(sc->ste_miibus); 435 436 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 437 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } else { 439 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 440 } 441 STE_UNLOCK(sc); 442 443 return; 444} 445 446static int 447ste_ifmedia_upd(ifp) 448 struct ifnet *ifp; 449{ 450 struct ste_softc *sc; 451 struct mii_data *mii; 452 453 sc = ifp->if_softc; 454 mii = device_get_softc(sc->ste_miibus); 455 sc->ste_link = 0; 456 if (mii->mii_instance) { 457 struct mii_softc *miisc; 458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 459 mii_phy_reset(miisc); 460 } 461 mii_mediachg(mii); 462 463 return(0); 464} 465 466static void 467ste_ifmedia_sts(ifp, ifmr) 468 struct ifnet *ifp; 469 struct ifmediareq *ifmr; 470{ 471 struct ste_softc *sc; 472 struct mii_data *mii; 473 474 sc = ifp->if_softc; 475 mii = device_get_softc(sc->ste_miibus); 476 477 mii_pollstat(mii); 478 ifmr->ifm_active = mii->mii_media_active; 479 ifmr->ifm_status = mii->mii_media_status; 480 481 return; 482} 483 484static void 485ste_wait(sc) 486 struct ste_softc *sc; 487{ 488 register int i; 489 490 for (i = 0; i < STE_TIMEOUT; i++) { 491 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 492 break; 493 } 494 495 if (i == STE_TIMEOUT) 496 printf("ste%d: command never completed!\n", sc->ste_unit); 497 498 return; 499} 500 501/* 502 * The EEPROM is slow: give it time to come ready after issuing 503 * it a command. 504 */ 505static int 506ste_eeprom_wait(sc) 507 struct ste_softc *sc; 508{ 509 int i; 510 511 DELAY(1000); 512 513 for (i = 0; i < 100; i++) { 514 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 515 DELAY(1000); 516 else 517 break; 518 } 519 520 if (i == 100) { 521 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 522 return(1); 523 } 524 525 return(0); 526} 527 528/* 529 * Read a sequence of words from the EEPROM. Note that ethernet address 530 * data is stored in the EEPROM in network byte order. 531 */ 532static int 533ste_read_eeprom(sc, dest, off, cnt, swap) 534 struct ste_softc *sc; 535 caddr_t dest; 536 int off; 537 int cnt; 538 int swap; 539{ 540 int err = 0, i; 541 u_int16_t word = 0, *ptr; 542 543 if (ste_eeprom_wait(sc)) 544 return(1); 545 546 for (i = 0; i < cnt; i++) { 547 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 548 err = ste_eeprom_wait(sc); 549 if (err) 550 break; 551 word = CSR_READ_2(sc, STE_EEPROM_DATA); 552 ptr = (u_int16_t *)(dest + (i * 2)); 553 if (swap) 554 *ptr = ntohs(word); 555 else 556 *ptr = word; 557 } 558 559 return(err ? 1 : 0); 560} 561 562static void 563ste_setmulti(sc) 564 struct ste_softc *sc; 565{ 566 struct ifnet *ifp; 567 int h = 0; 568 u_int32_t hashes[2] = { 0, 0 }; 569 struct ifmultiaddr *ifma; 570 571 ifp = &sc->arpcom.ac_if; 572 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 573 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 574 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 575 return; 576 } 577 578 /* first, zot all the existing hash bits */ 579 CSR_WRITE_2(sc, STE_MAR0, 0); 580 CSR_WRITE_2(sc, STE_MAR1, 0); 581 CSR_WRITE_2(sc, STE_MAR2, 0); 582 CSR_WRITE_2(sc, STE_MAR3, 0); 583 584 /* now program new ones */ 585 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 586 if (ifma->ifma_addr->sa_family != AF_LINK) 587 continue; 588 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 589 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 590 if (h < 32) 591 hashes[0] |= (1 << h); 592 else 593 hashes[1] |= (1 << (h - 32)); 594 } 595 596 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 597 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 598 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 599 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 600 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 601 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 602 603 return; 604} 605 606#ifdef DEVICE_POLLING 607static poll_handler_t ste_poll; 608 609static void 610ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 611{ 612 struct ste_softc *sc = ifp->if_softc; 613 614 STE_LOCK(sc); 615 if (!(ifp->if_capenable & IFCAP_POLLING)) { 616 ether_poll_deregister(ifp); 617 cmd = POLL_DEREGISTER; 618 } 619 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 620 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 621 goto done; 622 } 623 624 sc->rxcycles = count; 625 if (cmd == POLL_AND_CHECK_STATUS) 626 ste_rxeoc(sc); 627 ste_rxeof(sc); 628 ste_txeof(sc); 629 if (ifp->if_snd.ifq_head != NULL) 630 ste_start(ifp); 631 632 if (cmd == POLL_AND_CHECK_STATUS) { 633 u_int16_t status; 634 635 status = CSR_READ_2(sc, STE_ISR_ACK); 636 637 if (status & STE_ISR_TX_DONE) 638 ste_txeoc(sc); 639 640 if (status & STE_ISR_STATS_OFLOW) { 641 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 642 ste_stats_update(sc); 643 } 644 645 if (status & STE_ISR_LINKEVENT) 646 mii_pollstat(device_get_softc(sc->ste_miibus)); 647 648 if (status & STE_ISR_HOSTERR) { 649 ste_reset(sc); 650 ste_init(sc); 651 } 652 } 653done: 654 STE_UNLOCK(sc); 655} 656#endif /* DEVICE_POLLING */ 657 658static void 659ste_intr(xsc) 660 void *xsc; 661{ 662 struct ste_softc *sc; 663 struct ifnet *ifp; 664 u_int16_t status; 665 666 sc = xsc; 667 STE_LOCK(sc); 668 ifp = &sc->arpcom.ac_if; 669 670#ifdef DEVICE_POLLING 671 if (ifp->if_flags & IFF_POLLING) 672 goto done; 673 if ((ifp->if_capenable & IFCAP_POLLING) && 674 ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 675 CSR_WRITE_2(sc, STE_IMR, 0); 676 ste_poll(ifp, 0, 1); 677 goto done; 678 } 679#endif /* DEVICE_POLLING */ 680 681 /* See if this is really our interrupt. */ 682 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 683 STE_UNLOCK(sc); 684 return; 685 } 686 687 for (;;) { 688 status = CSR_READ_2(sc, STE_ISR_ACK); 689 690 if (!(status & STE_INTRS)) 691 break; 692 693 if (status & STE_ISR_RX_DMADONE) { 694 ste_rxeoc(sc); 695 ste_rxeof(sc); 696 } 697 698 if (status & STE_ISR_TX_DMADONE) 699 ste_txeof(sc); 700 701 if (status & STE_ISR_TX_DONE) 702 ste_txeoc(sc); 703 704 if (status & STE_ISR_STATS_OFLOW) { 705 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 706 ste_stats_update(sc); 707 } 708 709 if (status & STE_ISR_LINKEVENT) 710 mii_pollstat(device_get_softc(sc->ste_miibus)); 711 712 713 if (status & STE_ISR_HOSTERR) { 714 ste_reset(sc); 715 ste_init(sc); 716 } 717 } 718 719 /* Re-enable interrupts */ 720 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 721 722 if (ifp->if_snd.ifq_head != NULL) 723 ste_start(ifp); 724 725#ifdef DEVICE_POLLING 726done: 727#endif /* DEVICE_POLLING */ 728 STE_UNLOCK(sc); 729 730 return; 731} 732 733static void 734ste_rxeoc(struct ste_softc *sc) 735{ 736 struct ste_chain_onefrag *cur_rx; 737 738 STE_LOCK_ASSERT(sc); 739 740 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 741 cur_rx = sc->ste_cdata.ste_rx_head; 742 do { 743 cur_rx = cur_rx->ste_next; 744 /* If the ring is empty, just return. */ 745 if (cur_rx == sc->ste_cdata.ste_rx_head) 746 return; 747 } while (cur_rx->ste_ptr->ste_status == 0); 748 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 749 /* We've fallen behind the chip: catch it. */ 750 sc->ste_cdata.ste_rx_head = cur_rx; 751 ++ste_rxsyncs; 752 } 753 } 754} 755 756/* 757 * A frame has been uploaded: pass the resulting mbuf chain up to 758 * the higher level protocols. 759 */ 760static void 761ste_rxeof(sc) 762 struct ste_softc *sc; 763{ 764 struct mbuf *m; 765 struct ifnet *ifp; 766 struct ste_chain_onefrag *cur_rx; 767 int total_len = 0, count=0; 768 u_int32_t rxstat; 769 770 STE_LOCK_ASSERT(sc); 771 772 ifp = &sc->arpcom.ac_if; 773 774 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 775 & STE_RXSTAT_DMADONE) { 776#ifdef DEVICE_POLLING 777 if (ifp->if_flags & IFF_POLLING) { 778 if (sc->rxcycles <= 0) 779 break; 780 sc->rxcycles--; 781 } 782#endif /* DEVICE_POLLING */ 783 if ((STE_RX_LIST_CNT - count) < 3) { 784 break; 785 } 786 787 cur_rx = sc->ste_cdata.ste_rx_head; 788 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 789 790 /* 791 * If an error occurs, update stats, clear the 792 * status word and leave the mbuf cluster in place: 793 * it should simply get re-used next time this descriptor 794 * comes up in the ring. 795 */ 796 if (rxstat & STE_RXSTAT_FRAME_ERR) { 797 ifp->if_ierrors++; 798 cur_rx->ste_ptr->ste_status = 0; 799 continue; 800 } 801 802 /* 803 * If there error bit was not set, the upload complete 804 * bit should be set which means we have a valid packet. 805 * If not, something truly strange has happened. 806 */ 807 if (!(rxstat & STE_RXSTAT_DMADONE)) { 808 printf("ste%d: bad receive status -- packet dropped\n", 809 sc->ste_unit); 810 ifp->if_ierrors++; 811 cur_rx->ste_ptr->ste_status = 0; 812 continue; 813 } 814 815 /* No errors; receive the packet. */ 816 m = cur_rx->ste_mbuf; 817 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 818 819 /* 820 * Try to conjure up a new mbuf cluster. If that 821 * fails, it means we have an out of memory condition and 822 * should leave the buffer in place and continue. This will 823 * result in a lost packet, but there's little else we 824 * can do in this situation. 825 */ 826 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 827 ifp->if_ierrors++; 828 cur_rx->ste_ptr->ste_status = 0; 829 continue; 830 } 831 832 m->m_pkthdr.rcvif = ifp; 833 m->m_pkthdr.len = m->m_len = total_len; 834 835 ifp->if_ipackets++; 836 STE_UNLOCK(sc); 837 (*ifp->if_input)(ifp, m); 838 STE_LOCK(sc); 839 840 cur_rx->ste_ptr->ste_status = 0; 841 count++; 842 } 843 844 return; 845} 846 847static void 848ste_txeoc(sc) 849 struct ste_softc *sc; 850{ 851 u_int8_t txstat; 852 struct ifnet *ifp; 853 854 ifp = &sc->arpcom.ac_if; 855 856 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 857 STE_TXSTATUS_TXDONE) { 858 if (txstat & STE_TXSTATUS_UNDERRUN || 859 txstat & STE_TXSTATUS_EXCESSCOLLS || 860 txstat & STE_TXSTATUS_RECLAIMERR) { 861 ifp->if_oerrors++; 862 printf("ste%d: transmission error: %x\n", 863 sc->ste_unit, txstat); 864 865 ste_reset(sc); 866 ste_init(sc); 867 868 if (txstat & STE_TXSTATUS_UNDERRUN && 869 sc->ste_tx_thresh < STE_PACKET_SIZE) { 870 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 871 printf("ste%d: tx underrun, increasing tx" 872 " start threshold to %d bytes\n", 873 sc->ste_unit, sc->ste_tx_thresh); 874 } 875 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 876 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 877 (STE_PACKET_SIZE >> 4)); 878 } 879 ste_init(sc); 880 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 881 } 882 883 return; 884} 885 886static void 887ste_txeof(sc) 888 struct ste_softc *sc; 889{ 890 struct ste_chain *cur_tx; 891 struct ifnet *ifp; 892 int idx; 893 894 ifp = &sc->arpcom.ac_if; 895 896 idx = sc->ste_cdata.ste_tx_cons; 897 while(idx != sc->ste_cdata.ste_tx_prod) { 898 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 899 900 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 901 break; 902 903 m_freem(cur_tx->ste_mbuf); 904 cur_tx->ste_mbuf = NULL; 905 ifp->if_flags &= ~IFF_OACTIVE; 906 ifp->if_opackets++; 907 908 STE_INC(idx, STE_TX_LIST_CNT); 909 } 910 911 sc->ste_cdata.ste_tx_cons = idx; 912 if (idx == sc->ste_cdata.ste_tx_prod) 913 ifp->if_timer = 0; 914} 915 916static void 917ste_stats_update(xsc) 918 void *xsc; 919{ 920 struct ste_softc *sc; 921 struct ifnet *ifp; 922 struct mii_data *mii; 923 924 sc = xsc; 925 STE_LOCK(sc); 926 927 ifp = &sc->arpcom.ac_if; 928 mii = device_get_softc(sc->ste_miibus); 929 930 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 931 + CSR_READ_1(sc, STE_MULTI_COLLS) 932 + CSR_READ_1(sc, STE_SINGLE_COLLS); 933 934 if (!sc->ste_link) { 935 mii_pollstat(mii); 936 if (mii->mii_media_status & IFM_ACTIVE && 937 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 938 sc->ste_link++; 939 /* 940 * we don't get a call-back on re-init so do it 941 * otherwise we get stuck in the wrong link state 942 */ 943 ste_miibus_statchg(sc->ste_dev); 944 if (ifp->if_snd.ifq_head != NULL) 945 ste_start(ifp); 946 } 947 } 948 949 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 950 STE_UNLOCK(sc); 951 952 return; 953} 954 955 956/* 957 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 958 * IDs against our list and return a device name if we find a match. 959 */ 960static int 961ste_probe(dev) 962 device_t dev; 963{ 964 struct ste_type *t; 965 966 t = ste_devs; 967 968 while(t->ste_name != NULL) { 969 if ((pci_get_vendor(dev) == t->ste_vid) && 970 (pci_get_device(dev) == t->ste_did)) { 971 device_set_desc(dev, t->ste_name); 972 return(0); 973 } 974 t++; 975 } 976 977 return(ENXIO); 978} 979 980/* 981 * Attach the interface. Allocate softc structures, do ifmedia 982 * setup and ethernet/BPF attach. 983 */ 984static int 985ste_attach(dev) 986 device_t dev; 987{ 988 struct ste_softc *sc; 989 struct ifnet *ifp; 990 int unit, error = 0, rid; 991 992 sc = device_get_softc(dev); 993 unit = device_get_unit(dev); 994 sc->ste_dev = dev; 995 996 /* 997 * Only use one PHY since this chip reports multiple 998 * Note on the DFE-550 the PHY is at 1 on the DFE-580 999 * it is at 0 & 1. It is rev 0x12. 1000 */ 1001 if (pci_get_vendor(dev) == DL_VENDORID && 1002 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1003 pci_get_revid(dev) == 0x12 ) 1004 sc->ste_one_phy = 1; 1005 1006 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1007 MTX_DEF | MTX_RECURSE); 1008 /* 1009 * Map control/status registers. 1010 */ 1011 pci_enable_busmaster(dev); 1012 1013 rid = STE_RID; 1014 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1015 1016 if (sc->ste_res == NULL) { 1017 printf ("ste%d: couldn't map ports/memory\n", unit); 1018 error = ENXIO; 1019 goto fail; 1020 } 1021 1022 sc->ste_btag = rman_get_bustag(sc->ste_res); 1023 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1024 1025 /* Allocate interrupt */ 1026 rid = 0; 1027 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1028 RF_SHAREABLE | RF_ACTIVE); 1029 1030 if (sc->ste_irq == NULL) { 1031 printf("ste%d: couldn't map interrupt\n", unit); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 callout_handle_init(&sc->ste_stat_ch); 1037 1038 /* Reset the adapter. */ 1039 ste_reset(sc); 1040 1041 /* 1042 * Get station address from the EEPROM. 1043 */ 1044 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1045 STE_EEADDR_NODE0, 3, 0)) { 1046 printf("ste%d: failed to read station address\n", unit); 1047 error = ENXIO;; 1048 goto fail; 1049 } 1050 1051 sc->ste_unit = unit; 1052 1053 /* Allocate the descriptor queues. */ 1054 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1055 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1056 1057 if (sc->ste_ldata == NULL) { 1058 printf("ste%d: no memory for list buffers!\n", unit); 1059 error = ENXIO; 1060 goto fail; 1061 } 1062 1063 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1064 1065 /* Do MII setup. */ 1066 if (mii_phy_probe(dev, &sc->ste_miibus, 1067 ste_ifmedia_upd, ste_ifmedia_sts)) { 1068 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1069 error = ENXIO; 1070 goto fail; 1071 } 1072 1073 ifp = &sc->arpcom.ac_if; 1074 ifp->if_softc = sc; 1075 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1076 ifp->if_mtu = ETHERMTU; 1077 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 1078 IFF_NEEDSGIANT; 1079 ifp->if_ioctl = ste_ioctl; 1080 ifp->if_start = ste_start; 1081 ifp->if_watchdog = ste_watchdog; 1082 ifp->if_init = ste_init; 1083 ifp->if_baudrate = 10000000; 1084 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1085 1086 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1087 1088 /* 1089 * Call MI attach routine. 1090 */ 1091 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1092 1093 /* 1094 * Tell the upper layer(s) we support long frames. 1095 */ 1096 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1097 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1098#ifdef DEVICE_POLLING 1099 ifp->if_capabilities |= IFCAP_POLLING; 1100#endif 1101 ifp->if_capenable = ifp->if_capabilities; 1102 1103 /* Hook interrupt last to avoid having to lock softc */ 1104 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1105 ste_intr, sc, &sc->ste_intrhand); 1106 1107 if (error) { 1108 printf("ste%d: couldn't set up irq\n", unit); 1109 ether_ifdetach(ifp); 1110 goto fail; 1111 } 1112 1113fail: 1114 if (error) 1115 ste_detach(dev); 1116 1117 return(error); 1118} 1119 1120/* 1121 * Shutdown hardware and free up resources. This can be called any 1122 * time after the mutex has been initialized. It is called in both 1123 * the error case in attach and the normal detach case so it needs 1124 * to be careful about only freeing resources that have actually been 1125 * allocated. 1126 */ 1127static int 1128ste_detach(dev) 1129 device_t dev; 1130{ 1131 struct ste_softc *sc; 1132 struct ifnet *ifp; 1133 1134 sc = device_get_softc(dev); 1135 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1136 STE_LOCK(sc); 1137 ifp = &sc->arpcom.ac_if; 1138 1139 /* These should only be active if attach succeeded */ 1140 if (device_is_attached(dev)) { 1141 ste_stop(sc); 1142 ether_ifdetach(ifp); 1143 } 1144 if (sc->ste_miibus) 1145 device_delete_child(dev, sc->ste_miibus); 1146 bus_generic_detach(dev); 1147 1148 if (sc->ste_intrhand) 1149 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1150 if (sc->ste_irq) 1151 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1152 if (sc->ste_res) 1153 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1154 1155 if (sc->ste_ldata) { 1156 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1157 M_DEVBUF); 1158 } 1159 1160 STE_UNLOCK(sc); 1161 mtx_destroy(&sc->ste_mtx); 1162 1163 return(0); 1164} 1165 1166static int 1167ste_newbuf(sc, c, m) 1168 struct ste_softc *sc; 1169 struct ste_chain_onefrag *c; 1170 struct mbuf *m; 1171{ 1172 struct mbuf *m_new = NULL; 1173 1174 if (m == NULL) { 1175 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1176 if (m_new == NULL) 1177 return(ENOBUFS); 1178 MCLGET(m_new, M_DONTWAIT); 1179 if (!(m_new->m_flags & M_EXT)) { 1180 m_freem(m_new); 1181 return(ENOBUFS); 1182 } 1183 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1184 } else { 1185 m_new = m; 1186 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1187 m_new->m_data = m_new->m_ext.ext_buf; 1188 } 1189 1190 m_adj(m_new, ETHER_ALIGN); 1191 1192 c->ste_mbuf = m_new; 1193 c->ste_ptr->ste_status = 0; 1194 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1195 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1196 1197 return(0); 1198} 1199 1200static int 1201ste_init_rx_list(sc) 1202 struct ste_softc *sc; 1203{ 1204 struct ste_chain_data *cd; 1205 struct ste_list_data *ld; 1206 int i; 1207 1208 cd = &sc->ste_cdata; 1209 ld = sc->ste_ldata; 1210 1211 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1212 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1213 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1214 return(ENOBUFS); 1215 if (i == (STE_RX_LIST_CNT - 1)) { 1216 cd->ste_rx_chain[i].ste_next = 1217 &cd->ste_rx_chain[0]; 1218 ld->ste_rx_list[i].ste_next = 1219 vtophys(&ld->ste_rx_list[0]); 1220 } else { 1221 cd->ste_rx_chain[i].ste_next = 1222 &cd->ste_rx_chain[i + 1]; 1223 ld->ste_rx_list[i].ste_next = 1224 vtophys(&ld->ste_rx_list[i + 1]); 1225 } 1226 ld->ste_rx_list[i].ste_status = 0; 1227 } 1228 1229 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1230 1231 return(0); 1232} 1233 1234static void 1235ste_init_tx_list(sc) 1236 struct ste_softc *sc; 1237{ 1238 struct ste_chain_data *cd; 1239 struct ste_list_data *ld; 1240 int i; 1241 1242 cd = &sc->ste_cdata; 1243 ld = sc->ste_ldata; 1244 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1245 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1246 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1247 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1248 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1249 if (i == (STE_TX_LIST_CNT - 1)) 1250 cd->ste_tx_chain[i].ste_next = 1251 &cd->ste_tx_chain[0]; 1252 else 1253 cd->ste_tx_chain[i].ste_next = 1254 &cd->ste_tx_chain[i + 1]; 1255 } 1256 1257 cd->ste_tx_prod = 0; 1258 cd->ste_tx_cons = 0; 1259 1260 return; 1261} 1262 1263static void 1264ste_init(xsc) 1265 void *xsc; 1266{ 1267 struct ste_softc *sc; 1268 int i; 1269 struct ifnet *ifp; 1270 1271 sc = xsc; 1272 STE_LOCK(sc); 1273 ifp = &sc->arpcom.ac_if; 1274 1275 ste_stop(sc); 1276 1277 /* Init our MAC address */ 1278 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1279 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1280 } 1281 1282 /* Init RX list */ 1283 if (ste_init_rx_list(sc) == ENOBUFS) { 1284 printf("ste%d: initialization failed: no " 1285 "memory for RX buffers\n", sc->ste_unit); 1286 ste_stop(sc); 1287 STE_UNLOCK(sc); 1288 return; 1289 } 1290 1291 /* Set RX polling interval */ 1292 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1293 1294 /* Init TX descriptors */ 1295 ste_init_tx_list(sc); 1296 1297 /* Set the TX freethresh value */ 1298 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1299 1300 /* Set the TX start threshold for best performance. */ 1301 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1302 1303 /* Set the TX reclaim threshold. */ 1304 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1305 1306 /* Set up the RX filter. */ 1307 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1308 1309 /* If we want promiscuous mode, set the allframes bit. */ 1310 if (ifp->if_flags & IFF_PROMISC) { 1311 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1312 } else { 1313 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1314 } 1315 1316 /* Set capture broadcast bit to accept broadcast frames. */ 1317 if (ifp->if_flags & IFF_BROADCAST) { 1318 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1319 } else { 1320 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1321 } 1322 1323 ste_setmulti(sc); 1324 1325 /* Load the address of the RX list. */ 1326 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1327 ste_wait(sc); 1328 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1329 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1330 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1331 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1332 1333 /* Set TX polling interval (defer until we TX first packet */ 1334 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1335 1336 /* Load address of the TX list */ 1337 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1338 ste_wait(sc); 1339 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1340 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1341 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1342 ste_wait(sc); 1343 sc->ste_tx_prev = NULL; 1344 1345 /* Enable receiver and transmitter */ 1346 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1347 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1348 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1349 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1350 1351 /* Enable stats counters. */ 1352 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1353 1354 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1355#ifdef DEVICE_POLLING 1356 /* Disable interrupts if we are polling. */ 1357 if (ifp->if_flags & IFF_POLLING) 1358 CSR_WRITE_2(sc, STE_IMR, 0); 1359 else 1360#endif /* DEVICE_POLLING */ 1361 /* Enable interrupts. */ 1362 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1363 1364 /* Accept VLAN length packets */ 1365 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1366 1367 ste_ifmedia_upd(ifp); 1368 1369 ifp->if_flags |= IFF_RUNNING; 1370 ifp->if_flags &= ~IFF_OACTIVE; 1371 1372 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1373 STE_UNLOCK(sc); 1374 1375 return; 1376} 1377 1378static void 1379ste_stop(sc) 1380 struct ste_softc *sc; 1381{ 1382 int i; 1383 struct ifnet *ifp; 1384 1385 STE_LOCK(sc); 1386 ifp = &sc->arpcom.ac_if; 1387 1388 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1389 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1390#ifdef DEVICE_POLLING 1391 ether_poll_deregister(ifp); 1392#endif /* DEVICE_POLLING */ 1393 1394 CSR_WRITE_2(sc, STE_IMR, 0); 1395 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1396 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1397 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1398 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1399 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1400 ste_wait(sc); 1401 /* 1402 * Try really hard to stop the RX engine or under heavy RX 1403 * data chip will write into de-allocated memory. 1404 */ 1405 ste_reset(sc); 1406 1407 sc->ste_link = 0; 1408 1409 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1410 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1411 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1412 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1413 } 1414 } 1415 1416 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1417 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1418 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1419 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1420 } 1421 } 1422 1423 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1424 STE_UNLOCK(sc); 1425 1426 return; 1427} 1428 1429static void 1430ste_reset(sc) 1431 struct ste_softc *sc; 1432{ 1433 int i; 1434 1435 STE_SETBIT4(sc, STE_ASICCTL, 1436 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1437 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1438 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1439 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1440 STE_ASICCTL_EXTRESET_RESET); 1441 1442 DELAY(100000); 1443 1444 for (i = 0; i < STE_TIMEOUT; i++) { 1445 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1446 break; 1447 } 1448 1449 if (i == STE_TIMEOUT) 1450 printf("ste%d: global reset never completed\n", sc->ste_unit); 1451 1452 return; 1453} 1454 1455static int 1456ste_ioctl(ifp, command, data) 1457 struct ifnet *ifp; 1458 u_long command; 1459 caddr_t data; 1460{ 1461 struct ste_softc *sc; 1462 struct ifreq *ifr; 1463 struct mii_data *mii; 1464 int error = 0; 1465 1466 sc = ifp->if_softc; 1467 STE_LOCK(sc); 1468 ifr = (struct ifreq *)data; 1469 1470 switch(command) { 1471 case SIOCSIFFLAGS: 1472 if (ifp->if_flags & IFF_UP) { 1473 if (ifp->if_flags & IFF_RUNNING && 1474 ifp->if_flags & IFF_PROMISC && 1475 !(sc->ste_if_flags & IFF_PROMISC)) { 1476 STE_SETBIT1(sc, STE_RX_MODE, 1477 STE_RXMODE_PROMISC); 1478 } else if (ifp->if_flags & IFF_RUNNING && 1479 !(ifp->if_flags & IFF_PROMISC) && 1480 sc->ste_if_flags & IFF_PROMISC) { 1481 STE_CLRBIT1(sc, STE_RX_MODE, 1482 STE_RXMODE_PROMISC); 1483 } 1484 if (ifp->if_flags & IFF_RUNNING && 1485 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1486 ste_setmulti(sc); 1487 if (!(ifp->if_flags & IFF_RUNNING)) { 1488 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1489 ste_init(sc); 1490 } 1491 } else { 1492 if (ifp->if_flags & IFF_RUNNING) 1493 ste_stop(sc); 1494 } 1495 sc->ste_if_flags = ifp->if_flags; 1496 error = 0; 1497 break; 1498 case SIOCADDMULTI: 1499 case SIOCDELMULTI: 1500 ste_setmulti(sc); 1501 error = 0; 1502 break; 1503 case SIOCGIFMEDIA: 1504 case SIOCSIFMEDIA: 1505 mii = device_get_softc(sc->ste_miibus); 1506 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1507 break; 1508 case SIOCSIFCAP: 1509 ifp->if_capenable &= ~IFCAP_POLLING; 1510 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1511 break; 1512 default: 1513 error = ether_ioctl(ifp, command, data); 1514 break; 1515 } 1516 1517 STE_UNLOCK(sc); 1518 1519 return(error); 1520} 1521 1522static int 1523ste_encap(sc, c, m_head) 1524 struct ste_softc *sc; 1525 struct ste_chain *c; 1526 struct mbuf *m_head; 1527{ 1528 int frag = 0; 1529 struct ste_frag *f = NULL; 1530 struct mbuf *m; 1531 struct ste_desc *d; 1532 1533 d = c->ste_ptr; 1534 d->ste_ctl = 0; 1535 1536encap_retry: 1537 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1538 if (m->m_len != 0) { 1539 if (frag == STE_MAXFRAGS) 1540 break; 1541 f = &d->ste_frags[frag]; 1542 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1543 f->ste_len = m->m_len; 1544 frag++; 1545 } 1546 } 1547 1548 if (m != NULL) { 1549 struct mbuf *mn; 1550 1551 /* 1552 * We ran out of segments. We have to recopy this 1553 * mbuf chain first. Bail out if we can't get the 1554 * new buffers. 1555 */ 1556 mn = m_defrag(m_head, M_DONTWAIT); 1557 if (mn == NULL) { 1558 m_freem(m_head); 1559 return ENOMEM; 1560 } 1561 m_head = mn; 1562 goto encap_retry; 1563 } 1564 1565 c->ste_mbuf = m_head; 1566 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1567 d->ste_ctl = 1; 1568 1569 return(0); 1570} 1571 1572static void 1573ste_start(ifp) 1574 struct ifnet *ifp; 1575{ 1576 struct ste_softc *sc; 1577 struct mbuf *m_head = NULL; 1578 struct ste_chain *cur_tx; 1579 int idx; 1580 1581 sc = ifp->if_softc; 1582 STE_LOCK(sc); 1583 1584 if (!sc->ste_link) { 1585 STE_UNLOCK(sc); 1586 return; 1587 } 1588 1589 if (ifp->if_flags & IFF_OACTIVE) { 1590 STE_UNLOCK(sc); 1591 return; 1592 } 1593 1594 idx = sc->ste_cdata.ste_tx_prod; 1595 1596 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1597 /* 1598 * We cannot re-use the last (free) descriptor; 1599 * the chip may not have read its ste_next yet. 1600 */ 1601 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1602 sc->ste_cdata.ste_tx_cons) { 1603 ifp->if_flags |= IFF_OACTIVE; 1604 break; 1605 } 1606 1607 IF_DEQUEUE(&ifp->if_snd, m_head); 1608 if (m_head == NULL) 1609 break; 1610 1611 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1612 1613 if (ste_encap(sc, cur_tx, m_head) != 0) 1614 break; 1615 1616 cur_tx->ste_ptr->ste_next = 0; 1617 1618 if (sc->ste_tx_prev == NULL) { 1619 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1620 /* Load address of the TX list */ 1621 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1622 ste_wait(sc); 1623 1624 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1625 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1626 1627 /* Set TX polling interval to start TX engine */ 1628 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1629 1630 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1631 ste_wait(sc); 1632 }else{ 1633 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1634 sc->ste_tx_prev->ste_ptr->ste_next 1635 = cur_tx->ste_phys; 1636 } 1637 1638 sc->ste_tx_prev = cur_tx; 1639 1640 /* 1641 * If there's a BPF listener, bounce a copy of this frame 1642 * to him. 1643 */ 1644 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1645 1646 STE_INC(idx, STE_TX_LIST_CNT); 1647 ifp->if_timer = 5; 1648 } 1649 sc->ste_cdata.ste_tx_prod = idx; 1650 1651 STE_UNLOCK(sc); 1652 1653 return; 1654} 1655 1656static void 1657ste_watchdog(ifp) 1658 struct ifnet *ifp; 1659{ 1660 struct ste_softc *sc; 1661 1662 sc = ifp->if_softc; 1663 STE_LOCK(sc); 1664 1665 ifp->if_oerrors++; 1666 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1667 1668 ste_txeoc(sc); 1669 ste_txeof(sc); 1670 ste_rxeoc(sc); 1671 ste_rxeof(sc); 1672 ste_reset(sc); 1673 ste_init(sc); 1674 1675 if (ifp->if_snd.ifq_head != NULL) 1676 ste_start(ifp); 1677 STE_UNLOCK(sc); 1678 1679 return; 1680} 1681 1682static void 1683ste_shutdown(dev) 1684 device_t dev; 1685{ 1686 struct ste_softc *sc; 1687 1688 sc = device_get_softc(dev); 1689 1690 ste_stop(sc); 1691 1692 return; 1693} 1694