if_ste.c revision 129633
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 129633 2004-05-23 21:05:08Z yar $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44 45#include <net/if.h> 46#include <net/if_arp.h> 47#include <net/ethernet.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <vm/vm.h> /* for vtophys */ 55#include <vm/pmap.h> /* for vtophys */ 56#include <machine/bus_memio.h> 57#include <machine/bus_pio.h> 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69/* "controller miibus0" required. See GENERIC if you get errors here. */ 70#include "miibus_if.h" 71 72#define STE_USEIOSPACE 73 74#include <pci/if_stereg.h> 75 76MODULE_DEPEND(ste, pci, 1, 1, 1); 77MODULE_DEPEND(ste, ether, 1, 1, 1); 78MODULE_DEPEND(ste, miibus, 1, 1, 1); 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe (device_t); 90static int ste_attach (device_t); 91static int ste_detach (device_t); 92static void ste_init (void *); 93static void ste_intr (void *); 94static void ste_rxeoc (struct ste_softc *); 95static void ste_rxeof (struct ste_softc *); 96static void ste_txeoc (struct ste_softc *); 97static void ste_txeof (struct ste_softc *); 98static void ste_stats_update (void *); 99static void ste_stop (struct ste_softc *); 100static void ste_reset (struct ste_softc *); 101static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104static void ste_start (struct ifnet *); 105static void ste_watchdog (struct ifnet *); 106static void ste_shutdown (device_t); 107static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd (struct ifnet *); 111static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113static void ste_mii_sync (struct ste_softc *); 114static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg (device_t, int, int); 118static int ste_miibus_writereg (device_t, int, int, int); 119static void ste_miibus_statchg (device_t); 120 121static int ste_eeprom_wait (struct ste_softc *); 122static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123static void ste_wait (struct ste_softc *); 124static u_int8_t ste_calchash (caddr_t); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 168 169static int ste_rxsyncs; 170SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 171 172#define STE_SETBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 174 175#define STE_CLRBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 177 178#define STE_SETBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 180 181#define STE_CLRBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 183 184#define STE_SETBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186 187#define STE_CLRBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 189 190 191#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 192#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 193 194/* 195 * Sync the PHYs by setting data bit and strobing the clock 32 times. 196 */ 197static void 198ste_mii_sync(sc) 199 struct ste_softc *sc; 200{ 201 register int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211 212 return; 213} 214 215/* 216 * Clock a series of bits through the MII. 217 */ 218static void 219ste_mii_send(sc, bits, cnt) 220 struct ste_softc *sc; 221 u_int32_t bits; 222 int cnt; 223{ 224 int i; 225 226 MII_CLR(STE_PHYCTL_MCLK); 227 228 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 229 if (bits & i) { 230 MII_SET(STE_PHYCTL_MDATA); 231 } else { 232 MII_CLR(STE_PHYCTL_MDATA); 233 } 234 DELAY(1); 235 MII_CLR(STE_PHYCTL_MCLK); 236 DELAY(1); 237 MII_SET(STE_PHYCTL_MCLK); 238 } 239} 240 241/* 242 * Read an PHY register through the MII. 243 */ 244static int 245ste_mii_readreg(sc, frame) 246 struct ste_softc *sc; 247 struct ste_mii_frame *frame; 248 249{ 250 int i, ack; 251 252 STE_LOCK(sc); 253 254 /* 255 * Set up frame for RX. 256 */ 257 frame->mii_stdelim = STE_MII_STARTDELIM; 258 frame->mii_opcode = STE_MII_READOP; 259 frame->mii_turnaround = 0; 260 frame->mii_data = 0; 261 262 CSR_WRITE_2(sc, STE_PHYCTL, 0); 263 /* 264 * Turn on data xmit. 265 */ 266 MII_SET(STE_PHYCTL_MDIR); 267 268 ste_mii_sync(sc); 269 270 /* 271 * Send command/address info. 272 */ 273 ste_mii_send(sc, frame->mii_stdelim, 2); 274 ste_mii_send(sc, frame->mii_opcode, 2); 275 ste_mii_send(sc, frame->mii_phyaddr, 5); 276 ste_mii_send(sc, frame->mii_regaddr, 5); 277 278 /* Turn off xmit. */ 279 MII_CLR(STE_PHYCTL_MDIR); 280 281 /* Idle bit */ 282 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 283 DELAY(1); 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* Check for ack */ 288 MII_CLR(STE_PHYCTL_MCLK); 289 DELAY(1); 290 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 291 MII_SET(STE_PHYCTL_MCLK); 292 DELAY(1); 293 294 /* 295 * Now try reading data bits. If the ack failed, we still 296 * need to clock through 16 cycles to keep the PHY(s) in sync. 297 */ 298 if (ack) { 299 for(i = 0; i < 16; i++) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 MII_SET(STE_PHYCTL_MCLK); 303 DELAY(1); 304 } 305 goto fail; 306 } 307 308 for (i = 0x8000; i; i >>= 1) { 309 MII_CLR(STE_PHYCTL_MCLK); 310 DELAY(1); 311 if (!ack) { 312 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 313 frame->mii_data |= i; 314 DELAY(1); 315 } 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 } 319 320fail: 321 322 MII_CLR(STE_PHYCTL_MCLK); 323 DELAY(1); 324 MII_SET(STE_PHYCTL_MCLK); 325 DELAY(1); 326 327 STE_UNLOCK(sc); 328 329 if (ack) 330 return(1); 331 return(0); 332} 333 334/* 335 * Write to a PHY register through the MII. 336 */ 337static int 338ste_mii_writereg(sc, frame) 339 struct ste_softc *sc; 340 struct ste_mii_frame *frame; 341 342{ 343 STE_LOCK(sc); 344 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 STE_UNLOCK(sc); 379 380 return(0); 381} 382 383static int 384ste_miibus_readreg(dev, phy, reg) 385 device_t dev; 386 int phy, reg; 387{ 388 struct ste_softc *sc; 389 struct ste_mii_frame frame; 390 391 sc = device_get_softc(dev); 392 393 if ( sc->ste_one_phy && phy != 0 ) 394 return (0); 395 396 bzero((char *)&frame, sizeof(frame)); 397 398 frame.mii_phyaddr = phy; 399 frame.mii_regaddr = reg; 400 ste_mii_readreg(sc, &frame); 401 402 return(frame.mii_data); 403} 404 405static int 406ste_miibus_writereg(dev, phy, reg, data) 407 device_t dev; 408 int phy, reg, data; 409{ 410 struct ste_softc *sc; 411 struct ste_mii_frame frame; 412 413 sc = device_get_softc(dev); 414 bzero((char *)&frame, sizeof(frame)); 415 416 frame.mii_phyaddr = phy; 417 frame.mii_regaddr = reg; 418 frame.mii_data = data; 419 420 ste_mii_writereg(sc, &frame); 421 422 return(0); 423} 424 425static void 426ste_miibus_statchg(dev) 427 device_t dev; 428{ 429 struct ste_softc *sc; 430 struct mii_data *mii; 431 432 sc = device_get_softc(dev); 433 STE_LOCK(sc); 434 mii = device_get_softc(sc->ste_miibus); 435 436 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 437 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } else { 439 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 440 } 441 STE_UNLOCK(sc); 442 443 return; 444} 445 446static int 447ste_ifmedia_upd(ifp) 448 struct ifnet *ifp; 449{ 450 struct ste_softc *sc; 451 struct mii_data *mii; 452 453 sc = ifp->if_softc; 454 mii = device_get_softc(sc->ste_miibus); 455 sc->ste_link = 0; 456 if (mii->mii_instance) { 457 struct mii_softc *miisc; 458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 459 mii_phy_reset(miisc); 460 } 461 mii_mediachg(mii); 462 463 return(0); 464} 465 466static void 467ste_ifmedia_sts(ifp, ifmr) 468 struct ifnet *ifp; 469 struct ifmediareq *ifmr; 470{ 471 struct ste_softc *sc; 472 struct mii_data *mii; 473 474 sc = ifp->if_softc; 475 mii = device_get_softc(sc->ste_miibus); 476 477 mii_pollstat(mii); 478 ifmr->ifm_active = mii->mii_media_active; 479 ifmr->ifm_status = mii->mii_media_status; 480 481 return; 482} 483 484static void 485ste_wait(sc) 486 struct ste_softc *sc; 487{ 488 register int i; 489 490 for (i = 0; i < STE_TIMEOUT; i++) { 491 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 492 break; 493 } 494 495 if (i == STE_TIMEOUT) 496 printf("ste%d: command never completed!\n", sc->ste_unit); 497 498 return; 499} 500 501/* 502 * The EEPROM is slow: give it time to come ready after issuing 503 * it a command. 504 */ 505static int 506ste_eeprom_wait(sc) 507 struct ste_softc *sc; 508{ 509 int i; 510 511 DELAY(1000); 512 513 for (i = 0; i < 100; i++) { 514 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 515 DELAY(1000); 516 else 517 break; 518 } 519 520 if (i == 100) { 521 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 522 return(1); 523 } 524 525 return(0); 526} 527 528/* 529 * Read a sequence of words from the EEPROM. Note that ethernet address 530 * data is stored in the EEPROM in network byte order. 531 */ 532static int 533ste_read_eeprom(sc, dest, off, cnt, swap) 534 struct ste_softc *sc; 535 caddr_t dest; 536 int off; 537 int cnt; 538 int swap; 539{ 540 int err = 0, i; 541 u_int16_t word = 0, *ptr; 542 543 if (ste_eeprom_wait(sc)) 544 return(1); 545 546 for (i = 0; i < cnt; i++) { 547 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 548 err = ste_eeprom_wait(sc); 549 if (err) 550 break; 551 word = CSR_READ_2(sc, STE_EEPROM_DATA); 552 ptr = (u_int16_t *)(dest + (i * 2)); 553 if (swap) 554 *ptr = ntohs(word); 555 else 556 *ptr = word; 557 } 558 559 return(err ? 1 : 0); 560} 561 562static u_int8_t 563ste_calchash(addr) 564 caddr_t addr; 565{ 566 567 u_int32_t crc, carry; 568 int i, j; 569 u_int8_t c; 570 571 /* Compute CRC for the address value. */ 572 crc = 0xFFFFFFFF; /* initial value */ 573 574 for (i = 0; i < 6; i++) { 575 c = *(addr + i); 576 for (j = 0; j < 8; j++) { 577 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 578 crc <<= 1; 579 c >>= 1; 580 if (carry) 581 crc = (crc ^ 0x04c11db6) | carry; 582 } 583 } 584 585 /* return the filter bit position */ 586 return(crc & 0x0000003F); 587} 588 589static void 590ste_setmulti(sc) 591 struct ste_softc *sc; 592{ 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 598 ifp = &sc->arpcom.ac_if; 599 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 600 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 601 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 602 return; 603 } 604 605 /* first, zot all the existing hash bits */ 606 CSR_WRITE_2(sc, STE_MAR0, 0); 607 CSR_WRITE_2(sc, STE_MAR1, 0); 608 CSR_WRITE_2(sc, STE_MAR2, 0); 609 CSR_WRITE_2(sc, STE_MAR3, 0); 610 611 /* now program new ones */ 612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 613 if (ifma->ifma_addr->sa_family != AF_LINK) 614 continue; 615 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 616 if (h < 32) 617 hashes[0] |= (1 << h); 618 else 619 hashes[1] |= (1 << (h - 32)); 620 } 621 622 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 623 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 624 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 625 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 626 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 627 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 628 629 return; 630} 631 632#ifdef DEVICE_POLLING 633static poll_handler_t ste_poll; 634 635static void 636ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 637{ 638 struct ste_softc *sc = ifp->if_softc; 639 640 STE_LOCK(sc); 641 if (!(ifp->if_capenable & IFCAP_POLLING)) { 642 ether_poll_deregister(ifp); 643 cmd = POLL_DEREGISTER; 644 } 645 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 646 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 647 goto done; 648 } 649 650 sc->rxcycles = count; 651 if (cmd == POLL_AND_CHECK_STATUS) 652 ste_rxeoc(sc); 653 ste_rxeof(sc); 654 ste_txeof(sc); 655 if (ifp->if_snd.ifq_head != NULL) 656 ste_start(ifp); 657 658 if (cmd == POLL_AND_CHECK_STATUS) { 659 u_int16_t status; 660 661 status = CSR_READ_2(sc, STE_ISR_ACK); 662 663 if (status & STE_ISR_TX_DONE) 664 ste_txeoc(sc); 665 666 if (status & STE_ISR_STATS_OFLOW) { 667 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 668 ste_stats_update(sc); 669 } 670 671 if (status & STE_ISR_LINKEVENT) 672 mii_pollstat(device_get_softc(sc->ste_miibus)); 673 674 if (status & STE_ISR_HOSTERR) { 675 ste_reset(sc); 676 ste_init(sc); 677 } 678 } 679done: 680 STE_UNLOCK(sc); 681} 682#endif /* DEVICE_POLLING */ 683 684static void 685ste_intr(xsc) 686 void *xsc; 687{ 688 struct ste_softc *sc; 689 struct ifnet *ifp; 690 u_int16_t status; 691 692 sc = xsc; 693 STE_LOCK(sc); 694 ifp = &sc->arpcom.ac_if; 695 696#ifdef DEVICE_POLLING 697 if (ifp->if_flags & IFF_POLLING) 698 goto done; 699 if ((ifp->if_capenable & IFCAP_POLLING) && 700 ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 701 CSR_WRITE_2(sc, STE_IMR, 0); 702 ste_poll(ifp, 0, 1); 703 goto done; 704 } 705#endif /* DEVICE_POLLING */ 706 707 /* See if this is really our interrupt. */ 708 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 709 STE_UNLOCK(sc); 710 return; 711 } 712 713 for (;;) { 714 status = CSR_READ_2(sc, STE_ISR_ACK); 715 716 if (!(status & STE_INTRS)) 717 break; 718 719 if (status & STE_ISR_RX_DMADONE) { 720 ste_rxeoc(sc); 721 ste_rxeof(sc); 722 } 723 724 if (status & STE_ISR_TX_DMADONE) 725 ste_txeof(sc); 726 727 if (status & STE_ISR_TX_DONE) 728 ste_txeoc(sc); 729 730 if (status & STE_ISR_STATS_OFLOW) { 731 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 732 ste_stats_update(sc); 733 } 734 735 if (status & STE_ISR_LINKEVENT) 736 mii_pollstat(device_get_softc(sc->ste_miibus)); 737 738 739 if (status & STE_ISR_HOSTERR) { 740 ste_reset(sc); 741 ste_init(sc); 742 } 743 } 744 745 /* Re-enable interrupts */ 746 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 747 748 if (ifp->if_snd.ifq_head != NULL) 749 ste_start(ifp); 750 751#ifdef DEVICE_POLLING 752done: 753#endif /* DEVICE_POLLING */ 754 STE_UNLOCK(sc); 755 756 return; 757} 758 759static void 760ste_rxeoc(struct ste_softc *sc) 761{ 762 struct ste_chain_onefrag *cur_rx; 763 764 STE_LOCK_ASSERT(sc); 765 766 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 767 cur_rx = sc->ste_cdata.ste_rx_head; 768 do { 769 cur_rx = cur_rx->ste_next; 770 /* If the ring is empty, just return. */ 771 if (cur_rx == sc->ste_cdata.ste_rx_head) 772 return; 773 } while (cur_rx->ste_ptr->ste_status == 0); 774 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 775 /* We've fallen behind the chip: catch it. */ 776 sc->ste_cdata.ste_rx_head = cur_rx; 777 ++ste_rxsyncs; 778 } 779 } 780} 781 782/* 783 * A frame has been uploaded: pass the resulting mbuf chain up to 784 * the higher level protocols. 785 */ 786static void 787ste_rxeof(sc) 788 struct ste_softc *sc; 789{ 790 struct mbuf *m; 791 struct ifnet *ifp; 792 struct ste_chain_onefrag *cur_rx; 793 int total_len = 0, count=0; 794 u_int32_t rxstat; 795 796 STE_LOCK_ASSERT(sc); 797 798 ifp = &sc->arpcom.ac_if; 799 800 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 801 & STE_RXSTAT_DMADONE) { 802#ifdef DEVICE_POLLING 803 if (ifp->if_flags & IFF_POLLING) { 804 if (sc->rxcycles <= 0) 805 break; 806 sc->rxcycles--; 807 } 808#endif /* DEVICE_POLLING */ 809 if ((STE_RX_LIST_CNT - count) < 3) { 810 break; 811 } 812 813 cur_rx = sc->ste_cdata.ste_rx_head; 814 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 815 816 /* 817 * If an error occurs, update stats, clear the 818 * status word and leave the mbuf cluster in place: 819 * it should simply get re-used next time this descriptor 820 * comes up in the ring. 821 */ 822 if (rxstat & STE_RXSTAT_FRAME_ERR) { 823 ifp->if_ierrors++; 824 cur_rx->ste_ptr->ste_status = 0; 825 continue; 826 } 827 828 /* 829 * If there error bit was not set, the upload complete 830 * bit should be set which means we have a valid packet. 831 * If not, something truly strange has happened. 832 */ 833 if (!(rxstat & STE_RXSTAT_DMADONE)) { 834 printf("ste%d: bad receive status -- packet dropped\n", 835 sc->ste_unit); 836 ifp->if_ierrors++; 837 cur_rx->ste_ptr->ste_status = 0; 838 continue; 839 } 840 841 /* No errors; receive the packet. */ 842 m = cur_rx->ste_mbuf; 843 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 844 845 /* 846 * Try to conjure up a new mbuf cluster. If that 847 * fails, it means we have an out of memory condition and 848 * should leave the buffer in place and continue. This will 849 * result in a lost packet, but there's little else we 850 * can do in this situation. 851 */ 852 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 853 ifp->if_ierrors++; 854 cur_rx->ste_ptr->ste_status = 0; 855 continue; 856 } 857 858 m->m_pkthdr.rcvif = ifp; 859 m->m_pkthdr.len = m->m_len = total_len; 860 861 ifp->if_ipackets++; 862 STE_UNLOCK(sc); 863 (*ifp->if_input)(ifp, m); 864 STE_LOCK(sc); 865 866 cur_rx->ste_ptr->ste_status = 0; 867 count++; 868 } 869 870 return; 871} 872 873static void 874ste_txeoc(sc) 875 struct ste_softc *sc; 876{ 877 u_int8_t txstat; 878 struct ifnet *ifp; 879 880 ifp = &sc->arpcom.ac_if; 881 882 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 883 STE_TXSTATUS_TXDONE) { 884 if (txstat & STE_TXSTATUS_UNDERRUN || 885 txstat & STE_TXSTATUS_EXCESSCOLLS || 886 txstat & STE_TXSTATUS_RECLAIMERR) { 887 ifp->if_oerrors++; 888 printf("ste%d: transmission error: %x\n", 889 sc->ste_unit, txstat); 890 891 ste_reset(sc); 892 ste_init(sc); 893 894 if (txstat & STE_TXSTATUS_UNDERRUN && 895 sc->ste_tx_thresh < STE_PACKET_SIZE) { 896 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 897 printf("ste%d: tx underrun, increasing tx" 898 " start threshold to %d bytes\n", 899 sc->ste_unit, sc->ste_tx_thresh); 900 } 901 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 902 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 903 (STE_PACKET_SIZE >> 4)); 904 } 905 ste_init(sc); 906 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 907 } 908 909 return; 910} 911 912static void 913ste_txeof(sc) 914 struct ste_softc *sc; 915{ 916 struct ste_chain *cur_tx; 917 struct ifnet *ifp; 918 int idx; 919 920 ifp = &sc->arpcom.ac_if; 921 922 idx = sc->ste_cdata.ste_tx_cons; 923 while(idx != sc->ste_cdata.ste_tx_prod) { 924 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 925 926 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 927 break; 928 929 m_freem(cur_tx->ste_mbuf); 930 cur_tx->ste_mbuf = NULL; 931 ifp->if_flags &= ~IFF_OACTIVE; 932 ifp->if_opackets++; 933 934 STE_INC(idx, STE_TX_LIST_CNT); 935 } 936 937 sc->ste_cdata.ste_tx_cons = idx; 938 if (idx == sc->ste_cdata.ste_tx_prod) 939 ifp->if_timer = 0; 940} 941 942static void 943ste_stats_update(xsc) 944 void *xsc; 945{ 946 struct ste_softc *sc; 947 struct ifnet *ifp; 948 struct mii_data *mii; 949 950 sc = xsc; 951 STE_LOCK(sc); 952 953 ifp = &sc->arpcom.ac_if; 954 mii = device_get_softc(sc->ste_miibus); 955 956 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 957 + CSR_READ_1(sc, STE_MULTI_COLLS) 958 + CSR_READ_1(sc, STE_SINGLE_COLLS); 959 960 if (!sc->ste_link) { 961 mii_pollstat(mii); 962 if (mii->mii_media_status & IFM_ACTIVE && 963 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 964 sc->ste_link++; 965 /* 966 * we don't get a call-back on re-init so do it 967 * otherwise we get stuck in the wrong link state 968 */ 969 ste_miibus_statchg(sc->ste_dev); 970 if (ifp->if_snd.ifq_head != NULL) 971 ste_start(ifp); 972 } 973 } 974 975 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 976 STE_UNLOCK(sc); 977 978 return; 979} 980 981 982/* 983 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 984 * IDs against our list and return a device name if we find a match. 985 */ 986static int 987ste_probe(dev) 988 device_t dev; 989{ 990 struct ste_type *t; 991 992 t = ste_devs; 993 994 while(t->ste_name != NULL) { 995 if ((pci_get_vendor(dev) == t->ste_vid) && 996 (pci_get_device(dev) == t->ste_did)) { 997 device_set_desc(dev, t->ste_name); 998 return(0); 999 } 1000 t++; 1001 } 1002 1003 return(ENXIO); 1004} 1005 1006/* 1007 * Attach the interface. Allocate softc structures, do ifmedia 1008 * setup and ethernet/BPF attach. 1009 */ 1010static int 1011ste_attach(dev) 1012 device_t dev; 1013{ 1014 struct ste_softc *sc; 1015 struct ifnet *ifp; 1016 int unit, error = 0, rid; 1017 1018 sc = device_get_softc(dev); 1019 unit = device_get_unit(dev); 1020 sc->ste_dev = dev; 1021 1022 /* 1023 * Only use one PHY since this chip reports multiple 1024 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1025 * it is at 0 & 1. It is rev 0x12. 1026 */ 1027 if (pci_get_vendor(dev) == DL_VENDORID && 1028 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1029 pci_get_revid(dev) == 0x12 ) 1030 sc->ste_one_phy = 1; 1031 1032 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1033 MTX_DEF | MTX_RECURSE); 1034#ifndef BURN_BRIDGES 1035 /* 1036 * Handle power management nonsense. 1037 */ 1038 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1039 u_int32_t iobase, membase, irq; 1040 1041 /* Save important PCI config data. */ 1042 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 1043 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 1044 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 1045 1046 /* Reset the power state. */ 1047 printf("ste%d: chip is in D%d power mode " 1048 "-- setting to D0\n", unit, 1049 pci_get_powerstate(dev)); 1050 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1051 1052 /* Restore PCI config data. */ 1053 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 1054 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 1055 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 1056 } 1057#endif 1058 /* 1059 * Map control/status registers. 1060 */ 1061 pci_enable_busmaster(dev); 1062 1063 rid = STE_RID; 1064 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1065 1066 if (sc->ste_res == NULL) { 1067 printf ("ste%d: couldn't map ports/memory\n", unit); 1068 error = ENXIO; 1069 goto fail; 1070 } 1071 1072 sc->ste_btag = rman_get_bustag(sc->ste_res); 1073 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1074 1075 /* Allocate interrupt */ 1076 rid = 0; 1077 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1078 RF_SHAREABLE | RF_ACTIVE); 1079 1080 if (sc->ste_irq == NULL) { 1081 printf("ste%d: couldn't map interrupt\n", unit); 1082 error = ENXIO; 1083 goto fail; 1084 } 1085 1086 callout_handle_init(&sc->ste_stat_ch); 1087 1088 /* Reset the adapter. */ 1089 ste_reset(sc); 1090 1091 /* 1092 * Get station address from the EEPROM. 1093 */ 1094 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1095 STE_EEADDR_NODE0, 3, 0)) { 1096 printf("ste%d: failed to read station address\n", unit); 1097 error = ENXIO;; 1098 goto fail; 1099 } 1100 1101 sc->ste_unit = unit; 1102 1103 /* Allocate the descriptor queues. */ 1104 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1105 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1106 1107 if (sc->ste_ldata == NULL) { 1108 printf("ste%d: no memory for list buffers!\n", unit); 1109 error = ENXIO; 1110 goto fail; 1111 } 1112 1113 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1114 1115 /* Do MII setup. */ 1116 if (mii_phy_probe(dev, &sc->ste_miibus, 1117 ste_ifmedia_upd, ste_ifmedia_sts)) { 1118 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1119 error = ENXIO; 1120 goto fail; 1121 } 1122 1123 ifp = &sc->arpcom.ac_if; 1124 ifp->if_softc = sc; 1125 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1126 ifp->if_mtu = ETHERMTU; 1127 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1128 ifp->if_ioctl = ste_ioctl; 1129 ifp->if_start = ste_start; 1130 ifp->if_watchdog = ste_watchdog; 1131 ifp->if_init = ste_init; 1132 ifp->if_baudrate = 10000000; 1133 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1134 1135 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1136 1137 /* 1138 * Call MI attach routine. 1139 */ 1140 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1141 1142 /* 1143 * Tell the upper layer(s) we support long frames. 1144 */ 1145 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1146 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1147#ifdef DEVICE_POLLING 1148 ifp->if_capabilities |= IFCAP_POLLING; 1149#endif 1150 ifp->if_capenable = ifp->if_capabilities; 1151 1152 /* Hook interrupt last to avoid having to lock softc */ 1153 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1154 ste_intr, sc, &sc->ste_intrhand); 1155 1156 if (error) { 1157 printf("ste%d: couldn't set up irq\n", unit); 1158 ether_ifdetach(ifp); 1159 goto fail; 1160 } 1161 1162fail: 1163 if (error) 1164 ste_detach(dev); 1165 1166 return(error); 1167} 1168 1169/* 1170 * Shutdown hardware and free up resources. This can be called any 1171 * time after the mutex has been initialized. It is called in both 1172 * the error case in attach and the normal detach case so it needs 1173 * to be careful about only freeing resources that have actually been 1174 * allocated. 1175 */ 1176static int 1177ste_detach(dev) 1178 device_t dev; 1179{ 1180 struct ste_softc *sc; 1181 struct ifnet *ifp; 1182 1183 sc = device_get_softc(dev); 1184 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1185 STE_LOCK(sc); 1186 ifp = &sc->arpcom.ac_if; 1187 1188 /* These should only be active if attach succeeded */ 1189 if (device_is_attached(dev)) { 1190 ste_stop(sc); 1191 ether_ifdetach(ifp); 1192 } 1193 if (sc->ste_miibus) 1194 device_delete_child(dev, sc->ste_miibus); 1195 bus_generic_detach(dev); 1196 1197 if (sc->ste_intrhand) 1198 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1199 if (sc->ste_irq) 1200 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1201 if (sc->ste_res) 1202 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1203 1204 if (sc->ste_ldata) { 1205 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1206 M_DEVBUF); 1207 } 1208 1209 STE_UNLOCK(sc); 1210 mtx_destroy(&sc->ste_mtx); 1211 1212 return(0); 1213} 1214 1215static int 1216ste_newbuf(sc, c, m) 1217 struct ste_softc *sc; 1218 struct ste_chain_onefrag *c; 1219 struct mbuf *m; 1220{ 1221 struct mbuf *m_new = NULL; 1222 1223 if (m == NULL) { 1224 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1225 if (m_new == NULL) 1226 return(ENOBUFS); 1227 MCLGET(m_new, M_DONTWAIT); 1228 if (!(m_new->m_flags & M_EXT)) { 1229 m_freem(m_new); 1230 return(ENOBUFS); 1231 } 1232 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1233 } else { 1234 m_new = m; 1235 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1236 m_new->m_data = m_new->m_ext.ext_buf; 1237 } 1238 1239 m_adj(m_new, ETHER_ALIGN); 1240 1241 c->ste_mbuf = m_new; 1242 c->ste_ptr->ste_status = 0; 1243 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1244 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1245 1246 return(0); 1247} 1248 1249static int 1250ste_init_rx_list(sc) 1251 struct ste_softc *sc; 1252{ 1253 struct ste_chain_data *cd; 1254 struct ste_list_data *ld; 1255 int i; 1256 1257 cd = &sc->ste_cdata; 1258 ld = sc->ste_ldata; 1259 1260 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1261 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1262 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1263 return(ENOBUFS); 1264 if (i == (STE_RX_LIST_CNT - 1)) { 1265 cd->ste_rx_chain[i].ste_next = 1266 &cd->ste_rx_chain[0]; 1267 ld->ste_rx_list[i].ste_next = 1268 vtophys(&ld->ste_rx_list[0]); 1269 } else { 1270 cd->ste_rx_chain[i].ste_next = 1271 &cd->ste_rx_chain[i + 1]; 1272 ld->ste_rx_list[i].ste_next = 1273 vtophys(&ld->ste_rx_list[i + 1]); 1274 } 1275 ld->ste_rx_list[i].ste_status = 0; 1276 } 1277 1278 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1279 1280 return(0); 1281} 1282 1283static void 1284ste_init_tx_list(sc) 1285 struct ste_softc *sc; 1286{ 1287 struct ste_chain_data *cd; 1288 struct ste_list_data *ld; 1289 int i; 1290 1291 cd = &sc->ste_cdata; 1292 ld = sc->ste_ldata; 1293 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1294 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1295 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1296 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1297 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1298 if (i == (STE_TX_LIST_CNT - 1)) 1299 cd->ste_tx_chain[i].ste_next = 1300 &cd->ste_tx_chain[0]; 1301 else 1302 cd->ste_tx_chain[i].ste_next = 1303 &cd->ste_tx_chain[i + 1]; 1304 } 1305 1306 cd->ste_tx_prod = 0; 1307 cd->ste_tx_cons = 0; 1308 1309 return; 1310} 1311 1312static void 1313ste_init(xsc) 1314 void *xsc; 1315{ 1316 struct ste_softc *sc; 1317 int i; 1318 struct ifnet *ifp; 1319 1320 sc = xsc; 1321 STE_LOCK(sc); 1322 ifp = &sc->arpcom.ac_if; 1323 1324 ste_stop(sc); 1325 1326 /* Init our MAC address */ 1327 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1328 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1329 } 1330 1331 /* Init RX list */ 1332 if (ste_init_rx_list(sc) == ENOBUFS) { 1333 printf("ste%d: initialization failed: no " 1334 "memory for RX buffers\n", sc->ste_unit); 1335 ste_stop(sc); 1336 STE_UNLOCK(sc); 1337 return; 1338 } 1339 1340 /* Set RX polling interval */ 1341 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1342 1343 /* Init TX descriptors */ 1344 ste_init_tx_list(sc); 1345 1346 /* Set the TX freethresh value */ 1347 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1348 1349 /* Set the TX start threshold for best performance. */ 1350 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1351 1352 /* Set the TX reclaim threshold. */ 1353 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1354 1355 /* Set up the RX filter. */ 1356 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1357 1358 /* If we want promiscuous mode, set the allframes bit. */ 1359 if (ifp->if_flags & IFF_PROMISC) { 1360 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1361 } else { 1362 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1363 } 1364 1365 /* Set capture broadcast bit to accept broadcast frames. */ 1366 if (ifp->if_flags & IFF_BROADCAST) { 1367 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1368 } else { 1369 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1370 } 1371 1372 ste_setmulti(sc); 1373 1374 /* Load the address of the RX list. */ 1375 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1376 ste_wait(sc); 1377 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1378 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1379 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1380 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1381 1382 /* Set TX polling interval (defer until we TX first packet */ 1383 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1384 1385 /* Load address of the TX list */ 1386 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1387 ste_wait(sc); 1388 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1389 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1390 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1391 ste_wait(sc); 1392 sc->ste_tx_prev = NULL; 1393 1394 /* Enable receiver and transmitter */ 1395 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1396 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1397 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1398 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1399 1400 /* Enable stats counters. */ 1401 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1402 1403 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1404#ifdef DEVICE_POLLING 1405 /* Disable interrupts if we are polling. */ 1406 if (ifp->if_flags & IFF_POLLING) 1407 CSR_WRITE_2(sc, STE_IMR, 0); 1408 else 1409#endif /* DEVICE_POLLING */ 1410 /* Enable interrupts. */ 1411 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1412 1413 /* Accept VLAN length packets */ 1414 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1415 1416 ste_ifmedia_upd(ifp); 1417 1418 ifp->if_flags |= IFF_RUNNING; 1419 ifp->if_flags &= ~IFF_OACTIVE; 1420 1421 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1422 STE_UNLOCK(sc); 1423 1424 return; 1425} 1426 1427static void 1428ste_stop(sc) 1429 struct ste_softc *sc; 1430{ 1431 int i; 1432 struct ifnet *ifp; 1433 1434 STE_LOCK(sc); 1435 ifp = &sc->arpcom.ac_if; 1436 1437 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1438 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1439#ifdef DEVICE_POLLING 1440 ether_poll_deregister(ifp); 1441#endif /* DEVICE_POLLING */ 1442 1443 CSR_WRITE_2(sc, STE_IMR, 0); 1444 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1445 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1446 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1447 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1448 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1449 ste_wait(sc); 1450 /* 1451 * Try really hard to stop the RX engine or under heavy RX 1452 * data chip will write into de-allocated memory. 1453 */ 1454 ste_reset(sc); 1455 1456 sc->ste_link = 0; 1457 1458 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1459 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1460 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1461 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1462 } 1463 } 1464 1465 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1466 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1467 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1468 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1469 } 1470 } 1471 1472 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1473 STE_UNLOCK(sc); 1474 1475 return; 1476} 1477 1478static void 1479ste_reset(sc) 1480 struct ste_softc *sc; 1481{ 1482 int i; 1483 1484 STE_SETBIT4(sc, STE_ASICCTL, 1485 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1486 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1487 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1488 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1489 STE_ASICCTL_EXTRESET_RESET); 1490 1491 DELAY(100000); 1492 1493 for (i = 0; i < STE_TIMEOUT; i++) { 1494 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1495 break; 1496 } 1497 1498 if (i == STE_TIMEOUT) 1499 printf("ste%d: global reset never completed\n", sc->ste_unit); 1500 1501 return; 1502} 1503 1504static int 1505ste_ioctl(ifp, command, data) 1506 struct ifnet *ifp; 1507 u_long command; 1508 caddr_t data; 1509{ 1510 struct ste_softc *sc; 1511 struct ifreq *ifr; 1512 struct mii_data *mii; 1513 int error = 0; 1514 1515 sc = ifp->if_softc; 1516 STE_LOCK(sc); 1517 ifr = (struct ifreq *)data; 1518 1519 switch(command) { 1520 case SIOCSIFFLAGS: 1521 if (ifp->if_flags & IFF_UP) { 1522 if (ifp->if_flags & IFF_RUNNING && 1523 ifp->if_flags & IFF_PROMISC && 1524 !(sc->ste_if_flags & IFF_PROMISC)) { 1525 STE_SETBIT1(sc, STE_RX_MODE, 1526 STE_RXMODE_PROMISC); 1527 } else if (ifp->if_flags & IFF_RUNNING && 1528 !(ifp->if_flags & IFF_PROMISC) && 1529 sc->ste_if_flags & IFF_PROMISC) { 1530 STE_CLRBIT1(sc, STE_RX_MODE, 1531 STE_RXMODE_PROMISC); 1532 } 1533 if (ifp->if_flags & IFF_RUNNING && 1534 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1535 ste_setmulti(sc); 1536 if (!(ifp->if_flags & IFF_RUNNING)) { 1537 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1538 ste_init(sc); 1539 } 1540 } else { 1541 if (ifp->if_flags & IFF_RUNNING) 1542 ste_stop(sc); 1543 } 1544 sc->ste_if_flags = ifp->if_flags; 1545 error = 0; 1546 break; 1547 case SIOCADDMULTI: 1548 case SIOCDELMULTI: 1549 ste_setmulti(sc); 1550 error = 0; 1551 break; 1552 case SIOCGIFMEDIA: 1553 case SIOCSIFMEDIA: 1554 mii = device_get_softc(sc->ste_miibus); 1555 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1556 break; 1557 case SIOCSIFCAP: 1558 ifp->if_capenable &= ~IFCAP_POLLING; 1559 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1560 break; 1561 default: 1562 error = ether_ioctl(ifp, command, data); 1563 break; 1564 } 1565 1566 STE_UNLOCK(sc); 1567 1568 return(error); 1569} 1570 1571static int 1572ste_encap(sc, c, m_head) 1573 struct ste_softc *sc; 1574 struct ste_chain *c; 1575 struct mbuf *m_head; 1576{ 1577 int frag = 0; 1578 struct ste_frag *f = NULL; 1579 struct mbuf *m; 1580 struct ste_desc *d; 1581 1582 d = c->ste_ptr; 1583 d->ste_ctl = 0; 1584 1585encap_retry: 1586 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1587 if (m->m_len != 0) { 1588 if (frag == STE_MAXFRAGS) 1589 break; 1590 f = &d->ste_frags[frag]; 1591 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1592 f->ste_len = m->m_len; 1593 frag++; 1594 } 1595 } 1596 1597 if (m != NULL) { 1598 struct mbuf *mn; 1599 1600 /* 1601 * We ran out of segments. We have to recopy this 1602 * mbuf chain first. Bail out if we can't get the 1603 * new buffers. 1604 */ 1605 mn = m_defrag(m_head, M_DONTWAIT); 1606 if (mn == NULL) { 1607 m_freem(m_head); 1608 return ENOMEM; 1609 } 1610 m_head = mn; 1611 goto encap_retry; 1612 } 1613 1614 c->ste_mbuf = m_head; 1615 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1616 d->ste_ctl = 1; 1617 1618 return(0); 1619} 1620 1621static void 1622ste_start(ifp) 1623 struct ifnet *ifp; 1624{ 1625 struct ste_softc *sc; 1626 struct mbuf *m_head = NULL; 1627 struct ste_chain *cur_tx; 1628 int idx; 1629 1630 sc = ifp->if_softc; 1631 STE_LOCK(sc); 1632 1633 if (!sc->ste_link) { 1634 STE_UNLOCK(sc); 1635 return; 1636 } 1637 1638 if (ifp->if_flags & IFF_OACTIVE) { 1639 STE_UNLOCK(sc); 1640 return; 1641 } 1642 1643 idx = sc->ste_cdata.ste_tx_prod; 1644 1645 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1646 /* 1647 * We cannot re-use the last (free) descriptor; 1648 * the chip may not have read its ste_next yet. 1649 */ 1650 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1651 sc->ste_cdata.ste_tx_cons) { 1652 ifp->if_flags |= IFF_OACTIVE; 1653 break; 1654 } 1655 1656 IF_DEQUEUE(&ifp->if_snd, m_head); 1657 if (m_head == NULL) 1658 break; 1659 1660 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1661 1662 if (ste_encap(sc, cur_tx, m_head) != 0) 1663 break; 1664 1665 cur_tx->ste_ptr->ste_next = 0; 1666 1667 if (sc->ste_tx_prev == NULL) { 1668 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1669 /* Load address of the TX list */ 1670 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1671 ste_wait(sc); 1672 1673 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1674 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1675 1676 /* Set TX polling interval to start TX engine */ 1677 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1678 1679 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1680 ste_wait(sc); 1681 }else{ 1682 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1683 sc->ste_tx_prev->ste_ptr->ste_next 1684 = cur_tx->ste_phys; 1685 } 1686 1687 sc->ste_tx_prev = cur_tx; 1688 1689 /* 1690 * If there's a BPF listener, bounce a copy of this frame 1691 * to him. 1692 */ 1693 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1694 1695 STE_INC(idx, STE_TX_LIST_CNT); 1696 ifp->if_timer = 5; 1697 } 1698 sc->ste_cdata.ste_tx_prod = idx; 1699 1700 STE_UNLOCK(sc); 1701 1702 return; 1703} 1704 1705static void 1706ste_watchdog(ifp) 1707 struct ifnet *ifp; 1708{ 1709 struct ste_softc *sc; 1710 1711 sc = ifp->if_softc; 1712 STE_LOCK(sc); 1713 1714 ifp->if_oerrors++; 1715 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1716 1717 ste_txeoc(sc); 1718 ste_txeof(sc); 1719 ste_rxeoc(sc); 1720 ste_rxeof(sc); 1721 ste_reset(sc); 1722 ste_init(sc); 1723 1724 if (ifp->if_snd.ifq_head != NULL) 1725 ste_start(ifp); 1726 STE_UNLOCK(sc); 1727 1728 return; 1729} 1730 1731static void 1732ste_shutdown(dev) 1733 device_t dev; 1734{ 1735 struct ste_softc *sc; 1736 1737 sc = device_get_softc(dev); 1738 1739 ste_stop(sc); 1740 1741 return; 1742} 1743