if_ste.c revision 127937
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 127937 2004-04-06 11:04:54Z ru $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44 45#include <net/if.h> 46#include <net/if_arp.h> 47#include <net/ethernet.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <vm/vm.h> /* for vtophys */ 55#include <vm/pmap.h> /* for vtophys */ 56#include <machine/bus_memio.h> 57#include <machine/bus_pio.h> 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69/* "controller miibus0" required. See GENERIC if you get errors here. */ 70#include "miibus_if.h" 71 72#define STE_USEIOSPACE 73 74#include <pci/if_stereg.h> 75 76MODULE_DEPEND(ste, pci, 1, 1, 1); 77MODULE_DEPEND(ste, ether, 1, 1, 1); 78MODULE_DEPEND(ste, miibus, 1, 1, 1); 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe (device_t); 90static int ste_attach (device_t); 91static int ste_detach (device_t); 92static void ste_init (void *); 93static void ste_intr (void *); 94static void ste_rxeoc (struct ste_softc *); 95static void ste_rxeof (struct ste_softc *); 96static void ste_txeoc (struct ste_softc *); 97static void ste_txeof (struct ste_softc *); 98static void ste_stats_update (void *); 99static void ste_stop (struct ste_softc *); 100static void ste_reset (struct ste_softc *); 101static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104static void ste_start (struct ifnet *); 105static void ste_watchdog (struct ifnet *); 106static void ste_shutdown (device_t); 107static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd (struct ifnet *); 111static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113static void ste_mii_sync (struct ste_softc *); 114static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg (device_t, int, int); 118static int ste_miibus_writereg (device_t, int, int, int); 119static void ste_miibus_statchg (device_t); 120 121static int ste_eeprom_wait (struct ste_softc *); 122static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123static void ste_wait (struct ste_softc *); 124static u_int8_t ste_calchash (caddr_t); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 168 169static int ste_rxsyncs; 170SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 171 172#define STE_SETBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 174 175#define STE_CLRBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 177 178#define STE_SETBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 180 181#define STE_CLRBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 183 184#define STE_SETBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186 187#define STE_CLRBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 189 190 191#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 192#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 193 194/* 195 * Sync the PHYs by setting data bit and strobing the clock 32 times. 196 */ 197static void 198ste_mii_sync(sc) 199 struct ste_softc *sc; 200{ 201 register int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211 212 return; 213} 214 215/* 216 * Clock a series of bits through the MII. 217 */ 218static void 219ste_mii_send(sc, bits, cnt) 220 struct ste_softc *sc; 221 u_int32_t bits; 222 int cnt; 223{ 224 int i; 225 226 MII_CLR(STE_PHYCTL_MCLK); 227 228 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 229 if (bits & i) { 230 MII_SET(STE_PHYCTL_MDATA); 231 } else { 232 MII_CLR(STE_PHYCTL_MDATA); 233 } 234 DELAY(1); 235 MII_CLR(STE_PHYCTL_MCLK); 236 DELAY(1); 237 MII_SET(STE_PHYCTL_MCLK); 238 } 239} 240 241/* 242 * Read an PHY register through the MII. 243 */ 244static int 245ste_mii_readreg(sc, frame) 246 struct ste_softc *sc; 247 struct ste_mii_frame *frame; 248 249{ 250 int i, ack; 251 252 STE_LOCK(sc); 253 254 /* 255 * Set up frame for RX. 256 */ 257 frame->mii_stdelim = STE_MII_STARTDELIM; 258 frame->mii_opcode = STE_MII_READOP; 259 frame->mii_turnaround = 0; 260 frame->mii_data = 0; 261 262 CSR_WRITE_2(sc, STE_PHYCTL, 0); 263 /* 264 * Turn on data xmit. 265 */ 266 MII_SET(STE_PHYCTL_MDIR); 267 268 ste_mii_sync(sc); 269 270 /* 271 * Send command/address info. 272 */ 273 ste_mii_send(sc, frame->mii_stdelim, 2); 274 ste_mii_send(sc, frame->mii_opcode, 2); 275 ste_mii_send(sc, frame->mii_phyaddr, 5); 276 ste_mii_send(sc, frame->mii_regaddr, 5); 277 278 /* Turn off xmit. */ 279 MII_CLR(STE_PHYCTL_MDIR); 280 281 /* Idle bit */ 282 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 283 DELAY(1); 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* Check for ack */ 288 MII_CLR(STE_PHYCTL_MCLK); 289 DELAY(1); 290 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 291 MII_SET(STE_PHYCTL_MCLK); 292 DELAY(1); 293 294 /* 295 * Now try reading data bits. If the ack failed, we still 296 * need to clock through 16 cycles to keep the PHY(s) in sync. 297 */ 298 if (ack) { 299 for(i = 0; i < 16; i++) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 MII_SET(STE_PHYCTL_MCLK); 303 DELAY(1); 304 } 305 goto fail; 306 } 307 308 for (i = 0x8000; i; i >>= 1) { 309 MII_CLR(STE_PHYCTL_MCLK); 310 DELAY(1); 311 if (!ack) { 312 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 313 frame->mii_data |= i; 314 DELAY(1); 315 } 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 } 319 320fail: 321 322 MII_CLR(STE_PHYCTL_MCLK); 323 DELAY(1); 324 MII_SET(STE_PHYCTL_MCLK); 325 DELAY(1); 326 327 STE_UNLOCK(sc); 328 329 if (ack) 330 return(1); 331 return(0); 332} 333 334/* 335 * Write to a PHY register through the MII. 336 */ 337static int 338ste_mii_writereg(sc, frame) 339 struct ste_softc *sc; 340 struct ste_mii_frame *frame; 341 342{ 343 STE_LOCK(sc); 344 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 STE_UNLOCK(sc); 379 380 return(0); 381} 382 383static int 384ste_miibus_readreg(dev, phy, reg) 385 device_t dev; 386 int phy, reg; 387{ 388 struct ste_softc *sc; 389 struct ste_mii_frame frame; 390 391 sc = device_get_softc(dev); 392 393 if ( sc->ste_one_phy && phy != 0 ) 394 return (0); 395 396 bzero((char *)&frame, sizeof(frame)); 397 398 frame.mii_phyaddr = phy; 399 frame.mii_regaddr = reg; 400 ste_mii_readreg(sc, &frame); 401 402 return(frame.mii_data); 403} 404 405static int 406ste_miibus_writereg(dev, phy, reg, data) 407 device_t dev; 408 int phy, reg, data; 409{ 410 struct ste_softc *sc; 411 struct ste_mii_frame frame; 412 413 sc = device_get_softc(dev); 414 bzero((char *)&frame, sizeof(frame)); 415 416 frame.mii_phyaddr = phy; 417 frame.mii_regaddr = reg; 418 frame.mii_data = data; 419 420 ste_mii_writereg(sc, &frame); 421 422 return(0); 423} 424 425static void 426ste_miibus_statchg(dev) 427 device_t dev; 428{ 429 struct ste_softc *sc; 430 struct mii_data *mii; 431 432 sc = device_get_softc(dev); 433 STE_LOCK(sc); 434 mii = device_get_softc(sc->ste_miibus); 435 436 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 437 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } else { 439 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 440 } 441 STE_UNLOCK(sc); 442 443 return; 444} 445 446static int 447ste_ifmedia_upd(ifp) 448 struct ifnet *ifp; 449{ 450 struct ste_softc *sc; 451 struct mii_data *mii; 452 453 sc = ifp->if_softc; 454 mii = device_get_softc(sc->ste_miibus); 455 sc->ste_link = 0; 456 if (mii->mii_instance) { 457 struct mii_softc *miisc; 458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 459 mii_phy_reset(miisc); 460 } 461 mii_mediachg(mii); 462 463 return(0); 464} 465 466static void 467ste_ifmedia_sts(ifp, ifmr) 468 struct ifnet *ifp; 469 struct ifmediareq *ifmr; 470{ 471 struct ste_softc *sc; 472 struct mii_data *mii; 473 474 sc = ifp->if_softc; 475 mii = device_get_softc(sc->ste_miibus); 476 477 mii_pollstat(mii); 478 ifmr->ifm_active = mii->mii_media_active; 479 ifmr->ifm_status = mii->mii_media_status; 480 481 return; 482} 483 484static void 485ste_wait(sc) 486 struct ste_softc *sc; 487{ 488 register int i; 489 490 for (i = 0; i < STE_TIMEOUT; i++) { 491 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 492 break; 493 } 494 495 if (i == STE_TIMEOUT) 496 printf("ste%d: command never completed!\n", sc->ste_unit); 497 498 return; 499} 500 501/* 502 * The EEPROM is slow: give it time to come ready after issuing 503 * it a command. 504 */ 505static int 506ste_eeprom_wait(sc) 507 struct ste_softc *sc; 508{ 509 int i; 510 511 DELAY(1000); 512 513 for (i = 0; i < 100; i++) { 514 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 515 DELAY(1000); 516 else 517 break; 518 } 519 520 if (i == 100) { 521 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 522 return(1); 523 } 524 525 return(0); 526} 527 528/* 529 * Read a sequence of words from the EEPROM. Note that ethernet address 530 * data is stored in the EEPROM in network byte order. 531 */ 532static int 533ste_read_eeprom(sc, dest, off, cnt, swap) 534 struct ste_softc *sc; 535 caddr_t dest; 536 int off; 537 int cnt; 538 int swap; 539{ 540 int err = 0, i; 541 u_int16_t word = 0, *ptr; 542 543 if (ste_eeprom_wait(sc)) 544 return(1); 545 546 for (i = 0; i < cnt; i++) { 547 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 548 err = ste_eeprom_wait(sc); 549 if (err) 550 break; 551 word = CSR_READ_2(sc, STE_EEPROM_DATA); 552 ptr = (u_int16_t *)(dest + (i * 2)); 553 if (swap) 554 *ptr = ntohs(word); 555 else 556 *ptr = word; 557 } 558 559 return(err ? 1 : 0); 560} 561 562static u_int8_t 563ste_calchash(addr) 564 caddr_t addr; 565{ 566 567 u_int32_t crc, carry; 568 int i, j; 569 u_int8_t c; 570 571 /* Compute CRC for the address value. */ 572 crc = 0xFFFFFFFF; /* initial value */ 573 574 for (i = 0; i < 6; i++) { 575 c = *(addr + i); 576 for (j = 0; j < 8; j++) { 577 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 578 crc <<= 1; 579 c >>= 1; 580 if (carry) 581 crc = (crc ^ 0x04c11db6) | carry; 582 } 583 } 584 585 /* return the filter bit position */ 586 return(crc & 0x0000003F); 587} 588 589static void 590ste_setmulti(sc) 591 struct ste_softc *sc; 592{ 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 598 ifp = &sc->arpcom.ac_if; 599 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 600 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 601 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 602 return; 603 } 604 605 /* first, zot all the existing hash bits */ 606 CSR_WRITE_2(sc, STE_MAR0, 0); 607 CSR_WRITE_2(sc, STE_MAR1, 0); 608 CSR_WRITE_2(sc, STE_MAR2, 0); 609 CSR_WRITE_2(sc, STE_MAR3, 0); 610 611 /* now program new ones */ 612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 613 if (ifma->ifma_addr->sa_family != AF_LINK) 614 continue; 615 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 616 if (h < 32) 617 hashes[0] |= (1 << h); 618 else 619 hashes[1] |= (1 << (h - 32)); 620 } 621 622 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 623 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 624 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 625 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 626 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 627 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 628 629 return; 630} 631 632#ifdef DEVICE_POLLING 633static poll_handler_t ste_poll; 634 635static void 636ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 637{ 638 struct ste_softc *sc = ifp->if_softc; 639 640 STE_LOCK(sc); 641 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 642 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 643 goto done; 644 } 645 646 sc->rxcycles = count; 647 if (cmd == POLL_AND_CHECK_STATUS) 648 ste_rxeoc(sc); 649 ste_rxeof(sc); 650 ste_txeof(sc); 651 if (ifp->if_snd.ifq_head != NULL) 652 ste_start(ifp); 653 654 if (cmd == POLL_AND_CHECK_STATUS) { 655 u_int16_t status; 656 657 status = CSR_READ_2(sc, STE_ISR_ACK); 658 659 if (status & STE_ISR_TX_DONE) 660 ste_txeoc(sc); 661 662 if (status & STE_ISR_STATS_OFLOW) { 663 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 664 ste_stats_update(sc); 665 } 666 667 if (status & STE_ISR_LINKEVENT) 668 mii_pollstat(device_get_softc(sc->ste_miibus)); 669 670 if (status & STE_ISR_HOSTERR) { 671 ste_reset(sc); 672 ste_init(sc); 673 } 674 } 675done: 676 STE_UNLOCK(sc); 677} 678#endif /* DEVICE_POLLING */ 679 680static void 681ste_intr(xsc) 682 void *xsc; 683{ 684 struct ste_softc *sc; 685 struct ifnet *ifp; 686 u_int16_t status; 687 688 sc = xsc; 689 STE_LOCK(sc); 690 ifp = &sc->arpcom.ac_if; 691 692#ifdef DEVICE_POLLING 693 if (ifp->if_flags & IFF_POLLING) 694 goto done; 695 if (ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 696 CSR_WRITE_2(sc, STE_IMR, 0); 697 ste_poll(ifp, 0, 1); 698 goto done; 699 } 700#endif /* DEVICE_POLLING */ 701 702 /* See if this is really our interrupt. */ 703 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 704 STE_UNLOCK(sc); 705 return; 706 } 707 708 for (;;) { 709 status = CSR_READ_2(sc, STE_ISR_ACK); 710 711 if (!(status & STE_INTRS)) 712 break; 713 714 if (status & STE_ISR_RX_DMADONE) { 715 ste_rxeoc(sc); 716 ste_rxeof(sc); 717 } 718 719 if (status & STE_ISR_TX_DMADONE) 720 ste_txeof(sc); 721 722 if (status & STE_ISR_TX_DONE) 723 ste_txeoc(sc); 724 725 if (status & STE_ISR_STATS_OFLOW) { 726 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 727 ste_stats_update(sc); 728 } 729 730 if (status & STE_ISR_LINKEVENT) 731 mii_pollstat(device_get_softc(sc->ste_miibus)); 732 733 734 if (status & STE_ISR_HOSTERR) { 735 ste_reset(sc); 736 ste_init(sc); 737 } 738 } 739 740 /* Re-enable interrupts */ 741 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 742 743 if (ifp->if_snd.ifq_head != NULL) 744 ste_start(ifp); 745 746#ifdef DEVICE_POLLING 747done: 748#endif /* DEVICE_POLLING */ 749 STE_UNLOCK(sc); 750 751 return; 752} 753 754static void 755ste_rxeoc(struct ste_softc *sc) 756{ 757 struct ste_chain_onefrag *cur_rx; 758 759 STE_LOCK_ASSERT(sc); 760 761 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 762 cur_rx = sc->ste_cdata.ste_rx_head; 763 do { 764 cur_rx = cur_rx->ste_next; 765 /* If the ring is empty, just return. */ 766 if (cur_rx == sc->ste_cdata.ste_rx_head) 767 return; 768 } while (cur_rx->ste_ptr->ste_status == 0); 769 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 770 /* We've fallen behind the chip: catch it. */ 771 sc->ste_cdata.ste_rx_head = cur_rx; 772 ++ste_rxsyncs; 773 } 774 } 775} 776 777/* 778 * A frame has been uploaded: pass the resulting mbuf chain up to 779 * the higher level protocols. 780 */ 781static void 782ste_rxeof(sc) 783 struct ste_softc *sc; 784{ 785 struct mbuf *m; 786 struct ifnet *ifp; 787 struct ste_chain_onefrag *cur_rx; 788 int total_len = 0, count=0; 789 u_int32_t rxstat; 790 791 STE_LOCK_ASSERT(sc); 792 793 ifp = &sc->arpcom.ac_if; 794 795 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 796 & STE_RXSTAT_DMADONE) { 797#ifdef DEVICE_POLLING 798 if (ifp->if_flags & IFF_POLLING) { 799 if (sc->rxcycles <= 0) 800 break; 801 sc->rxcycles--; 802 } 803#endif /* DEVICE_POLLING */ 804 if ((STE_RX_LIST_CNT - count) < 3) { 805 break; 806 } 807 808 cur_rx = sc->ste_cdata.ste_rx_head; 809 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 810 811 /* 812 * If an error occurs, update stats, clear the 813 * status word and leave the mbuf cluster in place: 814 * it should simply get re-used next time this descriptor 815 * comes up in the ring. 816 */ 817 if (rxstat & STE_RXSTAT_FRAME_ERR) { 818 ifp->if_ierrors++; 819 cur_rx->ste_ptr->ste_status = 0; 820 continue; 821 } 822 823 /* 824 * If there error bit was not set, the upload complete 825 * bit should be set which means we have a valid packet. 826 * If not, something truly strange has happened. 827 */ 828 if (!(rxstat & STE_RXSTAT_DMADONE)) { 829 printf("ste%d: bad receive status -- packet dropped\n", 830 sc->ste_unit); 831 ifp->if_ierrors++; 832 cur_rx->ste_ptr->ste_status = 0; 833 continue; 834 } 835 836 /* No errors; receive the packet. */ 837 m = cur_rx->ste_mbuf; 838 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 839 840 /* 841 * Try to conjure up a new mbuf cluster. If that 842 * fails, it means we have an out of memory condition and 843 * should leave the buffer in place and continue. This will 844 * result in a lost packet, but there's little else we 845 * can do in this situation. 846 */ 847 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 848 ifp->if_ierrors++; 849 cur_rx->ste_ptr->ste_status = 0; 850 continue; 851 } 852 853 m->m_pkthdr.rcvif = ifp; 854 m->m_pkthdr.len = m->m_len = total_len; 855 856 ifp->if_ipackets++; 857 STE_UNLOCK(sc); 858 (*ifp->if_input)(ifp, m); 859 STE_LOCK(sc); 860 861 cur_rx->ste_ptr->ste_status = 0; 862 count++; 863 } 864 865 return; 866} 867 868static void 869ste_txeoc(sc) 870 struct ste_softc *sc; 871{ 872 u_int8_t txstat; 873 struct ifnet *ifp; 874 875 ifp = &sc->arpcom.ac_if; 876 877 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 878 STE_TXSTATUS_TXDONE) { 879 if (txstat & STE_TXSTATUS_UNDERRUN || 880 txstat & STE_TXSTATUS_EXCESSCOLLS || 881 txstat & STE_TXSTATUS_RECLAIMERR) { 882 ifp->if_oerrors++; 883 printf("ste%d: transmission error: %x\n", 884 sc->ste_unit, txstat); 885 886 ste_reset(sc); 887 ste_init(sc); 888 889 if (txstat & STE_TXSTATUS_UNDERRUN && 890 sc->ste_tx_thresh < STE_PACKET_SIZE) { 891 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 892 printf("ste%d: tx underrun, increasing tx" 893 " start threshold to %d bytes\n", 894 sc->ste_unit, sc->ste_tx_thresh); 895 } 896 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 897 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 898 (STE_PACKET_SIZE >> 4)); 899 } 900 ste_init(sc); 901 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 902 } 903 904 return; 905} 906 907static void 908ste_txeof(sc) 909 struct ste_softc *sc; 910{ 911 struct ste_chain *cur_tx; 912 struct ifnet *ifp; 913 int idx; 914 915 ifp = &sc->arpcom.ac_if; 916 917 idx = sc->ste_cdata.ste_tx_cons; 918 while(idx != sc->ste_cdata.ste_tx_prod) { 919 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 920 921 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 922 break; 923 924 m_freem(cur_tx->ste_mbuf); 925 cur_tx->ste_mbuf = NULL; 926 ifp->if_flags &= ~IFF_OACTIVE; 927 ifp->if_opackets++; 928 929 STE_INC(idx, STE_TX_LIST_CNT); 930 } 931 932 sc->ste_cdata.ste_tx_cons = idx; 933 if (idx == sc->ste_cdata.ste_tx_prod) 934 ifp->if_timer = 0; 935} 936 937static void 938ste_stats_update(xsc) 939 void *xsc; 940{ 941 struct ste_softc *sc; 942 struct ifnet *ifp; 943 struct mii_data *mii; 944 945 sc = xsc; 946 STE_LOCK(sc); 947 948 ifp = &sc->arpcom.ac_if; 949 mii = device_get_softc(sc->ste_miibus); 950 951 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 952 + CSR_READ_1(sc, STE_MULTI_COLLS) 953 + CSR_READ_1(sc, STE_SINGLE_COLLS); 954 955 if (!sc->ste_link) { 956 mii_pollstat(mii); 957 if (mii->mii_media_status & IFM_ACTIVE && 958 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 959 sc->ste_link++; 960 /* 961 * we don't get a call-back on re-init so do it 962 * otherwise we get stuck in the wrong link state 963 */ 964 ste_miibus_statchg(sc->ste_dev); 965 if (ifp->if_snd.ifq_head != NULL) 966 ste_start(ifp); 967 } 968 } 969 970 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 971 STE_UNLOCK(sc); 972 973 return; 974} 975 976 977/* 978 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 979 * IDs against our list and return a device name if we find a match. 980 */ 981static int 982ste_probe(dev) 983 device_t dev; 984{ 985 struct ste_type *t; 986 987 t = ste_devs; 988 989 while(t->ste_name != NULL) { 990 if ((pci_get_vendor(dev) == t->ste_vid) && 991 (pci_get_device(dev) == t->ste_did)) { 992 device_set_desc(dev, t->ste_name); 993 return(0); 994 } 995 t++; 996 } 997 998 return(ENXIO); 999} 1000 1001/* 1002 * Attach the interface. Allocate softc structures, do ifmedia 1003 * setup and ethernet/BPF attach. 1004 */ 1005static int 1006ste_attach(dev) 1007 device_t dev; 1008{ 1009 struct ste_softc *sc; 1010 struct ifnet *ifp; 1011 int unit, error = 0, rid; 1012 1013 sc = device_get_softc(dev); 1014 unit = device_get_unit(dev); 1015 sc->ste_dev = dev; 1016 1017 /* 1018 * Only use one PHY since this chip reports multiple 1019 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1020 * it is at 0 & 1. It is rev 0x12. 1021 */ 1022 if (pci_get_vendor(dev) == DL_VENDORID && 1023 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1024 pci_get_revid(dev) == 0x12 ) 1025 sc->ste_one_phy = 1; 1026 1027 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1028 MTX_DEF | MTX_RECURSE); 1029#ifndef BURN_BRIDGES 1030 /* 1031 * Handle power management nonsense. 1032 */ 1033 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1034 u_int32_t iobase, membase, irq; 1035 1036 /* Save important PCI config data. */ 1037 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 1038 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 1039 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 1040 1041 /* Reset the power state. */ 1042 printf("ste%d: chip is in D%d power mode " 1043 "-- setting to D0\n", unit, 1044 pci_get_powerstate(dev)); 1045 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1046 1047 /* Restore PCI config data. */ 1048 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 1049 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 1050 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 1051 } 1052#endif 1053 /* 1054 * Map control/status registers. 1055 */ 1056 pci_enable_busmaster(dev); 1057 1058 rid = STE_RID; 1059 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1060 1061 if (sc->ste_res == NULL) { 1062 printf ("ste%d: couldn't map ports/memory\n", unit); 1063 error = ENXIO; 1064 goto fail; 1065 } 1066 1067 sc->ste_btag = rman_get_bustag(sc->ste_res); 1068 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1069 1070 /* Allocate interrupt */ 1071 rid = 0; 1072 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1073 RF_SHAREABLE | RF_ACTIVE); 1074 1075 if (sc->ste_irq == NULL) { 1076 printf("ste%d: couldn't map interrupt\n", unit); 1077 error = ENXIO; 1078 goto fail; 1079 } 1080 1081 callout_handle_init(&sc->ste_stat_ch); 1082 1083 /* Reset the adapter. */ 1084 ste_reset(sc); 1085 1086 /* 1087 * Get station address from the EEPROM. 1088 */ 1089 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1090 STE_EEADDR_NODE0, 3, 0)) { 1091 printf("ste%d: failed to read station address\n", unit); 1092 error = ENXIO;; 1093 goto fail; 1094 } 1095 1096 sc->ste_unit = unit; 1097 1098 /* Allocate the descriptor queues. */ 1099 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1100 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1101 1102 if (sc->ste_ldata == NULL) { 1103 printf("ste%d: no memory for list buffers!\n", unit); 1104 error = ENXIO; 1105 goto fail; 1106 } 1107 1108 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1109 1110 /* Do MII setup. */ 1111 if (mii_phy_probe(dev, &sc->ste_miibus, 1112 ste_ifmedia_upd, ste_ifmedia_sts)) { 1113 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1114 error = ENXIO; 1115 goto fail; 1116 } 1117 1118 ifp = &sc->arpcom.ac_if; 1119 ifp->if_softc = sc; 1120 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1121 ifp->if_mtu = ETHERMTU; 1122 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1123 ifp->if_ioctl = ste_ioctl; 1124 ifp->if_start = ste_start; 1125 ifp->if_watchdog = ste_watchdog; 1126 ifp->if_init = ste_init; 1127 ifp->if_baudrate = 10000000; 1128 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1129 1130 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1131 1132 /* 1133 * Call MI attach routine. 1134 */ 1135 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1136 1137 /* 1138 * Tell the upper layer(s) we support long frames. 1139 */ 1140 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1141 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1142 1143 /* Hook interrupt last to avoid having to lock softc */ 1144 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1145 ste_intr, sc, &sc->ste_intrhand); 1146 1147 if (error) { 1148 printf("ste%d: couldn't set up irq\n", unit); 1149 ether_ifdetach(ifp); 1150 goto fail; 1151 } 1152 1153fail: 1154 if (error) 1155 ste_detach(dev); 1156 1157 return(error); 1158} 1159 1160/* 1161 * Shutdown hardware and free up resources. This can be called any 1162 * time after the mutex has been initialized. It is called in both 1163 * the error case in attach and the normal detach case so it needs 1164 * to be careful about only freeing resources that have actually been 1165 * allocated. 1166 */ 1167static int 1168ste_detach(dev) 1169 device_t dev; 1170{ 1171 struct ste_softc *sc; 1172 struct ifnet *ifp; 1173 1174 sc = device_get_softc(dev); 1175 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1176 STE_LOCK(sc); 1177 ifp = &sc->arpcom.ac_if; 1178 1179 /* These should only be active if attach succeeded */ 1180 if (device_is_attached(dev)) { 1181 ste_stop(sc); 1182 ether_ifdetach(ifp); 1183 } 1184 if (sc->ste_miibus) 1185 device_delete_child(dev, sc->ste_miibus); 1186 bus_generic_detach(dev); 1187 1188 if (sc->ste_intrhand) 1189 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1190 if (sc->ste_irq) 1191 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1192 if (sc->ste_res) 1193 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1194 1195 if (sc->ste_ldata) { 1196 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1197 M_DEVBUF); 1198 } 1199 1200 STE_UNLOCK(sc); 1201 mtx_destroy(&sc->ste_mtx); 1202 1203 return(0); 1204} 1205 1206static int 1207ste_newbuf(sc, c, m) 1208 struct ste_softc *sc; 1209 struct ste_chain_onefrag *c; 1210 struct mbuf *m; 1211{ 1212 struct mbuf *m_new = NULL; 1213 1214 if (m == NULL) { 1215 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1216 if (m_new == NULL) 1217 return(ENOBUFS); 1218 MCLGET(m_new, M_DONTWAIT); 1219 if (!(m_new->m_flags & M_EXT)) { 1220 m_freem(m_new); 1221 return(ENOBUFS); 1222 } 1223 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1224 } else { 1225 m_new = m; 1226 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1227 m_new->m_data = m_new->m_ext.ext_buf; 1228 } 1229 1230 m_adj(m_new, ETHER_ALIGN); 1231 1232 c->ste_mbuf = m_new; 1233 c->ste_ptr->ste_status = 0; 1234 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1235 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1236 1237 return(0); 1238} 1239 1240static int 1241ste_init_rx_list(sc) 1242 struct ste_softc *sc; 1243{ 1244 struct ste_chain_data *cd; 1245 struct ste_list_data *ld; 1246 int i; 1247 1248 cd = &sc->ste_cdata; 1249 ld = sc->ste_ldata; 1250 1251 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1252 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1253 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1254 return(ENOBUFS); 1255 if (i == (STE_RX_LIST_CNT - 1)) { 1256 cd->ste_rx_chain[i].ste_next = 1257 &cd->ste_rx_chain[0]; 1258 ld->ste_rx_list[i].ste_next = 1259 vtophys(&ld->ste_rx_list[0]); 1260 } else { 1261 cd->ste_rx_chain[i].ste_next = 1262 &cd->ste_rx_chain[i + 1]; 1263 ld->ste_rx_list[i].ste_next = 1264 vtophys(&ld->ste_rx_list[i + 1]); 1265 } 1266 ld->ste_rx_list[i].ste_status = 0; 1267 } 1268 1269 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1270 1271 return(0); 1272} 1273 1274static void 1275ste_init_tx_list(sc) 1276 struct ste_softc *sc; 1277{ 1278 struct ste_chain_data *cd; 1279 struct ste_list_data *ld; 1280 int i; 1281 1282 cd = &sc->ste_cdata; 1283 ld = sc->ste_ldata; 1284 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1285 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1286 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1287 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1288 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1289 if (i == (STE_TX_LIST_CNT - 1)) 1290 cd->ste_tx_chain[i].ste_next = 1291 &cd->ste_tx_chain[0]; 1292 else 1293 cd->ste_tx_chain[i].ste_next = 1294 &cd->ste_tx_chain[i + 1]; 1295 } 1296 1297 cd->ste_tx_prod = 0; 1298 cd->ste_tx_cons = 0; 1299 1300 return; 1301} 1302 1303static void 1304ste_init(xsc) 1305 void *xsc; 1306{ 1307 struct ste_softc *sc; 1308 int i; 1309 struct ifnet *ifp; 1310 1311 sc = xsc; 1312 STE_LOCK(sc); 1313 ifp = &sc->arpcom.ac_if; 1314 1315 ste_stop(sc); 1316 1317 /* Init our MAC address */ 1318 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1319 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1320 } 1321 1322 /* Init RX list */ 1323 if (ste_init_rx_list(sc) == ENOBUFS) { 1324 printf("ste%d: initialization failed: no " 1325 "memory for RX buffers\n", sc->ste_unit); 1326 ste_stop(sc); 1327 STE_UNLOCK(sc); 1328 return; 1329 } 1330 1331 /* Set RX polling interval */ 1332 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1333 1334 /* Init TX descriptors */ 1335 ste_init_tx_list(sc); 1336 1337 /* Set the TX freethresh value */ 1338 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1339 1340 /* Set the TX start threshold for best performance. */ 1341 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1342 1343 /* Set the TX reclaim threshold. */ 1344 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1345 1346 /* Set up the RX filter. */ 1347 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1348 1349 /* If we want promiscuous mode, set the allframes bit. */ 1350 if (ifp->if_flags & IFF_PROMISC) { 1351 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1352 } else { 1353 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1354 } 1355 1356 /* Set capture broadcast bit to accept broadcast frames. */ 1357 if (ifp->if_flags & IFF_BROADCAST) { 1358 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1359 } else { 1360 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1361 } 1362 1363 ste_setmulti(sc); 1364 1365 /* Load the address of the RX list. */ 1366 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1367 ste_wait(sc); 1368 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1369 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1370 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1371 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1372 1373 /* Set TX polling interval (defer until we TX first packet */ 1374 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1375 1376 /* Load address of the TX list */ 1377 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1378 ste_wait(sc); 1379 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1380 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1381 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1382 ste_wait(sc); 1383 sc->ste_tx_prev = NULL; 1384 1385 /* Enable receiver and transmitter */ 1386 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1387 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1388 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1389 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1390 1391 /* Enable stats counters. */ 1392 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1393 1394 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1395#ifdef DEVICE_POLLING 1396 /* Disable interrupts if we are polling. */ 1397 if (ifp->if_flags & IFF_POLLING) 1398 CSR_WRITE_2(sc, STE_IMR, 0); 1399 else 1400#endif /* DEVICE_POLLING */ 1401 /* Enable interrupts. */ 1402 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1403 1404 /* Accept VLAN length packets */ 1405 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1406 1407 ste_ifmedia_upd(ifp); 1408 1409 ifp->if_flags |= IFF_RUNNING; 1410 ifp->if_flags &= ~IFF_OACTIVE; 1411 1412 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1413 STE_UNLOCK(sc); 1414 1415 return; 1416} 1417 1418static void 1419ste_stop(sc) 1420 struct ste_softc *sc; 1421{ 1422 int i; 1423 struct ifnet *ifp; 1424 1425 STE_LOCK(sc); 1426 ifp = &sc->arpcom.ac_if; 1427 1428 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1429 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1430#ifdef DEVICE_POLLING 1431 ether_poll_deregister(ifp); 1432#endif /* DEVICE_POLLING */ 1433 1434 CSR_WRITE_2(sc, STE_IMR, 0); 1435 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1436 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1437 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1438 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1439 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1440 ste_wait(sc); 1441 /* 1442 * Try really hard to stop the RX engine or under heavy RX 1443 * data chip will write into de-allocated memory. 1444 */ 1445 ste_reset(sc); 1446 1447 sc->ste_link = 0; 1448 1449 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1450 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1451 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1452 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1453 } 1454 } 1455 1456 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1457 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1458 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1459 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1460 } 1461 } 1462 1463 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1464 STE_UNLOCK(sc); 1465 1466 return; 1467} 1468 1469static void 1470ste_reset(sc) 1471 struct ste_softc *sc; 1472{ 1473 int i; 1474 1475 STE_SETBIT4(sc, STE_ASICCTL, 1476 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1477 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1478 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1479 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1480 STE_ASICCTL_EXTRESET_RESET); 1481 1482 DELAY(100000); 1483 1484 for (i = 0; i < STE_TIMEOUT; i++) { 1485 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1486 break; 1487 } 1488 1489 if (i == STE_TIMEOUT) 1490 printf("ste%d: global reset never completed\n", sc->ste_unit); 1491 1492 return; 1493} 1494 1495static int 1496ste_ioctl(ifp, command, data) 1497 struct ifnet *ifp; 1498 u_long command; 1499 caddr_t data; 1500{ 1501 struct ste_softc *sc; 1502 struct ifreq *ifr; 1503 struct mii_data *mii; 1504 int error = 0; 1505 1506 sc = ifp->if_softc; 1507 STE_LOCK(sc); 1508 ifr = (struct ifreq *)data; 1509 1510 switch(command) { 1511 case SIOCSIFFLAGS: 1512 if (ifp->if_flags & IFF_UP) { 1513 if (ifp->if_flags & IFF_RUNNING && 1514 ifp->if_flags & IFF_PROMISC && 1515 !(sc->ste_if_flags & IFF_PROMISC)) { 1516 STE_SETBIT1(sc, STE_RX_MODE, 1517 STE_RXMODE_PROMISC); 1518 } else if (ifp->if_flags & IFF_RUNNING && 1519 !(ifp->if_flags & IFF_PROMISC) && 1520 sc->ste_if_flags & IFF_PROMISC) { 1521 STE_CLRBIT1(sc, STE_RX_MODE, 1522 STE_RXMODE_PROMISC); 1523 } 1524 if (ifp->if_flags & IFF_RUNNING && 1525 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1526 ste_setmulti(sc); 1527 if (!(ifp->if_flags & IFF_RUNNING)) { 1528 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1529 ste_init(sc); 1530 } 1531 } else { 1532 if (ifp->if_flags & IFF_RUNNING) 1533 ste_stop(sc); 1534 } 1535 sc->ste_if_flags = ifp->if_flags; 1536 error = 0; 1537 break; 1538 case SIOCADDMULTI: 1539 case SIOCDELMULTI: 1540 ste_setmulti(sc); 1541 error = 0; 1542 break; 1543 case SIOCGIFMEDIA: 1544 case SIOCSIFMEDIA: 1545 mii = device_get_softc(sc->ste_miibus); 1546 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1547 break; 1548 default: 1549 error = ether_ioctl(ifp, command, data); 1550 break; 1551 } 1552 1553 STE_UNLOCK(sc); 1554 1555 return(error); 1556} 1557 1558static int 1559ste_encap(sc, c, m_head) 1560 struct ste_softc *sc; 1561 struct ste_chain *c; 1562 struct mbuf *m_head; 1563{ 1564 int frag = 0; 1565 struct ste_frag *f = NULL; 1566 struct mbuf *m; 1567 struct ste_desc *d; 1568 1569 d = c->ste_ptr; 1570 d->ste_ctl = 0; 1571 1572encap_retry: 1573 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1574 if (m->m_len != 0) { 1575 if (frag == STE_MAXFRAGS) 1576 break; 1577 f = &d->ste_frags[frag]; 1578 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1579 f->ste_len = m->m_len; 1580 frag++; 1581 } 1582 } 1583 1584 if (m != NULL) { 1585 struct mbuf *mn; 1586 1587 /* 1588 * We ran out of segments. We have to recopy this 1589 * mbuf chain first. Bail out if we can't get the 1590 * new buffers. 1591 */ 1592 mn = m_defrag(m_head, M_DONTWAIT); 1593 if (mn == NULL) { 1594 m_freem(m_head); 1595 return ENOMEM; 1596 } 1597 m_head = mn; 1598 goto encap_retry; 1599 } 1600 1601 c->ste_mbuf = m_head; 1602 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1603 d->ste_ctl = 1; 1604 1605 return(0); 1606} 1607 1608static void 1609ste_start(ifp) 1610 struct ifnet *ifp; 1611{ 1612 struct ste_softc *sc; 1613 struct mbuf *m_head = NULL; 1614 struct ste_chain *cur_tx; 1615 int idx; 1616 1617 sc = ifp->if_softc; 1618 STE_LOCK(sc); 1619 1620 if (!sc->ste_link) { 1621 STE_UNLOCK(sc); 1622 return; 1623 } 1624 1625 if (ifp->if_flags & IFF_OACTIVE) { 1626 STE_UNLOCK(sc); 1627 return; 1628 } 1629 1630 idx = sc->ste_cdata.ste_tx_prod; 1631 1632 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1633 /* 1634 * We cannot re-use the last (free) descriptor; 1635 * the chip may not have read its ste_next yet. 1636 */ 1637 if (STE_NEXT(idx, STE_TX_LIST_CNT) == 1638 sc->ste_cdata.ste_tx_cons) { 1639 ifp->if_flags |= IFF_OACTIVE; 1640 break; 1641 } 1642 1643 IF_DEQUEUE(&ifp->if_snd, m_head); 1644 if (m_head == NULL) 1645 break; 1646 1647 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1648 1649 if (ste_encap(sc, cur_tx, m_head) != 0) 1650 break; 1651 1652 cur_tx->ste_ptr->ste_next = 0; 1653 1654 if (sc->ste_tx_prev == NULL) { 1655 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1656 /* Load address of the TX list */ 1657 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1658 ste_wait(sc); 1659 1660 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1661 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1662 1663 /* Set TX polling interval to start TX engine */ 1664 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1665 1666 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1667 ste_wait(sc); 1668 }else{ 1669 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1670 sc->ste_tx_prev->ste_ptr->ste_next 1671 = cur_tx->ste_phys; 1672 } 1673 1674 sc->ste_tx_prev = cur_tx; 1675 1676 /* 1677 * If there's a BPF listener, bounce a copy of this frame 1678 * to him. 1679 */ 1680 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1681 1682 STE_INC(idx, STE_TX_LIST_CNT); 1683 ifp->if_timer = 5; 1684 } 1685 sc->ste_cdata.ste_tx_prod = idx; 1686 1687 STE_UNLOCK(sc); 1688 1689 return; 1690} 1691 1692static void 1693ste_watchdog(ifp) 1694 struct ifnet *ifp; 1695{ 1696 struct ste_softc *sc; 1697 1698 sc = ifp->if_softc; 1699 STE_LOCK(sc); 1700 1701 ifp->if_oerrors++; 1702 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1703 1704 ste_txeoc(sc); 1705 ste_txeof(sc); 1706 ste_rxeoc(sc); 1707 ste_rxeof(sc); 1708 ste_reset(sc); 1709 ste_init(sc); 1710 1711 if (ifp->if_snd.ifq_head != NULL) 1712 ste_start(ifp); 1713 STE_UNLOCK(sc); 1714 1715 return; 1716} 1717 1718static void 1719ste_shutdown(dev) 1720 device_t dev; 1721{ 1722 struct ste_softc *sc; 1723 1724 sc = device_get_softc(dev); 1725 1726 ste_stop(sc); 1727 1728 return; 1729} 1730