if_ste.c revision 127775
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 127775 2004-04-02 23:36:49Z ru $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44 45#include <net/if.h> 46#include <net/if_arp.h> 47#include <net/ethernet.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <vm/vm.h> /* for vtophys */ 55#include <vm/pmap.h> /* for vtophys */ 56#include <machine/bus_memio.h> 57#include <machine/bus_pio.h> 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69/* "controller miibus0" required. See GENERIC if you get errors here. */ 70#include "miibus_if.h" 71 72#define STE_USEIOSPACE 73 74#include <pci/if_stereg.h> 75 76MODULE_DEPEND(ste, pci, 1, 1, 1); 77MODULE_DEPEND(ste, ether, 1, 1, 1); 78MODULE_DEPEND(ste, miibus, 1, 1, 1); 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe (device_t); 90static int ste_attach (device_t); 91static int ste_detach (device_t); 92static void ste_init (void *); 93static void ste_intr (void *); 94static void ste_rxeoc (struct ste_softc *); 95static void ste_rxeof (struct ste_softc *); 96static void ste_txeoc (struct ste_softc *); 97static void ste_txeof (struct ste_softc *); 98static void ste_stats_update (void *); 99static void ste_stop (struct ste_softc *); 100static void ste_reset (struct ste_softc *); 101static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104static void ste_start (struct ifnet *); 105static void ste_watchdog (struct ifnet *); 106static void ste_shutdown (device_t); 107static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd (struct ifnet *); 111static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113static void ste_mii_sync (struct ste_softc *); 114static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg (device_t, int, int); 118static int ste_miibus_writereg (device_t, int, int, int); 119static void ste_miibus_statchg (device_t); 120 121static int ste_eeprom_wait (struct ste_softc *); 122static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123static void ste_wait (struct ste_softc *); 124static u_int8_t ste_calchash (caddr_t); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 168 169static int ste_rxsyncs; 170SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 171 172#define STE_SETBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 174 175#define STE_CLRBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 177 178#define STE_SETBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 180 181#define STE_CLRBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 183 184#define STE_SETBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186 187#define STE_CLRBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 189 190 191#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 192#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 193 194/* 195 * Sync the PHYs by setting data bit and strobing the clock 32 times. 196 */ 197static void 198ste_mii_sync(sc) 199 struct ste_softc *sc; 200{ 201 register int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211 212 return; 213} 214 215/* 216 * Clock a series of bits through the MII. 217 */ 218static void 219ste_mii_send(sc, bits, cnt) 220 struct ste_softc *sc; 221 u_int32_t bits; 222 int cnt; 223{ 224 int i; 225 226 MII_CLR(STE_PHYCTL_MCLK); 227 228 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 229 if (bits & i) { 230 MII_SET(STE_PHYCTL_MDATA); 231 } else { 232 MII_CLR(STE_PHYCTL_MDATA); 233 } 234 DELAY(1); 235 MII_CLR(STE_PHYCTL_MCLK); 236 DELAY(1); 237 MII_SET(STE_PHYCTL_MCLK); 238 } 239} 240 241/* 242 * Read an PHY register through the MII. 243 */ 244static int 245ste_mii_readreg(sc, frame) 246 struct ste_softc *sc; 247 struct ste_mii_frame *frame; 248 249{ 250 int i, ack; 251 252 STE_LOCK(sc); 253 254 /* 255 * Set up frame for RX. 256 */ 257 frame->mii_stdelim = STE_MII_STARTDELIM; 258 frame->mii_opcode = STE_MII_READOP; 259 frame->mii_turnaround = 0; 260 frame->mii_data = 0; 261 262 CSR_WRITE_2(sc, STE_PHYCTL, 0); 263 /* 264 * Turn on data xmit. 265 */ 266 MII_SET(STE_PHYCTL_MDIR); 267 268 ste_mii_sync(sc); 269 270 /* 271 * Send command/address info. 272 */ 273 ste_mii_send(sc, frame->mii_stdelim, 2); 274 ste_mii_send(sc, frame->mii_opcode, 2); 275 ste_mii_send(sc, frame->mii_phyaddr, 5); 276 ste_mii_send(sc, frame->mii_regaddr, 5); 277 278 /* Turn off xmit. */ 279 MII_CLR(STE_PHYCTL_MDIR); 280 281 /* Idle bit */ 282 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 283 DELAY(1); 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* Check for ack */ 288 MII_CLR(STE_PHYCTL_MCLK); 289 DELAY(1); 290 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 291 MII_SET(STE_PHYCTL_MCLK); 292 DELAY(1); 293 294 /* 295 * Now try reading data bits. If the ack failed, we still 296 * need to clock through 16 cycles to keep the PHY(s) in sync. 297 */ 298 if (ack) { 299 for(i = 0; i < 16; i++) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 MII_SET(STE_PHYCTL_MCLK); 303 DELAY(1); 304 } 305 goto fail; 306 } 307 308 for (i = 0x8000; i; i >>= 1) { 309 MII_CLR(STE_PHYCTL_MCLK); 310 DELAY(1); 311 if (!ack) { 312 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 313 frame->mii_data |= i; 314 DELAY(1); 315 } 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 } 319 320fail: 321 322 MII_CLR(STE_PHYCTL_MCLK); 323 DELAY(1); 324 MII_SET(STE_PHYCTL_MCLK); 325 DELAY(1); 326 327 STE_UNLOCK(sc); 328 329 if (ack) 330 return(1); 331 return(0); 332} 333 334/* 335 * Write to a PHY register through the MII. 336 */ 337static int 338ste_mii_writereg(sc, frame) 339 struct ste_softc *sc; 340 struct ste_mii_frame *frame; 341 342{ 343 STE_LOCK(sc); 344 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 STE_UNLOCK(sc); 379 380 return(0); 381} 382 383static int 384ste_miibus_readreg(dev, phy, reg) 385 device_t dev; 386 int phy, reg; 387{ 388 struct ste_softc *sc; 389 struct ste_mii_frame frame; 390 391 sc = device_get_softc(dev); 392 393 if ( sc->ste_one_phy && phy != 0 ) 394 return (0); 395 396 bzero((char *)&frame, sizeof(frame)); 397 398 frame.mii_phyaddr = phy; 399 frame.mii_regaddr = reg; 400 ste_mii_readreg(sc, &frame); 401 402 return(frame.mii_data); 403} 404 405static int 406ste_miibus_writereg(dev, phy, reg, data) 407 device_t dev; 408 int phy, reg, data; 409{ 410 struct ste_softc *sc; 411 struct ste_mii_frame frame; 412 413 sc = device_get_softc(dev); 414 bzero((char *)&frame, sizeof(frame)); 415 416 frame.mii_phyaddr = phy; 417 frame.mii_regaddr = reg; 418 frame.mii_data = data; 419 420 ste_mii_writereg(sc, &frame); 421 422 return(0); 423} 424 425static void 426ste_miibus_statchg(dev) 427 device_t dev; 428{ 429 struct ste_softc *sc; 430 struct mii_data *mii; 431 432 sc = device_get_softc(dev); 433 STE_LOCK(sc); 434 mii = device_get_softc(sc->ste_miibus); 435 436 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 437 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 438 } else { 439 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 440 } 441 STE_UNLOCK(sc); 442 443 return; 444} 445 446static int 447ste_ifmedia_upd(ifp) 448 struct ifnet *ifp; 449{ 450 struct ste_softc *sc; 451 struct mii_data *mii; 452 453 sc = ifp->if_softc; 454 mii = device_get_softc(sc->ste_miibus); 455 sc->ste_link = 0; 456 if (mii->mii_instance) { 457 struct mii_softc *miisc; 458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 459 mii_phy_reset(miisc); 460 } 461 mii_mediachg(mii); 462 463 return(0); 464} 465 466static void 467ste_ifmedia_sts(ifp, ifmr) 468 struct ifnet *ifp; 469 struct ifmediareq *ifmr; 470{ 471 struct ste_softc *sc; 472 struct mii_data *mii; 473 474 sc = ifp->if_softc; 475 mii = device_get_softc(sc->ste_miibus); 476 477 mii_pollstat(mii); 478 ifmr->ifm_active = mii->mii_media_active; 479 ifmr->ifm_status = mii->mii_media_status; 480 481 return; 482} 483 484static void 485ste_wait(sc) 486 struct ste_softc *sc; 487{ 488 register int i; 489 490 for (i = 0; i < STE_TIMEOUT; i++) { 491 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 492 break; 493 } 494 495 if (i == STE_TIMEOUT) 496 printf("ste%d: command never completed!\n", sc->ste_unit); 497 498 return; 499} 500 501/* 502 * The EEPROM is slow: give it time to come ready after issuing 503 * it a command. 504 */ 505static int 506ste_eeprom_wait(sc) 507 struct ste_softc *sc; 508{ 509 int i; 510 511 DELAY(1000); 512 513 for (i = 0; i < 100; i++) { 514 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 515 DELAY(1000); 516 else 517 break; 518 } 519 520 if (i == 100) { 521 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 522 return(1); 523 } 524 525 return(0); 526} 527 528/* 529 * Read a sequence of words from the EEPROM. Note that ethernet address 530 * data is stored in the EEPROM in network byte order. 531 */ 532static int 533ste_read_eeprom(sc, dest, off, cnt, swap) 534 struct ste_softc *sc; 535 caddr_t dest; 536 int off; 537 int cnt; 538 int swap; 539{ 540 int err = 0, i; 541 u_int16_t word = 0, *ptr; 542 543 if (ste_eeprom_wait(sc)) 544 return(1); 545 546 for (i = 0; i < cnt; i++) { 547 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 548 err = ste_eeprom_wait(sc); 549 if (err) 550 break; 551 word = CSR_READ_2(sc, STE_EEPROM_DATA); 552 ptr = (u_int16_t *)(dest + (i * 2)); 553 if (swap) 554 *ptr = ntohs(word); 555 else 556 *ptr = word; 557 } 558 559 return(err ? 1 : 0); 560} 561 562static u_int8_t 563ste_calchash(addr) 564 caddr_t addr; 565{ 566 567 u_int32_t crc, carry; 568 int i, j; 569 u_int8_t c; 570 571 /* Compute CRC for the address value. */ 572 crc = 0xFFFFFFFF; /* initial value */ 573 574 for (i = 0; i < 6; i++) { 575 c = *(addr + i); 576 for (j = 0; j < 8; j++) { 577 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 578 crc <<= 1; 579 c >>= 1; 580 if (carry) 581 crc = (crc ^ 0x04c11db6) | carry; 582 } 583 } 584 585 /* return the filter bit position */ 586 return(crc & 0x0000003F); 587} 588 589static void 590ste_setmulti(sc) 591 struct ste_softc *sc; 592{ 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 598 ifp = &sc->arpcom.ac_if; 599 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 600 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 601 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 602 return; 603 } 604 605 /* first, zot all the existing hash bits */ 606 CSR_WRITE_2(sc, STE_MAR0, 0); 607 CSR_WRITE_2(sc, STE_MAR1, 0); 608 CSR_WRITE_2(sc, STE_MAR2, 0); 609 CSR_WRITE_2(sc, STE_MAR3, 0); 610 611 /* now program new ones */ 612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 613 if (ifma->ifma_addr->sa_family != AF_LINK) 614 continue; 615 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 616 if (h < 32) 617 hashes[0] |= (1 << h); 618 else 619 hashes[1] |= (1 << (h - 32)); 620 } 621 622 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 623 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 624 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 625 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 626 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 627 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 628 629 return; 630} 631 632#ifdef DEVICE_POLLING 633static poll_handler_t ste_poll; 634 635static void 636ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 637{ 638 struct ste_softc *sc = ifp->if_softc; 639 640 STE_LOCK(sc); 641 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 642 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 643 goto done; 644 } 645 646 sc->rxcycles = count; 647 if (cmd == POLL_AND_CHECK_STATUS) 648 ste_rxeoc(sc); 649 ste_rxeof(sc); 650 ste_txeof(sc); 651 if (ifp->if_snd.ifq_head != NULL) 652 ste_start(ifp); 653 654 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 655 u_int16_t status; 656 657 status = CSR_READ_2(sc, STE_ISR_ACK); 658 659 if (status & STE_ISR_TX_DONE) 660 ste_txeoc(sc); 661 662 if (status & STE_ISR_STATS_OFLOW) { 663 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 664 ste_stats_update(sc); 665 } 666 667 if (status & STE_ISR_LINKEVENT) 668 mii_pollstat(device_get_softc(sc->ste_miibus)); 669 670 if (status & STE_ISR_HOSTERR) { 671 ste_reset(sc); 672 ste_init(sc); 673 } 674 } 675done: 676 STE_UNLOCK(sc); 677} 678#endif /* DEVICE_POLLING */ 679 680static void 681ste_intr(xsc) 682 void *xsc; 683{ 684 struct ste_softc *sc; 685 struct ifnet *ifp; 686 u_int16_t status; 687 688 sc = xsc; 689 STE_LOCK(sc); 690 ifp = &sc->arpcom.ac_if; 691 692#ifdef DEVICE_POLLING 693 if (ifp->if_flags & IFF_POLLING) 694 goto done; 695 if (ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 696 CSR_WRITE_2(sc, STE_IMR, 0); 697 ste_poll(ifp, 0, 1); 698 goto done; 699 } 700#endif /* DEVICE_POLLING */ 701 702 /* See if this is really our interrupt. */ 703 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 704 STE_UNLOCK(sc); 705 return; 706 } 707 708 for (;;) { 709 status = CSR_READ_2(sc, STE_ISR_ACK); 710 711 if (!(status & STE_INTRS)) 712 break; 713 714 if (status & STE_ISR_RX_DMADONE) { 715 ste_rxeoc(sc); 716 ste_rxeof(sc); 717 } 718 719 if (status & STE_ISR_TX_DMADONE) 720 ste_txeof(sc); 721 722 if (status & STE_ISR_TX_DONE) 723 ste_txeoc(sc); 724 725 if (status & STE_ISR_STATS_OFLOW) { 726 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 727 ste_stats_update(sc); 728 } 729 730 if (status & STE_ISR_LINKEVENT) 731 mii_pollstat(device_get_softc(sc->ste_miibus)); 732 733 734 if (status & STE_ISR_HOSTERR) { 735 ste_reset(sc); 736 ste_init(sc); 737 } 738 } 739 740 /* Re-enable interrupts */ 741 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 742 743 if (ifp->if_snd.ifq_head != NULL) 744 ste_start(ifp); 745 746#ifdef DEVICE_POLLING 747done: 748#endif /* DEVICE_POLLING */ 749 STE_UNLOCK(sc); 750 751 return; 752} 753 754static void 755ste_rxeoc(struct ste_softc *sc) 756{ 757 struct ste_chain_onefrag *cur_rx; 758 759 STE_LOCK_ASSERT(sc); 760 761 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 762 cur_rx = sc->ste_cdata.ste_rx_head; 763 do { 764 cur_rx = cur_rx->ste_next; 765 /* If the ring is empty, just return. */ 766 if (cur_rx == sc->ste_cdata.ste_rx_head) 767 return; 768 } while (cur_rx->ste_ptr->ste_status == 0); 769 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 770 /* We've fallen behind the chip: catch it. */ 771 sc->ste_cdata.ste_rx_head = cur_rx; 772 ++ste_rxsyncs; 773 } 774 } 775} 776 777/* 778 * A frame has been uploaded: pass the resulting mbuf chain up to 779 * the higher level protocols. 780 */ 781static void 782ste_rxeof(sc) 783 struct ste_softc *sc; 784{ 785 struct mbuf *m; 786 struct ifnet *ifp; 787 struct ste_chain_onefrag *cur_rx; 788 int total_len = 0, count=0; 789 u_int32_t rxstat; 790 791 STE_LOCK_ASSERT(sc); 792 793 ifp = &sc->arpcom.ac_if; 794 795 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 796 & STE_RXSTAT_DMADONE) { 797#ifdef DEVICE_POLLING 798 if (ifp->if_flags & IFF_POLLING) { 799 if (sc->rxcycles <= 0) 800 break; 801 sc->rxcycles--; 802 } 803#endif /* DEVICE_POLLING */ 804 if ((STE_RX_LIST_CNT - count) < 3) { 805 break; 806 } 807 808 cur_rx = sc->ste_cdata.ste_rx_head; 809 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 810 811 /* 812 * If an error occurs, update stats, clear the 813 * status word and leave the mbuf cluster in place: 814 * it should simply get re-used next time this descriptor 815 * comes up in the ring. 816 */ 817 if (rxstat & STE_RXSTAT_FRAME_ERR) { 818 ifp->if_ierrors++; 819 cur_rx->ste_ptr->ste_status = 0; 820 continue; 821 } 822 823 /* 824 * If there error bit was not set, the upload complete 825 * bit should be set which means we have a valid packet. 826 * If not, something truly strange has happened. 827 */ 828 if (!(rxstat & STE_RXSTAT_DMADONE)) { 829 printf("ste%d: bad receive status -- packet dropped\n", 830 sc->ste_unit); 831 ifp->if_ierrors++; 832 cur_rx->ste_ptr->ste_status = 0; 833 continue; 834 } 835 836 /* No errors; receive the packet. */ 837 m = cur_rx->ste_mbuf; 838 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 839 840 /* 841 * Try to conjure up a new mbuf cluster. If that 842 * fails, it means we have an out of memory condition and 843 * should leave the buffer in place and continue. This will 844 * result in a lost packet, but there's little else we 845 * can do in this situation. 846 */ 847 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 848 ifp->if_ierrors++; 849 cur_rx->ste_ptr->ste_status = 0; 850 continue; 851 } 852 853 m->m_pkthdr.rcvif = ifp; 854 m->m_pkthdr.len = m->m_len = total_len; 855 856 ifp->if_ipackets++; 857 STE_UNLOCK(sc); 858 (*ifp->if_input)(ifp, m); 859 STE_LOCK(sc); 860 861 cur_rx->ste_ptr->ste_status = 0; 862 count++; 863 } 864 865 return; 866} 867 868static void 869ste_txeoc(sc) 870 struct ste_softc *sc; 871{ 872 u_int8_t txstat; 873 struct ifnet *ifp; 874 875 ifp = &sc->arpcom.ac_if; 876 877 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 878 STE_TXSTATUS_TXDONE) { 879 if (txstat & STE_TXSTATUS_UNDERRUN || 880 txstat & STE_TXSTATUS_EXCESSCOLLS || 881 txstat & STE_TXSTATUS_RECLAIMERR) { 882 ifp->if_oerrors++; 883 printf("ste%d: transmission error: %x\n", 884 sc->ste_unit, txstat); 885 886 ste_reset(sc); 887 ste_init(sc); 888 889 if (txstat & STE_TXSTATUS_UNDERRUN && 890 sc->ste_tx_thresh < STE_PACKET_SIZE) { 891 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 892 printf("ste%d: tx underrun, increasing tx" 893 " start threshold to %d bytes\n", 894 sc->ste_unit, sc->ste_tx_thresh); 895 } 896 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 897 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 898 (STE_PACKET_SIZE >> 4)); 899 } 900 ste_init(sc); 901 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 902 } 903 904 return; 905} 906 907static void 908ste_txeof(sc) 909 struct ste_softc *sc; 910{ 911 struct ste_chain *cur_tx; 912 struct ifnet *ifp; 913 int idx; 914 915 ifp = &sc->arpcom.ac_if; 916 917 idx = sc->ste_cdata.ste_tx_cons; 918 while(idx != sc->ste_cdata.ste_tx_prod) { 919 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 920 921 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 922 break; 923 924 m_freem(cur_tx->ste_mbuf); 925 cur_tx->ste_mbuf = NULL; 926 927 ifp->if_opackets++; 928 929 sc->ste_cdata.ste_tx_cnt--; 930 STE_INC(idx, STE_TX_LIST_CNT); 931 } 932 933 if (idx != sc->ste_cdata.ste_tx_cons) { 934 sc->ste_cdata.ste_tx_cons = idx; 935 ifp->if_flags &= ~IFF_OACTIVE; 936 if (idx == sc->ste_cdata.ste_tx_prod) 937 ifp->if_timer = 0; 938 } 939} 940 941static void 942ste_stats_update(xsc) 943 void *xsc; 944{ 945 struct ste_softc *sc; 946 struct ifnet *ifp; 947 struct mii_data *mii; 948 949 sc = xsc; 950 STE_LOCK(sc); 951 952 ifp = &sc->arpcom.ac_if; 953 mii = device_get_softc(sc->ste_miibus); 954 955 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 956 + CSR_READ_1(sc, STE_MULTI_COLLS) 957 + CSR_READ_1(sc, STE_SINGLE_COLLS); 958 959 if (!sc->ste_link) { 960 mii_pollstat(mii); 961 if (mii->mii_media_status & IFM_ACTIVE && 962 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 963 sc->ste_link++; 964 /* 965 * we don't get a call-back on re-init so do it 966 * otherwise we get stuck in the wrong link state 967 */ 968 ste_miibus_statchg(sc->ste_dev); 969 if (ifp->if_snd.ifq_head != NULL) 970 ste_start(ifp); 971 } 972 } 973 974 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 975 STE_UNLOCK(sc); 976 977 return; 978} 979 980 981/* 982 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 983 * IDs against our list and return a device name if we find a match. 984 */ 985static int 986ste_probe(dev) 987 device_t dev; 988{ 989 struct ste_type *t; 990 991 t = ste_devs; 992 993 while(t->ste_name != NULL) { 994 if ((pci_get_vendor(dev) == t->ste_vid) && 995 (pci_get_device(dev) == t->ste_did)) { 996 device_set_desc(dev, t->ste_name); 997 return(0); 998 } 999 t++; 1000 } 1001 1002 return(ENXIO); 1003} 1004 1005/* 1006 * Attach the interface. Allocate softc structures, do ifmedia 1007 * setup and ethernet/BPF attach. 1008 */ 1009static int 1010ste_attach(dev) 1011 device_t dev; 1012{ 1013 struct ste_softc *sc; 1014 struct ifnet *ifp; 1015 int unit, error = 0, rid; 1016 1017 sc = device_get_softc(dev); 1018 unit = device_get_unit(dev); 1019 sc->ste_dev = dev; 1020 1021 /* 1022 * Only use one PHY since this chip reports multiple 1023 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1024 * it is at 0 & 1. It is rev 0x12. 1025 */ 1026 if (pci_get_vendor(dev) == DL_VENDORID && 1027 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1028 pci_get_revid(dev) == 0x12 ) 1029 sc->ste_one_phy = 1; 1030 1031 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1032 MTX_DEF | MTX_RECURSE); 1033#ifndef BURN_BRIDGES 1034 /* 1035 * Handle power management nonsense. 1036 */ 1037 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1038 u_int32_t iobase, membase, irq; 1039 1040 /* Save important PCI config data. */ 1041 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 1042 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 1043 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 1044 1045 /* Reset the power state. */ 1046 printf("ste%d: chip is in D%d power mode " 1047 "-- setting to D0\n", unit, 1048 pci_get_powerstate(dev)); 1049 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1050 1051 /* Restore PCI config data. */ 1052 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 1053 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 1054 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 1055 } 1056#endif 1057 /* 1058 * Map control/status registers. 1059 */ 1060 pci_enable_busmaster(dev); 1061 1062 rid = STE_RID; 1063 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1064 1065 if (sc->ste_res == NULL) { 1066 printf ("ste%d: couldn't map ports/memory\n", unit); 1067 error = ENXIO; 1068 goto fail; 1069 } 1070 1071 sc->ste_btag = rman_get_bustag(sc->ste_res); 1072 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1073 1074 /* Allocate interrupt */ 1075 rid = 0; 1076 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1077 RF_SHAREABLE | RF_ACTIVE); 1078 1079 if (sc->ste_irq == NULL) { 1080 printf("ste%d: couldn't map interrupt\n", unit); 1081 error = ENXIO; 1082 goto fail; 1083 } 1084 1085 callout_handle_init(&sc->ste_stat_ch); 1086 1087 /* Reset the adapter. */ 1088 ste_reset(sc); 1089 1090 /* 1091 * Get station address from the EEPROM. 1092 */ 1093 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1094 STE_EEADDR_NODE0, 3, 0)) { 1095 printf("ste%d: failed to read station address\n", unit); 1096 error = ENXIO;; 1097 goto fail; 1098 } 1099 1100 sc->ste_unit = unit; 1101 1102 /* Allocate the descriptor queues. */ 1103 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1104 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1105 1106 if (sc->ste_ldata == NULL) { 1107 printf("ste%d: no memory for list buffers!\n", unit); 1108 error = ENXIO; 1109 goto fail; 1110 } 1111 1112 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1113 1114 /* Do MII setup. */ 1115 if (mii_phy_probe(dev, &sc->ste_miibus, 1116 ste_ifmedia_upd, ste_ifmedia_sts)) { 1117 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1118 error = ENXIO; 1119 goto fail; 1120 } 1121 1122 ifp = &sc->arpcom.ac_if; 1123 ifp->if_softc = sc; 1124 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1125 ifp->if_mtu = ETHERMTU; 1126 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1127 ifp->if_ioctl = ste_ioctl; 1128 ifp->if_start = ste_start; 1129 ifp->if_watchdog = ste_watchdog; 1130 ifp->if_init = ste_init; 1131 ifp->if_baudrate = 10000000; 1132 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1133 1134 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1135 1136 /* 1137 * Call MI attach routine. 1138 */ 1139 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1140 1141 /* 1142 * Tell the upper layer(s) we support long frames. 1143 */ 1144 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1145 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1146 1147 /* Hook interrupt last to avoid having to lock softc */ 1148 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1149 ste_intr, sc, &sc->ste_intrhand); 1150 1151 if (error) { 1152 printf("ste%d: couldn't set up irq\n", unit); 1153 ether_ifdetach(ifp); 1154 goto fail; 1155 } 1156 1157fail: 1158 if (error) 1159 ste_detach(dev); 1160 1161 return(error); 1162} 1163 1164/* 1165 * Shutdown hardware and free up resources. This can be called any 1166 * time after the mutex has been initialized. It is called in both 1167 * the error case in attach and the normal detach case so it needs 1168 * to be careful about only freeing resources that have actually been 1169 * allocated. 1170 */ 1171static int 1172ste_detach(dev) 1173 device_t dev; 1174{ 1175 struct ste_softc *sc; 1176 struct ifnet *ifp; 1177 1178 sc = device_get_softc(dev); 1179 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1180 STE_LOCK(sc); 1181 ifp = &sc->arpcom.ac_if; 1182 1183 /* These should only be active if attach succeeded */ 1184 if (device_is_attached(dev)) { 1185 ste_stop(sc); 1186 ether_ifdetach(ifp); 1187 } 1188 if (sc->ste_miibus) 1189 device_delete_child(dev, sc->ste_miibus); 1190 bus_generic_detach(dev); 1191 1192 if (sc->ste_intrhand) 1193 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1194 if (sc->ste_irq) 1195 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1196 if (sc->ste_res) 1197 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1198 1199 if (sc->ste_ldata) { 1200 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1201 M_DEVBUF); 1202 } 1203 1204 STE_UNLOCK(sc); 1205 mtx_destroy(&sc->ste_mtx); 1206 1207 return(0); 1208} 1209 1210static int 1211ste_newbuf(sc, c, m) 1212 struct ste_softc *sc; 1213 struct ste_chain_onefrag *c; 1214 struct mbuf *m; 1215{ 1216 struct mbuf *m_new = NULL; 1217 1218 if (m == NULL) { 1219 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1220 if (m_new == NULL) 1221 return(ENOBUFS); 1222 MCLGET(m_new, M_DONTWAIT); 1223 if (!(m_new->m_flags & M_EXT)) { 1224 m_freem(m_new); 1225 return(ENOBUFS); 1226 } 1227 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1228 } else { 1229 m_new = m; 1230 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1231 m_new->m_data = m_new->m_ext.ext_buf; 1232 } 1233 1234 m_adj(m_new, ETHER_ALIGN); 1235 1236 c->ste_mbuf = m_new; 1237 c->ste_ptr->ste_status = 0; 1238 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1239 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1240 1241 return(0); 1242} 1243 1244static int 1245ste_init_rx_list(sc) 1246 struct ste_softc *sc; 1247{ 1248 struct ste_chain_data *cd; 1249 struct ste_list_data *ld; 1250 int i; 1251 1252 cd = &sc->ste_cdata; 1253 ld = sc->ste_ldata; 1254 1255 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1256 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1257 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1258 return(ENOBUFS); 1259 if (i == (STE_RX_LIST_CNT - 1)) { 1260 cd->ste_rx_chain[i].ste_next = 1261 &cd->ste_rx_chain[0]; 1262 ld->ste_rx_list[i].ste_next = 1263 vtophys(&ld->ste_rx_list[0]); 1264 } else { 1265 cd->ste_rx_chain[i].ste_next = 1266 &cd->ste_rx_chain[i + 1]; 1267 ld->ste_rx_list[i].ste_next = 1268 vtophys(&ld->ste_rx_list[i + 1]); 1269 } 1270 ld->ste_rx_list[i].ste_status = 0; 1271 } 1272 1273 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1274 1275 return(0); 1276} 1277 1278static void 1279ste_init_tx_list(sc) 1280 struct ste_softc *sc; 1281{ 1282 struct ste_chain_data *cd; 1283 struct ste_list_data *ld; 1284 int i; 1285 1286 cd = &sc->ste_cdata; 1287 ld = sc->ste_ldata; 1288 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1289 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1290 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1291 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1292 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1293 if (i == (STE_TX_LIST_CNT - 1)) 1294 cd->ste_tx_chain[i].ste_next = 1295 &cd->ste_tx_chain[0]; 1296 else 1297 cd->ste_tx_chain[i].ste_next = 1298 &cd->ste_tx_chain[i + 1]; 1299 } 1300 1301 cd->ste_tx_prod = 0; 1302 cd->ste_tx_cons = 0; 1303 cd->ste_tx_cnt = 0; 1304 1305 return; 1306} 1307 1308static void 1309ste_init(xsc) 1310 void *xsc; 1311{ 1312 struct ste_softc *sc; 1313 int i; 1314 struct ifnet *ifp; 1315 1316 sc = xsc; 1317 STE_LOCK(sc); 1318 ifp = &sc->arpcom.ac_if; 1319 1320 ste_stop(sc); 1321 1322 /* Init our MAC address */ 1323 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1324 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1325 } 1326 1327 /* Init RX list */ 1328 if (ste_init_rx_list(sc) == ENOBUFS) { 1329 printf("ste%d: initialization failed: no " 1330 "memory for RX buffers\n", sc->ste_unit); 1331 ste_stop(sc); 1332 STE_UNLOCK(sc); 1333 return; 1334 } 1335 1336 /* Set RX polling interval */ 1337 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1338 1339 /* Init TX descriptors */ 1340 ste_init_tx_list(sc); 1341 1342 /* Set the TX freethresh value */ 1343 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1344 1345 /* Set the TX start threshold for best performance. */ 1346 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1347 1348 /* Set the TX reclaim threshold. */ 1349 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1350 1351 /* Set up the RX filter. */ 1352 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1353 1354 /* If we want promiscuous mode, set the allframes bit. */ 1355 if (ifp->if_flags & IFF_PROMISC) { 1356 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1357 } else { 1358 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1359 } 1360 1361 /* Set capture broadcast bit to accept broadcast frames. */ 1362 if (ifp->if_flags & IFF_BROADCAST) { 1363 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1364 } else { 1365 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1366 } 1367 1368 ste_setmulti(sc); 1369 1370 /* Load the address of the RX list. */ 1371 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1372 ste_wait(sc); 1373 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1374 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1375 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1376 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1377 1378 /* Set TX polling interval (defer until we TX first packet */ 1379 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1380 1381 /* Load address of the TX list */ 1382 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1383 ste_wait(sc); 1384 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1385 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1386 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1387 ste_wait(sc); 1388 sc->ste_tx_prev = NULL; 1389 1390 /* Enable receiver and transmitter */ 1391 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1392 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1393 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1394 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1395 1396 /* Enable stats counters. */ 1397 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1398 1399 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1400#ifdef DEVICE_POLLING 1401 /* Disable interrupts if we are polling. */ 1402 if (ifp->if_flags & IFF_POLLING) 1403 CSR_WRITE_2(sc, STE_IMR, 0); 1404 else 1405#endif /* DEVICE_POLLING */ 1406 /* Enable interrupts. */ 1407 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1408 1409 /* Accept VLAN length packets */ 1410 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1411 1412 ste_ifmedia_upd(ifp); 1413 1414 ifp->if_flags |= IFF_RUNNING; 1415 ifp->if_flags &= ~IFF_OACTIVE; 1416 1417 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1418 STE_UNLOCK(sc); 1419 1420 return; 1421} 1422 1423static void 1424ste_stop(sc) 1425 struct ste_softc *sc; 1426{ 1427 int i; 1428 struct ifnet *ifp; 1429 1430 STE_LOCK(sc); 1431 ifp = &sc->arpcom.ac_if; 1432 1433 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1434 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1435#ifdef DEVICE_POLLING 1436 ether_poll_deregister(ifp); 1437#endif /* DEVICE_POLLING */ 1438 1439 CSR_WRITE_2(sc, STE_IMR, 0); 1440 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1441 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1442 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1443 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1444 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1445 ste_wait(sc); 1446 /* 1447 * Try really hard to stop the RX engine or under heavy RX 1448 * data chip will write into de-allocated memory. 1449 */ 1450 ste_reset(sc); 1451 1452 sc->ste_link = 0; 1453 1454 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1455 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1456 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1457 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1458 } 1459 } 1460 1461 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1462 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1463 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1464 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1465 } 1466 } 1467 1468 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1469 STE_UNLOCK(sc); 1470 1471 return; 1472} 1473 1474static void 1475ste_reset(sc) 1476 struct ste_softc *sc; 1477{ 1478 int i; 1479 1480 STE_SETBIT4(sc, STE_ASICCTL, 1481 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1482 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1483 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1484 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1485 STE_ASICCTL_EXTRESET_RESET); 1486 1487 DELAY(100000); 1488 1489 for (i = 0; i < STE_TIMEOUT; i++) { 1490 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1491 break; 1492 } 1493 1494 if (i == STE_TIMEOUT) 1495 printf("ste%d: global reset never completed\n", sc->ste_unit); 1496 1497 return; 1498} 1499 1500static int 1501ste_ioctl(ifp, command, data) 1502 struct ifnet *ifp; 1503 u_long command; 1504 caddr_t data; 1505{ 1506 struct ste_softc *sc; 1507 struct ifreq *ifr; 1508 struct mii_data *mii; 1509 int error = 0; 1510 1511 sc = ifp->if_softc; 1512 STE_LOCK(sc); 1513 ifr = (struct ifreq *)data; 1514 1515 switch(command) { 1516 case SIOCSIFFLAGS: 1517 if (ifp->if_flags & IFF_UP) { 1518 if (ifp->if_flags & IFF_RUNNING && 1519 ifp->if_flags & IFF_PROMISC && 1520 !(sc->ste_if_flags & IFF_PROMISC)) { 1521 STE_SETBIT1(sc, STE_RX_MODE, 1522 STE_RXMODE_PROMISC); 1523 } else if (ifp->if_flags & IFF_RUNNING && 1524 !(ifp->if_flags & IFF_PROMISC) && 1525 sc->ste_if_flags & IFF_PROMISC) { 1526 STE_CLRBIT1(sc, STE_RX_MODE, 1527 STE_RXMODE_PROMISC); 1528 } 1529 if (ifp->if_flags & IFF_RUNNING && 1530 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1531 ste_setmulti(sc); 1532 if (!(ifp->if_flags & IFF_RUNNING)) { 1533 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1534 ste_init(sc); 1535 } 1536 } else { 1537 if (ifp->if_flags & IFF_RUNNING) 1538 ste_stop(sc); 1539 } 1540 sc->ste_if_flags = ifp->if_flags; 1541 error = 0; 1542 break; 1543 case SIOCADDMULTI: 1544 case SIOCDELMULTI: 1545 ste_setmulti(sc); 1546 error = 0; 1547 break; 1548 case SIOCGIFMEDIA: 1549 case SIOCSIFMEDIA: 1550 mii = device_get_softc(sc->ste_miibus); 1551 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1552 break; 1553 default: 1554 error = ether_ioctl(ifp, command, data); 1555 break; 1556 } 1557 1558 STE_UNLOCK(sc); 1559 1560 return(error); 1561} 1562 1563static int 1564ste_encap(sc, c, m_head) 1565 struct ste_softc *sc; 1566 struct ste_chain *c; 1567 struct mbuf *m_head; 1568{ 1569 int frag = 0; 1570 struct ste_frag *f = NULL; 1571 struct mbuf *m; 1572 struct ste_desc *d; 1573 1574 d = c->ste_ptr; 1575 d->ste_ctl = 0; 1576 1577encap_retry: 1578 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1579 if (m->m_len != 0) { 1580 if (frag == STE_MAXFRAGS) 1581 break; 1582 f = &d->ste_frags[frag]; 1583 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1584 f->ste_len = m->m_len; 1585 frag++; 1586 } 1587 } 1588 1589 if (m != NULL) { 1590 struct mbuf *mn; 1591 1592 /* 1593 * We ran out of segments. We have to recopy this 1594 * mbuf chain first. Bail out if we can't get the 1595 * new buffers. 1596 */ 1597 mn = m_defrag(m_head, M_DONTWAIT); 1598 if (mn == NULL) { 1599 m_freem(m_head); 1600 return ENOMEM; 1601 } 1602 m_head = mn; 1603 goto encap_retry; 1604 } 1605 1606 c->ste_mbuf = m_head; 1607 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1608 d->ste_ctl = 1; 1609 1610 return(0); 1611} 1612 1613static void 1614ste_start(ifp) 1615 struct ifnet *ifp; 1616{ 1617 struct ste_softc *sc; 1618 struct mbuf *m_head = NULL; 1619 struct ste_chain *cur_tx; 1620 int idx; 1621 1622 sc = ifp->if_softc; 1623 STE_LOCK(sc); 1624 1625 if (!sc->ste_link) { 1626 STE_UNLOCK(sc); 1627 return; 1628 } 1629 1630 if (ifp->if_flags & IFF_OACTIVE) { 1631 STE_UNLOCK(sc); 1632 return; 1633 } 1634 1635 idx = sc->ste_cdata.ste_tx_prod; 1636 1637 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1638 1639 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1640 ifp->if_flags |= IFF_OACTIVE; 1641 break; 1642 } 1643 1644 IF_DEQUEUE(&ifp->if_snd, m_head); 1645 if (m_head == NULL) 1646 break; 1647 1648 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1649 1650 if (ste_encap(sc, cur_tx, m_head) != 0) 1651 break; 1652 1653 cur_tx->ste_ptr->ste_next = 0; 1654 1655 if (sc->ste_tx_prev == NULL) { 1656 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1657 /* Load address of the TX list */ 1658 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1659 ste_wait(sc); 1660 1661 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1662 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1663 1664 /* Set TX polling interval to start TX engine */ 1665 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1666 1667 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1668 ste_wait(sc); 1669 }else{ 1670 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1671 sc->ste_tx_prev->ste_ptr->ste_next 1672 = cur_tx->ste_phys; 1673 } 1674 1675 sc->ste_tx_prev = cur_tx; 1676 1677 /* 1678 * If there's a BPF listener, bounce a copy of this frame 1679 * to him. 1680 */ 1681 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1682 1683 STE_INC(idx, STE_TX_LIST_CNT); 1684 sc->ste_cdata.ste_tx_cnt++; 1685 ifp->if_timer = 5; 1686 } 1687 sc->ste_cdata.ste_tx_prod = idx; 1688 1689 STE_UNLOCK(sc); 1690 1691 return; 1692} 1693 1694static void 1695ste_watchdog(ifp) 1696 struct ifnet *ifp; 1697{ 1698 struct ste_softc *sc; 1699 1700 sc = ifp->if_softc; 1701 STE_LOCK(sc); 1702 1703 ifp->if_oerrors++; 1704 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1705 1706 ste_txeoc(sc); 1707 ste_txeof(sc); 1708 ste_rxeoc(sc); 1709 ste_rxeof(sc); 1710 ste_reset(sc); 1711 ste_init(sc); 1712 1713 if (ifp->if_snd.ifq_head != NULL) 1714 ste_start(ifp); 1715 STE_UNLOCK(sc); 1716 1717 return; 1718} 1719 1720static void 1721ste_shutdown(dev) 1722 device_t dev; 1723{ 1724 struct ste_softc *sc; 1725 1726 sc = device_get_softc(dev); 1727 1728 ste_stop(sc); 1729 1730 return; 1731} 1732