if_ste.c revision 127709
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 127709 2004-04-01 12:55:38Z ru $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44 45#include <net/if.h> 46#include <net/if_arp.h> 47#include <net/ethernet.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <vm/vm.h> /* for vtophys */ 55#include <vm/pmap.h> /* for vtophys */ 56#include <machine/bus_memio.h> 57#include <machine/bus_pio.h> 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69/* "controller miibus0" required. See GENERIC if you get errors here. */ 70#include "miibus_if.h" 71 72#define STE_USEIOSPACE 73 74#include <pci/if_stereg.h> 75 76MODULE_DEPEND(ste, pci, 1, 1, 1); 77MODULE_DEPEND(ste, ether, 1, 1, 1); 78MODULE_DEPEND(ste, miibus, 1, 1, 1); 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe (device_t); 90static int ste_attach (device_t); 91static int ste_detach (device_t); 92static void ste_init (void *); 93static void ste_intr (void *); 94static void ste_rxeof (struct ste_softc *); 95static void ste_txeoc (struct ste_softc *); 96static void ste_txeof (struct ste_softc *); 97static void ste_stats_update (void *); 98static void ste_stop (struct ste_softc *); 99static void ste_reset (struct ste_softc *); 100static int ste_ioctl (struct ifnet *, u_long, caddr_t); 101static int ste_encap (struct ste_softc *, struct ste_chain *, 102 struct mbuf *); 103static void ste_start (struct ifnet *); 104static void ste_watchdog (struct ifnet *); 105static void ste_shutdown (device_t); 106static int ste_newbuf (struct ste_softc *, 107 struct ste_chain_onefrag *, 108 struct mbuf *); 109static int ste_ifmedia_upd (struct ifnet *); 110static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111 112static void ste_mii_sync (struct ste_softc *); 113static void ste_mii_send (struct ste_softc *, u_int32_t, int); 114static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 115static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_miibus_readreg (device_t, int, int); 117static int ste_miibus_writereg (device_t, int, int, int); 118static void ste_miibus_statchg (device_t); 119 120static int ste_eeprom_wait (struct ste_softc *); 121static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 122static void ste_wait (struct ste_softc *); 123static u_int8_t ste_calchash (caddr_t); 124static void ste_setmulti (struct ste_softc *); 125static int ste_init_rx_list (struct ste_softc *); 126static void ste_init_tx_list (struct ste_softc *); 127 128#ifdef STE_USEIOSPACE 129#define STE_RES SYS_RES_IOPORT 130#define STE_RID STE_PCI_LOIO 131#else 132#define STE_RES SYS_RES_MEMORY 133#define STE_RID STE_PCI_LOMEM 134#endif 135 136static device_method_t ste_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, ste_probe), 139 DEVMETHOD(device_attach, ste_attach), 140 DEVMETHOD(device_detach, ste_detach), 141 DEVMETHOD(device_shutdown, ste_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 149 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 150 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 151 152 { 0, 0 } 153}; 154 155static driver_t ste_driver = { 156 "ste", 157 ste_methods, 158 sizeof(struct ste_softc) 159}; 160 161static devclass_t ste_devclass; 162 163DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 164DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 165 166SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters"); 167 168static int ste_rxsyncs; 169SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 170 171#define STE_SETBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 173 174#define STE_CLRBIT4(sc, reg, x) \ 175 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 176 177#define STE_SETBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 179 180#define STE_CLRBIT2(sc, reg, x) \ 181 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 182 183#define STE_SETBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 185 186#define STE_CLRBIT1(sc, reg, x) \ 187 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 188 189 190#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 191#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 192 193/* 194 * Sync the PHYs by setting data bit and strobing the clock 32 times. 195 */ 196static void 197ste_mii_sync(sc) 198 struct ste_softc *sc; 199{ 200 register int i; 201 202 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 203 204 for (i = 0; i < 32; i++) { 205 MII_SET(STE_PHYCTL_MCLK); 206 DELAY(1); 207 MII_CLR(STE_PHYCTL_MCLK); 208 DELAY(1); 209 } 210 211 return; 212} 213 214/* 215 * Clock a series of bits through the MII. 216 */ 217static void 218ste_mii_send(sc, bits, cnt) 219 struct ste_softc *sc; 220 u_int32_t bits; 221 int cnt; 222{ 223 int i; 224 225 MII_CLR(STE_PHYCTL_MCLK); 226 227 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 228 if (bits & i) { 229 MII_SET(STE_PHYCTL_MDATA); 230 } else { 231 MII_CLR(STE_PHYCTL_MDATA); 232 } 233 DELAY(1); 234 MII_CLR(STE_PHYCTL_MCLK); 235 DELAY(1); 236 MII_SET(STE_PHYCTL_MCLK); 237 } 238} 239 240/* 241 * Read an PHY register through the MII. 242 */ 243static int 244ste_mii_readreg(sc, frame) 245 struct ste_softc *sc; 246 struct ste_mii_frame *frame; 247 248{ 249 int i, ack; 250 251 STE_LOCK(sc); 252 253 /* 254 * Set up frame for RX. 255 */ 256 frame->mii_stdelim = STE_MII_STARTDELIM; 257 frame->mii_opcode = STE_MII_READOP; 258 frame->mii_turnaround = 0; 259 frame->mii_data = 0; 260 261 CSR_WRITE_2(sc, STE_PHYCTL, 0); 262 /* 263 * Turn on data xmit. 264 */ 265 MII_SET(STE_PHYCTL_MDIR); 266 267 ste_mii_sync(sc); 268 269 /* 270 * Send command/address info. 271 */ 272 ste_mii_send(sc, frame->mii_stdelim, 2); 273 ste_mii_send(sc, frame->mii_opcode, 2); 274 ste_mii_send(sc, frame->mii_phyaddr, 5); 275 ste_mii_send(sc, frame->mii_regaddr, 5); 276 277 /* Turn off xmit. */ 278 MII_CLR(STE_PHYCTL_MDIR); 279 280 /* Idle bit */ 281 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 282 DELAY(1); 283 MII_SET(STE_PHYCTL_MCLK); 284 DELAY(1); 285 286 /* Check for ack */ 287 MII_CLR(STE_PHYCTL_MCLK); 288 DELAY(1); 289 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 290 MII_SET(STE_PHYCTL_MCLK); 291 DELAY(1); 292 293 /* 294 * Now try reading data bits. If the ack failed, we still 295 * need to clock through 16 cycles to keep the PHY(s) in sync. 296 */ 297 if (ack) { 298 for(i = 0; i < 16; i++) { 299 MII_CLR(STE_PHYCTL_MCLK); 300 DELAY(1); 301 MII_SET(STE_PHYCTL_MCLK); 302 DELAY(1); 303 } 304 goto fail; 305 } 306 307 for (i = 0x8000; i; i >>= 1) { 308 MII_CLR(STE_PHYCTL_MCLK); 309 DELAY(1); 310 if (!ack) { 311 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 312 frame->mii_data |= i; 313 DELAY(1); 314 } 315 MII_SET(STE_PHYCTL_MCLK); 316 DELAY(1); 317 } 318 319fail: 320 321 MII_CLR(STE_PHYCTL_MCLK); 322 DELAY(1); 323 MII_SET(STE_PHYCTL_MCLK); 324 DELAY(1); 325 326 STE_UNLOCK(sc); 327 328 if (ack) 329 return(1); 330 return(0); 331} 332 333/* 334 * Write to a PHY register through the MII. 335 */ 336static int 337ste_mii_writereg(sc, frame) 338 struct ste_softc *sc; 339 struct ste_mii_frame *frame; 340 341{ 342 STE_LOCK(sc); 343 344 /* 345 * Set up frame for TX. 346 */ 347 348 frame->mii_stdelim = STE_MII_STARTDELIM; 349 frame->mii_opcode = STE_MII_WRITEOP; 350 frame->mii_turnaround = STE_MII_TURNAROUND; 351 352 /* 353 * Turn on data output. 354 */ 355 MII_SET(STE_PHYCTL_MDIR); 356 357 ste_mii_sync(sc); 358 359 ste_mii_send(sc, frame->mii_stdelim, 2); 360 ste_mii_send(sc, frame->mii_opcode, 2); 361 ste_mii_send(sc, frame->mii_phyaddr, 5); 362 ste_mii_send(sc, frame->mii_regaddr, 5); 363 ste_mii_send(sc, frame->mii_turnaround, 2); 364 ste_mii_send(sc, frame->mii_data, 16); 365 366 /* Idle bit. */ 367 MII_SET(STE_PHYCTL_MCLK); 368 DELAY(1); 369 MII_CLR(STE_PHYCTL_MCLK); 370 DELAY(1); 371 372 /* 373 * Turn off xmit. 374 */ 375 MII_CLR(STE_PHYCTL_MDIR); 376 377 STE_UNLOCK(sc); 378 379 return(0); 380} 381 382static int 383ste_miibus_readreg(dev, phy, reg) 384 device_t dev; 385 int phy, reg; 386{ 387 struct ste_softc *sc; 388 struct ste_mii_frame frame; 389 390 sc = device_get_softc(dev); 391 392 if ( sc->ste_one_phy && phy != 0 ) 393 return (0); 394 395 bzero((char *)&frame, sizeof(frame)); 396 397 frame.mii_phyaddr = phy; 398 frame.mii_regaddr = reg; 399 ste_mii_readreg(sc, &frame); 400 401 return(frame.mii_data); 402} 403 404static int 405ste_miibus_writereg(dev, phy, reg, data) 406 device_t dev; 407 int phy, reg, data; 408{ 409 struct ste_softc *sc; 410 struct ste_mii_frame frame; 411 412 sc = device_get_softc(dev); 413 bzero((char *)&frame, sizeof(frame)); 414 415 frame.mii_phyaddr = phy; 416 frame.mii_regaddr = reg; 417 frame.mii_data = data; 418 419 ste_mii_writereg(sc, &frame); 420 421 return(0); 422} 423 424static void 425ste_miibus_statchg(dev) 426 device_t dev; 427{ 428 struct ste_softc *sc; 429 struct mii_data *mii; 430 431 sc = device_get_softc(dev); 432 STE_LOCK(sc); 433 mii = device_get_softc(sc->ste_miibus); 434 435 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 436 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 437 } else { 438 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 439 } 440 STE_UNLOCK(sc); 441 442 return; 443} 444 445static int 446ste_ifmedia_upd(ifp) 447 struct ifnet *ifp; 448{ 449 struct ste_softc *sc; 450 struct mii_data *mii; 451 452 sc = ifp->if_softc; 453 mii = device_get_softc(sc->ste_miibus); 454 sc->ste_link = 0; 455 if (mii->mii_instance) { 456 struct mii_softc *miisc; 457 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 458 mii_phy_reset(miisc); 459 } 460 mii_mediachg(mii); 461 462 return(0); 463} 464 465static void 466ste_ifmedia_sts(ifp, ifmr) 467 struct ifnet *ifp; 468 struct ifmediareq *ifmr; 469{ 470 struct ste_softc *sc; 471 struct mii_data *mii; 472 473 sc = ifp->if_softc; 474 mii = device_get_softc(sc->ste_miibus); 475 476 mii_pollstat(mii); 477 ifmr->ifm_active = mii->mii_media_active; 478 ifmr->ifm_status = mii->mii_media_status; 479 480 return; 481} 482 483static void 484ste_wait(sc) 485 struct ste_softc *sc; 486{ 487 register int i; 488 489 for (i = 0; i < STE_TIMEOUT; i++) { 490 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 491 break; 492 } 493 494 if (i == STE_TIMEOUT) 495 printf("ste%d: command never completed!\n", sc->ste_unit); 496 497 return; 498} 499 500/* 501 * The EEPROM is slow: give it time to come ready after issuing 502 * it a command. 503 */ 504static int 505ste_eeprom_wait(sc) 506 struct ste_softc *sc; 507{ 508 int i; 509 510 DELAY(1000); 511 512 for (i = 0; i < 100; i++) { 513 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 514 DELAY(1000); 515 else 516 break; 517 } 518 519 if (i == 100) { 520 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 521 return(1); 522 } 523 524 return(0); 525} 526 527/* 528 * Read a sequence of words from the EEPROM. Note that ethernet address 529 * data is stored in the EEPROM in network byte order. 530 */ 531static int 532ste_read_eeprom(sc, dest, off, cnt, swap) 533 struct ste_softc *sc; 534 caddr_t dest; 535 int off; 536 int cnt; 537 int swap; 538{ 539 int err = 0, i; 540 u_int16_t word = 0, *ptr; 541 542 if (ste_eeprom_wait(sc)) 543 return(1); 544 545 for (i = 0; i < cnt; i++) { 546 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 547 err = ste_eeprom_wait(sc); 548 if (err) 549 break; 550 word = CSR_READ_2(sc, STE_EEPROM_DATA); 551 ptr = (u_int16_t *)(dest + (i * 2)); 552 if (swap) 553 *ptr = ntohs(word); 554 else 555 *ptr = word; 556 } 557 558 return(err ? 1 : 0); 559} 560 561static u_int8_t 562ste_calchash(addr) 563 caddr_t addr; 564{ 565 566 u_int32_t crc, carry; 567 int i, j; 568 u_int8_t c; 569 570 /* Compute CRC for the address value. */ 571 crc = 0xFFFFFFFF; /* initial value */ 572 573 for (i = 0; i < 6; i++) { 574 c = *(addr + i); 575 for (j = 0; j < 8; j++) { 576 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 577 crc <<= 1; 578 c >>= 1; 579 if (carry) 580 crc = (crc ^ 0x04c11db6) | carry; 581 } 582 } 583 584 /* return the filter bit position */ 585 return(crc & 0x0000003F); 586} 587 588static void 589ste_setmulti(sc) 590 struct ste_softc *sc; 591{ 592 struct ifnet *ifp; 593 int h = 0; 594 u_int32_t hashes[2] = { 0, 0 }; 595 struct ifmultiaddr *ifma; 596 597 ifp = &sc->arpcom.ac_if; 598 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 599 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 600 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 601 return; 602 } 603 604 /* first, zot all the existing hash bits */ 605 CSR_WRITE_2(sc, STE_MAR0, 0); 606 CSR_WRITE_2(sc, STE_MAR1, 0); 607 CSR_WRITE_2(sc, STE_MAR2, 0); 608 CSR_WRITE_2(sc, STE_MAR3, 0); 609 610 /* now program new ones */ 611 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 612 if (ifma->ifma_addr->sa_family != AF_LINK) 613 continue; 614 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 615 if (h < 32) 616 hashes[0] |= (1 << h); 617 else 618 hashes[1] |= (1 << (h - 32)); 619 } 620 621 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 622 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 623 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 624 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 625 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 626 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 627 628 return; 629} 630 631#ifdef DEVICE_POLLING 632static poll_handler_t ste_poll; 633 634static void 635ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 636{ 637 struct ste_softc *sc = ifp->if_softc; 638 639 STE_LOCK(sc); 640 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 641 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 642 goto done; 643 } 644 645 sc->rxcycles = count; 646 ste_rxeof(sc); 647 ste_txeof(sc); 648 if (ifp->if_snd.ifq_head != NULL) 649 ste_start(ifp); 650 651 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 652 u_int16_t status; 653 654 status = CSR_READ_2(sc, STE_ISR_ACK); 655 656 if (status & STE_ISR_TX_DONE) 657 ste_txeoc(sc); 658 659 if (status & STE_ISR_STATS_OFLOW) { 660 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 661 ste_stats_update(sc); 662 } 663 664 if (status & STE_ISR_LINKEVENT) 665 mii_pollstat(device_get_softc(sc->ste_miibus)); 666 667 if (status & STE_ISR_HOSTERR) { 668 ste_reset(sc); 669 ste_init(sc); 670 } 671 } 672done: 673 STE_UNLOCK(sc); 674} 675#endif /* DEVICE_POLLING */ 676 677static void 678ste_intr(xsc) 679 void *xsc; 680{ 681 struct ste_softc *sc; 682 struct ifnet *ifp; 683 u_int16_t status; 684 685 sc = xsc; 686 STE_LOCK(sc); 687 ifp = &sc->arpcom.ac_if; 688 689#ifdef DEVICE_POLLING 690 if (ifp->if_flags & IFF_POLLING) 691 goto done; 692 if (ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 693 CSR_WRITE_2(sc, STE_IMR, 0); 694 ste_poll(ifp, 0, 1); 695 goto done; 696 } 697#endif /* DEVICE_POLLING */ 698 699 /* See if this is really our interrupt. */ 700 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 701 STE_UNLOCK(sc); 702 return; 703 } 704 705 for (;;) { 706 status = CSR_READ_2(sc, STE_ISR_ACK); 707 708 if (!(status & STE_INTRS)) 709 break; 710 711 if (status & STE_ISR_RX_DMADONE) 712 ste_rxeof(sc); 713 714 if (status & STE_ISR_TX_DMADONE) 715 ste_txeof(sc); 716 717 if (status & STE_ISR_TX_DONE) 718 ste_txeoc(sc); 719 720 if (status & STE_ISR_STATS_OFLOW) { 721 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 722 ste_stats_update(sc); 723 } 724 725 if (status & STE_ISR_LINKEVENT) 726 mii_pollstat(device_get_softc(sc->ste_miibus)); 727 728 729 if (status & STE_ISR_HOSTERR) { 730 ste_reset(sc); 731 ste_init(sc); 732 } 733 } 734 735 /* Re-enable interrupts */ 736 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 737 738 if (ifp->if_snd.ifq_head != NULL) 739 ste_start(ifp); 740 741#ifdef DEVICE_POLLING 742done: 743#endif /* DEVICE_POLLING */ 744 STE_UNLOCK(sc); 745 746 return; 747} 748 749/* 750 * A frame has been uploaded: pass the resulting mbuf chain up to 751 * the higher level protocols. 752 */ 753static void 754ste_rxeof(sc) 755 struct ste_softc *sc; 756{ 757 struct mbuf *m; 758 struct ifnet *ifp; 759 struct ste_chain_onefrag *cur_rx; 760 int total_len = 0, count=0; 761 u_int32_t rxstat; 762 763 STE_LOCK_ASSERT(sc); 764 765 ifp = &sc->arpcom.ac_if; 766 767 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 768 cur_rx = sc->ste_cdata.ste_rx_head; 769 do { 770 cur_rx = cur_rx->ste_next; 771 /* If the ring is empty, just return. */ 772 if (cur_rx == sc->ste_cdata.ste_rx_head) 773 return; 774 } while (cur_rx->ste_ptr->ste_status == 0); 775 /* We've fallen behind the chip: catch it. */ 776 sc->ste_cdata.ste_rx_head = cur_rx; 777 ++ste_rxsyncs; 778 }; 779 780 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 781 & STE_RXSTAT_DMADONE) { 782#ifdef DEVICE_POLLING 783 if (ifp->if_flags & IFF_POLLING) { 784 if (sc->rxcycles <= 0) 785 break; 786 sc->rxcycles--; 787 } 788#endif /* DEVICE_POLLING */ 789 if ((STE_RX_LIST_CNT - count) < 3) { 790 break; 791 } 792 793 cur_rx = sc->ste_cdata.ste_rx_head; 794 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 795 796 /* 797 * If an error occurs, update stats, clear the 798 * status word and leave the mbuf cluster in place: 799 * it should simply get re-used next time this descriptor 800 * comes up in the ring. 801 */ 802 if (rxstat & STE_RXSTAT_FRAME_ERR) { 803 ifp->if_ierrors++; 804 cur_rx->ste_ptr->ste_status = 0; 805 continue; 806 } 807 808 /* 809 * If there error bit was not set, the upload complete 810 * bit should be set which means we have a valid packet. 811 * If not, something truly strange has happened. 812 */ 813 if (!(rxstat & STE_RXSTAT_DMADONE)) { 814 printf("ste%d: bad receive status -- packet dropped\n", 815 sc->ste_unit); 816 ifp->if_ierrors++; 817 cur_rx->ste_ptr->ste_status = 0; 818 continue; 819 } 820 821 /* No errors; receive the packet. */ 822 m = cur_rx->ste_mbuf; 823 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 824 825 /* 826 * Try to conjure up a new mbuf cluster. If that 827 * fails, it means we have an out of memory condition and 828 * should leave the buffer in place and continue. This will 829 * result in a lost packet, but there's little else we 830 * can do in this situation. 831 */ 832 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 833 ifp->if_ierrors++; 834 cur_rx->ste_ptr->ste_status = 0; 835 continue; 836 } 837 838 m->m_pkthdr.rcvif = ifp; 839 m->m_pkthdr.len = m->m_len = total_len; 840 841 ifp->if_ipackets++; 842 STE_UNLOCK(sc); 843 (*ifp->if_input)(ifp, m); 844 STE_LOCK(sc); 845 846 cur_rx->ste_ptr->ste_status = 0; 847 count++; 848 } 849 850 return; 851} 852 853static void 854ste_txeoc(sc) 855 struct ste_softc *sc; 856{ 857 u_int8_t txstat; 858 struct ifnet *ifp; 859 860 ifp = &sc->arpcom.ac_if; 861 862 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 863 STE_TXSTATUS_TXDONE) { 864 if (txstat & STE_TXSTATUS_UNDERRUN || 865 txstat & STE_TXSTATUS_EXCESSCOLLS || 866 txstat & STE_TXSTATUS_RECLAIMERR) { 867 ifp->if_oerrors++; 868 printf("ste%d: transmission error: %x\n", 869 sc->ste_unit, txstat); 870 871 ste_reset(sc); 872 ste_init(sc); 873 874 if (txstat & STE_TXSTATUS_UNDERRUN && 875 sc->ste_tx_thresh < STE_PACKET_SIZE) { 876 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 877 printf("ste%d: tx underrun, increasing tx" 878 " start threshold to %d bytes\n", 879 sc->ste_unit, sc->ste_tx_thresh); 880 } 881 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 882 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 883 (STE_PACKET_SIZE >> 4)); 884 } 885 ste_init(sc); 886 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 887 } 888 889 return; 890} 891 892static void 893ste_txeof(sc) 894 struct ste_softc *sc; 895{ 896 struct ste_chain *cur_tx = NULL; 897 struct ifnet *ifp; 898 int idx; 899 900 ifp = &sc->arpcom.ac_if; 901 902 idx = sc->ste_cdata.ste_tx_cons; 903 while(idx != sc->ste_cdata.ste_tx_prod) { 904 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 905 906 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 907 break; 908 909 if (cur_tx->ste_mbuf != NULL) { 910 m_freem(cur_tx->ste_mbuf); 911 cur_tx->ste_mbuf = NULL; 912 } 913 914 ifp->if_opackets++; 915 916 sc->ste_cdata.ste_tx_cnt--; 917 STE_INC(idx, STE_TX_LIST_CNT); 918 ifp->if_timer = 0; 919 } 920 921 sc->ste_cdata.ste_tx_cons = idx; 922 923 if (cur_tx != NULL) 924 ifp->if_flags &= ~IFF_OACTIVE; 925 926 return; 927} 928 929static void 930ste_stats_update(xsc) 931 void *xsc; 932{ 933 struct ste_softc *sc; 934 struct ifnet *ifp; 935 struct mii_data *mii; 936 937 sc = xsc; 938 STE_LOCK(sc); 939 940 ifp = &sc->arpcom.ac_if; 941 mii = device_get_softc(sc->ste_miibus); 942 943 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 944 + CSR_READ_1(sc, STE_MULTI_COLLS) 945 + CSR_READ_1(sc, STE_SINGLE_COLLS); 946 947 if (!sc->ste_link) { 948 mii_pollstat(mii); 949 if (mii->mii_media_status & IFM_ACTIVE && 950 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 951 sc->ste_link++; 952 /* 953 * we don't get a call-back on re-init so do it 954 * otherwise we get stuck in the wrong link state 955 */ 956 ste_miibus_statchg(sc->ste_dev); 957 if (ifp->if_snd.ifq_head != NULL) 958 ste_start(ifp); 959 } 960 } 961 962 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 963 STE_UNLOCK(sc); 964 965 return; 966} 967 968 969/* 970 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 971 * IDs against our list and return a device name if we find a match. 972 */ 973static int 974ste_probe(dev) 975 device_t dev; 976{ 977 struct ste_type *t; 978 979 t = ste_devs; 980 981 while(t->ste_name != NULL) { 982 if ((pci_get_vendor(dev) == t->ste_vid) && 983 (pci_get_device(dev) == t->ste_did)) { 984 device_set_desc(dev, t->ste_name); 985 return(0); 986 } 987 t++; 988 } 989 990 return(ENXIO); 991} 992 993/* 994 * Attach the interface. Allocate softc structures, do ifmedia 995 * setup and ethernet/BPF attach. 996 */ 997static int 998ste_attach(dev) 999 device_t dev; 1000{ 1001 struct ste_softc *sc; 1002 struct ifnet *ifp; 1003 int unit, error = 0, rid; 1004 1005 sc = device_get_softc(dev); 1006 unit = device_get_unit(dev); 1007 sc->ste_dev = dev; 1008 1009 /* 1010 * Only use one PHY since this chip reports multiple 1011 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1012 * it is at 0 & 1. It is rev 0x12. 1013 */ 1014 if (pci_get_vendor(dev) == DL_VENDORID && 1015 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1016 pci_get_revid(dev) == 0x12 ) 1017 sc->ste_one_phy = 1; 1018 1019 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1020 MTX_DEF | MTX_RECURSE); 1021#ifndef BURN_BRIDGES 1022 /* 1023 * Handle power management nonsense. 1024 */ 1025 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1026 u_int32_t iobase, membase, irq; 1027 1028 /* Save important PCI config data. */ 1029 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 1030 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 1031 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 1032 1033 /* Reset the power state. */ 1034 printf("ste%d: chip is in D%d power mode " 1035 "-- setting to D0\n", unit, 1036 pci_get_powerstate(dev)); 1037 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1038 1039 /* Restore PCI config data. */ 1040 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 1041 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 1042 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 1043 } 1044#endif 1045 /* 1046 * Map control/status registers. 1047 */ 1048 pci_enable_busmaster(dev); 1049 1050 rid = STE_RID; 1051 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1052 1053 if (sc->ste_res == NULL) { 1054 printf ("ste%d: couldn't map ports/memory\n", unit); 1055 error = ENXIO; 1056 goto fail; 1057 } 1058 1059 sc->ste_btag = rman_get_bustag(sc->ste_res); 1060 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1061 1062 /* Allocate interrupt */ 1063 rid = 0; 1064 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1065 RF_SHAREABLE | RF_ACTIVE); 1066 1067 if (sc->ste_irq == NULL) { 1068 printf("ste%d: couldn't map interrupt\n", unit); 1069 error = ENXIO; 1070 goto fail; 1071 } 1072 1073 callout_handle_init(&sc->ste_stat_ch); 1074 1075 /* Reset the adapter. */ 1076 ste_reset(sc); 1077 1078 /* 1079 * Get station address from the EEPROM. 1080 */ 1081 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1082 STE_EEADDR_NODE0, 3, 0)) { 1083 printf("ste%d: failed to read station address\n", unit); 1084 error = ENXIO;; 1085 goto fail; 1086 } 1087 1088 sc->ste_unit = unit; 1089 1090 /* Allocate the descriptor queues. */ 1091 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1092 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1093 1094 if (sc->ste_ldata == NULL) { 1095 printf("ste%d: no memory for list buffers!\n", unit); 1096 error = ENXIO; 1097 goto fail; 1098 } 1099 1100 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1101 1102 /* Do MII setup. */ 1103 if (mii_phy_probe(dev, &sc->ste_miibus, 1104 ste_ifmedia_upd, ste_ifmedia_sts)) { 1105 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1106 error = ENXIO; 1107 goto fail; 1108 } 1109 1110 ifp = &sc->arpcom.ac_if; 1111 ifp->if_softc = sc; 1112 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1113 ifp->if_mtu = ETHERMTU; 1114 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1115 ifp->if_ioctl = ste_ioctl; 1116 ifp->if_start = ste_start; 1117 ifp->if_watchdog = ste_watchdog; 1118 ifp->if_init = ste_init; 1119 ifp->if_baudrate = 10000000; 1120 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1121 1122 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1123 1124 /* 1125 * Call MI attach routine. 1126 */ 1127 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1128 1129 /* 1130 * Tell the upper layer(s) we support long frames. 1131 */ 1132 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1133 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1134 1135 /* Hook interrupt last to avoid having to lock softc */ 1136 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1137 ste_intr, sc, &sc->ste_intrhand); 1138 1139 if (error) { 1140 printf("ste%d: couldn't set up irq\n", unit); 1141 ether_ifdetach(ifp); 1142 goto fail; 1143 } 1144 1145fail: 1146 if (error) 1147 ste_detach(dev); 1148 1149 return(error); 1150} 1151 1152/* 1153 * Shutdown hardware and free up resources. This can be called any 1154 * time after the mutex has been initialized. It is called in both 1155 * the error case in attach and the normal detach case so it needs 1156 * to be careful about only freeing resources that have actually been 1157 * allocated. 1158 */ 1159static int 1160ste_detach(dev) 1161 device_t dev; 1162{ 1163 struct ste_softc *sc; 1164 struct ifnet *ifp; 1165 1166 sc = device_get_softc(dev); 1167 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1168 STE_LOCK(sc); 1169 ifp = &sc->arpcom.ac_if; 1170 1171 /* These should only be active if attach succeeded */ 1172 if (device_is_attached(dev)) { 1173 ste_stop(sc); 1174 ether_ifdetach(ifp); 1175 } 1176 if (sc->ste_miibus) 1177 device_delete_child(dev, sc->ste_miibus); 1178 bus_generic_detach(dev); 1179 1180 if (sc->ste_intrhand) 1181 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1182 if (sc->ste_irq) 1183 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1184 if (sc->ste_res) 1185 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1186 1187 if (sc->ste_ldata) { 1188 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1189 M_DEVBUF); 1190 } 1191 1192 STE_UNLOCK(sc); 1193 mtx_destroy(&sc->ste_mtx); 1194 1195 return(0); 1196} 1197 1198static int 1199ste_newbuf(sc, c, m) 1200 struct ste_softc *sc; 1201 struct ste_chain_onefrag *c; 1202 struct mbuf *m; 1203{ 1204 struct mbuf *m_new = NULL; 1205 1206 if (m == NULL) { 1207 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1208 if (m_new == NULL) 1209 return(ENOBUFS); 1210 MCLGET(m_new, M_DONTWAIT); 1211 if (!(m_new->m_flags & M_EXT)) { 1212 m_freem(m_new); 1213 return(ENOBUFS); 1214 } 1215 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1216 } else { 1217 m_new = m; 1218 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1219 m_new->m_data = m_new->m_ext.ext_buf; 1220 } 1221 1222 m_adj(m_new, ETHER_ALIGN); 1223 1224 c->ste_mbuf = m_new; 1225 c->ste_ptr->ste_status = 0; 1226 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1227 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1228 1229 return(0); 1230} 1231 1232static int 1233ste_init_rx_list(sc) 1234 struct ste_softc *sc; 1235{ 1236 struct ste_chain_data *cd; 1237 struct ste_list_data *ld; 1238 int i; 1239 1240 cd = &sc->ste_cdata; 1241 ld = sc->ste_ldata; 1242 1243 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1244 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1245 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1246 return(ENOBUFS); 1247 if (i == (STE_RX_LIST_CNT - 1)) { 1248 cd->ste_rx_chain[i].ste_next = 1249 &cd->ste_rx_chain[0]; 1250 ld->ste_rx_list[i].ste_next = 1251 vtophys(&ld->ste_rx_list[0]); 1252 } else { 1253 cd->ste_rx_chain[i].ste_next = 1254 &cd->ste_rx_chain[i + 1]; 1255 ld->ste_rx_list[i].ste_next = 1256 vtophys(&ld->ste_rx_list[i + 1]); 1257 } 1258 ld->ste_rx_list[i].ste_status = 0; 1259 } 1260 1261 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1262 1263 return(0); 1264} 1265 1266static void 1267ste_init_tx_list(sc) 1268 struct ste_softc *sc; 1269{ 1270 struct ste_chain_data *cd; 1271 struct ste_list_data *ld; 1272 int i; 1273 1274 cd = &sc->ste_cdata; 1275 ld = sc->ste_ldata; 1276 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1277 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1278 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1279 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1280 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1281 if (i == (STE_TX_LIST_CNT - 1)) 1282 cd->ste_tx_chain[i].ste_next = 1283 &cd->ste_tx_chain[0]; 1284 else 1285 cd->ste_tx_chain[i].ste_next = 1286 &cd->ste_tx_chain[i + 1]; 1287 if (i == 0) 1288 cd->ste_tx_chain[i].ste_prev = 1289 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1290 else 1291 cd->ste_tx_chain[i].ste_prev = 1292 &cd->ste_tx_chain[i - 1]; 1293 } 1294 1295 cd->ste_tx_prod = 0; 1296 cd->ste_tx_cons = 0; 1297 cd->ste_tx_cnt = 0; 1298 1299 return; 1300} 1301 1302static void 1303ste_init(xsc) 1304 void *xsc; 1305{ 1306 struct ste_softc *sc; 1307 int i; 1308 struct ifnet *ifp; 1309 1310 sc = xsc; 1311 STE_LOCK(sc); 1312 ifp = &sc->arpcom.ac_if; 1313 1314 ste_stop(sc); 1315 1316 /* Init our MAC address */ 1317 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1318 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1319 } 1320 1321 /* Init RX list */ 1322 if (ste_init_rx_list(sc) == ENOBUFS) { 1323 printf("ste%d: initialization failed: no " 1324 "memory for RX buffers\n", sc->ste_unit); 1325 ste_stop(sc); 1326 STE_UNLOCK(sc); 1327 return; 1328 } 1329 1330 /* Set RX polling interval */ 1331 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1332 1333 /* Init TX descriptors */ 1334 ste_init_tx_list(sc); 1335 1336 /* Set the TX freethresh value */ 1337 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1338 1339 /* Set the TX start threshold for best performance. */ 1340 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1341 1342 /* Set the TX reclaim threshold. */ 1343 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1344 1345 /* Set up the RX filter. */ 1346 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1347 1348 /* If we want promiscuous mode, set the allframes bit. */ 1349 if (ifp->if_flags & IFF_PROMISC) { 1350 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1351 } else { 1352 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1353 } 1354 1355 /* Set capture broadcast bit to accept broadcast frames. */ 1356 if (ifp->if_flags & IFF_BROADCAST) { 1357 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1358 } else { 1359 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1360 } 1361 1362 ste_setmulti(sc); 1363 1364 /* Load the address of the RX list. */ 1365 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1366 ste_wait(sc); 1367 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1368 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1369 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1370 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1371 1372 /* Set TX polling interval (defer until we TX first packet */ 1373 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1374 1375 /* Load address of the TX list */ 1376 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1377 ste_wait(sc); 1378 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1379 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1380 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1381 ste_wait(sc); 1382 sc->ste_tx_prev_idx=-1; 1383 1384 /* Enable receiver and transmitter */ 1385 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1386 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1387 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1388 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1389 1390 /* Enable stats counters. */ 1391 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1392 1393 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1394#ifdef DEVICE_POLLING 1395 /* Disable interrupts if we are polling. */ 1396 if (ifp->if_flags & IFF_POLLING) 1397 CSR_WRITE_2(sc, STE_IMR, 0); 1398 else 1399#endif /* DEVICE_POLLING */ 1400 /* Enable interrupts. */ 1401 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1402 1403 /* Accept VLAN length packets */ 1404 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1405 1406 ste_ifmedia_upd(ifp); 1407 1408 ifp->if_flags |= IFF_RUNNING; 1409 ifp->if_flags &= ~IFF_OACTIVE; 1410 1411 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1412 STE_UNLOCK(sc); 1413 1414 return; 1415} 1416 1417static void 1418ste_stop(sc) 1419 struct ste_softc *sc; 1420{ 1421 int i; 1422 struct ifnet *ifp; 1423 1424 STE_LOCK(sc); 1425 ifp = &sc->arpcom.ac_if; 1426 1427 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1428 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1429#ifdef DEVICE_POLLING 1430 ether_poll_deregister(ifp); 1431#endif /* DEVICE_POLLING */ 1432 1433 CSR_WRITE_2(sc, STE_IMR, 0); 1434 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1435 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1436 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1437 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1438 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1439 ste_wait(sc); 1440 /* 1441 * Try really hard to stop the RX engine or under heavy RX 1442 * data chip will write into de-allocated memory. 1443 */ 1444 ste_reset(sc); 1445 1446 sc->ste_link = 0; 1447 1448 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1449 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1450 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1451 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1452 } 1453 } 1454 1455 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1456 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1457 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1458 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1459 } 1460 } 1461 1462 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1463 STE_UNLOCK(sc); 1464 1465 return; 1466} 1467 1468static void 1469ste_reset(sc) 1470 struct ste_softc *sc; 1471{ 1472 int i; 1473 1474 STE_SETBIT4(sc, STE_ASICCTL, 1475 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1476 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1477 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1478 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1479 STE_ASICCTL_EXTRESET_RESET); 1480 1481 DELAY(100000); 1482 1483 for (i = 0; i < STE_TIMEOUT; i++) { 1484 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1485 break; 1486 } 1487 1488 if (i == STE_TIMEOUT) 1489 printf("ste%d: global reset never completed\n", sc->ste_unit); 1490 1491 return; 1492} 1493 1494static int 1495ste_ioctl(ifp, command, data) 1496 struct ifnet *ifp; 1497 u_long command; 1498 caddr_t data; 1499{ 1500 struct ste_softc *sc; 1501 struct ifreq *ifr; 1502 struct mii_data *mii; 1503 int error = 0; 1504 1505 sc = ifp->if_softc; 1506 STE_LOCK(sc); 1507 ifr = (struct ifreq *)data; 1508 1509 switch(command) { 1510 case SIOCSIFFLAGS: 1511 if (ifp->if_flags & IFF_UP) { 1512 if (ifp->if_flags & IFF_RUNNING && 1513 ifp->if_flags & IFF_PROMISC && 1514 !(sc->ste_if_flags & IFF_PROMISC)) { 1515 STE_SETBIT1(sc, STE_RX_MODE, 1516 STE_RXMODE_PROMISC); 1517 } else if (ifp->if_flags & IFF_RUNNING && 1518 !(ifp->if_flags & IFF_PROMISC) && 1519 sc->ste_if_flags & IFF_PROMISC) { 1520 STE_CLRBIT1(sc, STE_RX_MODE, 1521 STE_RXMODE_PROMISC); 1522 } 1523 if (ifp->if_flags & IFF_RUNNING && 1524 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1525 ste_setmulti(sc); 1526 if (!(ifp->if_flags & IFF_RUNNING)) { 1527 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1528 ste_init(sc); 1529 } 1530 } else { 1531 if (ifp->if_flags & IFF_RUNNING) 1532 ste_stop(sc); 1533 } 1534 sc->ste_if_flags = ifp->if_flags; 1535 error = 0; 1536 break; 1537 case SIOCADDMULTI: 1538 case SIOCDELMULTI: 1539 ste_setmulti(sc); 1540 error = 0; 1541 break; 1542 case SIOCGIFMEDIA: 1543 case SIOCSIFMEDIA: 1544 mii = device_get_softc(sc->ste_miibus); 1545 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1546 break; 1547 default: 1548 error = ether_ioctl(ifp, command, data); 1549 break; 1550 } 1551 1552 STE_UNLOCK(sc); 1553 1554 return(error); 1555} 1556 1557static int 1558ste_encap(sc, c, m_head) 1559 struct ste_softc *sc; 1560 struct ste_chain *c; 1561 struct mbuf *m_head; 1562{ 1563 int frag = 0; 1564 struct ste_frag *f = NULL; 1565 struct mbuf *m; 1566 struct ste_desc *d; 1567 1568 d = c->ste_ptr; 1569 d->ste_ctl = 0; 1570 1571encap_retry: 1572 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1573 if (m->m_len != 0) { 1574 if (frag == STE_MAXFRAGS) 1575 break; 1576 f = &d->ste_frags[frag]; 1577 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1578 f->ste_len = m->m_len; 1579 frag++; 1580 } 1581 } 1582 1583 if (m != NULL) { 1584 struct mbuf *mn; 1585 1586 /* 1587 * We ran out of segments. We have to recopy this 1588 * mbuf chain first. Bail out if we can't get the 1589 * new buffers. 1590 */ 1591 mn = m_defrag(m_head, M_DONTWAIT); 1592 if (mn == NULL) { 1593 m_freem(m_head); 1594 return ENOMEM; 1595 } 1596 m_head = mn; 1597 goto encap_retry; 1598 } 1599 1600 c->ste_mbuf = m_head; 1601 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1602 d->ste_ctl = 1; 1603 1604 return(0); 1605} 1606 1607static void 1608ste_start(ifp) 1609 struct ifnet *ifp; 1610{ 1611 struct ste_softc *sc; 1612 struct mbuf *m_head = NULL; 1613 struct ste_chain *cur_tx = NULL; 1614 int idx; 1615 1616 sc = ifp->if_softc; 1617 STE_LOCK(sc); 1618 1619 if (!sc->ste_link) { 1620 STE_UNLOCK(sc); 1621 return; 1622 } 1623 1624 if (ifp->if_flags & IFF_OACTIVE) { 1625 STE_UNLOCK(sc); 1626 return; 1627 } 1628 1629 idx = sc->ste_cdata.ste_tx_prod; 1630 1631 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1632 1633 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1634 ifp->if_flags |= IFF_OACTIVE; 1635 break; 1636 } 1637 1638 IF_DEQUEUE(&ifp->if_snd, m_head); 1639 if (m_head == NULL) 1640 break; 1641 1642 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1643 1644 if (ste_encap(sc, cur_tx, m_head) != 0) 1645 break; 1646 1647 cur_tx->ste_ptr->ste_next = 0; 1648 1649 if(sc->ste_tx_prev_idx < 0){ 1650 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1651 /* Load address of the TX list */ 1652 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1653 ste_wait(sc); 1654 1655 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1656 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1657 1658 /* Set TX polling interval to start TX engine */ 1659 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1660 1661 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1662 ste_wait(sc); 1663 }else{ 1664 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1665 sc->ste_cdata.ste_tx_chain[ 1666 sc->ste_tx_prev_idx].ste_ptr->ste_next 1667 = cur_tx->ste_phys; 1668 } 1669 1670 sc->ste_tx_prev_idx=idx; 1671 1672 /* 1673 * If there's a BPF listener, bounce a copy of this frame 1674 * to him. 1675 */ 1676 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1677 1678 STE_INC(idx, STE_TX_LIST_CNT); 1679 sc->ste_cdata.ste_tx_cnt++; 1680 ifp->if_timer = 5; 1681 sc->ste_cdata.ste_tx_prod = idx; 1682 } 1683 1684 STE_UNLOCK(sc); 1685 1686 return; 1687} 1688 1689static void 1690ste_watchdog(ifp) 1691 struct ifnet *ifp; 1692{ 1693 struct ste_softc *sc; 1694 1695 sc = ifp->if_softc; 1696 STE_LOCK(sc); 1697 1698 ifp->if_oerrors++; 1699 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1700 1701 ste_txeoc(sc); 1702 ste_txeof(sc); 1703 ste_rxeof(sc); 1704 ste_reset(sc); 1705 ste_init(sc); 1706 1707 if (ifp->if_snd.ifq_head != NULL) 1708 ste_start(ifp); 1709 STE_UNLOCK(sc); 1710 1711 return; 1712} 1713 1714static void 1715ste_shutdown(dev) 1716 device_t dev; 1717{ 1718 struct ste_softc *sc; 1719 1720 sc = device_get_softc(dev); 1721 1722 ste_stop(sc); 1723 1724 return; 1725} 1726