if_ste.c revision 127688
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 127688 2004-03-31 21:10:01Z ru $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44 45#include <net/if.h> 46#include <net/if_arp.h> 47#include <net/ethernet.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <vm/vm.h> /* for vtophys */ 55#include <vm/pmap.h> /* for vtophys */ 56#include <machine/bus_memio.h> 57#include <machine/bus_pio.h> 58#include <machine/bus.h> 59#include <machine/resource.h> 60#include <sys/bus.h> 61#include <sys/rman.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69/* "controller miibus0" required. See GENERIC if you get errors here. */ 70#include "miibus_if.h" 71 72#define STE_USEIOSPACE 73 74#include <pci/if_stereg.h> 75 76MODULE_DEPEND(ste, pci, 1, 1, 1); 77MODULE_DEPEND(ste, ether, 1, 1, 1); 78MODULE_DEPEND(ste, miibus, 1, 1, 1); 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe (device_t); 90static int ste_attach (device_t); 91static int ste_detach (device_t); 92static void ste_init (void *); 93static void ste_intr (void *); 94static void ste_rxeof (struct ste_softc *); 95static void ste_txeoc (struct ste_softc *); 96static void ste_txeof (struct ste_softc *); 97static void ste_stats_update (void *); 98static void ste_stop (struct ste_softc *); 99static void ste_reset (struct ste_softc *); 100static int ste_ioctl (struct ifnet *, u_long, caddr_t); 101static int ste_encap (struct ste_softc *, struct ste_chain *, 102 struct mbuf *); 103static void ste_start (struct ifnet *); 104static void ste_watchdog (struct ifnet *); 105static void ste_shutdown (device_t); 106static int ste_newbuf (struct ste_softc *, 107 struct ste_chain_onefrag *, 108 struct mbuf *); 109static int ste_ifmedia_upd (struct ifnet *); 110static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111 112static void ste_mii_sync (struct ste_softc *); 113static void ste_mii_send (struct ste_softc *, u_int32_t, int); 114static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 115static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_miibus_readreg (device_t, int, int); 117static int ste_miibus_writereg (device_t, int, int, int); 118static void ste_miibus_statchg (device_t); 119 120static int ste_eeprom_wait (struct ste_softc *); 121static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 122static void ste_wait (struct ste_softc *); 123static u_int8_t ste_calchash (caddr_t); 124static void ste_setmulti (struct ste_softc *); 125static int ste_init_rx_list (struct ste_softc *); 126static void ste_init_tx_list (struct ste_softc *); 127 128#ifdef STE_USEIOSPACE 129#define STE_RES SYS_RES_IOPORT 130#define STE_RID STE_PCI_LOIO 131#else 132#define STE_RES SYS_RES_MEMORY 133#define STE_RID STE_PCI_LOMEM 134#endif 135 136static device_method_t ste_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, ste_probe), 139 DEVMETHOD(device_attach, ste_attach), 140 DEVMETHOD(device_detach, ste_detach), 141 DEVMETHOD(device_shutdown, ste_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 149 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 150 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 151 152 { 0, 0 } 153}; 154 155static driver_t ste_driver = { 156 "ste", 157 ste_methods, 158 sizeof(struct ste_softc) 159}; 160 161static devclass_t ste_devclass; 162 163DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 164DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 165 166static int ste_rxsyncs; 167SYSCTL_INT(_hw, OID_AUTO, ste_rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, ""); 168 169#define STE_SETBIT4(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 171 172#define STE_CLRBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 174 175#define STE_SETBIT2(sc, reg, x) \ 176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 177 178#define STE_CLRBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 180 181#define STE_SETBIT1(sc, reg, x) \ 182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 183 184#define STE_CLRBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 186 187 188#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 189#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 190 191/* 192 * Sync the PHYs by setting data bit and strobing the clock 32 times. 193 */ 194static void 195ste_mii_sync(sc) 196 struct ste_softc *sc; 197{ 198 register int i; 199 200 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 201 202 for (i = 0; i < 32; i++) { 203 MII_SET(STE_PHYCTL_MCLK); 204 DELAY(1); 205 MII_CLR(STE_PHYCTL_MCLK); 206 DELAY(1); 207 } 208 209 return; 210} 211 212/* 213 * Clock a series of bits through the MII. 214 */ 215static void 216ste_mii_send(sc, bits, cnt) 217 struct ste_softc *sc; 218 u_int32_t bits; 219 int cnt; 220{ 221 int i; 222 223 MII_CLR(STE_PHYCTL_MCLK); 224 225 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 226 if (bits & i) { 227 MII_SET(STE_PHYCTL_MDATA); 228 } else { 229 MII_CLR(STE_PHYCTL_MDATA); 230 } 231 DELAY(1); 232 MII_CLR(STE_PHYCTL_MCLK); 233 DELAY(1); 234 MII_SET(STE_PHYCTL_MCLK); 235 } 236} 237 238/* 239 * Read an PHY register through the MII. 240 */ 241static int 242ste_mii_readreg(sc, frame) 243 struct ste_softc *sc; 244 struct ste_mii_frame *frame; 245 246{ 247 int i, ack; 248 249 STE_LOCK(sc); 250 251 /* 252 * Set up frame for RX. 253 */ 254 frame->mii_stdelim = STE_MII_STARTDELIM; 255 frame->mii_opcode = STE_MII_READOP; 256 frame->mii_turnaround = 0; 257 frame->mii_data = 0; 258 259 CSR_WRITE_2(sc, STE_PHYCTL, 0); 260 /* 261 * Turn on data xmit. 262 */ 263 MII_SET(STE_PHYCTL_MDIR); 264 265 ste_mii_sync(sc); 266 267 /* 268 * Send command/address info. 269 */ 270 ste_mii_send(sc, frame->mii_stdelim, 2); 271 ste_mii_send(sc, frame->mii_opcode, 2); 272 ste_mii_send(sc, frame->mii_phyaddr, 5); 273 ste_mii_send(sc, frame->mii_regaddr, 5); 274 275 /* Turn off xmit. */ 276 MII_CLR(STE_PHYCTL_MDIR); 277 278 /* Idle bit */ 279 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 280 DELAY(1); 281 MII_SET(STE_PHYCTL_MCLK); 282 DELAY(1); 283 284 /* Check for ack */ 285 MII_CLR(STE_PHYCTL_MCLK); 286 DELAY(1); 287 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 288 MII_SET(STE_PHYCTL_MCLK); 289 DELAY(1); 290 291 /* 292 * Now try reading data bits. If the ack failed, we still 293 * need to clock through 16 cycles to keep the PHY(s) in sync. 294 */ 295 if (ack) { 296 for(i = 0; i < 16; i++) { 297 MII_CLR(STE_PHYCTL_MCLK); 298 DELAY(1); 299 MII_SET(STE_PHYCTL_MCLK); 300 DELAY(1); 301 } 302 goto fail; 303 } 304 305 for (i = 0x8000; i; i >>= 1) { 306 MII_CLR(STE_PHYCTL_MCLK); 307 DELAY(1); 308 if (!ack) { 309 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 310 frame->mii_data |= i; 311 DELAY(1); 312 } 313 MII_SET(STE_PHYCTL_MCLK); 314 DELAY(1); 315 } 316 317fail: 318 319 MII_CLR(STE_PHYCTL_MCLK); 320 DELAY(1); 321 MII_SET(STE_PHYCTL_MCLK); 322 DELAY(1); 323 324 STE_UNLOCK(sc); 325 326 if (ack) 327 return(1); 328 return(0); 329} 330 331/* 332 * Write to a PHY register through the MII. 333 */ 334static int 335ste_mii_writereg(sc, frame) 336 struct ste_softc *sc; 337 struct ste_mii_frame *frame; 338 339{ 340 STE_LOCK(sc); 341 342 /* 343 * Set up frame for TX. 344 */ 345 346 frame->mii_stdelim = STE_MII_STARTDELIM; 347 frame->mii_opcode = STE_MII_WRITEOP; 348 frame->mii_turnaround = STE_MII_TURNAROUND; 349 350 /* 351 * Turn on data output. 352 */ 353 MII_SET(STE_PHYCTL_MDIR); 354 355 ste_mii_sync(sc); 356 357 ste_mii_send(sc, frame->mii_stdelim, 2); 358 ste_mii_send(sc, frame->mii_opcode, 2); 359 ste_mii_send(sc, frame->mii_phyaddr, 5); 360 ste_mii_send(sc, frame->mii_regaddr, 5); 361 ste_mii_send(sc, frame->mii_turnaround, 2); 362 ste_mii_send(sc, frame->mii_data, 16); 363 364 /* Idle bit. */ 365 MII_SET(STE_PHYCTL_MCLK); 366 DELAY(1); 367 MII_CLR(STE_PHYCTL_MCLK); 368 DELAY(1); 369 370 /* 371 * Turn off xmit. 372 */ 373 MII_CLR(STE_PHYCTL_MDIR); 374 375 STE_UNLOCK(sc); 376 377 return(0); 378} 379 380static int 381ste_miibus_readreg(dev, phy, reg) 382 device_t dev; 383 int phy, reg; 384{ 385 struct ste_softc *sc; 386 struct ste_mii_frame frame; 387 388 sc = device_get_softc(dev); 389 390 if ( sc->ste_one_phy && phy != 0 ) 391 return (0); 392 393 bzero((char *)&frame, sizeof(frame)); 394 395 frame.mii_phyaddr = phy; 396 frame.mii_regaddr = reg; 397 ste_mii_readreg(sc, &frame); 398 399 return(frame.mii_data); 400} 401 402static int 403ste_miibus_writereg(dev, phy, reg, data) 404 device_t dev; 405 int phy, reg, data; 406{ 407 struct ste_softc *sc; 408 struct ste_mii_frame frame; 409 410 sc = device_get_softc(dev); 411 bzero((char *)&frame, sizeof(frame)); 412 413 frame.mii_phyaddr = phy; 414 frame.mii_regaddr = reg; 415 frame.mii_data = data; 416 417 ste_mii_writereg(sc, &frame); 418 419 return(0); 420} 421 422static void 423ste_miibus_statchg(dev) 424 device_t dev; 425{ 426 struct ste_softc *sc; 427 struct mii_data *mii; 428 429 sc = device_get_softc(dev); 430 STE_LOCK(sc); 431 mii = device_get_softc(sc->ste_miibus); 432 433 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 434 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 435 } else { 436 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 437 } 438 STE_UNLOCK(sc); 439 440 return; 441} 442 443static int 444ste_ifmedia_upd(ifp) 445 struct ifnet *ifp; 446{ 447 struct ste_softc *sc; 448 struct mii_data *mii; 449 450 sc = ifp->if_softc; 451 mii = device_get_softc(sc->ste_miibus); 452 sc->ste_link = 0; 453 if (mii->mii_instance) { 454 struct mii_softc *miisc; 455 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 456 mii_phy_reset(miisc); 457 } 458 mii_mediachg(mii); 459 460 return(0); 461} 462 463static void 464ste_ifmedia_sts(ifp, ifmr) 465 struct ifnet *ifp; 466 struct ifmediareq *ifmr; 467{ 468 struct ste_softc *sc; 469 struct mii_data *mii; 470 471 sc = ifp->if_softc; 472 mii = device_get_softc(sc->ste_miibus); 473 474 mii_pollstat(mii); 475 ifmr->ifm_active = mii->mii_media_active; 476 ifmr->ifm_status = mii->mii_media_status; 477 478 return; 479} 480 481static void 482ste_wait(sc) 483 struct ste_softc *sc; 484{ 485 register int i; 486 487 for (i = 0; i < STE_TIMEOUT; i++) { 488 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 489 break; 490 } 491 492 if (i == STE_TIMEOUT) 493 printf("ste%d: command never completed!\n", sc->ste_unit); 494 495 return; 496} 497 498/* 499 * The EEPROM is slow: give it time to come ready after issuing 500 * it a command. 501 */ 502static int 503ste_eeprom_wait(sc) 504 struct ste_softc *sc; 505{ 506 int i; 507 508 DELAY(1000); 509 510 for (i = 0; i < 100; i++) { 511 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 512 DELAY(1000); 513 else 514 break; 515 } 516 517 if (i == 100) { 518 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 519 return(1); 520 } 521 522 return(0); 523} 524 525/* 526 * Read a sequence of words from the EEPROM. Note that ethernet address 527 * data is stored in the EEPROM in network byte order. 528 */ 529static int 530ste_read_eeprom(sc, dest, off, cnt, swap) 531 struct ste_softc *sc; 532 caddr_t dest; 533 int off; 534 int cnt; 535 int swap; 536{ 537 int err = 0, i; 538 u_int16_t word = 0, *ptr; 539 540 if (ste_eeprom_wait(sc)) 541 return(1); 542 543 for (i = 0; i < cnt; i++) { 544 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 545 err = ste_eeprom_wait(sc); 546 if (err) 547 break; 548 word = CSR_READ_2(sc, STE_EEPROM_DATA); 549 ptr = (u_int16_t *)(dest + (i * 2)); 550 if (swap) 551 *ptr = ntohs(word); 552 else 553 *ptr = word; 554 } 555 556 return(err ? 1 : 0); 557} 558 559static u_int8_t 560ste_calchash(addr) 561 caddr_t addr; 562{ 563 564 u_int32_t crc, carry; 565 int i, j; 566 u_int8_t c; 567 568 /* Compute CRC for the address value. */ 569 crc = 0xFFFFFFFF; /* initial value */ 570 571 for (i = 0; i < 6; i++) { 572 c = *(addr + i); 573 for (j = 0; j < 8; j++) { 574 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 575 crc <<= 1; 576 c >>= 1; 577 if (carry) 578 crc = (crc ^ 0x04c11db6) | carry; 579 } 580 } 581 582 /* return the filter bit position */ 583 return(crc & 0x0000003F); 584} 585 586static void 587ste_setmulti(sc) 588 struct ste_softc *sc; 589{ 590 struct ifnet *ifp; 591 int h = 0; 592 u_int32_t hashes[2] = { 0, 0 }; 593 struct ifmultiaddr *ifma; 594 595 ifp = &sc->arpcom.ac_if; 596 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 597 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 598 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 599 return; 600 } 601 602 /* first, zot all the existing hash bits */ 603 CSR_WRITE_2(sc, STE_MAR0, 0); 604 CSR_WRITE_2(sc, STE_MAR1, 0); 605 CSR_WRITE_2(sc, STE_MAR2, 0); 606 CSR_WRITE_2(sc, STE_MAR3, 0); 607 608 /* now program new ones */ 609 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 610 if (ifma->ifma_addr->sa_family != AF_LINK) 611 continue; 612 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 613 if (h < 32) 614 hashes[0] |= (1 << h); 615 else 616 hashes[1] |= (1 << (h - 32)); 617 } 618 619 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 620 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 621 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 622 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 623 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 624 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 625 626 return; 627} 628 629#ifdef DEVICE_POLLING 630static poll_handler_t ste_poll; 631 632static void 633ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 634{ 635 struct ste_softc *sc = ifp->if_softc; 636 637 STE_LOCK(sc); 638 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 639 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 640 goto done; 641 } 642 643 sc->rxcycles = count; 644 ste_rxeof(sc); 645 ste_txeof(sc); 646 if (ifp->if_snd.ifq_head != NULL) 647 ste_start(ifp); 648 649 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 650 u_int16_t status; 651 652 status = CSR_READ_2(sc, STE_ISR_ACK); 653 654 if (status & STE_ISR_TX_DONE) 655 ste_txeoc(sc); 656 657 if (status & STE_ISR_STATS_OFLOW) { 658 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 659 ste_stats_update(sc); 660 } 661 662 if (status & STE_ISR_LINKEVENT) 663 mii_pollstat(device_get_softc(sc->ste_miibus)); 664 665 if (status & STE_ISR_HOSTERR) { 666 ste_reset(sc); 667 ste_init(sc); 668 } 669 } 670done: 671 STE_UNLOCK(sc); 672} 673#endif /* DEVICE_POLLING */ 674 675static void 676ste_intr(xsc) 677 void *xsc; 678{ 679 struct ste_softc *sc; 680 struct ifnet *ifp; 681 u_int16_t status; 682 683 sc = xsc; 684 STE_LOCK(sc); 685 ifp = &sc->arpcom.ac_if; 686 687#ifdef DEVICE_POLLING 688 if (ifp->if_flags & IFF_POLLING) 689 goto done; 690 if (ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 691 CSR_WRITE_2(sc, STE_IMR, 0); 692 ste_poll(ifp, 0, 1); 693 goto done; 694 } 695#endif /* DEVICE_POLLING */ 696 697 /* See if this is really our interrupt. */ 698 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 699 STE_UNLOCK(sc); 700 return; 701 } 702 703 for (;;) { 704 status = CSR_READ_2(sc, STE_ISR_ACK); 705 706 if (!(status & STE_INTRS)) 707 break; 708 709 if (status & STE_ISR_RX_DMADONE) 710 ste_rxeof(sc); 711 712 if (status & STE_ISR_TX_DMADONE) 713 ste_txeof(sc); 714 715 if (status & STE_ISR_TX_DONE) 716 ste_txeoc(sc); 717 718 if (status & STE_ISR_STATS_OFLOW) { 719 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 720 ste_stats_update(sc); 721 } 722 723 if (status & STE_ISR_LINKEVENT) 724 mii_pollstat(device_get_softc(sc->ste_miibus)); 725 726 727 if (status & STE_ISR_HOSTERR) { 728 ste_reset(sc); 729 ste_init(sc); 730 } 731 } 732 733 /* Re-enable interrupts */ 734 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 735 736 if (ifp->if_snd.ifq_head != NULL) 737 ste_start(ifp); 738 739#ifdef DEVICE_POLLING 740done: 741#endif /* DEVICE_POLLING */ 742 STE_UNLOCK(sc); 743 744 return; 745} 746 747/* 748 * A frame has been uploaded: pass the resulting mbuf chain up to 749 * the higher level protocols. 750 */ 751static void 752ste_rxeof(sc) 753 struct ste_softc *sc; 754{ 755 struct mbuf *m; 756 struct ifnet *ifp; 757 struct ste_chain_onefrag *cur_rx; 758 int total_len = 0, count=0; 759 u_int32_t rxstat; 760 761 STE_LOCK_ASSERT(sc); 762 763 ifp = &sc->arpcom.ac_if; 764 765 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) { 766 cur_rx = sc->ste_cdata.ste_rx_head; 767 do { 768 cur_rx = cur_rx->ste_next; 769 /* If the ring is empty, just return. */ 770 if (cur_rx == sc->ste_cdata.ste_rx_head) 771 return; 772 } while (cur_rx->ste_ptr->ste_status == 0); 773 /* We've fallen behind the chip: catch it. */ 774 sc->ste_cdata.ste_rx_head = cur_rx; 775 ++ste_rxsyncs; 776 }; 777 778 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 779 & STE_RXSTAT_DMADONE) { 780#ifdef DEVICE_POLLING 781 if (ifp->if_flags & IFF_POLLING) { 782 if (sc->rxcycles <= 0) 783 break; 784 sc->rxcycles--; 785 } 786#endif /* DEVICE_POLLING */ 787 if ((STE_RX_LIST_CNT - count) < 3) { 788 break; 789 } 790 791 cur_rx = sc->ste_cdata.ste_rx_head; 792 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 793 794 /* 795 * If an error occurs, update stats, clear the 796 * status word and leave the mbuf cluster in place: 797 * it should simply get re-used next time this descriptor 798 * comes up in the ring. 799 */ 800 if (rxstat & STE_RXSTAT_FRAME_ERR) { 801 ifp->if_ierrors++; 802 cur_rx->ste_ptr->ste_status = 0; 803 continue; 804 } 805 806 /* 807 * If there error bit was not set, the upload complete 808 * bit should be set which means we have a valid packet. 809 * If not, something truly strange has happened. 810 */ 811 if (!(rxstat & STE_RXSTAT_DMADONE)) { 812 printf("ste%d: bad receive status -- packet dropped\n", 813 sc->ste_unit); 814 ifp->if_ierrors++; 815 cur_rx->ste_ptr->ste_status = 0; 816 continue; 817 } 818 819 /* No errors; receive the packet. */ 820 m = cur_rx->ste_mbuf; 821 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 822 823 /* 824 * Try to conjure up a new mbuf cluster. If that 825 * fails, it means we have an out of memory condition and 826 * should leave the buffer in place and continue. This will 827 * result in a lost packet, but there's little else we 828 * can do in this situation. 829 */ 830 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 831 ifp->if_ierrors++; 832 cur_rx->ste_ptr->ste_status = 0; 833 continue; 834 } 835 836 m->m_pkthdr.rcvif = ifp; 837 m->m_pkthdr.len = m->m_len = total_len; 838 839 ifp->if_ipackets++; 840 STE_UNLOCK(sc); 841 (*ifp->if_input)(ifp, m); 842 STE_LOCK(sc); 843 844 cur_rx->ste_ptr->ste_status = 0; 845 count++; 846 } 847 848 return; 849} 850 851static void 852ste_txeoc(sc) 853 struct ste_softc *sc; 854{ 855 u_int8_t txstat; 856 struct ifnet *ifp; 857 858 ifp = &sc->arpcom.ac_if; 859 860 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 861 STE_TXSTATUS_TXDONE) { 862 if (txstat & STE_TXSTATUS_UNDERRUN || 863 txstat & STE_TXSTATUS_EXCESSCOLLS || 864 txstat & STE_TXSTATUS_RECLAIMERR) { 865 ifp->if_oerrors++; 866 printf("ste%d: transmission error: %x\n", 867 sc->ste_unit, txstat); 868 869 ste_reset(sc); 870 ste_init(sc); 871 872 if (txstat & STE_TXSTATUS_UNDERRUN && 873 sc->ste_tx_thresh < STE_PACKET_SIZE) { 874 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 875 printf("ste%d: tx underrun, increasing tx" 876 " start threshold to %d bytes\n", 877 sc->ste_unit, sc->ste_tx_thresh); 878 } 879 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 880 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 881 (STE_PACKET_SIZE >> 4)); 882 } 883 ste_init(sc); 884 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 885 } 886 887 return; 888} 889 890static void 891ste_txeof(sc) 892 struct ste_softc *sc; 893{ 894 struct ste_chain *cur_tx = NULL; 895 struct ifnet *ifp; 896 int idx; 897 898 ifp = &sc->arpcom.ac_if; 899 900 idx = sc->ste_cdata.ste_tx_cons; 901 while(idx != sc->ste_cdata.ste_tx_prod) { 902 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 903 904 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 905 break; 906 907 if (cur_tx->ste_mbuf != NULL) { 908 m_freem(cur_tx->ste_mbuf); 909 cur_tx->ste_mbuf = NULL; 910 } 911 912 ifp->if_opackets++; 913 914 sc->ste_cdata.ste_tx_cnt--; 915 STE_INC(idx, STE_TX_LIST_CNT); 916 ifp->if_timer = 0; 917 } 918 919 sc->ste_cdata.ste_tx_cons = idx; 920 921 if (cur_tx != NULL) 922 ifp->if_flags &= ~IFF_OACTIVE; 923 924 return; 925} 926 927static void 928ste_stats_update(xsc) 929 void *xsc; 930{ 931 struct ste_softc *sc; 932 struct ifnet *ifp; 933 struct mii_data *mii; 934 935 sc = xsc; 936 STE_LOCK(sc); 937 938 ifp = &sc->arpcom.ac_if; 939 mii = device_get_softc(sc->ste_miibus); 940 941 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 942 + CSR_READ_1(sc, STE_MULTI_COLLS) 943 + CSR_READ_1(sc, STE_SINGLE_COLLS); 944 945 if (!sc->ste_link) { 946 mii_pollstat(mii); 947 if (mii->mii_media_status & IFM_ACTIVE && 948 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 949 sc->ste_link++; 950 /* 951 * we don't get a call-back on re-init so do it 952 * otherwise we get stuck in the wrong link state 953 */ 954 ste_miibus_statchg(sc->ste_dev); 955 if (ifp->if_snd.ifq_head != NULL) 956 ste_start(ifp); 957 } 958 } 959 960 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 961 STE_UNLOCK(sc); 962 963 return; 964} 965 966 967/* 968 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 969 * IDs against our list and return a device name if we find a match. 970 */ 971static int 972ste_probe(dev) 973 device_t dev; 974{ 975 struct ste_type *t; 976 977 t = ste_devs; 978 979 while(t->ste_name != NULL) { 980 if ((pci_get_vendor(dev) == t->ste_vid) && 981 (pci_get_device(dev) == t->ste_did)) { 982 device_set_desc(dev, t->ste_name); 983 return(0); 984 } 985 t++; 986 } 987 988 return(ENXIO); 989} 990 991/* 992 * Attach the interface. Allocate softc structures, do ifmedia 993 * setup and ethernet/BPF attach. 994 */ 995static int 996ste_attach(dev) 997 device_t dev; 998{ 999 struct ste_softc *sc; 1000 struct ifnet *ifp; 1001 int unit, error = 0, rid; 1002 1003 sc = device_get_softc(dev); 1004 unit = device_get_unit(dev); 1005 sc->ste_dev = dev; 1006 1007 /* 1008 * Only use one PHY since this chip reports multiple 1009 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1010 * it is at 0 & 1. It is rev 0x12. 1011 */ 1012 if (pci_get_vendor(dev) == DL_VENDORID && 1013 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1014 pci_get_revid(dev) == 0x12 ) 1015 sc->ste_one_phy = 1; 1016 1017 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1018 MTX_DEF | MTX_RECURSE); 1019#ifndef BURN_BRIDGES 1020 /* 1021 * Handle power management nonsense. 1022 */ 1023 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1024 u_int32_t iobase, membase, irq; 1025 1026 /* Save important PCI config data. */ 1027 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 1028 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 1029 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 1030 1031 /* Reset the power state. */ 1032 printf("ste%d: chip is in D%d power mode " 1033 "-- setting to D0\n", unit, 1034 pci_get_powerstate(dev)); 1035 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1036 1037 /* Restore PCI config data. */ 1038 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 1039 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 1040 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 1041 } 1042#endif 1043 /* 1044 * Map control/status registers. 1045 */ 1046 pci_enable_busmaster(dev); 1047 1048 rid = STE_RID; 1049 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1050 1051 if (sc->ste_res == NULL) { 1052 printf ("ste%d: couldn't map ports/memory\n", unit); 1053 error = ENXIO; 1054 goto fail; 1055 } 1056 1057 sc->ste_btag = rman_get_bustag(sc->ste_res); 1058 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1059 1060 /* Allocate interrupt */ 1061 rid = 0; 1062 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1063 RF_SHAREABLE | RF_ACTIVE); 1064 1065 if (sc->ste_irq == NULL) { 1066 printf("ste%d: couldn't map interrupt\n", unit); 1067 error = ENXIO; 1068 goto fail; 1069 } 1070 1071 callout_handle_init(&sc->ste_stat_ch); 1072 1073 /* Reset the adapter. */ 1074 ste_reset(sc); 1075 1076 /* 1077 * Get station address from the EEPROM. 1078 */ 1079 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1080 STE_EEADDR_NODE0, 3, 0)) { 1081 printf("ste%d: failed to read station address\n", unit); 1082 error = ENXIO;; 1083 goto fail; 1084 } 1085 1086 sc->ste_unit = unit; 1087 1088 /* Allocate the descriptor queues. */ 1089 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1090 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1091 1092 if (sc->ste_ldata == NULL) { 1093 printf("ste%d: no memory for list buffers!\n", unit); 1094 error = ENXIO; 1095 goto fail; 1096 } 1097 1098 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1099 1100 /* Do MII setup. */ 1101 if (mii_phy_probe(dev, &sc->ste_miibus, 1102 ste_ifmedia_upd, ste_ifmedia_sts)) { 1103 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1104 error = ENXIO; 1105 goto fail; 1106 } 1107 1108 ifp = &sc->arpcom.ac_if; 1109 ifp->if_softc = sc; 1110 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1111 ifp->if_mtu = ETHERMTU; 1112 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1113 ifp->if_ioctl = ste_ioctl; 1114 ifp->if_start = ste_start; 1115 ifp->if_watchdog = ste_watchdog; 1116 ifp->if_init = ste_init; 1117 ifp->if_baudrate = 10000000; 1118 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1119 1120 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1121 1122 /* 1123 * Call MI attach routine. 1124 */ 1125 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1126 1127 /* 1128 * Tell the upper layer(s) we support long frames. 1129 */ 1130 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1131 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1132 1133 /* Hook interrupt last to avoid having to lock softc */ 1134 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1135 ste_intr, sc, &sc->ste_intrhand); 1136 1137 if (error) { 1138 printf("ste%d: couldn't set up irq\n", unit); 1139 ether_ifdetach(ifp); 1140 goto fail; 1141 } 1142 1143fail: 1144 if (error) 1145 ste_detach(dev); 1146 1147 return(error); 1148} 1149 1150/* 1151 * Shutdown hardware and free up resources. This can be called any 1152 * time after the mutex has been initialized. It is called in both 1153 * the error case in attach and the normal detach case so it needs 1154 * to be careful about only freeing resources that have actually been 1155 * allocated. 1156 */ 1157static int 1158ste_detach(dev) 1159 device_t dev; 1160{ 1161 struct ste_softc *sc; 1162 struct ifnet *ifp; 1163 1164 sc = device_get_softc(dev); 1165 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1166 STE_LOCK(sc); 1167 ifp = &sc->arpcom.ac_if; 1168 1169 /* These should only be active if attach succeeded */ 1170 if (device_is_attached(dev)) { 1171 ste_stop(sc); 1172 ether_ifdetach(ifp); 1173 } 1174 if (sc->ste_miibus) 1175 device_delete_child(dev, sc->ste_miibus); 1176 bus_generic_detach(dev); 1177 1178 if (sc->ste_intrhand) 1179 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1180 if (sc->ste_irq) 1181 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1182 if (sc->ste_res) 1183 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1184 1185 if (sc->ste_ldata) { 1186 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1187 M_DEVBUF); 1188 } 1189 1190 STE_UNLOCK(sc); 1191 mtx_destroy(&sc->ste_mtx); 1192 1193 return(0); 1194} 1195 1196static int 1197ste_newbuf(sc, c, m) 1198 struct ste_softc *sc; 1199 struct ste_chain_onefrag *c; 1200 struct mbuf *m; 1201{ 1202 struct mbuf *m_new = NULL; 1203 1204 if (m == NULL) { 1205 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1206 if (m_new == NULL) 1207 return(ENOBUFS); 1208 MCLGET(m_new, M_DONTWAIT); 1209 if (!(m_new->m_flags & M_EXT)) { 1210 m_freem(m_new); 1211 return(ENOBUFS); 1212 } 1213 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1214 } else { 1215 m_new = m; 1216 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1217 m_new->m_data = m_new->m_ext.ext_buf; 1218 } 1219 1220 m_adj(m_new, ETHER_ALIGN); 1221 1222 c->ste_mbuf = m_new; 1223 c->ste_ptr->ste_status = 0; 1224 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1225 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1226 1227 return(0); 1228} 1229 1230static int 1231ste_init_rx_list(sc) 1232 struct ste_softc *sc; 1233{ 1234 struct ste_chain_data *cd; 1235 struct ste_list_data *ld; 1236 int i; 1237 1238 cd = &sc->ste_cdata; 1239 ld = sc->ste_ldata; 1240 1241 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1242 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1243 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1244 return(ENOBUFS); 1245 if (i == (STE_RX_LIST_CNT - 1)) { 1246 cd->ste_rx_chain[i].ste_next = 1247 &cd->ste_rx_chain[0]; 1248 ld->ste_rx_list[i].ste_next = 1249 vtophys(&ld->ste_rx_list[0]); 1250 } else { 1251 cd->ste_rx_chain[i].ste_next = 1252 &cd->ste_rx_chain[i + 1]; 1253 ld->ste_rx_list[i].ste_next = 1254 vtophys(&ld->ste_rx_list[i + 1]); 1255 } 1256 ld->ste_rx_list[i].ste_status = 0; 1257 } 1258 1259 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1260 1261 return(0); 1262} 1263 1264static void 1265ste_init_tx_list(sc) 1266 struct ste_softc *sc; 1267{ 1268 struct ste_chain_data *cd; 1269 struct ste_list_data *ld; 1270 int i; 1271 1272 cd = &sc->ste_cdata; 1273 ld = sc->ste_ldata; 1274 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1275 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1276 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1277 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1278 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1279 if (i == (STE_TX_LIST_CNT - 1)) 1280 cd->ste_tx_chain[i].ste_next = 1281 &cd->ste_tx_chain[0]; 1282 else 1283 cd->ste_tx_chain[i].ste_next = 1284 &cd->ste_tx_chain[i + 1]; 1285 if (i == 0) 1286 cd->ste_tx_chain[i].ste_prev = 1287 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1288 else 1289 cd->ste_tx_chain[i].ste_prev = 1290 &cd->ste_tx_chain[i - 1]; 1291 } 1292 1293 cd->ste_tx_prod = 0; 1294 cd->ste_tx_cons = 0; 1295 cd->ste_tx_cnt = 0; 1296 1297 return; 1298} 1299 1300static void 1301ste_init(xsc) 1302 void *xsc; 1303{ 1304 struct ste_softc *sc; 1305 int i; 1306 struct ifnet *ifp; 1307 1308 sc = xsc; 1309 STE_LOCK(sc); 1310 ifp = &sc->arpcom.ac_if; 1311 1312 ste_stop(sc); 1313 1314 /* Init our MAC address */ 1315 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1316 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1317 } 1318 1319 /* Init RX list */ 1320 if (ste_init_rx_list(sc) == ENOBUFS) { 1321 printf("ste%d: initialization failed: no " 1322 "memory for RX buffers\n", sc->ste_unit); 1323 ste_stop(sc); 1324 STE_UNLOCK(sc); 1325 return; 1326 } 1327 1328 /* Set RX polling interval */ 1329 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1330 1331 /* Init TX descriptors */ 1332 ste_init_tx_list(sc); 1333 1334 /* Set the TX freethresh value */ 1335 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1336 1337 /* Set the TX start threshold for best performance. */ 1338 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1339 1340 /* Set the TX reclaim threshold. */ 1341 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1342 1343 /* Set up the RX filter. */ 1344 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1345 1346 /* If we want promiscuous mode, set the allframes bit. */ 1347 if (ifp->if_flags & IFF_PROMISC) { 1348 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1349 } else { 1350 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1351 } 1352 1353 /* Set capture broadcast bit to accept broadcast frames. */ 1354 if (ifp->if_flags & IFF_BROADCAST) { 1355 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1356 } else { 1357 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1358 } 1359 1360 ste_setmulti(sc); 1361 1362 /* Load the address of the RX list. */ 1363 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1364 ste_wait(sc); 1365 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1366 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1367 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1368 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1369 1370 /* Set TX polling interval (defer until we TX first packet */ 1371 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1372 1373 /* Load address of the TX list */ 1374 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1375 ste_wait(sc); 1376 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1377 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1378 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1379 ste_wait(sc); 1380 sc->ste_tx_prev_idx=-1; 1381 1382 /* Enable receiver and transmitter */ 1383 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1384 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1385 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1386 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1387 1388 /* Enable stats counters. */ 1389 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1390 1391 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1392#ifdef DEVICE_POLLING 1393 /* Disable interrupts if we are polling. */ 1394 if (ifp->if_flags & IFF_POLLING) 1395 CSR_WRITE_2(sc, STE_IMR, 0); 1396 else 1397#endif /* DEVICE_POLLING */ 1398 /* Enable interrupts. */ 1399 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1400 1401 /* Accept VLAN length packets */ 1402 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1403 1404 ste_ifmedia_upd(ifp); 1405 1406 ifp->if_flags |= IFF_RUNNING; 1407 ifp->if_flags &= ~IFF_OACTIVE; 1408 1409 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1410 STE_UNLOCK(sc); 1411 1412 return; 1413} 1414 1415static void 1416ste_stop(sc) 1417 struct ste_softc *sc; 1418{ 1419 int i; 1420 struct ifnet *ifp; 1421 1422 STE_LOCK(sc); 1423 ifp = &sc->arpcom.ac_if; 1424 1425 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1426 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1427#ifdef DEVICE_POLLING 1428 ether_poll_deregister(ifp); 1429#endif /* DEVICE_POLLING */ 1430 1431 CSR_WRITE_2(sc, STE_IMR, 0); 1432 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1433 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1434 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1435 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1436 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1437 ste_wait(sc); 1438 /* 1439 * Try really hard to stop the RX engine or under heavy RX 1440 * data chip will write into de-allocated memory. 1441 */ 1442 ste_reset(sc); 1443 1444 sc->ste_link = 0; 1445 1446 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1447 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1448 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1449 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1450 } 1451 } 1452 1453 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1454 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1455 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1456 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1457 } 1458 } 1459 1460 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1461 STE_UNLOCK(sc); 1462 1463 return; 1464} 1465 1466static void 1467ste_reset(sc) 1468 struct ste_softc *sc; 1469{ 1470 int i; 1471 1472 STE_SETBIT4(sc, STE_ASICCTL, 1473 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1474 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1475 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1476 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1477 STE_ASICCTL_EXTRESET_RESET); 1478 1479 DELAY(100000); 1480 1481 for (i = 0; i < STE_TIMEOUT; i++) { 1482 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1483 break; 1484 } 1485 1486 if (i == STE_TIMEOUT) 1487 printf("ste%d: global reset never completed\n", sc->ste_unit); 1488 1489 return; 1490} 1491 1492static int 1493ste_ioctl(ifp, command, data) 1494 struct ifnet *ifp; 1495 u_long command; 1496 caddr_t data; 1497{ 1498 struct ste_softc *sc; 1499 struct ifreq *ifr; 1500 struct mii_data *mii; 1501 int error = 0; 1502 1503 sc = ifp->if_softc; 1504 STE_LOCK(sc); 1505 ifr = (struct ifreq *)data; 1506 1507 switch(command) { 1508 case SIOCSIFFLAGS: 1509 if (ifp->if_flags & IFF_UP) { 1510 if (ifp->if_flags & IFF_RUNNING && 1511 ifp->if_flags & IFF_PROMISC && 1512 !(sc->ste_if_flags & IFF_PROMISC)) { 1513 STE_SETBIT1(sc, STE_RX_MODE, 1514 STE_RXMODE_PROMISC); 1515 } else if (ifp->if_flags & IFF_RUNNING && 1516 !(ifp->if_flags & IFF_PROMISC) && 1517 sc->ste_if_flags & IFF_PROMISC) { 1518 STE_CLRBIT1(sc, STE_RX_MODE, 1519 STE_RXMODE_PROMISC); 1520 } 1521 if (ifp->if_flags & IFF_RUNNING && 1522 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1523 ste_setmulti(sc); 1524 if (!(ifp->if_flags & IFF_RUNNING)) { 1525 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1526 ste_init(sc); 1527 } 1528 } else { 1529 if (ifp->if_flags & IFF_RUNNING) 1530 ste_stop(sc); 1531 } 1532 sc->ste_if_flags = ifp->if_flags; 1533 error = 0; 1534 break; 1535 case SIOCADDMULTI: 1536 case SIOCDELMULTI: 1537 ste_setmulti(sc); 1538 error = 0; 1539 break; 1540 case SIOCGIFMEDIA: 1541 case SIOCSIFMEDIA: 1542 mii = device_get_softc(sc->ste_miibus); 1543 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1544 break; 1545 default: 1546 error = ether_ioctl(ifp, command, data); 1547 break; 1548 } 1549 1550 STE_UNLOCK(sc); 1551 1552 return(error); 1553} 1554 1555static int 1556ste_encap(sc, c, m_head) 1557 struct ste_softc *sc; 1558 struct ste_chain *c; 1559 struct mbuf *m_head; 1560{ 1561 int frag = 0; 1562 struct ste_frag *f = NULL; 1563 struct mbuf *m; 1564 struct ste_desc *d; 1565 1566 d = c->ste_ptr; 1567 d->ste_ctl = 0; 1568 1569encap_retry: 1570 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1571 if (m->m_len != 0) { 1572 if (frag == STE_MAXFRAGS) 1573 break; 1574 f = &d->ste_frags[frag]; 1575 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1576 f->ste_len = m->m_len; 1577 frag++; 1578 } 1579 } 1580 1581 if (m != NULL) { 1582 struct mbuf *mn; 1583 1584 /* 1585 * We ran out of segments. We have to recopy this 1586 * mbuf chain first. Bail out if we can't get the 1587 * new buffers. 1588 */ 1589 mn = m_defrag(m_head, M_DONTWAIT); 1590 if (mn == NULL) { 1591 m_freem(m_head); 1592 return ENOMEM; 1593 } 1594 m_head = mn; 1595 goto encap_retry; 1596 } 1597 1598 c->ste_mbuf = m_head; 1599 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1600 d->ste_ctl = 1; 1601 1602 return(0); 1603} 1604 1605static void 1606ste_start(ifp) 1607 struct ifnet *ifp; 1608{ 1609 struct ste_softc *sc; 1610 struct mbuf *m_head = NULL; 1611 struct ste_chain *cur_tx = NULL; 1612 int idx; 1613 1614 sc = ifp->if_softc; 1615 STE_LOCK(sc); 1616 1617 if (!sc->ste_link) { 1618 STE_UNLOCK(sc); 1619 return; 1620 } 1621 1622 if (ifp->if_flags & IFF_OACTIVE) { 1623 STE_UNLOCK(sc); 1624 return; 1625 } 1626 1627 idx = sc->ste_cdata.ste_tx_prod; 1628 1629 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1630 1631 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1632 ifp->if_flags |= IFF_OACTIVE; 1633 break; 1634 } 1635 1636 IF_DEQUEUE(&ifp->if_snd, m_head); 1637 if (m_head == NULL) 1638 break; 1639 1640 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1641 1642 if (ste_encap(sc, cur_tx, m_head) != 0) 1643 break; 1644 1645 cur_tx->ste_ptr->ste_next = 0; 1646 1647 if(sc->ste_tx_prev_idx < 0){ 1648 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1649 /* Load address of the TX list */ 1650 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1651 ste_wait(sc); 1652 1653 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1654 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1655 1656 /* Set TX polling interval to start TX engine */ 1657 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1658 1659 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1660 ste_wait(sc); 1661 }else{ 1662 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1663 sc->ste_cdata.ste_tx_chain[ 1664 sc->ste_tx_prev_idx].ste_ptr->ste_next 1665 = cur_tx->ste_phys; 1666 } 1667 1668 sc->ste_tx_prev_idx=idx; 1669 1670 /* 1671 * If there's a BPF listener, bounce a copy of this frame 1672 * to him. 1673 */ 1674 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1675 1676 STE_INC(idx, STE_TX_LIST_CNT); 1677 sc->ste_cdata.ste_tx_cnt++; 1678 ifp->if_timer = 5; 1679 sc->ste_cdata.ste_tx_prod = idx; 1680 } 1681 1682 STE_UNLOCK(sc); 1683 1684 return; 1685} 1686 1687static void 1688ste_watchdog(ifp) 1689 struct ifnet *ifp; 1690{ 1691 struct ste_softc *sc; 1692 1693 sc = ifp->if_softc; 1694 STE_LOCK(sc); 1695 1696 ifp->if_oerrors++; 1697 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1698 1699 ste_txeoc(sc); 1700 ste_txeof(sc); 1701 ste_rxeof(sc); 1702 ste_reset(sc); 1703 ste_init(sc); 1704 1705 if (ifp->if_snd.ifq_head != NULL) 1706 ste_start(ifp); 1707 STE_UNLOCK(sc); 1708 1709 return; 1710} 1711 1712static void 1713ste_shutdown(dev) 1714 device_t dev; 1715{ 1716 struct ste_softc *sc; 1717 1718 sc = device_get_softc(dev); 1719 1720 ste_stop(sc); 1721 1722 return; 1723} 1724