if_ste.c revision 127686
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 127686 2004-03-31 20:39:20Z ru $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_vlan_var.h> 50 51#include <net/bpf.h> 52 53#include <vm/vm.h> /* for vtophys */ 54#include <vm/pmap.h> /* for vtophys */ 55#include <machine/bus_memio.h> 56#include <machine/bus_pio.h> 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/bus.h> 60#include <sys/rman.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68/* "controller miibus0" required. See GENERIC if you get errors here. */ 69#include "miibus_if.h" 70 71#define STE_USEIOSPACE 72 73#include <pci/if_stereg.h> 74 75MODULE_DEPEND(ste, pci, 1, 1, 1); 76MODULE_DEPEND(ste, ether, 1, 1, 1); 77MODULE_DEPEND(ste, miibus, 1, 1, 1); 78 79/* 80 * Various supported device vendors/types and their names. 81 */ 82static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 85 { 0, 0, NULL } 86}; 87 88static int ste_probe (device_t); 89static int ste_attach (device_t); 90static int ste_detach (device_t); 91static void ste_init (void *); 92static void ste_intr (void *); 93static void ste_rxeof (struct ste_softc *); 94static void ste_txeoc (struct ste_softc *); 95static void ste_txeof (struct ste_softc *); 96static void ste_stats_update (void *); 97static void ste_stop (struct ste_softc *); 98static void ste_reset (struct ste_softc *); 99static int ste_ioctl (struct ifnet *, u_long, caddr_t); 100static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102static void ste_start (struct ifnet *); 103static void ste_watchdog (struct ifnet *); 104static void ste_shutdown (device_t); 105static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108static int ste_ifmedia_upd (struct ifnet *); 109static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111static void ste_mii_sync (struct ste_softc *); 112static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 114static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 115static int ste_miibus_readreg (device_t, int, int); 116static int ste_miibus_writereg (device_t, int, int, int); 117static void ste_miibus_statchg (device_t); 118 119static int ste_eeprom_wait (struct ste_softc *); 120static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 121static void ste_wait (struct ste_softc *); 122static u_int8_t ste_calchash (caddr_t); 123static void ste_setmulti (struct ste_softc *); 124static int ste_init_rx_list (struct ste_softc *); 125static void ste_init_tx_list (struct ste_softc *); 126 127#ifdef STE_USEIOSPACE 128#define STE_RES SYS_RES_IOPORT 129#define STE_RID STE_PCI_LOIO 130#else 131#define STE_RES SYS_RES_MEMORY 132#define STE_RID STE_PCI_LOMEM 133#endif 134 135static device_method_t ste_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ste_probe), 138 DEVMETHOD(device_attach, ste_attach), 139 DEVMETHOD(device_detach, ste_detach), 140 DEVMETHOD(device_shutdown, ste_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 150 151 { 0, 0 } 152}; 153 154static driver_t ste_driver = { 155 "ste", 156 ste_methods, 157 sizeof(struct ste_softc) 158}; 159 160static devclass_t ste_devclass; 161 162DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 163DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 164 165#define STE_SETBIT4(sc, reg, x) \ 166 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 167 168#define STE_CLRBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 170 171#define STE_SETBIT2(sc, reg, x) \ 172 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 173 174#define STE_CLRBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 176 177#define STE_SETBIT1(sc, reg, x) \ 178 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 179 180#define STE_CLRBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 182 183 184#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 185#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 186 187/* 188 * Sync the PHYs by setting data bit and strobing the clock 32 times. 189 */ 190static void 191ste_mii_sync(sc) 192 struct ste_softc *sc; 193{ 194 register int i; 195 196 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 197 198 for (i = 0; i < 32; i++) { 199 MII_SET(STE_PHYCTL_MCLK); 200 DELAY(1); 201 MII_CLR(STE_PHYCTL_MCLK); 202 DELAY(1); 203 } 204 205 return; 206} 207 208/* 209 * Clock a series of bits through the MII. 210 */ 211static void 212ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216{ 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232} 233 234/* 235 * Read an PHY register through the MII. 236 */ 237static int 238ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242{ 243 int i, ack; 244 245 STE_LOCK(sc); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 STE_UNLOCK(sc); 321 322 if (ack) 323 return(1); 324 return(0); 325} 326 327/* 328 * Write to a PHY register through the MII. 329 */ 330static int 331ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335{ 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374} 375 376static int 377ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396} 397 398static int 399ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402{ 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416} 417 418static void 419ste_miibus_statchg(dev) 420 device_t dev; 421{ 422 struct ste_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 STE_LOCK(sc); 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 STE_UNLOCK(sc); 435 436 return; 437} 438 439static int 440ste_ifmedia_upd(ifp) 441 struct ifnet *ifp; 442{ 443 struct ste_softc *sc; 444 struct mii_data *mii; 445 446 sc = ifp->if_softc; 447 mii = device_get_softc(sc->ste_miibus); 448 sc->ste_link = 0; 449 if (mii->mii_instance) { 450 struct mii_softc *miisc; 451 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 452 mii_phy_reset(miisc); 453 } 454 mii_mediachg(mii); 455 456 return(0); 457} 458 459static void 460ste_ifmedia_sts(ifp, ifmr) 461 struct ifnet *ifp; 462 struct ifmediareq *ifmr; 463{ 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->ste_miibus); 469 470 mii_pollstat(mii); 471 ifmr->ifm_active = mii->mii_media_active; 472 ifmr->ifm_status = mii->mii_media_status; 473 474 return; 475} 476 477static void 478ste_wait(sc) 479 struct ste_softc *sc; 480{ 481 register int i; 482 483 for (i = 0; i < STE_TIMEOUT; i++) { 484 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 485 break; 486 } 487 488 if (i == STE_TIMEOUT) 489 printf("ste%d: command never completed!\n", sc->ste_unit); 490 491 return; 492} 493 494/* 495 * The EEPROM is slow: give it time to come ready after issuing 496 * it a command. 497 */ 498static int 499ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501{ 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 515 return(1); 516 } 517 518 return(0); 519} 520 521/* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525static int 526ste_read_eeprom(sc, dest, off, cnt, swap) 527 struct ste_softc *sc; 528 caddr_t dest; 529 int off; 530 int cnt; 531 int swap; 532{ 533 int err = 0, i; 534 u_int16_t word = 0, *ptr; 535 536 if (ste_eeprom_wait(sc)) 537 return(1); 538 539 for (i = 0; i < cnt; i++) { 540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 541 err = ste_eeprom_wait(sc); 542 if (err) 543 break; 544 word = CSR_READ_2(sc, STE_EEPROM_DATA); 545 ptr = (u_int16_t *)(dest + (i * 2)); 546 if (swap) 547 *ptr = ntohs(word); 548 else 549 *ptr = word; 550 } 551 552 return(err ? 1 : 0); 553} 554 555static u_int8_t 556ste_calchash(addr) 557 caddr_t addr; 558{ 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580} 581 582static void 583ste_setmulti(sc) 584 struct ste_softc *sc; 585{ 586 struct ifnet *ifp; 587 int h = 0; 588 u_int32_t hashes[2] = { 0, 0 }; 589 struct ifmultiaddr *ifma; 590 591 ifp = &sc->arpcom.ac_if; 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 594 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 595 return; 596 } 597 598 /* first, zot all the existing hash bits */ 599 CSR_WRITE_2(sc, STE_MAR0, 0); 600 CSR_WRITE_2(sc, STE_MAR1, 0); 601 CSR_WRITE_2(sc, STE_MAR2, 0); 602 CSR_WRITE_2(sc, STE_MAR3, 0); 603 604 /* now program new ones */ 605 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623} 624 625#ifdef DEVICE_POLLING 626static poll_handler_t ste_poll; 627 628static void 629ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 630{ 631 struct ste_softc *sc = ifp->if_softc; 632 633 STE_LOCK(sc); 634 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 635 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 636 goto done; 637 } 638 639 sc->rxcycles = count; 640 ste_rxeof(sc); 641 ste_txeof(sc); 642 if (ifp->if_snd.ifq_head != NULL) 643 ste_start(ifp); 644 645 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 646 u_int16_t status; 647 648 status = CSR_READ_2(sc, STE_ISR_ACK); 649 650 if (status & STE_ISR_TX_DONE) 651 ste_txeoc(sc); 652 653 if (status & STE_ISR_STATS_OFLOW) { 654 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 655 ste_stats_update(sc); 656 } 657 658 if (status & STE_ISR_LINKEVENT) 659 mii_pollstat(device_get_softc(sc->ste_miibus)); 660 661 if (status & STE_ISR_HOSTERR) { 662 ste_reset(sc); 663 ste_init(sc); 664 } 665 } 666done: 667 STE_UNLOCK(sc); 668} 669#endif /* DEVICE_POLLING */ 670 671static void 672ste_intr(xsc) 673 void *xsc; 674{ 675 struct ste_softc *sc; 676 struct ifnet *ifp; 677 u_int16_t status; 678 679 sc = xsc; 680 STE_LOCK(sc); 681 ifp = &sc->arpcom.ac_if; 682 683#ifdef DEVICE_POLLING 684 if (ifp->if_flags & IFF_POLLING) 685 goto done; 686 if (ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */ 687 CSR_WRITE_2(sc, STE_IMR, 0); 688 ste_poll(ifp, 0, 1); 689 goto done; 690 } 691#endif /* DEVICE_POLLING */ 692 693 /* See if this is really our interrupt. */ 694 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 695 STE_UNLOCK(sc); 696 return; 697 } 698 699 for (;;) { 700 status = CSR_READ_2(sc, STE_ISR_ACK); 701 702 if (!(status & STE_INTRS)) 703 break; 704 705 if (status & STE_ISR_RX_DMADONE) 706 ste_rxeof(sc); 707 708 if (status & STE_ISR_TX_DMADONE) 709 ste_txeof(sc); 710 711 if (status & STE_ISR_TX_DONE) 712 ste_txeoc(sc); 713 714 if (status & STE_ISR_STATS_OFLOW) { 715 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 716 ste_stats_update(sc); 717 } 718 719 if (status & STE_ISR_LINKEVENT) 720 mii_pollstat(device_get_softc(sc->ste_miibus)); 721 722 723 if (status & STE_ISR_HOSTERR) { 724 ste_reset(sc); 725 ste_init(sc); 726 } 727 } 728 729 /* Re-enable interrupts */ 730 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 731 732 if (ifp->if_snd.ifq_head != NULL) 733 ste_start(ifp); 734 735#ifdef DEVICE_POLLING 736done: 737#endif /* DEVICE_POLLING */ 738 STE_UNLOCK(sc); 739 740 return; 741} 742 743/* 744 * A frame has been uploaded: pass the resulting mbuf chain up to 745 * the higher level protocols. 746 */ 747static void 748ste_rxeof(sc) 749 struct ste_softc *sc; 750{ 751 struct mbuf *m; 752 struct ifnet *ifp; 753 struct ste_chain_onefrag *cur_rx; 754 int total_len = 0, count=0; 755 u_int32_t rxstat; 756 757 STE_LOCK_ASSERT(sc); 758 759 ifp = &sc->arpcom.ac_if; 760 761 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 762 & STE_RXSTAT_DMADONE) { 763#ifdef DEVICE_POLLING 764 if (ifp->if_flags & IFF_POLLING) { 765 if (sc->rxcycles <= 0) 766 break; 767 sc->rxcycles--; 768 } 769#endif /* DEVICE_POLLING */ 770 if ((STE_RX_LIST_CNT - count) < 3) { 771 break; 772 } 773 774 cur_rx = sc->ste_cdata.ste_rx_head; 775 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 776 777 /* 778 * If an error occurs, update stats, clear the 779 * status word and leave the mbuf cluster in place: 780 * it should simply get re-used next time this descriptor 781 * comes up in the ring. 782 */ 783 if (rxstat & STE_RXSTAT_FRAME_ERR) { 784 ifp->if_ierrors++; 785 cur_rx->ste_ptr->ste_status = 0; 786 continue; 787 } 788 789 /* 790 * If there error bit was not set, the upload complete 791 * bit should be set which means we have a valid packet. 792 * If not, something truly strange has happened. 793 */ 794 if (!(rxstat & STE_RXSTAT_DMADONE)) { 795 printf("ste%d: bad receive status -- packet dropped\n", 796 sc->ste_unit); 797 ifp->if_ierrors++; 798 cur_rx->ste_ptr->ste_status = 0; 799 continue; 800 } 801 802 /* No errors; receive the packet. */ 803 m = cur_rx->ste_mbuf; 804 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 805 806 /* 807 * Try to conjure up a new mbuf cluster. If that 808 * fails, it means we have an out of memory condition and 809 * should leave the buffer in place and continue. This will 810 * result in a lost packet, but there's little else we 811 * can do in this situation. 812 */ 813 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 814 ifp->if_ierrors++; 815 cur_rx->ste_ptr->ste_status = 0; 816 continue; 817 } 818 819 m->m_pkthdr.rcvif = ifp; 820 m->m_pkthdr.len = m->m_len = total_len; 821 822 ifp->if_ipackets++; 823 STE_UNLOCK(sc); 824 (*ifp->if_input)(ifp, m); 825 STE_LOCK(sc); 826 827 cur_rx->ste_ptr->ste_status = 0; 828 count++; 829 } 830 831 return; 832} 833 834static void 835ste_txeoc(sc) 836 struct ste_softc *sc; 837{ 838 u_int8_t txstat; 839 struct ifnet *ifp; 840 841 ifp = &sc->arpcom.ac_if; 842 843 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 844 STE_TXSTATUS_TXDONE) { 845 if (txstat & STE_TXSTATUS_UNDERRUN || 846 txstat & STE_TXSTATUS_EXCESSCOLLS || 847 txstat & STE_TXSTATUS_RECLAIMERR) { 848 ifp->if_oerrors++; 849 printf("ste%d: transmission error: %x\n", 850 sc->ste_unit, txstat); 851 852 ste_reset(sc); 853 ste_init(sc); 854 855 if (txstat & STE_TXSTATUS_UNDERRUN && 856 sc->ste_tx_thresh < STE_PACKET_SIZE) { 857 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 858 printf("ste%d: tx underrun, increasing tx" 859 " start threshold to %d bytes\n", 860 sc->ste_unit, sc->ste_tx_thresh); 861 } 862 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 863 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 864 (STE_PACKET_SIZE >> 4)); 865 } 866 ste_init(sc); 867 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 868 } 869 870 return; 871} 872 873static void 874ste_txeof(sc) 875 struct ste_softc *sc; 876{ 877 struct ste_chain *cur_tx = NULL; 878 struct ifnet *ifp; 879 int idx; 880 881 ifp = &sc->arpcom.ac_if; 882 883 idx = sc->ste_cdata.ste_tx_cons; 884 while(idx != sc->ste_cdata.ste_tx_prod) { 885 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 886 887 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 888 break; 889 890 if (cur_tx->ste_mbuf != NULL) { 891 m_freem(cur_tx->ste_mbuf); 892 cur_tx->ste_mbuf = NULL; 893 } 894 895 ifp->if_opackets++; 896 897 sc->ste_cdata.ste_tx_cnt--; 898 STE_INC(idx, STE_TX_LIST_CNT); 899 ifp->if_timer = 0; 900 } 901 902 sc->ste_cdata.ste_tx_cons = idx; 903 904 if (cur_tx != NULL) 905 ifp->if_flags &= ~IFF_OACTIVE; 906 907 return; 908} 909 910static void 911ste_stats_update(xsc) 912 void *xsc; 913{ 914 struct ste_softc *sc; 915 struct ifnet *ifp; 916 struct mii_data *mii; 917 918 sc = xsc; 919 STE_LOCK(sc); 920 921 ifp = &sc->arpcom.ac_if; 922 mii = device_get_softc(sc->ste_miibus); 923 924 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 925 + CSR_READ_1(sc, STE_MULTI_COLLS) 926 + CSR_READ_1(sc, STE_SINGLE_COLLS); 927 928 if (!sc->ste_link) { 929 mii_pollstat(mii); 930 if (mii->mii_media_status & IFM_ACTIVE && 931 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 932 sc->ste_link++; 933 /* 934 * we don't get a call-back on re-init so do it 935 * otherwise we get stuck in the wrong link state 936 */ 937 ste_miibus_statchg(sc->ste_dev); 938 if (ifp->if_snd.ifq_head != NULL) 939 ste_start(ifp); 940 } 941 } 942 943 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 944 STE_UNLOCK(sc); 945 946 return; 947} 948 949 950/* 951 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 952 * IDs against our list and return a device name if we find a match. 953 */ 954static int 955ste_probe(dev) 956 device_t dev; 957{ 958 struct ste_type *t; 959 960 t = ste_devs; 961 962 while(t->ste_name != NULL) { 963 if ((pci_get_vendor(dev) == t->ste_vid) && 964 (pci_get_device(dev) == t->ste_did)) { 965 device_set_desc(dev, t->ste_name); 966 return(0); 967 } 968 t++; 969 } 970 971 return(ENXIO); 972} 973 974/* 975 * Attach the interface. Allocate softc structures, do ifmedia 976 * setup and ethernet/BPF attach. 977 */ 978static int 979ste_attach(dev) 980 device_t dev; 981{ 982 struct ste_softc *sc; 983 struct ifnet *ifp; 984 int unit, error = 0, rid; 985 986 sc = device_get_softc(dev); 987 unit = device_get_unit(dev); 988 sc->ste_dev = dev; 989 990 /* 991 * Only use one PHY since this chip reports multiple 992 * Note on the DFE-550 the PHY is at 1 on the DFE-580 993 * it is at 0 & 1. It is rev 0x12. 994 */ 995 if (pci_get_vendor(dev) == DL_VENDORID && 996 pci_get_device(dev) == DL_DEVICEID_DL10050 && 997 pci_get_revid(dev) == 0x12 ) 998 sc->ste_one_phy = 1; 999 1000 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1001 MTX_DEF | MTX_RECURSE); 1002#ifndef BURN_BRIDGES 1003 /* 1004 * Handle power management nonsense. 1005 */ 1006 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1007 u_int32_t iobase, membase, irq; 1008 1009 /* Save important PCI config data. */ 1010 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 1011 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 1012 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 1013 1014 /* Reset the power state. */ 1015 printf("ste%d: chip is in D%d power mode " 1016 "-- setting to D0\n", unit, 1017 pci_get_powerstate(dev)); 1018 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1019 1020 /* Restore PCI config data. */ 1021 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 1022 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 1023 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 1024 } 1025#endif 1026 /* 1027 * Map control/status registers. 1028 */ 1029 pci_enable_busmaster(dev); 1030 1031 rid = STE_RID; 1032 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 1033 1034 if (sc->ste_res == NULL) { 1035 printf ("ste%d: couldn't map ports/memory\n", unit); 1036 error = ENXIO; 1037 goto fail; 1038 } 1039 1040 sc->ste_btag = rman_get_bustag(sc->ste_res); 1041 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1042 1043 /* Allocate interrupt */ 1044 rid = 0; 1045 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1046 RF_SHAREABLE | RF_ACTIVE); 1047 1048 if (sc->ste_irq == NULL) { 1049 printf("ste%d: couldn't map interrupt\n", unit); 1050 error = ENXIO; 1051 goto fail; 1052 } 1053 1054 callout_handle_init(&sc->ste_stat_ch); 1055 1056 /* Reset the adapter. */ 1057 ste_reset(sc); 1058 1059 /* 1060 * Get station address from the EEPROM. 1061 */ 1062 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1063 STE_EEADDR_NODE0, 3, 0)) { 1064 printf("ste%d: failed to read station address\n", unit); 1065 error = ENXIO;; 1066 goto fail; 1067 } 1068 1069 sc->ste_unit = unit; 1070 1071 /* Allocate the descriptor queues. */ 1072 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1073 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1074 1075 if (sc->ste_ldata == NULL) { 1076 printf("ste%d: no memory for list buffers!\n", unit); 1077 error = ENXIO; 1078 goto fail; 1079 } 1080 1081 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1082 1083 /* Do MII setup. */ 1084 if (mii_phy_probe(dev, &sc->ste_miibus, 1085 ste_ifmedia_upd, ste_ifmedia_sts)) { 1086 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1087 error = ENXIO; 1088 goto fail; 1089 } 1090 1091 ifp = &sc->arpcom.ac_if; 1092 ifp->if_softc = sc; 1093 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1094 ifp->if_mtu = ETHERMTU; 1095 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1096 ifp->if_ioctl = ste_ioctl; 1097 ifp->if_start = ste_start; 1098 ifp->if_watchdog = ste_watchdog; 1099 ifp->if_init = ste_init; 1100 ifp->if_baudrate = 10000000; 1101 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1102 1103 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1104 1105 /* 1106 * Call MI attach routine. 1107 */ 1108 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1109 1110 /* 1111 * Tell the upper layer(s) we support long frames. 1112 */ 1113 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1114 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1115 1116 /* Hook interrupt last to avoid having to lock softc */ 1117 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1118 ste_intr, sc, &sc->ste_intrhand); 1119 1120 if (error) { 1121 printf("ste%d: couldn't set up irq\n", unit); 1122 ether_ifdetach(ifp); 1123 goto fail; 1124 } 1125 1126fail: 1127 if (error) 1128 ste_detach(dev); 1129 1130 return(error); 1131} 1132 1133/* 1134 * Shutdown hardware and free up resources. This can be called any 1135 * time after the mutex has been initialized. It is called in both 1136 * the error case in attach and the normal detach case so it needs 1137 * to be careful about only freeing resources that have actually been 1138 * allocated. 1139 */ 1140static int 1141ste_detach(dev) 1142 device_t dev; 1143{ 1144 struct ste_softc *sc; 1145 struct ifnet *ifp; 1146 1147 sc = device_get_softc(dev); 1148 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1149 STE_LOCK(sc); 1150 ifp = &sc->arpcom.ac_if; 1151 1152 /* These should only be active if attach succeeded */ 1153 if (device_is_attached(dev)) { 1154 ste_stop(sc); 1155 ether_ifdetach(ifp); 1156 } 1157 if (sc->ste_miibus) 1158 device_delete_child(dev, sc->ste_miibus); 1159 bus_generic_detach(dev); 1160 1161 if (sc->ste_intrhand) 1162 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1163 if (sc->ste_irq) 1164 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1165 if (sc->ste_res) 1166 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1167 1168 if (sc->ste_ldata) { 1169 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1170 M_DEVBUF); 1171 } 1172 1173 STE_UNLOCK(sc); 1174 mtx_destroy(&sc->ste_mtx); 1175 1176 return(0); 1177} 1178 1179static int 1180ste_newbuf(sc, c, m) 1181 struct ste_softc *sc; 1182 struct ste_chain_onefrag *c; 1183 struct mbuf *m; 1184{ 1185 struct mbuf *m_new = NULL; 1186 1187 if (m == NULL) { 1188 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1189 if (m_new == NULL) 1190 return(ENOBUFS); 1191 MCLGET(m_new, M_DONTWAIT); 1192 if (!(m_new->m_flags & M_EXT)) { 1193 m_freem(m_new); 1194 return(ENOBUFS); 1195 } 1196 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1197 } else { 1198 m_new = m; 1199 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1200 m_new->m_data = m_new->m_ext.ext_buf; 1201 } 1202 1203 m_adj(m_new, ETHER_ALIGN); 1204 1205 c->ste_mbuf = m_new; 1206 c->ste_ptr->ste_status = 0; 1207 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1208 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1209 1210 return(0); 1211} 1212 1213static int 1214ste_init_rx_list(sc) 1215 struct ste_softc *sc; 1216{ 1217 struct ste_chain_data *cd; 1218 struct ste_list_data *ld; 1219 int i; 1220 1221 cd = &sc->ste_cdata; 1222 ld = sc->ste_ldata; 1223 1224 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1225 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1226 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1227 return(ENOBUFS); 1228 if (i == (STE_RX_LIST_CNT - 1)) { 1229 cd->ste_rx_chain[i].ste_next = 1230 &cd->ste_rx_chain[0]; 1231 ld->ste_rx_list[i].ste_next = 1232 vtophys(&ld->ste_rx_list[0]); 1233 } else { 1234 cd->ste_rx_chain[i].ste_next = 1235 &cd->ste_rx_chain[i + 1]; 1236 ld->ste_rx_list[i].ste_next = 1237 vtophys(&ld->ste_rx_list[i + 1]); 1238 } 1239 ld->ste_rx_list[i].ste_status = 0; 1240 } 1241 1242 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1243 1244 return(0); 1245} 1246 1247static void 1248ste_init_tx_list(sc) 1249 struct ste_softc *sc; 1250{ 1251 struct ste_chain_data *cd; 1252 struct ste_list_data *ld; 1253 int i; 1254 1255 cd = &sc->ste_cdata; 1256 ld = sc->ste_ldata; 1257 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1258 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1259 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1260 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1261 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1262 if (i == (STE_TX_LIST_CNT - 1)) 1263 cd->ste_tx_chain[i].ste_next = 1264 &cd->ste_tx_chain[0]; 1265 else 1266 cd->ste_tx_chain[i].ste_next = 1267 &cd->ste_tx_chain[i + 1]; 1268 if (i == 0) 1269 cd->ste_tx_chain[i].ste_prev = 1270 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1271 else 1272 cd->ste_tx_chain[i].ste_prev = 1273 &cd->ste_tx_chain[i - 1]; 1274 } 1275 1276 cd->ste_tx_prod = 0; 1277 cd->ste_tx_cons = 0; 1278 cd->ste_tx_cnt = 0; 1279 1280 return; 1281} 1282 1283static void 1284ste_init(xsc) 1285 void *xsc; 1286{ 1287 struct ste_softc *sc; 1288 int i; 1289 struct ifnet *ifp; 1290 1291 sc = xsc; 1292 STE_LOCK(sc); 1293 ifp = &sc->arpcom.ac_if; 1294 1295 ste_stop(sc); 1296 1297 /* Init our MAC address */ 1298 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1299 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1300 } 1301 1302 /* Init RX list */ 1303 if (ste_init_rx_list(sc) == ENOBUFS) { 1304 printf("ste%d: initialization failed: no " 1305 "memory for RX buffers\n", sc->ste_unit); 1306 ste_stop(sc); 1307 STE_UNLOCK(sc); 1308 return; 1309 } 1310 1311 /* Set RX polling interval */ 1312 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1313 1314 /* Init TX descriptors */ 1315 ste_init_tx_list(sc); 1316 1317 /* Set the TX freethresh value */ 1318 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1319 1320 /* Set the TX start threshold for best performance. */ 1321 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1322 1323 /* Set the TX reclaim threshold. */ 1324 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1325 1326 /* Set up the RX filter. */ 1327 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1328 1329 /* If we want promiscuous mode, set the allframes bit. */ 1330 if (ifp->if_flags & IFF_PROMISC) { 1331 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1332 } else { 1333 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1334 } 1335 1336 /* Set capture broadcast bit to accept broadcast frames. */ 1337 if (ifp->if_flags & IFF_BROADCAST) { 1338 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1339 } else { 1340 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1341 } 1342 1343 ste_setmulti(sc); 1344 1345 /* Load the address of the RX list. */ 1346 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1347 ste_wait(sc); 1348 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1349 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1350 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1351 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1352 1353 /* Set TX polling interval (defer until we TX first packet */ 1354 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1355 1356 /* Load address of the TX list */ 1357 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1358 ste_wait(sc); 1359 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1360 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1361 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1362 ste_wait(sc); 1363 sc->ste_tx_prev_idx=-1; 1364 1365 /* Enable receiver and transmitter */ 1366 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1367 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1368 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1369 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1370 1371 /* Enable stats counters. */ 1372 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1373 1374 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1375#ifdef DEVICE_POLLING 1376 /* Disable interrupts if we are polling. */ 1377 if (ifp->if_flags & IFF_POLLING) 1378 CSR_WRITE_2(sc, STE_IMR, 0); 1379 else 1380#endif /* DEVICE_POLLING */ 1381 /* Enable interrupts. */ 1382 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1383 1384 /* Accept VLAN length packets */ 1385 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1386 1387 ste_ifmedia_upd(ifp); 1388 1389 ifp->if_flags |= IFF_RUNNING; 1390 ifp->if_flags &= ~IFF_OACTIVE; 1391 1392 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1393 STE_UNLOCK(sc); 1394 1395 return; 1396} 1397 1398static void 1399ste_stop(sc) 1400 struct ste_softc *sc; 1401{ 1402 int i; 1403 struct ifnet *ifp; 1404 1405 STE_LOCK(sc); 1406 ifp = &sc->arpcom.ac_if; 1407 1408 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1409 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1410#ifdef DEVICE_POLLING 1411 ether_poll_deregister(ifp); 1412#endif /* DEVICE_POLLING */ 1413 1414 CSR_WRITE_2(sc, STE_IMR, 0); 1415 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1416 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1417 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1418 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1419 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1420 ste_wait(sc); 1421 /* 1422 * Try really hard to stop the RX engine or under heavy RX 1423 * data chip will write into de-allocated memory. 1424 */ 1425 ste_reset(sc); 1426 1427 sc->ste_link = 0; 1428 1429 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1430 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1431 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1432 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1433 } 1434 } 1435 1436 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1437 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1438 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1439 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1440 } 1441 } 1442 1443 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1444 STE_UNLOCK(sc); 1445 1446 return; 1447} 1448 1449static void 1450ste_reset(sc) 1451 struct ste_softc *sc; 1452{ 1453 int i; 1454 1455 STE_SETBIT4(sc, STE_ASICCTL, 1456 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1457 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1458 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1459 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1460 STE_ASICCTL_EXTRESET_RESET); 1461 1462 DELAY(100000); 1463 1464 for (i = 0; i < STE_TIMEOUT; i++) { 1465 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1466 break; 1467 } 1468 1469 if (i == STE_TIMEOUT) 1470 printf("ste%d: global reset never completed\n", sc->ste_unit); 1471 1472 return; 1473} 1474 1475static int 1476ste_ioctl(ifp, command, data) 1477 struct ifnet *ifp; 1478 u_long command; 1479 caddr_t data; 1480{ 1481 struct ste_softc *sc; 1482 struct ifreq *ifr; 1483 struct mii_data *mii; 1484 int error = 0; 1485 1486 sc = ifp->if_softc; 1487 STE_LOCK(sc); 1488 ifr = (struct ifreq *)data; 1489 1490 switch(command) { 1491 case SIOCSIFFLAGS: 1492 if (ifp->if_flags & IFF_UP) { 1493 if (ifp->if_flags & IFF_RUNNING && 1494 ifp->if_flags & IFF_PROMISC && 1495 !(sc->ste_if_flags & IFF_PROMISC)) { 1496 STE_SETBIT1(sc, STE_RX_MODE, 1497 STE_RXMODE_PROMISC); 1498 } else if (ifp->if_flags & IFF_RUNNING && 1499 !(ifp->if_flags & IFF_PROMISC) && 1500 sc->ste_if_flags & IFF_PROMISC) { 1501 STE_CLRBIT1(sc, STE_RX_MODE, 1502 STE_RXMODE_PROMISC); 1503 } 1504 if (ifp->if_flags & IFF_RUNNING && 1505 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1506 ste_setmulti(sc); 1507 if (!(ifp->if_flags & IFF_RUNNING)) { 1508 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1509 ste_init(sc); 1510 } 1511 } else { 1512 if (ifp->if_flags & IFF_RUNNING) 1513 ste_stop(sc); 1514 } 1515 sc->ste_if_flags = ifp->if_flags; 1516 error = 0; 1517 break; 1518 case SIOCADDMULTI: 1519 case SIOCDELMULTI: 1520 ste_setmulti(sc); 1521 error = 0; 1522 break; 1523 case SIOCGIFMEDIA: 1524 case SIOCSIFMEDIA: 1525 mii = device_get_softc(sc->ste_miibus); 1526 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1527 break; 1528 default: 1529 error = ether_ioctl(ifp, command, data); 1530 break; 1531 } 1532 1533 STE_UNLOCK(sc); 1534 1535 return(error); 1536} 1537 1538static int 1539ste_encap(sc, c, m_head) 1540 struct ste_softc *sc; 1541 struct ste_chain *c; 1542 struct mbuf *m_head; 1543{ 1544 int frag = 0; 1545 struct ste_frag *f = NULL; 1546 struct mbuf *m; 1547 struct ste_desc *d; 1548 1549 d = c->ste_ptr; 1550 d->ste_ctl = 0; 1551 1552encap_retry: 1553 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1554 if (m->m_len != 0) { 1555 if (frag == STE_MAXFRAGS) 1556 break; 1557 f = &d->ste_frags[frag]; 1558 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1559 f->ste_len = m->m_len; 1560 frag++; 1561 } 1562 } 1563 1564 if (m != NULL) { 1565 struct mbuf *mn; 1566 1567 /* 1568 * We ran out of segments. We have to recopy this 1569 * mbuf chain first. Bail out if we can't get the 1570 * new buffers. 1571 */ 1572 mn = m_defrag(m_head, M_DONTWAIT); 1573 if (mn == NULL) { 1574 m_freem(m_head); 1575 return ENOMEM; 1576 } 1577 m_head = mn; 1578 goto encap_retry; 1579 } 1580 1581 c->ste_mbuf = m_head; 1582 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1583 d->ste_ctl = 1; 1584 1585 return(0); 1586} 1587 1588static void 1589ste_start(ifp) 1590 struct ifnet *ifp; 1591{ 1592 struct ste_softc *sc; 1593 struct mbuf *m_head = NULL; 1594 struct ste_chain *cur_tx = NULL; 1595 int idx; 1596 1597 sc = ifp->if_softc; 1598 STE_LOCK(sc); 1599 1600 if (!sc->ste_link) { 1601 STE_UNLOCK(sc); 1602 return; 1603 } 1604 1605 if (ifp->if_flags & IFF_OACTIVE) { 1606 STE_UNLOCK(sc); 1607 return; 1608 } 1609 1610 idx = sc->ste_cdata.ste_tx_prod; 1611 1612 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1613 1614 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1615 ifp->if_flags |= IFF_OACTIVE; 1616 break; 1617 } 1618 1619 IF_DEQUEUE(&ifp->if_snd, m_head); 1620 if (m_head == NULL) 1621 break; 1622 1623 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1624 1625 if (ste_encap(sc, cur_tx, m_head) != 0) 1626 break; 1627 1628 cur_tx->ste_ptr->ste_next = 0; 1629 1630 if(sc->ste_tx_prev_idx < 0){ 1631 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1632 /* Load address of the TX list */ 1633 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1634 ste_wait(sc); 1635 1636 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1637 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1638 1639 /* Set TX polling interval to start TX engine */ 1640 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1641 1642 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1643 ste_wait(sc); 1644 }else{ 1645 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1646 sc->ste_cdata.ste_tx_chain[ 1647 sc->ste_tx_prev_idx].ste_ptr->ste_next 1648 = cur_tx->ste_phys; 1649 } 1650 1651 sc->ste_tx_prev_idx=idx; 1652 1653 /* 1654 * If there's a BPF listener, bounce a copy of this frame 1655 * to him. 1656 */ 1657 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1658 1659 STE_INC(idx, STE_TX_LIST_CNT); 1660 sc->ste_cdata.ste_tx_cnt++; 1661 ifp->if_timer = 5; 1662 sc->ste_cdata.ste_tx_prod = idx; 1663 } 1664 1665 STE_UNLOCK(sc); 1666 1667 return; 1668} 1669 1670static void 1671ste_watchdog(ifp) 1672 struct ifnet *ifp; 1673{ 1674 struct ste_softc *sc; 1675 1676 sc = ifp->if_softc; 1677 STE_LOCK(sc); 1678 1679 ifp->if_oerrors++; 1680 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1681 1682 ste_txeoc(sc); 1683 ste_txeof(sc); 1684 ste_rxeof(sc); 1685 ste_reset(sc); 1686 ste_init(sc); 1687 1688 if (ifp->if_snd.ifq_head != NULL) 1689 ste_start(ifp); 1690 STE_UNLOCK(sc); 1691 1692 return; 1693} 1694 1695static void 1696ste_shutdown(dev) 1697 device_t dev; 1698{ 1699 struct ste_softc *sc; 1700 1701 sc = device_get_softc(dev); 1702 1703 ste_stop(sc); 1704 1705 return; 1706} 1707