if_ste.c revision 126966
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 126966 2004-03-14 07:12:25Z mdodd $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_vlan_var.h> 50 51#include <net/bpf.h> 52 53#include <vm/vm.h> /* for vtophys */ 54#include <vm/pmap.h> /* for vtophys */ 55#include <machine/bus_memio.h> 56#include <machine/bus_pio.h> 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/bus.h> 60#include <sys/rman.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68/* "controller miibus0" required. See GENERIC if you get errors here. */ 69#include "miibus_if.h" 70 71#define STE_USEIOSPACE 72 73#include <pci/if_stereg.h> 74 75MODULE_DEPEND(ste, pci, 1, 1, 1); 76MODULE_DEPEND(ste, ether, 1, 1, 1); 77MODULE_DEPEND(ste, miibus, 1, 1, 1); 78 79/* 80 * Various supported device vendors/types and their names. 81 */ 82static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 85 { 0, 0, NULL } 86}; 87 88static int ste_probe (device_t); 89static int ste_attach (device_t); 90static int ste_detach (device_t); 91static void ste_init (void *); 92static void ste_intr (void *); 93static void ste_rxeof (struct ste_softc *); 94static void ste_txeoc (struct ste_softc *); 95static void ste_txeof (struct ste_softc *); 96static void ste_stats_update (void *); 97static void ste_stop (struct ste_softc *); 98static void ste_reset (struct ste_softc *); 99static int ste_ioctl (struct ifnet *, u_long, caddr_t); 100static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102static void ste_start (struct ifnet *); 103static void ste_watchdog (struct ifnet *); 104static void ste_shutdown (device_t); 105static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108static int ste_ifmedia_upd (struct ifnet *); 109static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111static void ste_mii_sync (struct ste_softc *); 112static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 114static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 115static int ste_miibus_readreg (device_t, int, int); 116static int ste_miibus_writereg (device_t, int, int, int); 117static void ste_miibus_statchg (device_t); 118 119static int ste_eeprom_wait (struct ste_softc *); 120static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 121static void ste_wait (struct ste_softc *); 122static u_int8_t ste_calchash (caddr_t); 123static void ste_setmulti (struct ste_softc *); 124static int ste_init_rx_list (struct ste_softc *); 125static void ste_init_tx_list (struct ste_softc *); 126 127#ifdef STE_USEIOSPACE 128#define STE_RES SYS_RES_IOPORT 129#define STE_RID STE_PCI_LOIO 130#else 131#define STE_RES SYS_RES_MEMORY 132#define STE_RID STE_PCI_LOMEM 133#endif 134 135static device_method_t ste_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ste_probe), 138 DEVMETHOD(device_attach, ste_attach), 139 DEVMETHOD(device_detach, ste_detach), 140 DEVMETHOD(device_shutdown, ste_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 150 151 { 0, 0 } 152}; 153 154static driver_t ste_driver = { 155 "ste", 156 ste_methods, 157 sizeof(struct ste_softc) 158}; 159 160static devclass_t ste_devclass; 161 162DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 163DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 164 165#define STE_SETBIT4(sc, reg, x) \ 166 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 167 168#define STE_CLRBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 170 171#define STE_SETBIT2(sc, reg, x) \ 172 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 173 174#define STE_CLRBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 176 177#define STE_SETBIT1(sc, reg, x) \ 178 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 179 180#define STE_CLRBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 182 183 184#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 185#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 186 187/* 188 * Sync the PHYs by setting data bit and strobing the clock 32 times. 189 */ 190static void 191ste_mii_sync(sc) 192 struct ste_softc *sc; 193{ 194 register int i; 195 196 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 197 198 for (i = 0; i < 32; i++) { 199 MII_SET(STE_PHYCTL_MCLK); 200 DELAY(1); 201 MII_CLR(STE_PHYCTL_MCLK); 202 DELAY(1); 203 } 204 205 return; 206} 207 208/* 209 * Clock a series of bits through the MII. 210 */ 211static void 212ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216{ 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232} 233 234/* 235 * Read an PHY register through the MII. 236 */ 237static int 238ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242{ 243 int i, ack; 244 245 STE_LOCK(sc); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 STE_UNLOCK(sc); 321 322 if (ack) 323 return(1); 324 return(0); 325} 326 327/* 328 * Write to a PHY register through the MII. 329 */ 330static int 331ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335{ 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374} 375 376static int 377ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396} 397 398static int 399ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402{ 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416} 417 418static void 419ste_miibus_statchg(dev) 420 device_t dev; 421{ 422 struct ste_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 STE_LOCK(sc); 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 STE_UNLOCK(sc); 435 436 return; 437} 438 439static int 440ste_ifmedia_upd(ifp) 441 struct ifnet *ifp; 442{ 443 struct ste_softc *sc; 444 struct mii_data *mii; 445 446 sc = ifp->if_softc; 447 mii = device_get_softc(sc->ste_miibus); 448 sc->ste_link = 0; 449 if (mii->mii_instance) { 450 struct mii_softc *miisc; 451 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 452 mii_phy_reset(miisc); 453 } 454 mii_mediachg(mii); 455 456 return(0); 457} 458 459static void 460ste_ifmedia_sts(ifp, ifmr) 461 struct ifnet *ifp; 462 struct ifmediareq *ifmr; 463{ 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->ste_miibus); 469 470 mii_pollstat(mii); 471 ifmr->ifm_active = mii->mii_media_active; 472 ifmr->ifm_status = mii->mii_media_status; 473 474 return; 475} 476 477static void 478ste_wait(sc) 479 struct ste_softc *sc; 480{ 481 register int i; 482 483 for (i = 0; i < STE_TIMEOUT; i++) { 484 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 485 break; 486 } 487 488 if (i == STE_TIMEOUT) 489 printf("ste%d: command never completed!\n", sc->ste_unit); 490 491 return; 492} 493 494/* 495 * The EEPROM is slow: give it time to come ready after issuing 496 * it a command. 497 */ 498static int 499ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501{ 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 515 return(1); 516 } 517 518 return(0); 519} 520 521/* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525static int 526ste_read_eeprom(sc, dest, off, cnt, swap) 527 struct ste_softc *sc; 528 caddr_t dest; 529 int off; 530 int cnt; 531 int swap; 532{ 533 int err = 0, i; 534 u_int16_t word = 0, *ptr; 535 536 if (ste_eeprom_wait(sc)) 537 return(1); 538 539 for (i = 0; i < cnt; i++) { 540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 541 err = ste_eeprom_wait(sc); 542 if (err) 543 break; 544 word = CSR_READ_2(sc, STE_EEPROM_DATA); 545 ptr = (u_int16_t *)(dest + (i * 2)); 546 if (swap) 547 *ptr = ntohs(word); 548 else 549 *ptr = word; 550 } 551 552 return(err ? 1 : 0); 553} 554 555static u_int8_t 556ste_calchash(addr) 557 caddr_t addr; 558{ 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580} 581 582static void 583ste_setmulti(sc) 584 struct ste_softc *sc; 585{ 586 struct ifnet *ifp; 587 int h = 0; 588 u_int32_t hashes[2] = { 0, 0 }; 589 struct ifmultiaddr *ifma; 590 591 ifp = &sc->arpcom.ac_if; 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 594 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 595 return; 596 } 597 598 /* first, zot all the existing hash bits */ 599 CSR_WRITE_2(sc, STE_MAR0, 0); 600 CSR_WRITE_2(sc, STE_MAR1, 0); 601 CSR_WRITE_2(sc, STE_MAR2, 0); 602 CSR_WRITE_2(sc, STE_MAR3, 0); 603 604 /* now program new ones */ 605 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623} 624 625static void 626ste_intr(xsc) 627 void *xsc; 628{ 629 struct ste_softc *sc; 630 struct ifnet *ifp; 631 u_int16_t status; 632 633 sc = xsc; 634 STE_LOCK(sc); 635 ifp = &sc->arpcom.ac_if; 636 637 /* See if this is really our interrupt. */ 638 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 639 STE_UNLOCK(sc); 640 return; 641 } 642 643 for (;;) { 644 status = CSR_READ_2(sc, STE_ISR_ACK); 645 646 if (!(status & STE_INTRS)) 647 break; 648 649 if (status & STE_ISR_RX_DMADONE) 650 ste_rxeof(sc); 651 652 if (status & STE_ISR_TX_DMADONE) 653 ste_txeof(sc); 654 655 if (status & STE_ISR_TX_DONE) 656 ste_txeoc(sc); 657 658 if (status & STE_ISR_STATS_OFLOW) { 659 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 660 ste_stats_update(sc); 661 } 662 663 if (status & STE_ISR_LINKEVENT) 664 mii_pollstat(device_get_softc(sc->ste_miibus)); 665 666 667 if (status & STE_ISR_HOSTERR) { 668 ste_reset(sc); 669 ste_init(sc); 670 } 671 } 672 673 /* Re-enable interrupts */ 674 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 675 676 if (ifp->if_snd.ifq_head != NULL) 677 ste_start(ifp); 678 679 STE_UNLOCK(sc); 680 681 return; 682} 683 684/* 685 * A frame has been uploaded: pass the resulting mbuf chain up to 686 * the higher level protocols. 687 */ 688static void 689ste_rxeof(sc) 690 struct ste_softc *sc; 691{ 692 struct mbuf *m; 693 struct ifnet *ifp; 694 struct ste_chain_onefrag *cur_rx; 695 int total_len = 0, count=0; 696 u_int32_t rxstat; 697 698 STE_LOCK_ASSERT(sc); 699 700 ifp = &sc->arpcom.ac_if; 701 702 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 703 & STE_RXSTAT_DMADONE) { 704 if ((STE_RX_LIST_CNT - count) < 3) { 705 break; 706 } 707 708 cur_rx = sc->ste_cdata.ste_rx_head; 709 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 710 711 /* 712 * If an error occurs, update stats, clear the 713 * status word and leave the mbuf cluster in place: 714 * it should simply get re-used next time this descriptor 715 * comes up in the ring. 716 */ 717 if (rxstat & STE_RXSTAT_FRAME_ERR) { 718 ifp->if_ierrors++; 719 cur_rx->ste_ptr->ste_status = 0; 720 continue; 721 } 722 723 /* 724 * If there error bit was not set, the upload complete 725 * bit should be set which means we have a valid packet. 726 * If not, something truly strange has happened. 727 */ 728 if (!(rxstat & STE_RXSTAT_DMADONE)) { 729 printf("ste%d: bad receive status -- packet dropped\n", 730 sc->ste_unit); 731 ifp->if_ierrors++; 732 cur_rx->ste_ptr->ste_status = 0; 733 continue; 734 } 735 736 /* No errors; receive the packet. */ 737 m = cur_rx->ste_mbuf; 738 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 739 740 /* 741 * Try to conjure up a new mbuf cluster. If that 742 * fails, it means we have an out of memory condition and 743 * should leave the buffer in place and continue. This will 744 * result in a lost packet, but there's little else we 745 * can do in this situation. 746 */ 747 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 748 ifp->if_ierrors++; 749 cur_rx->ste_ptr->ste_status = 0; 750 continue; 751 } 752 753 m->m_pkthdr.rcvif = ifp; 754 m->m_pkthdr.len = m->m_len = total_len; 755 756 ifp->if_ipackets++; 757 STE_UNLOCK(sc); 758 (*ifp->if_input)(ifp, m); 759 STE_LOCK(sc); 760 761 cur_rx->ste_ptr->ste_status = 0; 762 count++; 763 } 764 765 return; 766} 767 768static void 769ste_txeoc(sc) 770 struct ste_softc *sc; 771{ 772 u_int8_t txstat; 773 struct ifnet *ifp; 774 775 ifp = &sc->arpcom.ac_if; 776 777 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 778 STE_TXSTATUS_TXDONE) { 779 if (txstat & STE_TXSTATUS_UNDERRUN || 780 txstat & STE_TXSTATUS_EXCESSCOLLS || 781 txstat & STE_TXSTATUS_RECLAIMERR) { 782 ifp->if_oerrors++; 783 printf("ste%d: transmission error: %x\n", 784 sc->ste_unit, txstat); 785 786 ste_reset(sc); 787 ste_init(sc); 788 789 if (txstat & STE_TXSTATUS_UNDERRUN && 790 sc->ste_tx_thresh < STE_PACKET_SIZE) { 791 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 792 printf("ste%d: tx underrun, increasing tx" 793 " start threshold to %d bytes\n", 794 sc->ste_unit, sc->ste_tx_thresh); 795 } 796 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 797 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 798 (STE_PACKET_SIZE >> 4)); 799 } 800 ste_init(sc); 801 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 802 } 803 804 return; 805} 806 807static void 808ste_txeof(sc) 809 struct ste_softc *sc; 810{ 811 struct ste_chain *cur_tx = NULL; 812 struct ifnet *ifp; 813 int idx; 814 815 ifp = &sc->arpcom.ac_if; 816 817 idx = sc->ste_cdata.ste_tx_cons; 818 while(idx != sc->ste_cdata.ste_tx_prod) { 819 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 820 821 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 822 break; 823 824 if (cur_tx->ste_mbuf != NULL) { 825 m_freem(cur_tx->ste_mbuf); 826 cur_tx->ste_mbuf = NULL; 827 } 828 829 ifp->if_opackets++; 830 831 sc->ste_cdata.ste_tx_cnt--; 832 STE_INC(idx, STE_TX_LIST_CNT); 833 ifp->if_timer = 0; 834 } 835 836 sc->ste_cdata.ste_tx_cons = idx; 837 838 if (cur_tx != NULL) 839 ifp->if_flags &= ~IFF_OACTIVE; 840 841 return; 842} 843 844static void 845ste_stats_update(xsc) 846 void *xsc; 847{ 848 struct ste_softc *sc; 849 struct ifnet *ifp; 850 struct mii_data *mii; 851 852 sc = xsc; 853 STE_LOCK(sc); 854 855 ifp = &sc->arpcom.ac_if; 856 mii = device_get_softc(sc->ste_miibus); 857 858 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 859 + CSR_READ_1(sc, STE_MULTI_COLLS) 860 + CSR_READ_1(sc, STE_SINGLE_COLLS); 861 862 if (!sc->ste_link) { 863 mii_pollstat(mii); 864 if (mii->mii_media_status & IFM_ACTIVE && 865 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 866 sc->ste_link++; 867 /* 868 * we don't get a call-back on re-init so do it 869 * otherwise we get stuck in the wrong link state 870 */ 871 ste_miibus_statchg(sc->ste_dev); 872 if (ifp->if_snd.ifq_head != NULL) 873 ste_start(ifp); 874 } 875 } 876 877 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 878 STE_UNLOCK(sc); 879 880 return; 881} 882 883 884/* 885 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 886 * IDs against our list and return a device name if we find a match. 887 */ 888static int 889ste_probe(dev) 890 device_t dev; 891{ 892 struct ste_type *t; 893 894 t = ste_devs; 895 896 while(t->ste_name != NULL) { 897 if ((pci_get_vendor(dev) == t->ste_vid) && 898 (pci_get_device(dev) == t->ste_did)) { 899 device_set_desc(dev, t->ste_name); 900 return(0); 901 } 902 t++; 903 } 904 905 return(ENXIO); 906} 907 908/* 909 * Attach the interface. Allocate softc structures, do ifmedia 910 * setup and ethernet/BPF attach. 911 */ 912static int 913ste_attach(dev) 914 device_t dev; 915{ 916 struct ste_softc *sc; 917 struct ifnet *ifp; 918 int unit, error = 0, rid; 919 920 sc = device_get_softc(dev); 921 unit = device_get_unit(dev); 922 sc->ste_dev = dev; 923 924 /* 925 * Only use one PHY since this chip reports multiple 926 * Note on the DFE-550 the PHY is at 1 on the DFE-580 927 * it is at 0 & 1. It is rev 0x12. 928 */ 929 if (pci_get_vendor(dev) == DL_VENDORID && 930 pci_get_device(dev) == DL_DEVICEID_DL10050 && 931 pci_get_revid(dev) == 0x12 ) 932 sc->ste_one_phy = 1; 933 934 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 935 MTX_DEF | MTX_RECURSE); 936#ifndef BURN_BRIDGES 937 /* 938 * Handle power management nonsense. 939 */ 940 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 941 u_int32_t iobase, membase, irq; 942 943 /* Save important PCI config data. */ 944 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 945 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 946 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 947 948 /* Reset the power state. */ 949 printf("ste%d: chip is in D%d power mode " 950 "-- setting to D0\n", unit, 951 pci_get_powerstate(dev)); 952 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 953 954 /* Restore PCI config data. */ 955 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 956 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 957 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 958 } 959#endif 960 /* 961 * Map control/status registers. 962 */ 963 pci_enable_busmaster(dev); 964 965 rid = STE_RID; 966 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 967 0, ~0, 1, RF_ACTIVE); 968 969 if (sc->ste_res == NULL) { 970 printf ("ste%d: couldn't map ports/memory\n", unit); 971 error = ENXIO; 972 goto fail; 973 } 974 975 sc->ste_btag = rman_get_bustag(sc->ste_res); 976 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 977 978 /* Allocate interrupt */ 979 rid = 0; 980 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 981 RF_SHAREABLE | RF_ACTIVE); 982 983 if (sc->ste_irq == NULL) { 984 printf("ste%d: couldn't map interrupt\n", unit); 985 error = ENXIO; 986 goto fail; 987 } 988 989 callout_handle_init(&sc->ste_stat_ch); 990 991 /* Reset the adapter. */ 992 ste_reset(sc); 993 994 /* 995 * Get station address from the EEPROM. 996 */ 997 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 998 STE_EEADDR_NODE0, 3, 0)) { 999 printf("ste%d: failed to read station address\n", unit); 1000 error = ENXIO;; 1001 goto fail; 1002 } 1003 1004 sc->ste_unit = unit; 1005 1006 /* Allocate the descriptor queues. */ 1007 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1008 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1009 1010 if (sc->ste_ldata == NULL) { 1011 printf("ste%d: no memory for list buffers!\n", unit); 1012 error = ENXIO; 1013 goto fail; 1014 } 1015 1016 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1017 1018 /* Do MII setup. */ 1019 if (mii_phy_probe(dev, &sc->ste_miibus, 1020 ste_ifmedia_upd, ste_ifmedia_sts)) { 1021 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1022 error = ENXIO; 1023 goto fail; 1024 } 1025 1026 ifp = &sc->arpcom.ac_if; 1027 ifp->if_softc = sc; 1028 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1029 ifp->if_mtu = ETHERMTU; 1030 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1031 ifp->if_ioctl = ste_ioctl; 1032 ifp->if_start = ste_start; 1033 ifp->if_watchdog = ste_watchdog; 1034 ifp->if_init = ste_init; 1035 ifp->if_baudrate = 10000000; 1036 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1037 1038 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1039 1040 /* 1041 * Call MI attach routine. 1042 */ 1043 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1044 1045 /* 1046 * Tell the upper layer(s) we support long frames. 1047 */ 1048 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1049 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1050 1051 /* Hook interrupt last to avoid having to lock softc */ 1052 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1053 ste_intr, sc, &sc->ste_intrhand); 1054 1055 if (error) { 1056 printf("ste%d: couldn't set up irq\n", unit); 1057 ether_ifdetach(ifp); 1058 goto fail; 1059 } 1060 1061fail: 1062 if (error) 1063 ste_detach(dev); 1064 1065 return(error); 1066} 1067 1068/* 1069 * Shutdown hardware and free up resources. This can be called any 1070 * time after the mutex has been initialized. It is called in both 1071 * the error case in attach and the normal detach case so it needs 1072 * to be careful about only freeing resources that have actually been 1073 * allocated. 1074 */ 1075static int 1076ste_detach(dev) 1077 device_t dev; 1078{ 1079 struct ste_softc *sc; 1080 struct ifnet *ifp; 1081 1082 sc = device_get_softc(dev); 1083 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1084 STE_LOCK(sc); 1085 ifp = &sc->arpcom.ac_if; 1086 1087 /* These should only be active if attach succeeded */ 1088 if (device_is_attached(dev)) { 1089 ste_stop(sc); 1090 ether_ifdetach(ifp); 1091 } 1092 if (sc->ste_miibus) 1093 device_delete_child(dev, sc->ste_miibus); 1094 bus_generic_detach(dev); 1095 1096 if (sc->ste_intrhand) 1097 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1098 if (sc->ste_irq) 1099 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1100 if (sc->ste_res) 1101 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1102 1103 if (sc->ste_ldata) { 1104 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1105 M_DEVBUF); 1106 } 1107 1108 STE_UNLOCK(sc); 1109 mtx_destroy(&sc->ste_mtx); 1110 1111 return(0); 1112} 1113 1114static int 1115ste_newbuf(sc, c, m) 1116 struct ste_softc *sc; 1117 struct ste_chain_onefrag *c; 1118 struct mbuf *m; 1119{ 1120 struct mbuf *m_new = NULL; 1121 1122 if (m == NULL) { 1123 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1124 if (m_new == NULL) 1125 return(ENOBUFS); 1126 MCLGET(m_new, M_DONTWAIT); 1127 if (!(m_new->m_flags & M_EXT)) { 1128 m_freem(m_new); 1129 return(ENOBUFS); 1130 } 1131 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1132 } else { 1133 m_new = m; 1134 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1135 m_new->m_data = m_new->m_ext.ext_buf; 1136 } 1137 1138 m_adj(m_new, ETHER_ALIGN); 1139 1140 c->ste_mbuf = m_new; 1141 c->ste_ptr->ste_status = 0; 1142 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1143 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1144 1145 return(0); 1146} 1147 1148static int 1149ste_init_rx_list(sc) 1150 struct ste_softc *sc; 1151{ 1152 struct ste_chain_data *cd; 1153 struct ste_list_data *ld; 1154 int i; 1155 1156 cd = &sc->ste_cdata; 1157 ld = sc->ste_ldata; 1158 1159 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1160 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1161 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1162 return(ENOBUFS); 1163 if (i == (STE_RX_LIST_CNT - 1)) { 1164 cd->ste_rx_chain[i].ste_next = 1165 &cd->ste_rx_chain[0]; 1166 ld->ste_rx_list[i].ste_next = 1167 vtophys(&ld->ste_rx_list[0]); 1168 } else { 1169 cd->ste_rx_chain[i].ste_next = 1170 &cd->ste_rx_chain[i + 1]; 1171 ld->ste_rx_list[i].ste_next = 1172 vtophys(&ld->ste_rx_list[i + 1]); 1173 } 1174 ld->ste_rx_list[i].ste_status = 0; 1175 } 1176 1177 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1178 1179 return(0); 1180} 1181 1182static void 1183ste_init_tx_list(sc) 1184 struct ste_softc *sc; 1185{ 1186 struct ste_chain_data *cd; 1187 struct ste_list_data *ld; 1188 int i; 1189 1190 cd = &sc->ste_cdata; 1191 ld = sc->ste_ldata; 1192 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1193 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1194 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1195 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1196 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1197 if (i == (STE_TX_LIST_CNT - 1)) 1198 cd->ste_tx_chain[i].ste_next = 1199 &cd->ste_tx_chain[0]; 1200 else 1201 cd->ste_tx_chain[i].ste_next = 1202 &cd->ste_tx_chain[i + 1]; 1203 if (i == 0) 1204 cd->ste_tx_chain[i].ste_prev = 1205 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1206 else 1207 cd->ste_tx_chain[i].ste_prev = 1208 &cd->ste_tx_chain[i - 1]; 1209 } 1210 1211 cd->ste_tx_prod = 0; 1212 cd->ste_tx_cons = 0; 1213 cd->ste_tx_cnt = 0; 1214 1215 return; 1216} 1217 1218static void 1219ste_init(xsc) 1220 void *xsc; 1221{ 1222 struct ste_softc *sc; 1223 int i; 1224 struct ifnet *ifp; 1225 1226 sc = xsc; 1227 STE_LOCK(sc); 1228 ifp = &sc->arpcom.ac_if; 1229 1230 ste_stop(sc); 1231 1232 /* Init our MAC address */ 1233 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1234 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1235 } 1236 1237 /* Init RX list */ 1238 if (ste_init_rx_list(sc) == ENOBUFS) { 1239 printf("ste%d: initialization failed: no " 1240 "memory for RX buffers\n", sc->ste_unit); 1241 ste_stop(sc); 1242 STE_UNLOCK(sc); 1243 return; 1244 } 1245 1246 /* Set RX polling interval */ 1247 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1248 1249 /* Init TX descriptors */ 1250 ste_init_tx_list(sc); 1251 1252 /* Set the TX freethresh value */ 1253 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1254 1255 /* Set the TX start threshold for best performance. */ 1256 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1257 1258 /* Set the TX reclaim threshold. */ 1259 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1260 1261 /* Set up the RX filter. */ 1262 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1263 1264 /* If we want promiscuous mode, set the allframes bit. */ 1265 if (ifp->if_flags & IFF_PROMISC) { 1266 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1267 } else { 1268 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1269 } 1270 1271 /* Set capture broadcast bit to accept broadcast frames. */ 1272 if (ifp->if_flags & IFF_BROADCAST) { 1273 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1274 } else { 1275 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1276 } 1277 1278 ste_setmulti(sc); 1279 1280 /* Load the address of the RX list. */ 1281 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1282 ste_wait(sc); 1283 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1284 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1286 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1287 1288 /* Set TX polling interval (defer until we TX first packet */ 1289 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1290 1291 /* Load address of the TX list */ 1292 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1293 ste_wait(sc); 1294 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1296 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1297 ste_wait(sc); 1298 sc->ste_tx_prev_idx=-1; 1299 1300 /* Enable receiver and transmitter */ 1301 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1302 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1303 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1304 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1305 1306 /* Enable stats counters. */ 1307 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1308 1309 /* Enable interrupts. */ 1310 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1311 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1312 1313 /* Accept VLAN length packets */ 1314 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1315 1316 ste_ifmedia_upd(ifp); 1317 1318 ifp->if_flags |= IFF_RUNNING; 1319 ifp->if_flags &= ~IFF_OACTIVE; 1320 1321 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1322 STE_UNLOCK(sc); 1323 1324 return; 1325} 1326 1327static void 1328ste_stop(sc) 1329 struct ste_softc *sc; 1330{ 1331 int i; 1332 struct ifnet *ifp; 1333 1334 STE_LOCK(sc); 1335 ifp = &sc->arpcom.ac_if; 1336 1337 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1338 1339 CSR_WRITE_2(sc, STE_IMR, 0); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1341 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1342 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1343 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1344 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1345 ste_wait(sc); 1346 /* 1347 * Try really hard to stop the RX engine or under heavy RX 1348 * data chip will write into de-allocated memory. 1349 */ 1350 ste_reset(sc); 1351 1352 sc->ste_link = 0; 1353 1354 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1355 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1356 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1357 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1358 } 1359 } 1360 1361 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1362 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1363 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1364 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1365 } 1366 } 1367 1368 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1369 1370 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1371 STE_UNLOCK(sc); 1372 1373 return; 1374} 1375 1376static void 1377ste_reset(sc) 1378 struct ste_softc *sc; 1379{ 1380 int i; 1381 1382 STE_SETBIT4(sc, STE_ASICCTL, 1383 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1384 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1385 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1386 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1387 STE_ASICCTL_EXTRESET_RESET); 1388 1389 DELAY(100000); 1390 1391 for (i = 0; i < STE_TIMEOUT; i++) { 1392 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1393 break; 1394 } 1395 1396 if (i == STE_TIMEOUT) 1397 printf("ste%d: global reset never completed\n", sc->ste_unit); 1398 1399 return; 1400} 1401 1402static int 1403ste_ioctl(ifp, command, data) 1404 struct ifnet *ifp; 1405 u_long command; 1406 caddr_t data; 1407{ 1408 struct ste_softc *sc; 1409 struct ifreq *ifr; 1410 struct mii_data *mii; 1411 int error = 0; 1412 1413 sc = ifp->if_softc; 1414 STE_LOCK(sc); 1415 ifr = (struct ifreq *)data; 1416 1417 switch(command) { 1418 case SIOCSIFFLAGS: 1419 if (ifp->if_flags & IFF_UP) { 1420 if (ifp->if_flags & IFF_RUNNING && 1421 ifp->if_flags & IFF_PROMISC && 1422 !(sc->ste_if_flags & IFF_PROMISC)) { 1423 STE_SETBIT1(sc, STE_RX_MODE, 1424 STE_RXMODE_PROMISC); 1425 } else if (ifp->if_flags & IFF_RUNNING && 1426 !(ifp->if_flags & IFF_PROMISC) && 1427 sc->ste_if_flags & IFF_PROMISC) { 1428 STE_CLRBIT1(sc, STE_RX_MODE, 1429 STE_RXMODE_PROMISC); 1430 } 1431 if (!(ifp->if_flags & IFF_RUNNING)) { 1432 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1433 ste_init(sc); 1434 } 1435 } else { 1436 if (ifp->if_flags & IFF_RUNNING) 1437 ste_stop(sc); 1438 } 1439 sc->ste_if_flags = ifp->if_flags; 1440 error = 0; 1441 break; 1442 case SIOCADDMULTI: 1443 case SIOCDELMULTI: 1444 ste_setmulti(sc); 1445 error = 0; 1446 break; 1447 case SIOCGIFMEDIA: 1448 case SIOCSIFMEDIA: 1449 mii = device_get_softc(sc->ste_miibus); 1450 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1451 break; 1452 default: 1453 error = ether_ioctl(ifp, command, data); 1454 break; 1455 } 1456 1457 STE_UNLOCK(sc); 1458 1459 return(error); 1460} 1461 1462static int 1463ste_encap(sc, c, m_head) 1464 struct ste_softc *sc; 1465 struct ste_chain *c; 1466 struct mbuf *m_head; 1467{ 1468 int frag = 0; 1469 struct ste_frag *f = NULL; 1470 struct mbuf *m; 1471 struct ste_desc *d; 1472 1473 d = c->ste_ptr; 1474 d->ste_ctl = 0; 1475 1476encap_retry: 1477 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1478 if (m->m_len != 0) { 1479 if (frag == STE_MAXFRAGS) 1480 break; 1481 f = &d->ste_frags[frag]; 1482 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1483 f->ste_len = m->m_len; 1484 frag++; 1485 } 1486 } 1487 1488 if (m != NULL) { 1489 struct mbuf *mn; 1490 1491 /* 1492 * We ran out of segments. We have to recopy this 1493 * mbuf chain first. Bail out if we can't get the 1494 * new buffers. Code borrowed from if_fxp.c 1495 */ 1496 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1497 if (mn == NULL) { 1498 m_freem(m_head); 1499 return ENOMEM; 1500 } 1501 if (m_head->m_pkthdr.len > MHLEN) { 1502 MCLGET(mn, M_DONTWAIT); 1503 if ((mn->m_flags & M_EXT) == 0) { 1504 m_freem(mn); 1505 m_freem(m_head); 1506 return ENOMEM; 1507 } 1508 } 1509 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1510 mtod(mn, caddr_t)); 1511 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1512 m_freem(m_head); 1513 m_head = mn; 1514 goto encap_retry; 1515 } 1516 1517 c->ste_mbuf = m_head; 1518 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1519 d->ste_ctl = 1; 1520 1521 return(0); 1522} 1523 1524static void 1525ste_start(ifp) 1526 struct ifnet *ifp; 1527{ 1528 struct ste_softc *sc; 1529 struct mbuf *m_head = NULL; 1530 struct ste_chain *cur_tx = NULL; 1531 int idx; 1532 1533 sc = ifp->if_softc; 1534 STE_LOCK(sc); 1535 1536 if (!sc->ste_link) { 1537 STE_UNLOCK(sc); 1538 return; 1539 } 1540 1541 if (ifp->if_flags & IFF_OACTIVE) { 1542 STE_UNLOCK(sc); 1543 return; 1544 } 1545 1546 idx = sc->ste_cdata.ste_tx_prod; 1547 1548 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1549 1550 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1551 ifp->if_flags |= IFF_OACTIVE; 1552 break; 1553 } 1554 1555 IF_DEQUEUE(&ifp->if_snd, m_head); 1556 if (m_head == NULL) 1557 break; 1558 1559 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1560 1561 if (ste_encap(sc, cur_tx, m_head) != 0) 1562 break; 1563 1564 cur_tx->ste_ptr->ste_next = 0; 1565 1566 if(sc->ste_tx_prev_idx < 0){ 1567 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1568 /* Load address of the TX list */ 1569 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1570 ste_wait(sc); 1571 1572 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1573 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1574 1575 /* Set TX polling interval to start TX engine */ 1576 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1577 1578 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1579 ste_wait(sc); 1580 }else{ 1581 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1582 sc->ste_cdata.ste_tx_chain[ 1583 sc->ste_tx_prev_idx].ste_ptr->ste_next 1584 = cur_tx->ste_phys; 1585 } 1586 1587 sc->ste_tx_prev_idx=idx; 1588 1589 /* 1590 * If there's a BPF listener, bounce a copy of this frame 1591 * to him. 1592 */ 1593 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1594 1595 STE_INC(idx, STE_TX_LIST_CNT); 1596 sc->ste_cdata.ste_tx_cnt++; 1597 ifp->if_timer = 5; 1598 sc->ste_cdata.ste_tx_prod = idx; 1599 } 1600 1601 STE_UNLOCK(sc); 1602 1603 return; 1604} 1605 1606static void 1607ste_watchdog(ifp) 1608 struct ifnet *ifp; 1609{ 1610 struct ste_softc *sc; 1611 1612 sc = ifp->if_softc; 1613 STE_LOCK(sc); 1614 1615 ifp->if_oerrors++; 1616 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1617 1618 ste_txeoc(sc); 1619 ste_txeof(sc); 1620 ste_rxeof(sc); 1621 ste_reset(sc); 1622 ste_init(sc); 1623 1624 if (ifp->if_snd.ifq_head != NULL) 1625 ste_start(ifp); 1626 STE_UNLOCK(sc); 1627 1628 return; 1629} 1630 1631static void 1632ste_shutdown(dev) 1633 device_t dev; 1634{ 1635 struct ste_softc *sc; 1636 1637 sc = device_get_softc(dev); 1638 1639 ste_stop(sc); 1640 1641 return; 1642} 1643