if_ste.c revision 113506
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 113506 2003-04-15 06:37:30Z mdodd $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_vlan_var.h> 50 51#include <net/bpf.h> 52 53#include <vm/vm.h> /* for vtophys */ 54#include <vm/pmap.h> /* for vtophys */ 55#include <machine/bus_memio.h> 56#include <machine/bus_pio.h> 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/bus.h> 60#include <sys/rman.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <pci/pcireg.h> 66#include <pci/pcivar.h> 67 68/* "controller miibus0" required. See GENERIC if you get errors here. */ 69#include "miibus_if.h" 70 71#define STE_USEIOSPACE 72 73#include <pci/if_stereg.h> 74 75MODULE_DEPEND(ste, pci, 1, 1, 1); 76MODULE_DEPEND(ste, ether, 1, 1, 1); 77MODULE_DEPEND(ste, miibus, 1, 1, 1); 78 79/* 80 * Various supported device vendors/types and their names. 81 */ 82static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 85 { 0, 0, NULL } 86}; 87 88static int ste_probe (device_t); 89static int ste_attach (device_t); 90static int ste_detach (device_t); 91static void ste_init (void *); 92static void ste_intr (void *); 93static void ste_rxeof (struct ste_softc *); 94static void ste_txeoc (struct ste_softc *); 95static void ste_txeof (struct ste_softc *); 96static void ste_stats_update (void *); 97static void ste_stop (struct ste_softc *); 98static void ste_reset (struct ste_softc *); 99static int ste_ioctl (struct ifnet *, u_long, caddr_t); 100static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102static void ste_start (struct ifnet *); 103static void ste_watchdog (struct ifnet *); 104static void ste_shutdown (device_t); 105static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108static int ste_ifmedia_upd (struct ifnet *); 109static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111static void ste_mii_sync (struct ste_softc *); 112static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 114static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 115static int ste_miibus_readreg (device_t, int, int); 116static int ste_miibus_writereg (device_t, int, int, int); 117static void ste_miibus_statchg (device_t); 118 119static int ste_eeprom_wait (struct ste_softc *); 120static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 121static void ste_wait (struct ste_softc *); 122static u_int8_t ste_calchash (caddr_t); 123static void ste_setmulti (struct ste_softc *); 124static int ste_init_rx_list (struct ste_softc *); 125static void ste_init_tx_list (struct ste_softc *); 126 127#ifdef STE_USEIOSPACE 128#define STE_RES SYS_RES_IOPORT 129#define STE_RID STE_PCI_LOIO 130#else 131#define STE_RES SYS_RES_MEMORY 132#define STE_RID STE_PCI_LOMEM 133#endif 134 135static device_method_t ste_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ste_probe), 138 DEVMETHOD(device_attach, ste_attach), 139 DEVMETHOD(device_detach, ste_detach), 140 DEVMETHOD(device_shutdown, ste_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 150 151 { 0, 0 } 152}; 153 154static driver_t ste_driver = { 155 "ste", 156 ste_methods, 157 sizeof(struct ste_softc) 158}; 159 160static devclass_t ste_devclass; 161 162DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 163DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 164 165#define STE_SETBIT4(sc, reg, x) \ 166 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 167 168#define STE_CLRBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 170 171#define STE_SETBIT2(sc, reg, x) \ 172 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 173 174#define STE_CLRBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 176 177#define STE_SETBIT1(sc, reg, x) \ 178 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 179 180#define STE_CLRBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 182 183 184#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 185#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 186 187/* 188 * Sync the PHYs by setting data bit and strobing the clock 32 times. 189 */ 190static void 191ste_mii_sync(sc) 192 struct ste_softc *sc; 193{ 194 register int i; 195 196 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 197 198 for (i = 0; i < 32; i++) { 199 MII_SET(STE_PHYCTL_MCLK); 200 DELAY(1); 201 MII_CLR(STE_PHYCTL_MCLK); 202 DELAY(1); 203 } 204 205 return; 206} 207 208/* 209 * Clock a series of bits through the MII. 210 */ 211static void 212ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216{ 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232} 233 234/* 235 * Read an PHY register through the MII. 236 */ 237static int 238ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242{ 243 int i, ack; 244 245 STE_LOCK(sc); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 STE_UNLOCK(sc); 321 322 if (ack) 323 return(1); 324 return(0); 325} 326 327/* 328 * Write to a PHY register through the MII. 329 */ 330static int 331ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335{ 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374} 375 376static int 377ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396} 397 398static int 399ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402{ 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416} 417 418static void 419ste_miibus_statchg(dev) 420 device_t dev; 421{ 422 struct ste_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 STE_LOCK(sc); 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 STE_UNLOCK(sc); 435 436 return; 437} 438 439static int 440ste_ifmedia_upd(ifp) 441 struct ifnet *ifp; 442{ 443 struct ste_softc *sc; 444 struct mii_data *mii; 445 446 sc = ifp->if_softc; 447 mii = device_get_softc(sc->ste_miibus); 448 sc->ste_link = 0; 449 if (mii->mii_instance) { 450 struct mii_softc *miisc; 451 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 452 mii_phy_reset(miisc); 453 } 454 mii_mediachg(mii); 455 456 return(0); 457} 458 459static void 460ste_ifmedia_sts(ifp, ifmr) 461 struct ifnet *ifp; 462 struct ifmediareq *ifmr; 463{ 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->ste_miibus); 469 470 mii_pollstat(mii); 471 ifmr->ifm_active = mii->mii_media_active; 472 ifmr->ifm_status = mii->mii_media_status; 473 474 return; 475} 476 477static void 478ste_wait(sc) 479 struct ste_softc *sc; 480{ 481 register int i; 482 483 for (i = 0; i < STE_TIMEOUT; i++) { 484 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 485 break; 486 } 487 488 if (i == STE_TIMEOUT) 489 printf("ste%d: command never completed!\n", sc->ste_unit); 490 491 return; 492} 493 494/* 495 * The EEPROM is slow: give it time to come ready after issuing 496 * it a command. 497 */ 498static int 499ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501{ 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 515 return(1); 516 } 517 518 return(0); 519} 520 521/* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525static int 526ste_read_eeprom(sc, dest, off, cnt, swap) 527 struct ste_softc *sc; 528 caddr_t dest; 529 int off; 530 int cnt; 531 int swap; 532{ 533 int err = 0, i; 534 u_int16_t word = 0, *ptr; 535 536 if (ste_eeprom_wait(sc)) 537 return(1); 538 539 for (i = 0; i < cnt; i++) { 540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 541 err = ste_eeprom_wait(sc); 542 if (err) 543 break; 544 word = CSR_READ_2(sc, STE_EEPROM_DATA); 545 ptr = (u_int16_t *)(dest + (i * 2)); 546 if (swap) 547 *ptr = ntohs(word); 548 else 549 *ptr = word; 550 } 551 552 return(err ? 1 : 0); 553} 554 555static u_int8_t 556ste_calchash(addr) 557 caddr_t addr; 558{ 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580} 581 582static void 583ste_setmulti(sc) 584 struct ste_softc *sc; 585{ 586 struct ifnet *ifp; 587 int h = 0; 588 u_int32_t hashes[2] = { 0, 0 }; 589 struct ifmultiaddr *ifma; 590 591 ifp = &sc->arpcom.ac_if; 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 594 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 595 return; 596 } 597 598 /* first, zot all the existing hash bits */ 599 CSR_WRITE_2(sc, STE_MAR0, 0); 600 CSR_WRITE_2(sc, STE_MAR1, 0); 601 CSR_WRITE_2(sc, STE_MAR2, 0); 602 CSR_WRITE_2(sc, STE_MAR3, 0); 603 604 /* now program new ones */ 605 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623} 624 625static void 626ste_intr(xsc) 627 void *xsc; 628{ 629 struct ste_softc *sc; 630 struct ifnet *ifp; 631 u_int16_t status; 632 633 sc = xsc; 634 STE_LOCK(sc); 635 ifp = &sc->arpcom.ac_if; 636 637 /* See if this is really our interrupt. */ 638 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 639 STE_UNLOCK(sc); 640 return; 641 } 642 643 for (;;) { 644 status = CSR_READ_2(sc, STE_ISR_ACK); 645 646 if (!(status & STE_INTRS)) 647 break; 648 649 if (status & STE_ISR_RX_DMADONE) 650 ste_rxeof(sc); 651 652 if (status & STE_ISR_TX_DMADONE) 653 ste_txeof(sc); 654 655 if (status & STE_ISR_TX_DONE) 656 ste_txeoc(sc); 657 658 if (status & STE_ISR_STATS_OFLOW) { 659 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 660 ste_stats_update(sc); 661 } 662 663 if (status & STE_ISR_LINKEVENT) 664 mii_pollstat(device_get_softc(sc->ste_miibus)); 665 666 667 if (status & STE_ISR_HOSTERR) { 668 ste_reset(sc); 669 ste_init(sc); 670 } 671 } 672 673 /* Re-enable interrupts */ 674 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 675 676 if (ifp->if_snd.ifq_head != NULL) 677 ste_start(ifp); 678 679 STE_UNLOCK(sc); 680 681 return; 682} 683 684/* 685 * A frame has been uploaded: pass the resulting mbuf chain up to 686 * the higher level protocols. 687 */ 688static void 689ste_rxeof(sc) 690 struct ste_softc *sc; 691{ 692 struct mbuf *m; 693 struct ifnet *ifp; 694 struct ste_chain_onefrag *cur_rx; 695 int total_len = 0, count=0; 696 u_int32_t rxstat; 697 698 ifp = &sc->arpcom.ac_if; 699 700 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 701 & STE_RXSTAT_DMADONE) { 702 if ((STE_RX_LIST_CNT - count) < 3) { 703 break; 704 } 705 706 cur_rx = sc->ste_cdata.ste_rx_head; 707 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 708 709 /* 710 * If an error occurs, update stats, clear the 711 * status word and leave the mbuf cluster in place: 712 * it should simply get re-used next time this descriptor 713 * comes up in the ring. 714 */ 715 if (rxstat & STE_RXSTAT_FRAME_ERR) { 716 ifp->if_ierrors++; 717 cur_rx->ste_ptr->ste_status = 0; 718 continue; 719 } 720 721 /* 722 * If there error bit was not set, the upload complete 723 * bit should be set which means we have a valid packet. 724 * If not, something truly strange has happened. 725 */ 726 if (!(rxstat & STE_RXSTAT_DMADONE)) { 727 printf("ste%d: bad receive status -- packet dropped\n", 728 sc->ste_unit); 729 ifp->if_ierrors++; 730 cur_rx->ste_ptr->ste_status = 0; 731 continue; 732 } 733 734 /* No errors; receive the packet. */ 735 m = cur_rx->ste_mbuf; 736 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 737 738 /* 739 * Try to conjure up a new mbuf cluster. If that 740 * fails, it means we have an out of memory condition and 741 * should leave the buffer in place and continue. This will 742 * result in a lost packet, but there's little else we 743 * can do in this situation. 744 */ 745 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 746 ifp->if_ierrors++; 747 cur_rx->ste_ptr->ste_status = 0; 748 continue; 749 } 750 751 m->m_pkthdr.rcvif = ifp; 752 m->m_pkthdr.len = m->m_len = total_len; 753 754 ifp->if_ipackets++; 755 (*ifp->if_input)(ifp, m); 756 757 cur_rx->ste_ptr->ste_status = 0; 758 count++; 759 } 760 761 return; 762} 763 764static void 765ste_txeoc(sc) 766 struct ste_softc *sc; 767{ 768 u_int8_t txstat; 769 struct ifnet *ifp; 770 771 ifp = &sc->arpcom.ac_if; 772 773 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 774 STE_TXSTATUS_TXDONE) { 775 if (txstat & STE_TXSTATUS_UNDERRUN || 776 txstat & STE_TXSTATUS_EXCESSCOLLS || 777 txstat & STE_TXSTATUS_RECLAIMERR) { 778 ifp->if_oerrors++; 779 printf("ste%d: transmission error: %x\n", 780 sc->ste_unit, txstat); 781 782 ste_reset(sc); 783 ste_init(sc); 784 785 if (txstat & STE_TXSTATUS_UNDERRUN && 786 sc->ste_tx_thresh < STE_PACKET_SIZE) { 787 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 788 printf("ste%d: tx underrun, increasing tx" 789 " start threshold to %d bytes\n", 790 sc->ste_unit, sc->ste_tx_thresh); 791 } 792 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 793 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 794 (STE_PACKET_SIZE >> 4)); 795 } 796 ste_init(sc); 797 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 798 } 799 800 return; 801} 802 803static void 804ste_txeof(sc) 805 struct ste_softc *sc; 806{ 807 struct ste_chain *cur_tx = NULL; 808 struct ifnet *ifp; 809 int idx; 810 811 ifp = &sc->arpcom.ac_if; 812 813 idx = sc->ste_cdata.ste_tx_cons; 814 while(idx != sc->ste_cdata.ste_tx_prod) { 815 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 816 817 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 818 break; 819 820 if (cur_tx->ste_mbuf != NULL) { 821 m_freem(cur_tx->ste_mbuf); 822 cur_tx->ste_mbuf = NULL; 823 } 824 825 ifp->if_opackets++; 826 827 sc->ste_cdata.ste_tx_cnt--; 828 STE_INC(idx, STE_TX_LIST_CNT); 829 ifp->if_timer = 0; 830 } 831 832 sc->ste_cdata.ste_tx_cons = idx; 833 834 if (cur_tx != NULL) 835 ifp->if_flags &= ~IFF_OACTIVE; 836 837 return; 838} 839 840static void 841ste_stats_update(xsc) 842 void *xsc; 843{ 844 struct ste_softc *sc; 845 struct ifnet *ifp; 846 struct mii_data *mii; 847 848 sc = xsc; 849 STE_LOCK(sc); 850 851 ifp = &sc->arpcom.ac_if; 852 mii = device_get_softc(sc->ste_miibus); 853 854 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 855 + CSR_READ_1(sc, STE_MULTI_COLLS) 856 + CSR_READ_1(sc, STE_SINGLE_COLLS); 857 858 if (!sc->ste_link) { 859 mii_pollstat(mii); 860 if (mii->mii_media_status & IFM_ACTIVE && 861 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 862 sc->ste_link++; 863 /* 864 * we don't get a call-back on re-init so do it 865 * otherwise we get stuck in the wrong link state 866 */ 867 ste_miibus_statchg(sc->ste_dev); 868 if (ifp->if_snd.ifq_head != NULL) 869 ste_start(ifp); 870 } 871 } 872 873 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 874 STE_UNLOCK(sc); 875 876 return; 877} 878 879 880/* 881 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 882 * IDs against our list and return a device name if we find a match. 883 */ 884static int 885ste_probe(dev) 886 device_t dev; 887{ 888 struct ste_type *t; 889 890 t = ste_devs; 891 892 while(t->ste_name != NULL) { 893 if ((pci_get_vendor(dev) == t->ste_vid) && 894 (pci_get_device(dev) == t->ste_did)) { 895 device_set_desc(dev, t->ste_name); 896 return(0); 897 } 898 t++; 899 } 900 901 return(ENXIO); 902} 903 904/* 905 * Attach the interface. Allocate softc structures, do ifmedia 906 * setup and ethernet/BPF attach. 907 */ 908static int 909ste_attach(dev) 910 device_t dev; 911{ 912 u_int32_t command; 913 struct ste_softc *sc; 914 struct ifnet *ifp; 915 int unit, error = 0, rid; 916 917 sc = device_get_softc(dev); 918 unit = device_get_unit(dev); 919 sc->ste_dev = dev; 920 921 /* 922 * Only use one PHY since this chip reports multiple 923 * Note on the DFE-550 the PHY is at 1 on the DFE-580 924 * it is at 0 & 1. It is rev 0x12. 925 */ 926 if (pci_get_vendor(dev) == DL_VENDORID && 927 pci_get_device(dev) == DL_DEVICEID_DL10050 && 928 pci_get_revid(dev) == 0x12 ) 929 sc->ste_one_phy = 1; 930 931 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 932 MTX_DEF | MTX_RECURSE); 933 934 /* 935 * Handle power management nonsense. 936 */ 937 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 938 u_int32_t iobase, membase, irq; 939 940 /* Save important PCI config data. */ 941 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 942 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 943 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 944 945 /* Reset the power state. */ 946 printf("ste%d: chip is in D%d power mode " 947 "-- setting to D0\n", unit, 948 pci_get_powerstate(dev)); 949 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 950 951 /* Restore PCI config data. */ 952 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 953 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 954 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 955 } 956 957 /* 958 * Map control/status registers. 959 */ 960 pci_enable_busmaster(dev); 961 pci_enable_io(dev, SYS_RES_IOPORT); 962 pci_enable_io(dev, SYS_RES_MEMORY); 963 command = pci_read_config(dev, PCIR_COMMAND, 4); 964 965#ifdef STE_USEIOSPACE 966 if (!(command & PCIM_CMD_PORTEN)) { 967 printf("ste%d: failed to enable I/O ports!\n", unit); 968 error = ENXIO; 969 goto fail; 970 } 971#else 972 if (!(command & PCIM_CMD_MEMEN)) { 973 printf("ste%d: failed to enable memory mapping!\n", unit); 974 error = ENXIO; 975 goto fail; 976 } 977#endif 978 979 rid = STE_RID; 980 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 981 0, ~0, 1, RF_ACTIVE); 982 983 if (sc->ste_res == NULL) { 984 printf ("ste%d: couldn't map ports/memory\n", unit); 985 error = ENXIO; 986 goto fail; 987 } 988 989 sc->ste_btag = rman_get_bustag(sc->ste_res); 990 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 991 992 /* Allocate interrupt */ 993 rid = 0; 994 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 995 RF_SHAREABLE | RF_ACTIVE); 996 997 if (sc->ste_irq == NULL) { 998 printf("ste%d: couldn't map interrupt\n", unit); 999 error = ENXIO; 1000 goto fail; 1001 } 1002 1003 callout_handle_init(&sc->ste_stat_ch); 1004 1005 /* Reset the adapter. */ 1006 ste_reset(sc); 1007 1008 /* 1009 * Get station address from the EEPROM. 1010 */ 1011 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1012 STE_EEADDR_NODE0, 3, 0)) { 1013 printf("ste%d: failed to read station address\n", unit); 1014 error = ENXIO;; 1015 goto fail; 1016 } 1017 1018 /* 1019 * A Sundance chip was detected. Inform the world. 1020 */ 1021 printf("ste%d: Ethernet address: %6D\n", unit, 1022 sc->arpcom.ac_enaddr, ":"); 1023 1024 sc->ste_unit = unit; 1025 1026 /* Allocate the descriptor queues. */ 1027 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1028 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1029 1030 if (sc->ste_ldata == NULL) { 1031 printf("ste%d: no memory for list buffers!\n", unit); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1037 1038 /* Do MII setup. */ 1039 if (mii_phy_probe(dev, &sc->ste_miibus, 1040 ste_ifmedia_upd, ste_ifmedia_sts)) { 1041 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1042 error = ENXIO; 1043 goto fail; 1044 } 1045 1046 ifp = &sc->arpcom.ac_if; 1047 ifp->if_softc = sc; 1048 ifp->if_unit = unit; 1049 ifp->if_name = "ste"; 1050 ifp->if_mtu = ETHERMTU; 1051 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1052 ifp->if_ioctl = ste_ioctl; 1053 ifp->if_output = ether_output; 1054 ifp->if_start = ste_start; 1055 ifp->if_watchdog = ste_watchdog; 1056 ifp->if_init = ste_init; 1057 ifp->if_baudrate = 10000000; 1058 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1059 1060 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1061 1062 /* 1063 * Call MI attach routine. 1064 */ 1065 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1066 1067 /* 1068 * Tell the upper layer(s) we support long frames. 1069 */ 1070 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1071 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1072 1073 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1074 ste_intr, sc, &sc->ste_intrhand); 1075 1076 if (error) { 1077 printf("ste%d: couldn't set up irq\n", unit); 1078 goto fail; 1079 } 1080 1081fail: 1082 if (error) 1083 ste_detach(dev); 1084 1085 return(error); 1086} 1087 1088static int 1089ste_detach(dev) 1090 device_t dev; 1091{ 1092 struct ste_softc *sc; 1093 struct ifnet *ifp; 1094 1095 sc = device_get_softc(dev); 1096 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1097 STE_LOCK(sc); 1098 ifp = &sc->arpcom.ac_if; 1099 1100 if (device_is_alive(dev)) { 1101 if (bus_child_present(dev)) 1102 ste_stop(sc); 1103 ether_ifdetach(ifp); 1104 device_delete_child(dev, sc->ste_miibus); 1105 bus_generic_detach(dev); 1106 } 1107 1108 if (sc->ste_intrhand) 1109 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1110 if (sc->ste_irq) 1111 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1112 if (sc->ste_res) 1113 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1114 1115 if (sc->ste_ldata) { 1116 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1117 M_DEVBUF); 1118 } 1119 1120 STE_UNLOCK(sc); 1121 mtx_destroy(&sc->ste_mtx); 1122 1123 return(0); 1124} 1125 1126static int 1127ste_newbuf(sc, c, m) 1128 struct ste_softc *sc; 1129 struct ste_chain_onefrag *c; 1130 struct mbuf *m; 1131{ 1132 struct mbuf *m_new = NULL; 1133 1134 if (m == NULL) { 1135 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1136 if (m_new == NULL) 1137 return(ENOBUFS); 1138 MCLGET(m_new, M_DONTWAIT); 1139 if (!(m_new->m_flags & M_EXT)) { 1140 m_freem(m_new); 1141 return(ENOBUFS); 1142 } 1143 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1144 } else { 1145 m_new = m; 1146 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1147 m_new->m_data = m_new->m_ext.ext_buf; 1148 } 1149 1150 m_adj(m_new, ETHER_ALIGN); 1151 1152 c->ste_mbuf = m_new; 1153 c->ste_ptr->ste_status = 0; 1154 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1155 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1156 1157 return(0); 1158} 1159 1160static int 1161ste_init_rx_list(sc) 1162 struct ste_softc *sc; 1163{ 1164 struct ste_chain_data *cd; 1165 struct ste_list_data *ld; 1166 int i; 1167 1168 cd = &sc->ste_cdata; 1169 ld = sc->ste_ldata; 1170 1171 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1172 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1173 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1174 return(ENOBUFS); 1175 if (i == (STE_RX_LIST_CNT - 1)) { 1176 cd->ste_rx_chain[i].ste_next = 1177 &cd->ste_rx_chain[0]; 1178 ld->ste_rx_list[i].ste_next = 1179 vtophys(&ld->ste_rx_list[0]); 1180 } else { 1181 cd->ste_rx_chain[i].ste_next = 1182 &cd->ste_rx_chain[i + 1]; 1183 ld->ste_rx_list[i].ste_next = 1184 vtophys(&ld->ste_rx_list[i + 1]); 1185 } 1186 ld->ste_rx_list[i].ste_status = 0; 1187 } 1188 1189 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1190 1191 return(0); 1192} 1193 1194static void 1195ste_init_tx_list(sc) 1196 struct ste_softc *sc; 1197{ 1198 struct ste_chain_data *cd; 1199 struct ste_list_data *ld; 1200 int i; 1201 1202 cd = &sc->ste_cdata; 1203 ld = sc->ste_ldata; 1204 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1205 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1206 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1207 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1208 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1209 if (i == (STE_TX_LIST_CNT - 1)) 1210 cd->ste_tx_chain[i].ste_next = 1211 &cd->ste_tx_chain[0]; 1212 else 1213 cd->ste_tx_chain[i].ste_next = 1214 &cd->ste_tx_chain[i + 1]; 1215 if (i == 0) 1216 cd->ste_tx_chain[i].ste_prev = 1217 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1218 else 1219 cd->ste_tx_chain[i].ste_prev = 1220 &cd->ste_tx_chain[i - 1]; 1221 } 1222 1223 cd->ste_tx_prod = 0; 1224 cd->ste_tx_cons = 0; 1225 cd->ste_tx_cnt = 0; 1226 1227 return; 1228} 1229 1230static void 1231ste_init(xsc) 1232 void *xsc; 1233{ 1234 struct ste_softc *sc; 1235 int i; 1236 struct ifnet *ifp; 1237 struct mii_data *mii; 1238 1239 sc = xsc; 1240 STE_LOCK(sc); 1241 ifp = &sc->arpcom.ac_if; 1242 mii = device_get_softc(sc->ste_miibus); 1243 1244 ste_stop(sc); 1245 1246 /* Init our MAC address */ 1247 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1248 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1249 } 1250 1251 /* Init RX list */ 1252 if (ste_init_rx_list(sc) == ENOBUFS) { 1253 printf("ste%d: initialization failed: no " 1254 "memory for RX buffers\n", sc->ste_unit); 1255 ste_stop(sc); 1256 STE_UNLOCK(sc); 1257 return; 1258 } 1259 1260 /* Set RX polling interval */ 1261 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1262 1263 /* Init TX descriptors */ 1264 ste_init_tx_list(sc); 1265 1266 /* Set the TX freethresh value */ 1267 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1268 1269 /* Set the TX start threshold for best performance. */ 1270 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1271 1272 /* Set the TX reclaim threshold. */ 1273 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1274 1275 /* Set up the RX filter. */ 1276 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1277 1278 /* If we want promiscuous mode, set the allframes bit. */ 1279 if (ifp->if_flags & IFF_PROMISC) { 1280 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1281 } else { 1282 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1283 } 1284 1285 /* Set capture broadcast bit to accept broadcast frames. */ 1286 if (ifp->if_flags & IFF_BROADCAST) { 1287 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1288 } else { 1289 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1290 } 1291 1292 ste_setmulti(sc); 1293 1294 /* Load the address of the RX list. */ 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1296 ste_wait(sc); 1297 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1298 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1299 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1300 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1301 1302 /* Set TX polling interval (defer until we TX first packet */ 1303 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1304 1305 /* Load address of the TX list */ 1306 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1307 ste_wait(sc); 1308 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1309 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1310 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1311 ste_wait(sc); 1312 sc->ste_tx_prev_idx=-1; 1313 1314 /* Enable receiver and transmitter */ 1315 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1316 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1317 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1318 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1319 1320 /* Enable stats counters. */ 1321 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1322 1323 /* Enable interrupts. */ 1324 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1325 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1326 1327 /* Accept VLAN length packets */ 1328 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1329 1330 ste_ifmedia_upd(ifp); 1331 1332 ifp->if_flags |= IFF_RUNNING; 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 1335 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1336 STE_UNLOCK(sc); 1337 1338 return; 1339} 1340 1341static void 1342ste_stop(sc) 1343 struct ste_softc *sc; 1344{ 1345 int i; 1346 struct ifnet *ifp; 1347 1348 STE_LOCK(sc); 1349 ifp = &sc->arpcom.ac_if; 1350 1351 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1352 1353 CSR_WRITE_2(sc, STE_IMR, 0); 1354 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1355 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1356 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1357 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1358 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1359 ste_wait(sc); 1360 /* 1361 * Try really hard to stop the RX engine or under heavy RX 1362 * data chip will write into de-allocated memory. 1363 */ 1364 ste_reset(sc); 1365 1366 sc->ste_link = 0; 1367 1368 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1369 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1370 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1371 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1372 } 1373 } 1374 1375 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1376 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1377 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1378 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1379 } 1380 } 1381 1382 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1383 1384 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1385 STE_UNLOCK(sc); 1386 1387 return; 1388} 1389 1390static void 1391ste_reset(sc) 1392 struct ste_softc *sc; 1393{ 1394 int i; 1395 1396 STE_SETBIT4(sc, STE_ASICCTL, 1397 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1398 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1399 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1400 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1401 STE_ASICCTL_EXTRESET_RESET); 1402 1403 DELAY(100000); 1404 1405 for (i = 0; i < STE_TIMEOUT; i++) { 1406 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1407 break; 1408 } 1409 1410 if (i == STE_TIMEOUT) 1411 printf("ste%d: global reset never completed\n", sc->ste_unit); 1412 1413 return; 1414} 1415 1416static int 1417ste_ioctl(ifp, command, data) 1418 struct ifnet *ifp; 1419 u_long command; 1420 caddr_t data; 1421{ 1422 struct ste_softc *sc; 1423 struct ifreq *ifr; 1424 struct mii_data *mii; 1425 int error = 0; 1426 1427 sc = ifp->if_softc; 1428 STE_LOCK(sc); 1429 ifr = (struct ifreq *)data; 1430 1431 switch(command) { 1432 case SIOCSIFFLAGS: 1433 if (ifp->if_flags & IFF_UP) { 1434 if (ifp->if_flags & IFF_RUNNING && 1435 ifp->if_flags & IFF_PROMISC && 1436 !(sc->ste_if_flags & IFF_PROMISC)) { 1437 STE_SETBIT1(sc, STE_RX_MODE, 1438 STE_RXMODE_PROMISC); 1439 } else if (ifp->if_flags & IFF_RUNNING && 1440 !(ifp->if_flags & IFF_PROMISC) && 1441 sc->ste_if_flags & IFF_PROMISC) { 1442 STE_CLRBIT1(sc, STE_RX_MODE, 1443 STE_RXMODE_PROMISC); 1444 } 1445 if (!(ifp->if_flags & IFF_RUNNING)) { 1446 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1447 ste_init(sc); 1448 } 1449 } else { 1450 if (ifp->if_flags & IFF_RUNNING) 1451 ste_stop(sc); 1452 } 1453 sc->ste_if_flags = ifp->if_flags; 1454 error = 0; 1455 break; 1456 case SIOCADDMULTI: 1457 case SIOCDELMULTI: 1458 ste_setmulti(sc); 1459 error = 0; 1460 break; 1461 case SIOCGIFMEDIA: 1462 case SIOCSIFMEDIA: 1463 mii = device_get_softc(sc->ste_miibus); 1464 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1465 break; 1466 default: 1467 error = ether_ioctl(ifp, command, data); 1468 break; 1469 } 1470 1471 STE_UNLOCK(sc); 1472 1473 return(error); 1474} 1475 1476static int 1477ste_encap(sc, c, m_head) 1478 struct ste_softc *sc; 1479 struct ste_chain *c; 1480 struct mbuf *m_head; 1481{ 1482 int frag = 0; 1483 struct ste_frag *f = NULL; 1484 struct mbuf *m; 1485 struct ste_desc *d; 1486 int total_len = 0; 1487 1488 d = c->ste_ptr; 1489 d->ste_ctl = 0; 1490 1491encap_retry: 1492 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1493 if (m->m_len != 0) { 1494 if (frag == STE_MAXFRAGS) 1495 break; 1496 total_len += m->m_len; 1497 f = &d->ste_frags[frag]; 1498 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1499 f->ste_len = m->m_len; 1500 frag++; 1501 } 1502 } 1503 1504 if (m != NULL) { 1505 struct mbuf *mn; 1506 1507 /* 1508 * We ran out of segments. We have to recopy this 1509 * mbuf chain first. Bail out if we can't get the 1510 * new buffers. Code borrowed from if_fxp.c 1511 */ 1512 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1513 if (mn == NULL) { 1514 m_freem(m_head); 1515 return ENOMEM; 1516 } 1517 if (m_head->m_pkthdr.len > MHLEN) { 1518 MCLGET(mn, M_DONTWAIT); 1519 if ((mn->m_flags & M_EXT) == 0) { 1520 m_freem(mn); 1521 m_freem(m_head); 1522 return ENOMEM; 1523 } 1524 } 1525 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1526 mtod(mn, caddr_t)); 1527 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1528 m_freem(m_head); 1529 m_head = mn; 1530 goto encap_retry; 1531 } 1532 1533 c->ste_mbuf = m_head; 1534 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1535 d->ste_ctl = 1; 1536 1537 return(0); 1538} 1539 1540static void 1541ste_start(ifp) 1542 struct ifnet *ifp; 1543{ 1544 struct ste_softc *sc; 1545 struct mbuf *m_head = NULL; 1546 struct ste_chain *cur_tx = NULL; 1547 int idx; 1548 1549 sc = ifp->if_softc; 1550 STE_LOCK(sc); 1551 1552 if (!sc->ste_link) { 1553 STE_UNLOCK(sc); 1554 return; 1555 } 1556 1557 if (ifp->if_flags & IFF_OACTIVE) { 1558 STE_UNLOCK(sc); 1559 return; 1560 } 1561 1562 idx = sc->ste_cdata.ste_tx_prod; 1563 1564 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1565 1566 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1567 ifp->if_flags |= IFF_OACTIVE; 1568 break; 1569 } 1570 1571 IF_DEQUEUE(&ifp->if_snd, m_head); 1572 if (m_head == NULL) 1573 break; 1574 1575 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1576 1577 if (ste_encap(sc, cur_tx, m_head) != 0) 1578 break; 1579 1580 cur_tx->ste_ptr->ste_next = 0; 1581 1582 if(sc->ste_tx_prev_idx < 0){ 1583 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1584 /* Load address of the TX list */ 1585 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1586 ste_wait(sc); 1587 1588 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1589 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1590 1591 /* Set TX polling interval to start TX engine */ 1592 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1593 1594 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1595 ste_wait(sc); 1596 }else{ 1597 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1598 sc->ste_cdata.ste_tx_chain[ 1599 sc->ste_tx_prev_idx].ste_ptr->ste_next 1600 = cur_tx->ste_phys; 1601 } 1602 1603 sc->ste_tx_prev_idx=idx; 1604 1605 /* 1606 * If there's a BPF listener, bounce a copy of this frame 1607 * to him. 1608 */ 1609 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1610 1611 STE_INC(idx, STE_TX_LIST_CNT); 1612 sc->ste_cdata.ste_tx_cnt++; 1613 ifp->if_timer = 5; 1614 sc->ste_cdata.ste_tx_prod = idx; 1615 } 1616 1617 STE_UNLOCK(sc); 1618 1619 return; 1620} 1621 1622static void 1623ste_watchdog(ifp) 1624 struct ifnet *ifp; 1625{ 1626 struct ste_softc *sc; 1627 1628 sc = ifp->if_softc; 1629 STE_LOCK(sc); 1630 1631 ifp->if_oerrors++; 1632 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1633 1634 ste_txeoc(sc); 1635 ste_txeof(sc); 1636 ste_rxeof(sc); 1637 ste_reset(sc); 1638 ste_init(sc); 1639 1640 if (ifp->if_snd.ifq_head != NULL) 1641 ste_start(ifp); 1642 STE_UNLOCK(sc); 1643 1644 return; 1645} 1646 1647static void 1648ste_shutdown(dev) 1649 device_t dev; 1650{ 1651 struct ste_softc *sc; 1652 1653 sc = device_get_softc(dev); 1654 1655 ste_stop(sc); 1656 1657 return; 1658} 1659