if_ste.c revision 113038
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 113038 2003-04-03 21:36:33Z obrien $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_vlan_var.h> 50 51#include <net/bpf.h> 52 53#include <vm/vm.h> /* for vtophys */ 54#include <vm/pmap.h> /* for vtophys */ 55#include <machine/bus_memio.h> 56#include <machine/bus_pio.h> 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/bus.h> 60#include <sys/rman.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <pci/pcireg.h> 66#include <pci/pcivar.h> 67 68/* "controller miibus0" required. See GENERIC if you get errors here. */ 69#include "miibus_if.h" 70 71#define STE_USEIOSPACE 72 73#include <pci/if_stereg.h> 74 75MODULE_DEPEND(ste, miibus, 1, 1, 1); 76 77/* 78 * Various supported device vendors/types and their names. 79 */ 80static struct ste_type ste_devs[] = { 81 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 82 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 83 { 0, 0, NULL } 84}; 85 86static int ste_probe (device_t); 87static int ste_attach (device_t); 88static int ste_detach (device_t); 89static void ste_init (void *); 90static void ste_intr (void *); 91static void ste_rxeof (struct ste_softc *); 92static void ste_txeoc (struct ste_softc *); 93static void ste_txeof (struct ste_softc *); 94static void ste_stats_update (void *); 95static void ste_stop (struct ste_softc *); 96static void ste_reset (struct ste_softc *); 97static int ste_ioctl (struct ifnet *, u_long, caddr_t); 98static int ste_encap (struct ste_softc *, struct ste_chain *, 99 struct mbuf *); 100static void ste_start (struct ifnet *); 101static void ste_watchdog (struct ifnet *); 102static void ste_shutdown (device_t); 103static int ste_newbuf (struct ste_softc *, 104 struct ste_chain_onefrag *, 105 struct mbuf *); 106static int ste_ifmedia_upd (struct ifnet *); 107static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 108 109static void ste_mii_sync (struct ste_softc *); 110static void ste_mii_send (struct ste_softc *, u_int32_t, int); 111static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 112static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 113static int ste_miibus_readreg (device_t, int, int); 114static int ste_miibus_writereg (device_t, int, int, int); 115static void ste_miibus_statchg (device_t); 116 117static int ste_eeprom_wait (struct ste_softc *); 118static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 119static void ste_wait (struct ste_softc *); 120static u_int8_t ste_calchash (caddr_t); 121static void ste_setmulti (struct ste_softc *); 122static int ste_init_rx_list (struct ste_softc *); 123static void ste_init_tx_list (struct ste_softc *); 124 125#ifdef STE_USEIOSPACE 126#define STE_RES SYS_RES_IOPORT 127#define STE_RID STE_PCI_LOIO 128#else 129#define STE_RES SYS_RES_MEMORY 130#define STE_RID STE_PCI_LOMEM 131#endif 132 133static device_method_t ste_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, ste_probe), 136 DEVMETHOD(device_attach, ste_attach), 137 DEVMETHOD(device_detach, ste_detach), 138 DEVMETHOD(device_shutdown, ste_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 146 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 147 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 148 149 { 0, 0 } 150}; 151 152static driver_t ste_driver = { 153 "ste", 154 ste_methods, 155 sizeof(struct ste_softc) 156}; 157 158static devclass_t ste_devclass; 159 160DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 161DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 162 163#define STE_SETBIT4(sc, reg, x) \ 164 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 165 166#define STE_CLRBIT4(sc, reg, x) \ 167 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 168 169#define STE_SETBIT2(sc, reg, x) \ 170 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 171 172#define STE_CLRBIT2(sc, reg, x) \ 173 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 174 175#define STE_SETBIT1(sc, reg, x) \ 176 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 177 178#define STE_CLRBIT1(sc, reg, x) \ 179 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 180 181 182#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 183#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 184 185/* 186 * Sync the PHYs by setting data bit and strobing the clock 32 times. 187 */ 188static void 189ste_mii_sync(sc) 190 struct ste_softc *sc; 191{ 192 register int i; 193 194 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 195 196 for (i = 0; i < 32; i++) { 197 MII_SET(STE_PHYCTL_MCLK); 198 DELAY(1); 199 MII_CLR(STE_PHYCTL_MCLK); 200 DELAY(1); 201 } 202 203 return; 204} 205 206/* 207 * Clock a series of bits through the MII. 208 */ 209static void 210ste_mii_send(sc, bits, cnt) 211 struct ste_softc *sc; 212 u_int32_t bits; 213 int cnt; 214{ 215 int i; 216 217 MII_CLR(STE_PHYCTL_MCLK); 218 219 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 220 if (bits & i) { 221 MII_SET(STE_PHYCTL_MDATA); 222 } else { 223 MII_CLR(STE_PHYCTL_MDATA); 224 } 225 DELAY(1); 226 MII_CLR(STE_PHYCTL_MCLK); 227 DELAY(1); 228 MII_SET(STE_PHYCTL_MCLK); 229 } 230} 231 232/* 233 * Read an PHY register through the MII. 234 */ 235static int 236ste_mii_readreg(sc, frame) 237 struct ste_softc *sc; 238 struct ste_mii_frame *frame; 239 240{ 241 int i, ack; 242 243 STE_LOCK(sc); 244 245 /* 246 * Set up frame for RX. 247 */ 248 frame->mii_stdelim = STE_MII_STARTDELIM; 249 frame->mii_opcode = STE_MII_READOP; 250 frame->mii_turnaround = 0; 251 frame->mii_data = 0; 252 253 CSR_WRITE_2(sc, STE_PHYCTL, 0); 254 /* 255 * Turn on data xmit. 256 */ 257 MII_SET(STE_PHYCTL_MDIR); 258 259 ste_mii_sync(sc); 260 261 /* 262 * Send command/address info. 263 */ 264 ste_mii_send(sc, frame->mii_stdelim, 2); 265 ste_mii_send(sc, frame->mii_opcode, 2); 266 ste_mii_send(sc, frame->mii_phyaddr, 5); 267 ste_mii_send(sc, frame->mii_regaddr, 5); 268 269 /* Turn off xmit. */ 270 MII_CLR(STE_PHYCTL_MDIR); 271 272 /* Idle bit */ 273 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 274 DELAY(1); 275 MII_SET(STE_PHYCTL_MCLK); 276 DELAY(1); 277 278 /* Check for ack */ 279 MII_CLR(STE_PHYCTL_MCLK); 280 DELAY(1); 281 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 285 /* 286 * Now try reading data bits. If the ack failed, we still 287 * need to clock through 16 cycles to keep the PHY(s) in sync. 288 */ 289 if (ack) { 290 for(i = 0; i < 16; i++) { 291 MII_CLR(STE_PHYCTL_MCLK); 292 DELAY(1); 293 MII_SET(STE_PHYCTL_MCLK); 294 DELAY(1); 295 } 296 goto fail; 297 } 298 299 for (i = 0x8000; i; i >>= 1) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 if (!ack) { 303 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 304 frame->mii_data |= i; 305 DELAY(1); 306 } 307 MII_SET(STE_PHYCTL_MCLK); 308 DELAY(1); 309 } 310 311fail: 312 313 MII_CLR(STE_PHYCTL_MCLK); 314 DELAY(1); 315 MII_SET(STE_PHYCTL_MCLK); 316 DELAY(1); 317 318 STE_UNLOCK(sc); 319 320 if (ack) 321 return(1); 322 return(0); 323} 324 325/* 326 * Write to a PHY register through the MII. 327 */ 328static int 329ste_mii_writereg(sc, frame) 330 struct ste_softc *sc; 331 struct ste_mii_frame *frame; 332 333{ 334 STE_LOCK(sc); 335 336 /* 337 * Set up frame for TX. 338 */ 339 340 frame->mii_stdelim = STE_MII_STARTDELIM; 341 frame->mii_opcode = STE_MII_WRITEOP; 342 frame->mii_turnaround = STE_MII_TURNAROUND; 343 344 /* 345 * Turn on data output. 346 */ 347 MII_SET(STE_PHYCTL_MDIR); 348 349 ste_mii_sync(sc); 350 351 ste_mii_send(sc, frame->mii_stdelim, 2); 352 ste_mii_send(sc, frame->mii_opcode, 2); 353 ste_mii_send(sc, frame->mii_phyaddr, 5); 354 ste_mii_send(sc, frame->mii_regaddr, 5); 355 ste_mii_send(sc, frame->mii_turnaround, 2); 356 ste_mii_send(sc, frame->mii_data, 16); 357 358 /* Idle bit. */ 359 MII_SET(STE_PHYCTL_MCLK); 360 DELAY(1); 361 MII_CLR(STE_PHYCTL_MCLK); 362 DELAY(1); 363 364 /* 365 * Turn off xmit. 366 */ 367 MII_CLR(STE_PHYCTL_MDIR); 368 369 STE_UNLOCK(sc); 370 371 return(0); 372} 373 374static int 375ste_miibus_readreg(dev, phy, reg) 376 device_t dev; 377 int phy, reg; 378{ 379 struct ste_softc *sc; 380 struct ste_mii_frame frame; 381 382 sc = device_get_softc(dev); 383 384 if ( sc->ste_one_phy && phy != 0 ) 385 return (0); 386 387 bzero((char *)&frame, sizeof(frame)); 388 389 frame.mii_phyaddr = phy; 390 frame.mii_regaddr = reg; 391 ste_mii_readreg(sc, &frame); 392 393 return(frame.mii_data); 394} 395 396static int 397ste_miibus_writereg(dev, phy, reg, data) 398 device_t dev; 399 int phy, reg, data; 400{ 401 struct ste_softc *sc; 402 struct ste_mii_frame frame; 403 404 sc = device_get_softc(dev); 405 bzero((char *)&frame, sizeof(frame)); 406 407 frame.mii_phyaddr = phy; 408 frame.mii_regaddr = reg; 409 frame.mii_data = data; 410 411 ste_mii_writereg(sc, &frame); 412 413 return(0); 414} 415 416static void 417ste_miibus_statchg(dev) 418 device_t dev; 419{ 420 struct ste_softc *sc; 421 struct mii_data *mii; 422 423 sc = device_get_softc(dev); 424 STE_LOCK(sc); 425 mii = device_get_softc(sc->ste_miibus); 426 427 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 428 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 429 } else { 430 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } 432 STE_UNLOCK(sc); 433 434 return; 435} 436 437static int 438ste_ifmedia_upd(ifp) 439 struct ifnet *ifp; 440{ 441 struct ste_softc *sc; 442 struct mii_data *mii; 443 444 sc = ifp->if_softc; 445 mii = device_get_softc(sc->ste_miibus); 446 sc->ste_link = 0; 447 if (mii->mii_instance) { 448 struct mii_softc *miisc; 449 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 450 mii_phy_reset(miisc); 451 } 452 mii_mediachg(mii); 453 454 return(0); 455} 456 457static void 458ste_ifmedia_sts(ifp, ifmr) 459 struct ifnet *ifp; 460 struct ifmediareq *ifmr; 461{ 462 struct ste_softc *sc; 463 struct mii_data *mii; 464 465 sc = ifp->if_softc; 466 mii = device_get_softc(sc->ste_miibus); 467 468 mii_pollstat(mii); 469 ifmr->ifm_active = mii->mii_media_active; 470 ifmr->ifm_status = mii->mii_media_status; 471 472 return; 473} 474 475static void 476ste_wait(sc) 477 struct ste_softc *sc; 478{ 479 register int i; 480 481 for (i = 0; i < STE_TIMEOUT; i++) { 482 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 483 break; 484 } 485 486 if (i == STE_TIMEOUT) 487 printf("ste%d: command never completed!\n", sc->ste_unit); 488 489 return; 490} 491 492/* 493 * The EEPROM is slow: give it time to come ready after issuing 494 * it a command. 495 */ 496static int 497ste_eeprom_wait(sc) 498 struct ste_softc *sc; 499{ 500 int i; 501 502 DELAY(1000); 503 504 for (i = 0; i < 100; i++) { 505 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 506 DELAY(1000); 507 else 508 break; 509 } 510 511 if (i == 100) { 512 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 513 return(1); 514 } 515 516 return(0); 517} 518 519/* 520 * Read a sequence of words from the EEPROM. Note that ethernet address 521 * data is stored in the EEPROM in network byte order. 522 */ 523static int 524ste_read_eeprom(sc, dest, off, cnt, swap) 525 struct ste_softc *sc; 526 caddr_t dest; 527 int off; 528 int cnt; 529 int swap; 530{ 531 int err = 0, i; 532 u_int16_t word = 0, *ptr; 533 534 if (ste_eeprom_wait(sc)) 535 return(1); 536 537 for (i = 0; i < cnt; i++) { 538 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 539 err = ste_eeprom_wait(sc); 540 if (err) 541 break; 542 word = CSR_READ_2(sc, STE_EEPROM_DATA); 543 ptr = (u_int16_t *)(dest + (i * 2)); 544 if (swap) 545 *ptr = ntohs(word); 546 else 547 *ptr = word; 548 } 549 550 return(err ? 1 : 0); 551} 552 553static u_int8_t 554ste_calchash(addr) 555 caddr_t addr; 556{ 557 558 u_int32_t crc, carry; 559 int i, j; 560 u_int8_t c; 561 562 /* Compute CRC for the address value. */ 563 crc = 0xFFFFFFFF; /* initial value */ 564 565 for (i = 0; i < 6; i++) { 566 c = *(addr + i); 567 for (j = 0; j < 8; j++) { 568 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 569 crc <<= 1; 570 c >>= 1; 571 if (carry) 572 crc = (crc ^ 0x04c11db6) | carry; 573 } 574 } 575 576 /* return the filter bit position */ 577 return(crc & 0x0000003F); 578} 579 580static void 581ste_setmulti(sc) 582 struct ste_softc *sc; 583{ 584 struct ifnet *ifp; 585 int h = 0; 586 u_int32_t hashes[2] = { 0, 0 }; 587 struct ifmultiaddr *ifma; 588 589 ifp = &sc->arpcom.ac_if; 590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 592 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 593 return; 594 } 595 596 /* first, zot all the existing hash bits */ 597 CSR_WRITE_2(sc, STE_MAR0, 0); 598 CSR_WRITE_2(sc, STE_MAR1, 0); 599 CSR_WRITE_2(sc, STE_MAR2, 0); 600 CSR_WRITE_2(sc, STE_MAR3, 0); 601 602 /* now program new ones */ 603 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 604 if (ifma->ifma_addr->sa_family != AF_LINK) 605 continue; 606 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 607 if (h < 32) 608 hashes[0] |= (1 << h); 609 else 610 hashes[1] |= (1 << (h - 32)); 611 } 612 613 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 614 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 615 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 617 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 618 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 619 620 return; 621} 622 623static void 624ste_intr(xsc) 625 void *xsc; 626{ 627 struct ste_softc *sc; 628 struct ifnet *ifp; 629 u_int16_t status; 630 631 sc = xsc; 632 STE_LOCK(sc); 633 ifp = &sc->arpcom.ac_if; 634 635 /* See if this is really our interrupt. */ 636 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 637 STE_UNLOCK(sc); 638 return; 639 } 640 641 for (;;) { 642 status = CSR_READ_2(sc, STE_ISR_ACK); 643 644 if (!(status & STE_INTRS)) 645 break; 646 647 if (status & STE_ISR_RX_DMADONE) 648 ste_rxeof(sc); 649 650 if (status & STE_ISR_TX_DMADONE) 651 ste_txeof(sc); 652 653 if (status & STE_ISR_TX_DONE) 654 ste_txeoc(sc); 655 656 if (status & STE_ISR_STATS_OFLOW) { 657 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 658 ste_stats_update(sc); 659 } 660 661 if (status & STE_ISR_LINKEVENT) 662 mii_pollstat(device_get_softc(sc->ste_miibus)); 663 664 665 if (status & STE_ISR_HOSTERR) { 666 ste_reset(sc); 667 ste_init(sc); 668 } 669 } 670 671 /* Re-enable interrupts */ 672 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 673 674 if (ifp->if_snd.ifq_head != NULL) 675 ste_start(ifp); 676 677 STE_UNLOCK(sc); 678 679 return; 680} 681 682/* 683 * A frame has been uploaded: pass the resulting mbuf chain up to 684 * the higher level protocols. 685 */ 686static void 687ste_rxeof(sc) 688 struct ste_softc *sc; 689{ 690 struct mbuf *m; 691 struct ifnet *ifp; 692 struct ste_chain_onefrag *cur_rx; 693 int total_len = 0, count=0; 694 u_int32_t rxstat; 695 696 ifp = &sc->arpcom.ac_if; 697 698 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 699 & STE_RXSTAT_DMADONE) { 700 if ((STE_RX_LIST_CNT - count) < 3) { 701 break; 702 } 703 704 cur_rx = sc->ste_cdata.ste_rx_head; 705 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 706 707 /* 708 * If an error occurs, update stats, clear the 709 * status word and leave the mbuf cluster in place: 710 * it should simply get re-used next time this descriptor 711 * comes up in the ring. 712 */ 713 if (rxstat & STE_RXSTAT_FRAME_ERR) { 714 ifp->if_ierrors++; 715 cur_rx->ste_ptr->ste_status = 0; 716 continue; 717 } 718 719 /* 720 * If there error bit was not set, the upload complete 721 * bit should be set which means we have a valid packet. 722 * If not, something truly strange has happened. 723 */ 724 if (!(rxstat & STE_RXSTAT_DMADONE)) { 725 printf("ste%d: bad receive status -- packet dropped\n", 726 sc->ste_unit); 727 ifp->if_ierrors++; 728 cur_rx->ste_ptr->ste_status = 0; 729 continue; 730 } 731 732 /* No errors; receive the packet. */ 733 m = cur_rx->ste_mbuf; 734 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 735 736 /* 737 * Try to conjure up a new mbuf cluster. If that 738 * fails, it means we have an out of memory condition and 739 * should leave the buffer in place and continue. This will 740 * result in a lost packet, but there's little else we 741 * can do in this situation. 742 */ 743 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 744 ifp->if_ierrors++; 745 cur_rx->ste_ptr->ste_status = 0; 746 continue; 747 } 748 749 m->m_pkthdr.rcvif = ifp; 750 m->m_pkthdr.len = m->m_len = total_len; 751 752 ifp->if_ipackets++; 753 (*ifp->if_input)(ifp, m); 754 755 cur_rx->ste_ptr->ste_status = 0; 756 count++; 757 } 758 759 return; 760} 761 762static void 763ste_txeoc(sc) 764 struct ste_softc *sc; 765{ 766 u_int8_t txstat; 767 struct ifnet *ifp; 768 769 ifp = &sc->arpcom.ac_if; 770 771 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 772 STE_TXSTATUS_TXDONE) { 773 if (txstat & STE_TXSTATUS_UNDERRUN || 774 txstat & STE_TXSTATUS_EXCESSCOLLS || 775 txstat & STE_TXSTATUS_RECLAIMERR) { 776 ifp->if_oerrors++; 777 printf("ste%d: transmission error: %x\n", 778 sc->ste_unit, txstat); 779 780 ste_reset(sc); 781 ste_init(sc); 782 783 if (txstat & STE_TXSTATUS_UNDERRUN && 784 sc->ste_tx_thresh < STE_PACKET_SIZE) { 785 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 786 printf("ste%d: tx underrun, increasing tx" 787 " start threshold to %d bytes\n", 788 sc->ste_unit, sc->ste_tx_thresh); 789 } 790 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 791 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 792 (STE_PACKET_SIZE >> 4)); 793 } 794 ste_init(sc); 795 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 796 } 797 798 return; 799} 800 801static void 802ste_txeof(sc) 803 struct ste_softc *sc; 804{ 805 struct ste_chain *cur_tx = NULL; 806 struct ifnet *ifp; 807 int idx; 808 809 ifp = &sc->arpcom.ac_if; 810 811 idx = sc->ste_cdata.ste_tx_cons; 812 while(idx != sc->ste_cdata.ste_tx_prod) { 813 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 814 815 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 816 break; 817 818 if (cur_tx->ste_mbuf != NULL) { 819 m_freem(cur_tx->ste_mbuf); 820 cur_tx->ste_mbuf = NULL; 821 } 822 823 ifp->if_opackets++; 824 825 sc->ste_cdata.ste_tx_cnt--; 826 STE_INC(idx, STE_TX_LIST_CNT); 827 ifp->if_timer = 0; 828 } 829 830 sc->ste_cdata.ste_tx_cons = idx; 831 832 if (cur_tx != NULL) 833 ifp->if_flags &= ~IFF_OACTIVE; 834 835 return; 836} 837 838static void 839ste_stats_update(xsc) 840 void *xsc; 841{ 842 struct ste_softc *sc; 843 struct ifnet *ifp; 844 struct mii_data *mii; 845 846 sc = xsc; 847 STE_LOCK(sc); 848 849 ifp = &sc->arpcom.ac_if; 850 mii = device_get_softc(sc->ste_miibus); 851 852 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 853 + CSR_READ_1(sc, STE_MULTI_COLLS) 854 + CSR_READ_1(sc, STE_SINGLE_COLLS); 855 856 if (!sc->ste_link) { 857 mii_pollstat(mii); 858 if (mii->mii_media_status & IFM_ACTIVE && 859 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 860 sc->ste_link++; 861 /* 862 * we don't get a call-back on re-init so do it 863 * otherwise we get stuck in the wrong link state 864 */ 865 ste_miibus_statchg(sc->ste_dev); 866 if (ifp->if_snd.ifq_head != NULL) 867 ste_start(ifp); 868 } 869 } 870 871 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 872 STE_UNLOCK(sc); 873 874 return; 875} 876 877 878/* 879 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 880 * IDs against our list and return a device name if we find a match. 881 */ 882static int 883ste_probe(dev) 884 device_t dev; 885{ 886 struct ste_type *t; 887 888 t = ste_devs; 889 890 while(t->ste_name != NULL) { 891 if ((pci_get_vendor(dev) == t->ste_vid) && 892 (pci_get_device(dev) == t->ste_did)) { 893 device_set_desc(dev, t->ste_name); 894 return(0); 895 } 896 t++; 897 } 898 899 return(ENXIO); 900} 901 902/* 903 * Attach the interface. Allocate softc structures, do ifmedia 904 * setup and ethernet/BPF attach. 905 */ 906static int 907ste_attach(dev) 908 device_t dev; 909{ 910 u_int32_t command; 911 struct ste_softc *sc; 912 struct ifnet *ifp; 913 int unit, error = 0, rid; 914 915 sc = device_get_softc(dev); 916 unit = device_get_unit(dev); 917 sc->ste_dev = dev; 918 919 /* 920 * Only use one PHY since this chip reports multiple 921 * Note on the DFE-550 the PHY is at 1 on the DFE-580 922 * it is at 0 & 1. It is rev 0x12. 923 */ 924 if (pci_get_vendor(dev) == DL_VENDORID && 925 pci_get_device(dev) == DL_DEVICEID_DL10050 && 926 pci_get_revid(dev) == 0x12 ) 927 sc->ste_one_phy = 1; 928 929 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 930 MTX_DEF | MTX_RECURSE); 931 932 /* 933 * Handle power management nonsense. 934 */ 935 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 936 u_int32_t iobase, membase, irq; 937 938 /* Save important PCI config data. */ 939 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 940 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 941 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 942 943 /* Reset the power state. */ 944 printf("ste%d: chip is in D%d power mode " 945 "-- setting to D0\n", unit, 946 pci_get_powerstate(dev)); 947 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 948 949 /* Restore PCI config data. */ 950 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 951 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 952 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 953 } 954 955 /* 956 * Map control/status registers. 957 */ 958 pci_enable_busmaster(dev); 959 pci_enable_io(dev, SYS_RES_IOPORT); 960 pci_enable_io(dev, SYS_RES_MEMORY); 961 command = pci_read_config(dev, PCIR_COMMAND, 4); 962 963#ifdef STE_USEIOSPACE 964 if (!(command & PCIM_CMD_PORTEN)) { 965 printf("ste%d: failed to enable I/O ports!\n", unit); 966 error = ENXIO; 967 goto fail; 968 } 969#else 970 if (!(command & PCIM_CMD_MEMEN)) { 971 printf("ste%d: failed to enable memory mapping!\n", unit); 972 error = ENXIO; 973 goto fail; 974 } 975#endif 976 977 rid = STE_RID; 978 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 979 0, ~0, 1, RF_ACTIVE); 980 981 if (sc->ste_res == NULL) { 982 printf ("ste%d: couldn't map ports/memory\n", unit); 983 error = ENXIO; 984 goto fail; 985 } 986 987 sc->ste_btag = rman_get_bustag(sc->ste_res); 988 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 989 990 /* Allocate interrupt */ 991 rid = 0; 992 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 993 RF_SHAREABLE | RF_ACTIVE); 994 995 if (sc->ste_irq == NULL) { 996 printf("ste%d: couldn't map interrupt\n", unit); 997 error = ENXIO; 998 goto fail; 999 } 1000 1001 callout_handle_init(&sc->ste_stat_ch); 1002 1003 /* Reset the adapter. */ 1004 ste_reset(sc); 1005 1006 /* 1007 * Get station address from the EEPROM. 1008 */ 1009 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1010 STE_EEADDR_NODE0, 3, 0)) { 1011 printf("ste%d: failed to read station address\n", unit); 1012 error = ENXIO;; 1013 goto fail; 1014 } 1015 1016 /* 1017 * A Sundance chip was detected. Inform the world. 1018 */ 1019 printf("ste%d: Ethernet address: %6D\n", unit, 1020 sc->arpcom.ac_enaddr, ":"); 1021 1022 sc->ste_unit = unit; 1023 1024 /* Allocate the descriptor queues. */ 1025 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1026 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1027 1028 if (sc->ste_ldata == NULL) { 1029 printf("ste%d: no memory for list buffers!\n", unit); 1030 error = ENXIO; 1031 goto fail; 1032 } 1033 1034 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1035 1036 /* Do MII setup. */ 1037 if (mii_phy_probe(dev, &sc->ste_miibus, 1038 ste_ifmedia_upd, ste_ifmedia_sts)) { 1039 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1040 error = ENXIO; 1041 goto fail; 1042 } 1043 1044 ifp = &sc->arpcom.ac_if; 1045 ifp->if_softc = sc; 1046 ifp->if_unit = unit; 1047 ifp->if_name = "ste"; 1048 ifp->if_mtu = ETHERMTU; 1049 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1050 ifp->if_ioctl = ste_ioctl; 1051 ifp->if_output = ether_output; 1052 ifp->if_start = ste_start; 1053 ifp->if_watchdog = ste_watchdog; 1054 ifp->if_init = ste_init; 1055 ifp->if_baudrate = 10000000; 1056 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1057 1058 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1059 1060 /* 1061 * Call MI attach routine. 1062 */ 1063 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1064 1065 /* 1066 * Tell the upper layer(s) we support long frames. 1067 */ 1068 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1069 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1070 1071 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1072 ste_intr, sc, &sc->ste_intrhand); 1073 1074 if (error) { 1075 printf("ste%d: couldn't set up irq\n", unit); 1076 goto fail; 1077 } 1078 1079fail: 1080 if (error) 1081 ste_detach(dev); 1082 1083 return(error); 1084} 1085 1086static int 1087ste_detach(dev) 1088 device_t dev; 1089{ 1090 struct ste_softc *sc; 1091 struct ifnet *ifp; 1092 1093 sc = device_get_softc(dev); 1094 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1095 STE_LOCK(sc); 1096 ifp = &sc->arpcom.ac_if; 1097 1098 if (device_is_alive(dev)) { 1099 if (bus_child_present(dev)) 1100 ste_stop(sc); 1101 ether_ifdetach(ifp); 1102 device_delete_child(dev, sc->ste_miibus); 1103 bus_generic_detach(dev); 1104 } 1105 1106 if (sc->ste_intrhand) 1107 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1108 if (sc->ste_irq) 1109 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1110 if (sc->ste_res) 1111 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1112 1113 if (sc->ste_ldata) { 1114 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1115 M_DEVBUF); 1116 } 1117 1118 STE_UNLOCK(sc); 1119 mtx_destroy(&sc->ste_mtx); 1120 1121 return(0); 1122} 1123 1124static int 1125ste_newbuf(sc, c, m) 1126 struct ste_softc *sc; 1127 struct ste_chain_onefrag *c; 1128 struct mbuf *m; 1129{ 1130 struct mbuf *m_new = NULL; 1131 1132 if (m == NULL) { 1133 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1134 if (m_new == NULL) 1135 return(ENOBUFS); 1136 MCLGET(m_new, M_DONTWAIT); 1137 if (!(m_new->m_flags & M_EXT)) { 1138 m_freem(m_new); 1139 return(ENOBUFS); 1140 } 1141 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1142 } else { 1143 m_new = m; 1144 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1145 m_new->m_data = m_new->m_ext.ext_buf; 1146 } 1147 1148 m_adj(m_new, ETHER_ALIGN); 1149 1150 c->ste_mbuf = m_new; 1151 c->ste_ptr->ste_status = 0; 1152 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1153 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1154 1155 return(0); 1156} 1157 1158static int 1159ste_init_rx_list(sc) 1160 struct ste_softc *sc; 1161{ 1162 struct ste_chain_data *cd; 1163 struct ste_list_data *ld; 1164 int i; 1165 1166 cd = &sc->ste_cdata; 1167 ld = sc->ste_ldata; 1168 1169 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1170 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1171 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1172 return(ENOBUFS); 1173 if (i == (STE_RX_LIST_CNT - 1)) { 1174 cd->ste_rx_chain[i].ste_next = 1175 &cd->ste_rx_chain[0]; 1176 ld->ste_rx_list[i].ste_next = 1177 vtophys(&ld->ste_rx_list[0]); 1178 } else { 1179 cd->ste_rx_chain[i].ste_next = 1180 &cd->ste_rx_chain[i + 1]; 1181 ld->ste_rx_list[i].ste_next = 1182 vtophys(&ld->ste_rx_list[i + 1]); 1183 } 1184 ld->ste_rx_list[i].ste_status = 0; 1185 } 1186 1187 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1188 1189 return(0); 1190} 1191 1192static void 1193ste_init_tx_list(sc) 1194 struct ste_softc *sc; 1195{ 1196 struct ste_chain_data *cd; 1197 struct ste_list_data *ld; 1198 int i; 1199 1200 cd = &sc->ste_cdata; 1201 ld = sc->ste_ldata; 1202 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1203 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1204 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1205 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1206 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1207 if (i == (STE_TX_LIST_CNT - 1)) 1208 cd->ste_tx_chain[i].ste_next = 1209 &cd->ste_tx_chain[0]; 1210 else 1211 cd->ste_tx_chain[i].ste_next = 1212 &cd->ste_tx_chain[i + 1]; 1213 if (i == 0) 1214 cd->ste_tx_chain[i].ste_prev = 1215 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1216 else 1217 cd->ste_tx_chain[i].ste_prev = 1218 &cd->ste_tx_chain[i - 1]; 1219 } 1220 1221 cd->ste_tx_prod = 0; 1222 cd->ste_tx_cons = 0; 1223 cd->ste_tx_cnt = 0; 1224 1225 return; 1226} 1227 1228static void 1229ste_init(xsc) 1230 void *xsc; 1231{ 1232 struct ste_softc *sc; 1233 int i; 1234 struct ifnet *ifp; 1235 struct mii_data *mii; 1236 1237 sc = xsc; 1238 STE_LOCK(sc); 1239 ifp = &sc->arpcom.ac_if; 1240 mii = device_get_softc(sc->ste_miibus); 1241 1242 ste_stop(sc); 1243 1244 /* Init our MAC address */ 1245 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1246 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1247 } 1248 1249 /* Init RX list */ 1250 if (ste_init_rx_list(sc) == ENOBUFS) { 1251 printf("ste%d: initialization failed: no " 1252 "memory for RX buffers\n", sc->ste_unit); 1253 ste_stop(sc); 1254 STE_UNLOCK(sc); 1255 return; 1256 } 1257 1258 /* Set RX polling interval */ 1259 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1260 1261 /* Init TX descriptors */ 1262 ste_init_tx_list(sc); 1263 1264 /* Set the TX freethresh value */ 1265 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1266 1267 /* Set the TX start threshold for best performance. */ 1268 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1269 1270 /* Set the TX reclaim threshold. */ 1271 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1272 1273 /* Set up the RX filter. */ 1274 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1275 1276 /* If we want promiscuous mode, set the allframes bit. */ 1277 if (ifp->if_flags & IFF_PROMISC) { 1278 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1279 } else { 1280 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1281 } 1282 1283 /* Set capture broadcast bit to accept broadcast frames. */ 1284 if (ifp->if_flags & IFF_BROADCAST) { 1285 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1286 } else { 1287 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1288 } 1289 1290 ste_setmulti(sc); 1291 1292 /* Load the address of the RX list. */ 1293 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1294 ste_wait(sc); 1295 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1296 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1297 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1298 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1299 1300 /* Set TX polling interval (defer until we TX first packet */ 1301 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1302 1303 /* Load address of the TX list */ 1304 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1305 ste_wait(sc); 1306 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1307 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1308 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1309 ste_wait(sc); 1310 sc->ste_tx_prev_idx=-1; 1311 1312 /* Enable receiver and transmitter */ 1313 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1314 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1315 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1316 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1317 1318 /* Enable stats counters. */ 1319 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1320 1321 /* Enable interrupts. */ 1322 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1323 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1324 1325 /* Accept VLAN length packets */ 1326 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1327 1328 ste_ifmedia_upd(ifp); 1329 1330 ifp->if_flags |= IFF_RUNNING; 1331 ifp->if_flags &= ~IFF_OACTIVE; 1332 1333 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1334 STE_UNLOCK(sc); 1335 1336 return; 1337} 1338 1339static void 1340ste_stop(sc) 1341 struct ste_softc *sc; 1342{ 1343 int i; 1344 struct ifnet *ifp; 1345 1346 STE_LOCK(sc); 1347 ifp = &sc->arpcom.ac_if; 1348 1349 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1350 1351 CSR_WRITE_2(sc, STE_IMR, 0); 1352 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1353 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1354 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1355 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1356 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1357 ste_wait(sc); 1358 /* 1359 * Try really hard to stop the RX engine or under heavy RX 1360 * data chip will write into de-allocated memory. 1361 */ 1362 ste_reset(sc); 1363 1364 sc->ste_link = 0; 1365 1366 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1367 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1368 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1369 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1370 } 1371 } 1372 1373 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1374 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1375 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1376 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1377 } 1378 } 1379 1380 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1381 1382 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1383 STE_UNLOCK(sc); 1384 1385 return; 1386} 1387 1388static void 1389ste_reset(sc) 1390 struct ste_softc *sc; 1391{ 1392 int i; 1393 1394 STE_SETBIT4(sc, STE_ASICCTL, 1395 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1396 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1397 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1398 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1399 STE_ASICCTL_EXTRESET_RESET); 1400 1401 DELAY(100000); 1402 1403 for (i = 0; i < STE_TIMEOUT; i++) { 1404 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1405 break; 1406 } 1407 1408 if (i == STE_TIMEOUT) 1409 printf("ste%d: global reset never completed\n", sc->ste_unit); 1410 1411 return; 1412} 1413 1414static int 1415ste_ioctl(ifp, command, data) 1416 struct ifnet *ifp; 1417 u_long command; 1418 caddr_t data; 1419{ 1420 struct ste_softc *sc; 1421 struct ifreq *ifr; 1422 struct mii_data *mii; 1423 int error = 0; 1424 1425 sc = ifp->if_softc; 1426 STE_LOCK(sc); 1427 ifr = (struct ifreq *)data; 1428 1429 switch(command) { 1430 case SIOCSIFFLAGS: 1431 if (ifp->if_flags & IFF_UP) { 1432 if (ifp->if_flags & IFF_RUNNING && 1433 ifp->if_flags & IFF_PROMISC && 1434 !(sc->ste_if_flags & IFF_PROMISC)) { 1435 STE_SETBIT1(sc, STE_RX_MODE, 1436 STE_RXMODE_PROMISC); 1437 } else if (ifp->if_flags & IFF_RUNNING && 1438 !(ifp->if_flags & IFF_PROMISC) && 1439 sc->ste_if_flags & IFF_PROMISC) { 1440 STE_CLRBIT1(sc, STE_RX_MODE, 1441 STE_RXMODE_PROMISC); 1442 } 1443 if (!(ifp->if_flags & IFF_RUNNING)) { 1444 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1445 ste_init(sc); 1446 } 1447 } else { 1448 if (ifp->if_flags & IFF_RUNNING) 1449 ste_stop(sc); 1450 } 1451 sc->ste_if_flags = ifp->if_flags; 1452 error = 0; 1453 break; 1454 case SIOCADDMULTI: 1455 case SIOCDELMULTI: 1456 ste_setmulti(sc); 1457 error = 0; 1458 break; 1459 case SIOCGIFMEDIA: 1460 case SIOCSIFMEDIA: 1461 mii = device_get_softc(sc->ste_miibus); 1462 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1463 break; 1464 default: 1465 error = ether_ioctl(ifp, command, data); 1466 break; 1467 } 1468 1469 STE_UNLOCK(sc); 1470 1471 return(error); 1472} 1473 1474static int 1475ste_encap(sc, c, m_head) 1476 struct ste_softc *sc; 1477 struct ste_chain *c; 1478 struct mbuf *m_head; 1479{ 1480 int frag = 0; 1481 struct ste_frag *f = NULL; 1482 struct mbuf *m; 1483 struct ste_desc *d; 1484 int total_len = 0; 1485 1486 d = c->ste_ptr; 1487 d->ste_ctl = 0; 1488 1489encap_retry: 1490 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1491 if (m->m_len != 0) { 1492 if (frag == STE_MAXFRAGS) 1493 break; 1494 total_len += m->m_len; 1495 f = &d->ste_frags[frag]; 1496 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1497 f->ste_len = m->m_len; 1498 frag++; 1499 } 1500 } 1501 1502 if (m != NULL) { 1503 struct mbuf *mn; 1504 1505 /* 1506 * We ran out of segments. We have to recopy this 1507 * mbuf chain first. Bail out if we can't get the 1508 * new buffers. Code borrowed from if_fxp.c 1509 */ 1510 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1511 if (mn == NULL) { 1512 m_freem(m_head); 1513 return ENOMEM; 1514 } 1515 if (m_head->m_pkthdr.len > MHLEN) { 1516 MCLGET(mn, M_DONTWAIT); 1517 if ((mn->m_flags & M_EXT) == 0) { 1518 m_freem(mn); 1519 m_freem(m_head); 1520 return ENOMEM; 1521 } 1522 } 1523 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1524 mtod(mn, caddr_t)); 1525 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1526 m_freem(m_head); 1527 m_head = mn; 1528 goto encap_retry; 1529 } 1530 1531 c->ste_mbuf = m_head; 1532 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1533 d->ste_ctl = 1; 1534 1535 return(0); 1536} 1537 1538static void 1539ste_start(ifp) 1540 struct ifnet *ifp; 1541{ 1542 struct ste_softc *sc; 1543 struct mbuf *m_head = NULL; 1544 struct ste_chain *cur_tx = NULL; 1545 int idx; 1546 1547 sc = ifp->if_softc; 1548 STE_LOCK(sc); 1549 1550 if (!sc->ste_link) { 1551 STE_UNLOCK(sc); 1552 return; 1553 } 1554 1555 if (ifp->if_flags & IFF_OACTIVE) { 1556 STE_UNLOCK(sc); 1557 return; 1558 } 1559 1560 idx = sc->ste_cdata.ste_tx_prod; 1561 1562 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1563 1564 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1565 ifp->if_flags |= IFF_OACTIVE; 1566 break; 1567 } 1568 1569 IF_DEQUEUE(&ifp->if_snd, m_head); 1570 if (m_head == NULL) 1571 break; 1572 1573 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1574 1575 if (ste_encap(sc, cur_tx, m_head) != 0) 1576 break; 1577 1578 cur_tx->ste_ptr->ste_next = 0; 1579 1580 if(sc->ste_tx_prev_idx < 0){ 1581 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1582 /* Load address of the TX list */ 1583 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1584 ste_wait(sc); 1585 1586 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1587 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1588 1589 /* Set TX polling interval to start TX engine */ 1590 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1591 1592 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1593 ste_wait(sc); 1594 }else{ 1595 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1596 sc->ste_cdata.ste_tx_chain[ 1597 sc->ste_tx_prev_idx].ste_ptr->ste_next 1598 = cur_tx->ste_phys; 1599 } 1600 1601 sc->ste_tx_prev_idx=idx; 1602 1603 /* 1604 * If there's a BPF listener, bounce a copy of this frame 1605 * to him. 1606 */ 1607 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1608 1609 STE_INC(idx, STE_TX_LIST_CNT); 1610 sc->ste_cdata.ste_tx_cnt++; 1611 ifp->if_timer = 5; 1612 sc->ste_cdata.ste_tx_prod = idx; 1613 } 1614 1615 STE_UNLOCK(sc); 1616 1617 return; 1618} 1619 1620static void 1621ste_watchdog(ifp) 1622 struct ifnet *ifp; 1623{ 1624 struct ste_softc *sc; 1625 1626 sc = ifp->if_softc; 1627 STE_LOCK(sc); 1628 1629 ifp->if_oerrors++; 1630 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1631 1632 ste_txeoc(sc); 1633 ste_txeof(sc); 1634 ste_rxeof(sc); 1635 ste_reset(sc); 1636 ste_init(sc); 1637 1638 if (ifp->if_snd.ifq_head != NULL) 1639 ste_start(ifp); 1640 STE_UNLOCK(sc); 1641 1642 return; 1643} 1644 1645static void 1646ste_shutdown(dev) 1647 device_t dev; 1648{ 1649 struct ste_softc *sc; 1650 1651 sc = device_get_softc(dev); 1652 1653 ste_stop(sc); 1654 1655 return; 1656} 1657