if_ste.c revision 112880
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 112880 2003-03-31 20:22:00Z jhb $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48#include <net/if_vlan_var.h> 49 50#include <net/bpf.h> 51 52#include <vm/vm.h> /* for vtophys */ 53#include <vm/pmap.h> /* for vtophys */ 54#include <machine/bus_memio.h> 55#include <machine/bus_pio.h> 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <pci/pcireg.h> 65#include <pci/pcivar.h> 66 67/* "controller miibus0" required. See GENERIC if you get errors here. */ 68#include "miibus_if.h" 69 70#define STE_USEIOSPACE 71 72#include <pci/if_stereg.h> 73 74MODULE_DEPEND(ste, miibus, 1, 1, 1); 75 76#if !defined(lint) 77static const char rcsid[] = 78 "$FreeBSD: head/sys/pci/if_ste.c 112880 2003-03-31 20:22:00Z jhb $"; 79#endif 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 87 { 0, 0, NULL } 88}; 89 90static int ste_probe (device_t); 91static int ste_attach (device_t); 92static int ste_detach (device_t); 93static void ste_init (void *); 94static void ste_intr (void *); 95static void ste_rxeof (struct ste_softc *); 96static void ste_txeoc (struct ste_softc *); 97static void ste_txeof (struct ste_softc *); 98static void ste_stats_update (void *); 99static void ste_stop (struct ste_softc *); 100static void ste_reset (struct ste_softc *); 101static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104static void ste_start (struct ifnet *); 105static void ste_watchdog (struct ifnet *); 106static void ste_shutdown (device_t); 107static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd (struct ifnet *); 111static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113static void ste_mii_sync (struct ste_softc *); 114static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg (device_t, int, int); 118static int ste_miibus_writereg (device_t, int, int, int); 119static void ste_miibus_statchg (device_t); 120 121static int ste_eeprom_wait (struct ste_softc *); 122static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123static void ste_wait (struct ste_softc *); 124static u_int8_t ste_calchash (caddr_t); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167#define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 169 170#define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 172 173#define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 175 176#define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 178 179#define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 181 182#define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 184 185 186#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189/* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192static void 193ste_mii_sync(sc) 194 struct ste_softc *sc; 195{ 196 register int i; 197 198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 199 200 for (i = 0; i < 32; i++) { 201 MII_SET(STE_PHYCTL_MCLK); 202 DELAY(1); 203 MII_CLR(STE_PHYCTL_MCLK); 204 DELAY(1); 205 } 206 207 return; 208} 209 210/* 211 * Clock a series of bits through the MII. 212 */ 213static void 214ste_mii_send(sc, bits, cnt) 215 struct ste_softc *sc; 216 u_int32_t bits; 217 int cnt; 218{ 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234} 235 236/* 237 * Read an PHY register through the MII. 238 */ 239static int 240ste_mii_readreg(sc, frame) 241 struct ste_softc *sc; 242 struct ste_mii_frame *frame; 243 244{ 245 int i, ack; 246 247 STE_LOCK(sc); 248 249 /* 250 * Set up frame for RX. 251 */ 252 frame->mii_stdelim = STE_MII_STARTDELIM; 253 frame->mii_opcode = STE_MII_READOP; 254 frame->mii_turnaround = 0; 255 frame->mii_data = 0; 256 257 CSR_WRITE_2(sc, STE_PHYCTL, 0); 258 /* 259 * Turn on data xmit. 260 */ 261 MII_SET(STE_PHYCTL_MDIR); 262 263 ste_mii_sync(sc); 264 265 /* 266 * Send command/address info. 267 */ 268 ste_mii_send(sc, frame->mii_stdelim, 2); 269 ste_mii_send(sc, frame->mii_opcode, 2); 270 ste_mii_send(sc, frame->mii_phyaddr, 5); 271 ste_mii_send(sc, frame->mii_regaddr, 5); 272 273 /* Turn off xmit. */ 274 MII_CLR(STE_PHYCTL_MDIR); 275 276 /* Idle bit */ 277 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 278 DELAY(1); 279 MII_SET(STE_PHYCTL_MCLK); 280 DELAY(1); 281 282 /* Check for ack */ 283 MII_CLR(STE_PHYCTL_MCLK); 284 DELAY(1); 285 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 286 MII_SET(STE_PHYCTL_MCLK); 287 DELAY(1); 288 289 /* 290 * Now try reading data bits. If the ack failed, we still 291 * need to clock through 16 cycles to keep the PHY(s) in sync. 292 */ 293 if (ack) { 294 for(i = 0; i < 16; i++) { 295 MII_CLR(STE_PHYCTL_MCLK); 296 DELAY(1); 297 MII_SET(STE_PHYCTL_MCLK); 298 DELAY(1); 299 } 300 goto fail; 301 } 302 303 for (i = 0x8000; i; i >>= 1) { 304 MII_CLR(STE_PHYCTL_MCLK); 305 DELAY(1); 306 if (!ack) { 307 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 308 frame->mii_data |= i; 309 DELAY(1); 310 } 311 MII_SET(STE_PHYCTL_MCLK); 312 DELAY(1); 313 } 314 315fail: 316 317 MII_CLR(STE_PHYCTL_MCLK); 318 DELAY(1); 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 322 STE_UNLOCK(sc); 323 324 if (ack) 325 return(1); 326 return(0); 327} 328 329/* 330 * Write to a PHY register through the MII. 331 */ 332static int 333ste_mii_writereg(sc, frame) 334 struct ste_softc *sc; 335 struct ste_mii_frame *frame; 336 337{ 338 STE_LOCK(sc); 339 340 /* 341 * Set up frame for TX. 342 */ 343 344 frame->mii_stdelim = STE_MII_STARTDELIM; 345 frame->mii_opcode = STE_MII_WRITEOP; 346 frame->mii_turnaround = STE_MII_TURNAROUND; 347 348 /* 349 * Turn on data output. 350 */ 351 MII_SET(STE_PHYCTL_MDIR); 352 353 ste_mii_sync(sc); 354 355 ste_mii_send(sc, frame->mii_stdelim, 2); 356 ste_mii_send(sc, frame->mii_opcode, 2); 357 ste_mii_send(sc, frame->mii_phyaddr, 5); 358 ste_mii_send(sc, frame->mii_regaddr, 5); 359 ste_mii_send(sc, frame->mii_turnaround, 2); 360 ste_mii_send(sc, frame->mii_data, 16); 361 362 /* Idle bit. */ 363 MII_SET(STE_PHYCTL_MCLK); 364 DELAY(1); 365 MII_CLR(STE_PHYCTL_MCLK); 366 DELAY(1); 367 368 /* 369 * Turn off xmit. 370 */ 371 MII_CLR(STE_PHYCTL_MDIR); 372 373 STE_UNLOCK(sc); 374 375 return(0); 376} 377 378static int 379ste_miibus_readreg(dev, phy, reg) 380 device_t dev; 381 int phy, reg; 382{ 383 struct ste_softc *sc; 384 struct ste_mii_frame frame; 385 386 sc = device_get_softc(dev); 387 388 if ( sc->ste_one_phy && phy != 0 ) 389 return (0); 390 391 bzero((char *)&frame, sizeof(frame)); 392 393 frame.mii_phyaddr = phy; 394 frame.mii_regaddr = reg; 395 ste_mii_readreg(sc, &frame); 396 397 return(frame.mii_data); 398} 399 400static int 401ste_miibus_writereg(dev, phy, reg, data) 402 device_t dev; 403 int phy, reg, data; 404{ 405 struct ste_softc *sc; 406 struct ste_mii_frame frame; 407 408 sc = device_get_softc(dev); 409 bzero((char *)&frame, sizeof(frame)); 410 411 frame.mii_phyaddr = phy; 412 frame.mii_regaddr = reg; 413 frame.mii_data = data; 414 415 ste_mii_writereg(sc, &frame); 416 417 return(0); 418} 419 420static void 421ste_miibus_statchg(dev) 422 device_t dev; 423{ 424 struct ste_softc *sc; 425 struct mii_data *mii; 426 427 sc = device_get_softc(dev); 428 STE_LOCK(sc); 429 mii = device_get_softc(sc->ste_miibus); 430 431 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 432 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } else { 434 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 435 } 436 STE_UNLOCK(sc); 437 438 return; 439} 440 441static int 442ste_ifmedia_upd(ifp) 443 struct ifnet *ifp; 444{ 445 struct ste_softc *sc; 446 struct mii_data *mii; 447 448 sc = ifp->if_softc; 449 mii = device_get_softc(sc->ste_miibus); 450 sc->ste_link = 0; 451 if (mii->mii_instance) { 452 struct mii_softc *miisc; 453 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 454 mii_phy_reset(miisc); 455 } 456 mii_mediachg(mii); 457 458 return(0); 459} 460 461static void 462ste_ifmedia_sts(ifp, ifmr) 463 struct ifnet *ifp; 464 struct ifmediareq *ifmr; 465{ 466 struct ste_softc *sc; 467 struct mii_data *mii; 468 469 sc = ifp->if_softc; 470 mii = device_get_softc(sc->ste_miibus); 471 472 mii_pollstat(mii); 473 ifmr->ifm_active = mii->mii_media_active; 474 ifmr->ifm_status = mii->mii_media_status; 475 476 return; 477} 478 479static void 480ste_wait(sc) 481 struct ste_softc *sc; 482{ 483 register int i; 484 485 for (i = 0; i < STE_TIMEOUT; i++) { 486 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 487 break; 488 } 489 490 if (i == STE_TIMEOUT) 491 printf("ste%d: command never completed!\n", sc->ste_unit); 492 493 return; 494} 495 496/* 497 * The EEPROM is slow: give it time to come ready after issuing 498 * it a command. 499 */ 500static int 501ste_eeprom_wait(sc) 502 struct ste_softc *sc; 503{ 504 int i; 505 506 DELAY(1000); 507 508 for (i = 0; i < 100; i++) { 509 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 510 DELAY(1000); 511 else 512 break; 513 } 514 515 if (i == 100) { 516 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 517 return(1); 518 } 519 520 return(0); 521} 522 523/* 524 * Read a sequence of words from the EEPROM. Note that ethernet address 525 * data is stored in the EEPROM in network byte order. 526 */ 527static int 528ste_read_eeprom(sc, dest, off, cnt, swap) 529 struct ste_softc *sc; 530 caddr_t dest; 531 int off; 532 int cnt; 533 int swap; 534{ 535 int err = 0, i; 536 u_int16_t word = 0, *ptr; 537 538 if (ste_eeprom_wait(sc)) 539 return(1); 540 541 for (i = 0; i < cnt; i++) { 542 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 543 err = ste_eeprom_wait(sc); 544 if (err) 545 break; 546 word = CSR_READ_2(sc, STE_EEPROM_DATA); 547 ptr = (u_int16_t *)(dest + (i * 2)); 548 if (swap) 549 *ptr = ntohs(word); 550 else 551 *ptr = word; 552 } 553 554 return(err ? 1 : 0); 555} 556 557static u_int8_t 558ste_calchash(addr) 559 caddr_t addr; 560{ 561 562 u_int32_t crc, carry; 563 int i, j; 564 u_int8_t c; 565 566 /* Compute CRC for the address value. */ 567 crc = 0xFFFFFFFF; /* initial value */ 568 569 for (i = 0; i < 6; i++) { 570 c = *(addr + i); 571 for (j = 0; j < 8; j++) { 572 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 573 crc <<= 1; 574 c >>= 1; 575 if (carry) 576 crc = (crc ^ 0x04c11db6) | carry; 577 } 578 } 579 580 /* return the filter bit position */ 581 return(crc & 0x0000003F); 582} 583 584static void 585ste_setmulti(sc) 586 struct ste_softc *sc; 587{ 588 struct ifnet *ifp; 589 int h = 0; 590 u_int32_t hashes[2] = { 0, 0 }; 591 struct ifmultiaddr *ifma; 592 593 ifp = &sc->arpcom.ac_if; 594 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 595 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 596 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 597 return; 598 } 599 600 /* first, zot all the existing hash bits */ 601 CSR_WRITE_2(sc, STE_MAR0, 0); 602 CSR_WRITE_2(sc, STE_MAR1, 0); 603 CSR_WRITE_2(sc, STE_MAR2, 0); 604 CSR_WRITE_2(sc, STE_MAR3, 0); 605 606 /* now program new ones */ 607 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 608 if (ifma->ifma_addr->sa_family != AF_LINK) 609 continue; 610 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 611 if (h < 32) 612 hashes[0] |= (1 << h); 613 else 614 hashes[1] |= (1 << (h - 32)); 615 } 616 617 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 619 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 620 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 621 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 622 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 623 624 return; 625} 626 627static void 628ste_intr(xsc) 629 void *xsc; 630{ 631 struct ste_softc *sc; 632 struct ifnet *ifp; 633 u_int16_t status; 634 635 sc = xsc; 636 STE_LOCK(sc); 637 ifp = &sc->arpcom.ac_if; 638 639 /* See if this is really our interrupt. */ 640 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 641 STE_UNLOCK(sc); 642 return; 643 } 644 645 for (;;) { 646 status = CSR_READ_2(sc, STE_ISR_ACK); 647 648 if (!(status & STE_INTRS)) 649 break; 650 651 if (status & STE_ISR_RX_DMADONE) 652 ste_rxeof(sc); 653 654 if (status & STE_ISR_TX_DMADONE) 655 ste_txeof(sc); 656 657 if (status & STE_ISR_TX_DONE) 658 ste_txeoc(sc); 659 660 if (status & STE_ISR_STATS_OFLOW) { 661 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 662 ste_stats_update(sc); 663 } 664 665 if (status & STE_ISR_LINKEVENT) 666 mii_pollstat(device_get_softc(sc->ste_miibus)); 667 668 669 if (status & STE_ISR_HOSTERR) { 670 ste_reset(sc); 671 ste_init(sc); 672 } 673 } 674 675 /* Re-enable interrupts */ 676 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 677 678 if (ifp->if_snd.ifq_head != NULL) 679 ste_start(ifp); 680 681 STE_UNLOCK(sc); 682 683 return; 684} 685 686/* 687 * A frame has been uploaded: pass the resulting mbuf chain up to 688 * the higher level protocols. 689 */ 690static void 691ste_rxeof(sc) 692 struct ste_softc *sc; 693{ 694 struct mbuf *m; 695 struct ifnet *ifp; 696 struct ste_chain_onefrag *cur_rx; 697 int total_len = 0, count=0; 698 u_int32_t rxstat; 699 700 ifp = &sc->arpcom.ac_if; 701 702 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 703 & STE_RXSTAT_DMADONE) { 704 if ((STE_RX_LIST_CNT - count) < 3) { 705 break; 706 } 707 708 cur_rx = sc->ste_cdata.ste_rx_head; 709 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 710 711 /* 712 * If an error occurs, update stats, clear the 713 * status word and leave the mbuf cluster in place: 714 * it should simply get re-used next time this descriptor 715 * comes up in the ring. 716 */ 717 if (rxstat & STE_RXSTAT_FRAME_ERR) { 718 ifp->if_ierrors++; 719 cur_rx->ste_ptr->ste_status = 0; 720 continue; 721 } 722 723 /* 724 * If there error bit was not set, the upload complete 725 * bit should be set which means we have a valid packet. 726 * If not, something truly strange has happened. 727 */ 728 if (!(rxstat & STE_RXSTAT_DMADONE)) { 729 printf("ste%d: bad receive status -- packet dropped\n", 730 sc->ste_unit); 731 ifp->if_ierrors++; 732 cur_rx->ste_ptr->ste_status = 0; 733 continue; 734 } 735 736 /* No errors; receive the packet. */ 737 m = cur_rx->ste_mbuf; 738 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 739 740 /* 741 * Try to conjure up a new mbuf cluster. If that 742 * fails, it means we have an out of memory condition and 743 * should leave the buffer in place and continue. This will 744 * result in a lost packet, but there's little else we 745 * can do in this situation. 746 */ 747 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 748 ifp->if_ierrors++; 749 cur_rx->ste_ptr->ste_status = 0; 750 continue; 751 } 752 753 m->m_pkthdr.rcvif = ifp; 754 m->m_pkthdr.len = m->m_len = total_len; 755 756 ifp->if_ipackets++; 757 (*ifp->if_input)(ifp, m); 758 759 cur_rx->ste_ptr->ste_status = 0; 760 count++; 761 } 762 763 return; 764} 765 766static void 767ste_txeoc(sc) 768 struct ste_softc *sc; 769{ 770 u_int8_t txstat; 771 struct ifnet *ifp; 772 773 ifp = &sc->arpcom.ac_if; 774 775 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 776 STE_TXSTATUS_TXDONE) { 777 if (txstat & STE_TXSTATUS_UNDERRUN || 778 txstat & STE_TXSTATUS_EXCESSCOLLS || 779 txstat & STE_TXSTATUS_RECLAIMERR) { 780 ifp->if_oerrors++; 781 printf("ste%d: transmission error: %x\n", 782 sc->ste_unit, txstat); 783 784 ste_reset(sc); 785 ste_init(sc); 786 787 if (txstat & STE_TXSTATUS_UNDERRUN && 788 sc->ste_tx_thresh < STE_PACKET_SIZE) { 789 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 790 printf("ste%d: tx underrun, increasing tx" 791 " start threshold to %d bytes\n", 792 sc->ste_unit, sc->ste_tx_thresh); 793 } 794 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 795 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 796 (STE_PACKET_SIZE >> 4)); 797 } 798 ste_init(sc); 799 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 800 } 801 802 return; 803} 804 805static void 806ste_txeof(sc) 807 struct ste_softc *sc; 808{ 809 struct ste_chain *cur_tx = NULL; 810 struct ifnet *ifp; 811 int idx; 812 813 ifp = &sc->arpcom.ac_if; 814 815 idx = sc->ste_cdata.ste_tx_cons; 816 while(idx != sc->ste_cdata.ste_tx_prod) { 817 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 818 819 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 820 break; 821 822 if (cur_tx->ste_mbuf != NULL) { 823 m_freem(cur_tx->ste_mbuf); 824 cur_tx->ste_mbuf = NULL; 825 } 826 827 ifp->if_opackets++; 828 829 sc->ste_cdata.ste_tx_cnt--; 830 STE_INC(idx, STE_TX_LIST_CNT); 831 ifp->if_timer = 0; 832 } 833 834 sc->ste_cdata.ste_tx_cons = idx; 835 836 if (cur_tx != NULL) 837 ifp->if_flags &= ~IFF_OACTIVE; 838 839 return; 840} 841 842static void 843ste_stats_update(xsc) 844 void *xsc; 845{ 846 struct ste_softc *sc; 847 struct ifnet *ifp; 848 struct mii_data *mii; 849 850 sc = xsc; 851 STE_LOCK(sc); 852 853 ifp = &sc->arpcom.ac_if; 854 mii = device_get_softc(sc->ste_miibus); 855 856 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 857 + CSR_READ_1(sc, STE_MULTI_COLLS) 858 + CSR_READ_1(sc, STE_SINGLE_COLLS); 859 860 if (!sc->ste_link) { 861 mii_pollstat(mii); 862 if (mii->mii_media_status & IFM_ACTIVE && 863 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 864 sc->ste_link++; 865 /* 866 * we don't get a call-back on re-init so do it 867 * otherwise we get stuck in the wrong link state 868 */ 869 ste_miibus_statchg(sc->ste_dev); 870 if (ifp->if_snd.ifq_head != NULL) 871 ste_start(ifp); 872 } 873 } 874 875 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 876 STE_UNLOCK(sc); 877 878 return; 879} 880 881 882/* 883 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 884 * IDs against our list and return a device name if we find a match. 885 */ 886static int 887ste_probe(dev) 888 device_t dev; 889{ 890 struct ste_type *t; 891 892 t = ste_devs; 893 894 while(t->ste_name != NULL) { 895 if ((pci_get_vendor(dev) == t->ste_vid) && 896 (pci_get_device(dev) == t->ste_did)) { 897 device_set_desc(dev, t->ste_name); 898 return(0); 899 } 900 t++; 901 } 902 903 return(ENXIO); 904} 905 906/* 907 * Attach the interface. Allocate softc structures, do ifmedia 908 * setup and ethernet/BPF attach. 909 */ 910static int 911ste_attach(dev) 912 device_t dev; 913{ 914 u_int32_t command; 915 struct ste_softc *sc; 916 struct ifnet *ifp; 917 int unit, error = 0, rid; 918 919 sc = device_get_softc(dev); 920 unit = device_get_unit(dev); 921 sc->ste_dev = dev; 922 923 /* 924 * Only use one PHY since this chip reports multiple 925 * Note on the DFE-550 the PHY is at 1 on the DFE-580 926 * it is at 0 & 1. It is rev 0x12. 927 */ 928 if (pci_get_vendor(dev) == DL_VENDORID && 929 pci_get_device(dev) == DL_DEVICEID_DL10050 && 930 pci_get_revid(dev) == 0x12 ) 931 sc->ste_one_phy = 1; 932 933 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 934 MTX_DEF | MTX_RECURSE); 935 936 /* 937 * Handle power management nonsense. 938 */ 939 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 940 u_int32_t iobase, membase, irq; 941 942 /* Save important PCI config data. */ 943 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 944 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 945 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 946 947 /* Reset the power state. */ 948 printf("ste%d: chip is in D%d power mode " 949 "-- setting to D0\n", unit, 950 pci_get_powerstate(dev)); 951 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 952 953 /* Restore PCI config data. */ 954 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 955 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 956 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 957 } 958 959 /* 960 * Map control/status registers. 961 */ 962 pci_enable_busmaster(dev); 963 pci_enable_io(dev, SYS_RES_IOPORT); 964 pci_enable_io(dev, SYS_RES_MEMORY); 965 command = pci_read_config(dev, PCIR_COMMAND, 4); 966 967#ifdef STE_USEIOSPACE 968 if (!(command & PCIM_CMD_PORTEN)) { 969 printf("ste%d: failed to enable I/O ports!\n", unit); 970 error = ENXIO; 971 goto fail; 972 } 973#else 974 if (!(command & PCIM_CMD_MEMEN)) { 975 printf("ste%d: failed to enable memory mapping!\n", unit); 976 error = ENXIO; 977 goto fail; 978 } 979#endif 980 981 rid = STE_RID; 982 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 983 0, ~0, 1, RF_ACTIVE); 984 985 if (sc->ste_res == NULL) { 986 printf ("ste%d: couldn't map ports/memory\n", unit); 987 error = ENXIO; 988 goto fail; 989 } 990 991 sc->ste_btag = rman_get_bustag(sc->ste_res); 992 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 993 994 /* Allocate interrupt */ 995 rid = 0; 996 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 997 RF_SHAREABLE | RF_ACTIVE); 998 999 if (sc->ste_irq == NULL) { 1000 printf("ste%d: couldn't map interrupt\n", unit); 1001 error = ENXIO; 1002 goto fail; 1003 } 1004 1005 callout_handle_init(&sc->ste_stat_ch); 1006 1007 /* Reset the adapter. */ 1008 ste_reset(sc); 1009 1010 /* 1011 * Get station address from the EEPROM. 1012 */ 1013 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1014 STE_EEADDR_NODE0, 3, 0)) { 1015 printf("ste%d: failed to read station address\n", unit); 1016 error = ENXIO;; 1017 goto fail; 1018 } 1019 1020 /* 1021 * A Sundance chip was detected. Inform the world. 1022 */ 1023 printf("ste%d: Ethernet address: %6D\n", unit, 1024 sc->arpcom.ac_enaddr, ":"); 1025 1026 sc->ste_unit = unit; 1027 1028 /* Allocate the descriptor queues. */ 1029 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1030 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1031 1032 if (sc->ste_ldata == NULL) { 1033 printf("ste%d: no memory for list buffers!\n", unit); 1034 error = ENXIO; 1035 goto fail; 1036 } 1037 1038 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1039 1040 /* Do MII setup. */ 1041 if (mii_phy_probe(dev, &sc->ste_miibus, 1042 ste_ifmedia_upd, ste_ifmedia_sts)) { 1043 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1044 error = ENXIO; 1045 goto fail; 1046 } 1047 1048 ifp = &sc->arpcom.ac_if; 1049 ifp->if_softc = sc; 1050 ifp->if_unit = unit; 1051 ifp->if_name = "ste"; 1052 ifp->if_mtu = ETHERMTU; 1053 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1054 ifp->if_ioctl = ste_ioctl; 1055 ifp->if_output = ether_output; 1056 ifp->if_start = ste_start; 1057 ifp->if_watchdog = ste_watchdog; 1058 ifp->if_init = ste_init; 1059 ifp->if_baudrate = 10000000; 1060 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1061 1062 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1063 1064 /* 1065 * Call MI attach routine. 1066 */ 1067 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1068 1069 /* 1070 * Tell the upper layer(s) we support long frames. 1071 */ 1072 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1073 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1074 1075 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1076 ste_intr, sc, &sc->ste_intrhand); 1077 1078 if (error) { 1079 printf("ste%d: couldn't set up irq\n", unit); 1080 goto fail; 1081 } 1082 1083fail: 1084 if (error) 1085 ste_detach(dev); 1086 1087 return(error); 1088} 1089 1090static int 1091ste_detach(dev) 1092 device_t dev; 1093{ 1094 struct ste_softc *sc; 1095 struct ifnet *ifp; 1096 1097 sc = device_get_softc(dev); 1098 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1099 STE_LOCK(sc); 1100 ifp = &sc->arpcom.ac_if; 1101 1102 if (device_is_alive(dev)) { 1103 if (bus_child_present(dev)) 1104 ste_stop(sc); 1105 ether_ifdetach(ifp); 1106 device_delete_child(dev, sc->ste_miibus); 1107 bus_generic_detach(dev); 1108 } 1109 1110 if (sc->ste_intrhand) 1111 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1112 if (sc->ste_irq) 1113 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1114 if (sc->ste_res) 1115 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1116 1117 if (sc->ste_ldata) { 1118 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1119 M_DEVBUF); 1120 } 1121 1122 STE_UNLOCK(sc); 1123 mtx_destroy(&sc->ste_mtx); 1124 1125 return(0); 1126} 1127 1128static int 1129ste_newbuf(sc, c, m) 1130 struct ste_softc *sc; 1131 struct ste_chain_onefrag *c; 1132 struct mbuf *m; 1133{ 1134 struct mbuf *m_new = NULL; 1135 1136 if (m == NULL) { 1137 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1138 if (m_new == NULL) 1139 return(ENOBUFS); 1140 MCLGET(m_new, M_DONTWAIT); 1141 if (!(m_new->m_flags & M_EXT)) { 1142 m_freem(m_new); 1143 return(ENOBUFS); 1144 } 1145 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1146 } else { 1147 m_new = m; 1148 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1149 m_new->m_data = m_new->m_ext.ext_buf; 1150 } 1151 1152 m_adj(m_new, ETHER_ALIGN); 1153 1154 c->ste_mbuf = m_new; 1155 c->ste_ptr->ste_status = 0; 1156 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1157 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1158 1159 return(0); 1160} 1161 1162static int 1163ste_init_rx_list(sc) 1164 struct ste_softc *sc; 1165{ 1166 struct ste_chain_data *cd; 1167 struct ste_list_data *ld; 1168 int i; 1169 1170 cd = &sc->ste_cdata; 1171 ld = sc->ste_ldata; 1172 1173 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1174 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1175 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1176 return(ENOBUFS); 1177 if (i == (STE_RX_LIST_CNT - 1)) { 1178 cd->ste_rx_chain[i].ste_next = 1179 &cd->ste_rx_chain[0]; 1180 ld->ste_rx_list[i].ste_next = 1181 vtophys(&ld->ste_rx_list[0]); 1182 } else { 1183 cd->ste_rx_chain[i].ste_next = 1184 &cd->ste_rx_chain[i + 1]; 1185 ld->ste_rx_list[i].ste_next = 1186 vtophys(&ld->ste_rx_list[i + 1]); 1187 } 1188 ld->ste_rx_list[i].ste_status = 0; 1189 } 1190 1191 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1192 1193 return(0); 1194} 1195 1196static void 1197ste_init_tx_list(sc) 1198 struct ste_softc *sc; 1199{ 1200 struct ste_chain_data *cd; 1201 struct ste_list_data *ld; 1202 int i; 1203 1204 cd = &sc->ste_cdata; 1205 ld = sc->ste_ldata; 1206 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1207 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1208 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1209 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1210 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1211 if (i == (STE_TX_LIST_CNT - 1)) 1212 cd->ste_tx_chain[i].ste_next = 1213 &cd->ste_tx_chain[0]; 1214 else 1215 cd->ste_tx_chain[i].ste_next = 1216 &cd->ste_tx_chain[i + 1]; 1217 if (i == 0) 1218 cd->ste_tx_chain[i].ste_prev = 1219 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1220 else 1221 cd->ste_tx_chain[i].ste_prev = 1222 &cd->ste_tx_chain[i - 1]; 1223 } 1224 1225 cd->ste_tx_prod = 0; 1226 cd->ste_tx_cons = 0; 1227 cd->ste_tx_cnt = 0; 1228 1229 return; 1230} 1231 1232static void 1233ste_init(xsc) 1234 void *xsc; 1235{ 1236 struct ste_softc *sc; 1237 int i; 1238 struct ifnet *ifp; 1239 struct mii_data *mii; 1240 1241 sc = xsc; 1242 STE_LOCK(sc); 1243 ifp = &sc->arpcom.ac_if; 1244 mii = device_get_softc(sc->ste_miibus); 1245 1246 ste_stop(sc); 1247 1248 /* Init our MAC address */ 1249 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1250 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1251 } 1252 1253 /* Init RX list */ 1254 if (ste_init_rx_list(sc) == ENOBUFS) { 1255 printf("ste%d: initialization failed: no " 1256 "memory for RX buffers\n", sc->ste_unit); 1257 ste_stop(sc); 1258 STE_UNLOCK(sc); 1259 return; 1260 } 1261 1262 /* Set RX polling interval */ 1263 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1264 1265 /* Init TX descriptors */ 1266 ste_init_tx_list(sc); 1267 1268 /* Set the TX freethresh value */ 1269 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1270 1271 /* Set the TX start threshold for best performance. */ 1272 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1273 1274 /* Set the TX reclaim threshold. */ 1275 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1276 1277 /* Set up the RX filter. */ 1278 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1279 1280 /* If we want promiscuous mode, set the allframes bit. */ 1281 if (ifp->if_flags & IFF_PROMISC) { 1282 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1283 } else { 1284 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1285 } 1286 1287 /* Set capture broadcast bit to accept broadcast frames. */ 1288 if (ifp->if_flags & IFF_BROADCAST) { 1289 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1290 } else { 1291 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1292 } 1293 1294 ste_setmulti(sc); 1295 1296 /* Load the address of the RX list. */ 1297 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1298 ste_wait(sc); 1299 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1300 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1302 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1303 1304 /* Set TX polling interval (defer until we TX first packet */ 1305 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1306 1307 /* Load address of the TX list */ 1308 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1309 ste_wait(sc); 1310 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1311 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1312 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1313 ste_wait(sc); 1314 sc->ste_tx_prev_idx=-1; 1315 1316 /* Enable receiver and transmitter */ 1317 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1318 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1319 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1320 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1321 1322 /* Enable stats counters. */ 1323 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1324 1325 /* Enable interrupts. */ 1326 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1327 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1328 1329 /* Accept VLAN length packets */ 1330 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1331 1332 ste_ifmedia_upd(ifp); 1333 1334 ifp->if_flags |= IFF_RUNNING; 1335 ifp->if_flags &= ~IFF_OACTIVE; 1336 1337 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1338 STE_UNLOCK(sc); 1339 1340 return; 1341} 1342 1343static void 1344ste_stop(sc) 1345 struct ste_softc *sc; 1346{ 1347 int i; 1348 struct ifnet *ifp; 1349 1350 STE_LOCK(sc); 1351 ifp = &sc->arpcom.ac_if; 1352 1353 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1354 1355 CSR_WRITE_2(sc, STE_IMR, 0); 1356 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1357 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1358 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1359 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1360 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1361 ste_wait(sc); 1362 /* 1363 * Try really hard to stop the RX engine or under heavy RX 1364 * data chip will write into de-allocated memory. 1365 */ 1366 ste_reset(sc); 1367 1368 sc->ste_link = 0; 1369 1370 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1371 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1372 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1373 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1374 } 1375 } 1376 1377 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1378 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1379 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1380 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1381 } 1382 } 1383 1384 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1385 1386 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1387 STE_UNLOCK(sc); 1388 1389 return; 1390} 1391 1392static void 1393ste_reset(sc) 1394 struct ste_softc *sc; 1395{ 1396 int i; 1397 1398 STE_SETBIT4(sc, STE_ASICCTL, 1399 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1400 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1401 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1402 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1403 STE_ASICCTL_EXTRESET_RESET); 1404 1405 DELAY(100000); 1406 1407 for (i = 0; i < STE_TIMEOUT; i++) { 1408 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1409 break; 1410 } 1411 1412 if (i == STE_TIMEOUT) 1413 printf("ste%d: global reset never completed\n", sc->ste_unit); 1414 1415 return; 1416} 1417 1418static int 1419ste_ioctl(ifp, command, data) 1420 struct ifnet *ifp; 1421 u_long command; 1422 caddr_t data; 1423{ 1424 struct ste_softc *sc; 1425 struct ifreq *ifr; 1426 struct mii_data *mii; 1427 int error = 0; 1428 1429 sc = ifp->if_softc; 1430 STE_LOCK(sc); 1431 ifr = (struct ifreq *)data; 1432 1433 switch(command) { 1434 case SIOCSIFFLAGS: 1435 if (ifp->if_flags & IFF_UP) { 1436 if (ifp->if_flags & IFF_RUNNING && 1437 ifp->if_flags & IFF_PROMISC && 1438 !(sc->ste_if_flags & IFF_PROMISC)) { 1439 STE_SETBIT1(sc, STE_RX_MODE, 1440 STE_RXMODE_PROMISC); 1441 } else if (ifp->if_flags & IFF_RUNNING && 1442 !(ifp->if_flags & IFF_PROMISC) && 1443 sc->ste_if_flags & IFF_PROMISC) { 1444 STE_CLRBIT1(sc, STE_RX_MODE, 1445 STE_RXMODE_PROMISC); 1446 } 1447 if (!(ifp->if_flags & IFF_RUNNING)) { 1448 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1449 ste_init(sc); 1450 } 1451 } else { 1452 if (ifp->if_flags & IFF_RUNNING) 1453 ste_stop(sc); 1454 } 1455 sc->ste_if_flags = ifp->if_flags; 1456 error = 0; 1457 break; 1458 case SIOCADDMULTI: 1459 case SIOCDELMULTI: 1460 ste_setmulti(sc); 1461 error = 0; 1462 break; 1463 case SIOCGIFMEDIA: 1464 case SIOCSIFMEDIA: 1465 mii = device_get_softc(sc->ste_miibus); 1466 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1467 break; 1468 default: 1469 error = ether_ioctl(ifp, command, data); 1470 break; 1471 } 1472 1473 STE_UNLOCK(sc); 1474 1475 return(error); 1476} 1477 1478static int 1479ste_encap(sc, c, m_head) 1480 struct ste_softc *sc; 1481 struct ste_chain *c; 1482 struct mbuf *m_head; 1483{ 1484 int frag = 0; 1485 struct ste_frag *f = NULL; 1486 struct mbuf *m; 1487 struct ste_desc *d; 1488 int total_len = 0; 1489 1490 d = c->ste_ptr; 1491 d->ste_ctl = 0; 1492 1493encap_retry: 1494 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1495 if (m->m_len != 0) { 1496 if (frag == STE_MAXFRAGS) 1497 break; 1498 total_len += m->m_len; 1499 f = &d->ste_frags[frag]; 1500 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1501 f->ste_len = m->m_len; 1502 frag++; 1503 } 1504 } 1505 1506 if (m != NULL) { 1507 struct mbuf *mn; 1508 1509 /* 1510 * We ran out of segments. We have to recopy this 1511 * mbuf chain first. Bail out if we can't get the 1512 * new buffers. Code borrowed from if_fxp.c 1513 */ 1514 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1515 if (mn == NULL) { 1516 m_freem(m_head); 1517 return ENOMEM; 1518 } 1519 if (m_head->m_pkthdr.len > MHLEN) { 1520 MCLGET(mn, M_DONTWAIT); 1521 if ((mn->m_flags & M_EXT) == 0) { 1522 m_freem(mn); 1523 m_freem(m_head); 1524 return ENOMEM; 1525 } 1526 } 1527 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1528 mtod(mn, caddr_t)); 1529 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len; 1530 m_freem(m_head); 1531 m_head = mn; 1532 goto encap_retry; 1533 } 1534 1535 c->ste_mbuf = m_head; 1536 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1537 d->ste_ctl = 1; 1538 1539 return(0); 1540} 1541 1542static void 1543ste_start(ifp) 1544 struct ifnet *ifp; 1545{ 1546 struct ste_softc *sc; 1547 struct mbuf *m_head = NULL; 1548 struct ste_chain *cur_tx = NULL; 1549 int idx; 1550 1551 sc = ifp->if_softc; 1552 STE_LOCK(sc); 1553 1554 if (!sc->ste_link) { 1555 STE_UNLOCK(sc); 1556 return; 1557 } 1558 1559 if (ifp->if_flags & IFF_OACTIVE) { 1560 STE_UNLOCK(sc); 1561 return; 1562 } 1563 1564 idx = sc->ste_cdata.ste_tx_prod; 1565 1566 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1567 1568 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1569 ifp->if_flags |= IFF_OACTIVE; 1570 break; 1571 } 1572 1573 IF_DEQUEUE(&ifp->if_snd, m_head); 1574 if (m_head == NULL) 1575 break; 1576 1577 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1578 1579 if (ste_encap(sc, cur_tx, m_head) != 0) 1580 break; 1581 1582 cur_tx->ste_ptr->ste_next = 0; 1583 1584 if(sc->ste_tx_prev_idx < 0){ 1585 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1586 /* Load address of the TX list */ 1587 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1588 ste_wait(sc); 1589 1590 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1591 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1592 1593 /* Set TX polling interval to start TX engine */ 1594 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1595 1596 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1597 ste_wait(sc); 1598 }else{ 1599 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1600 sc->ste_cdata.ste_tx_chain[ 1601 sc->ste_tx_prev_idx].ste_ptr->ste_next 1602 = cur_tx->ste_phys; 1603 } 1604 1605 sc->ste_tx_prev_idx=idx; 1606 1607 /* 1608 * If there's a BPF listener, bounce a copy of this frame 1609 * to him. 1610 */ 1611 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1612 1613 STE_INC(idx, STE_TX_LIST_CNT); 1614 sc->ste_cdata.ste_tx_cnt++; 1615 ifp->if_timer = 5; 1616 sc->ste_cdata.ste_tx_prod = idx; 1617 } 1618 1619 STE_UNLOCK(sc); 1620 1621 return; 1622} 1623 1624static void 1625ste_watchdog(ifp) 1626 struct ifnet *ifp; 1627{ 1628 struct ste_softc *sc; 1629 1630 sc = ifp->if_softc; 1631 STE_LOCK(sc); 1632 1633 ifp->if_oerrors++; 1634 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1635 1636 ste_txeoc(sc); 1637 ste_txeof(sc); 1638 ste_rxeof(sc); 1639 ste_reset(sc); 1640 ste_init(sc); 1641 1642 if (ifp->if_snd.ifq_head != NULL) 1643 ste_start(ifp); 1644 STE_UNLOCK(sc); 1645 1646 return; 1647} 1648 1649static void 1650ste_shutdown(dev) 1651 device_t dev; 1652{ 1653 struct ste_softc *sc; 1654 1655 sc = device_get_softc(dev); 1656 1657 ste_stop(sc); 1658 1659 return; 1660} 1661