if_ste.c revision 102113
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 102113 2002-08-19 16:54:26Z ambrisko $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48#include <net/if_vlan_var.h> 49 50#include <net/bpf.h> 51 52#include <vm/vm.h> /* for vtophys */ 53#include <vm/pmap.h> /* for vtophys */ 54#include <machine/bus_memio.h> 55#include <machine/bus_pio.h> 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <pci/pcireg.h> 65#include <pci/pcivar.h> 66 67/* "controller miibus0" required. See GENERIC if you get errors here. */ 68#include "miibus_if.h" 69 70#define STE_USEIOSPACE 71 72#include <pci/if_stereg.h> 73 74MODULE_DEPEND(ste, miibus, 1, 1, 1); 75 76#if !defined(lint) 77static const char rcsid[] = 78 "$FreeBSD: head/sys/pci/if_ste.c 102113 2002-08-19 16:54:26Z ambrisko $"; 79#endif 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 87 { 0, 0, NULL } 88}; 89 90static int ste_probe (device_t); 91static int ste_attach (device_t); 92static int ste_detach (device_t); 93static void ste_init (void *); 94static void ste_intr (void *); 95static void ste_rxeof (struct ste_softc *); 96static void ste_txeoc (struct ste_softc *); 97static void ste_txeof (struct ste_softc *); 98static void ste_stats_update (void *); 99static void ste_stop (struct ste_softc *); 100static void ste_reset (struct ste_softc *); 101static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104static void ste_start (struct ifnet *); 105static void ste_watchdog (struct ifnet *); 106static void ste_shutdown (device_t); 107static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd (struct ifnet *); 111static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113static void ste_mii_sync (struct ste_softc *); 114static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg (device_t, int, int); 118static int ste_miibus_writereg (device_t, int, int, int); 119static void ste_miibus_statchg (device_t); 120 121static int ste_eeprom_wait (struct ste_softc *); 122static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123static void ste_wait (struct ste_softc *); 124static u_int8_t ste_calchash (caddr_t); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167#define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170#define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173#define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 175 176#define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 178 179#define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 181 182#define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 184 185 186#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189/* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192static void ste_mii_sync(sc) 193 struct ste_softc *sc; 194{ 195 register int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205 206 return; 207} 208 209/* 210 * Clock a series of bits through the MII. 211 */ 212static void ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216{ 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232} 233 234/* 235 * Read an PHY register through the MII. 236 */ 237static int ste_mii_readreg(sc, frame) 238 struct ste_softc *sc; 239 struct ste_mii_frame *frame; 240 241{ 242 int i, ack; 243 244 STE_LOCK(sc); 245 246 /* 247 * Set up frame for RX. 248 */ 249 frame->mii_stdelim = STE_MII_STARTDELIM; 250 frame->mii_opcode = STE_MII_READOP; 251 frame->mii_turnaround = 0; 252 frame->mii_data = 0; 253 254 CSR_WRITE_2(sc, STE_PHYCTL, 0); 255 /* 256 * Turn on data xmit. 257 */ 258 MII_SET(STE_PHYCTL_MDIR); 259 260 ste_mii_sync(sc); 261 262 /* 263 * Send command/address info. 264 */ 265 ste_mii_send(sc, frame->mii_stdelim, 2); 266 ste_mii_send(sc, frame->mii_opcode, 2); 267 ste_mii_send(sc, frame->mii_phyaddr, 5); 268 ste_mii_send(sc, frame->mii_regaddr, 5); 269 270 /* Turn off xmit. */ 271 MII_CLR(STE_PHYCTL_MDIR); 272 273 /* Idle bit */ 274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 275 DELAY(1); 276 MII_SET(STE_PHYCTL_MCLK); 277 DELAY(1); 278 279 /* Check for ack */ 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 285 286 /* 287 * Now try reading data bits. If the ack failed, we still 288 * need to clock through 16 cycles to keep the PHY(s) in sync. 289 */ 290 if (ack) { 291 for(i = 0; i < 16; i++) { 292 MII_CLR(STE_PHYCTL_MCLK); 293 DELAY(1); 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 } 297 goto fail; 298 } 299 300 for (i = 0x8000; i; i >>= 1) { 301 MII_CLR(STE_PHYCTL_MCLK); 302 DELAY(1); 303 if (!ack) { 304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 305 frame->mii_data |= i; 306 DELAY(1); 307 } 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 } 311 312fail: 313 314 MII_CLR(STE_PHYCTL_MCLK); 315 DELAY(1); 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 319 STE_UNLOCK(sc); 320 321 if (ack) 322 return(1); 323 return(0); 324} 325 326/* 327 * Write to a PHY register through the MII. 328 */ 329static int ste_mii_writereg(sc, frame) 330 struct ste_softc *sc; 331 struct ste_mii_frame *frame; 332 333{ 334 STE_LOCK(sc); 335 336 /* 337 * Set up frame for TX. 338 */ 339 340 frame->mii_stdelim = STE_MII_STARTDELIM; 341 frame->mii_opcode = STE_MII_WRITEOP; 342 frame->mii_turnaround = STE_MII_TURNAROUND; 343 344 /* 345 * Turn on data output. 346 */ 347 MII_SET(STE_PHYCTL_MDIR); 348 349 ste_mii_sync(sc); 350 351 ste_mii_send(sc, frame->mii_stdelim, 2); 352 ste_mii_send(sc, frame->mii_opcode, 2); 353 ste_mii_send(sc, frame->mii_phyaddr, 5); 354 ste_mii_send(sc, frame->mii_regaddr, 5); 355 ste_mii_send(sc, frame->mii_turnaround, 2); 356 ste_mii_send(sc, frame->mii_data, 16); 357 358 /* Idle bit. */ 359 MII_SET(STE_PHYCTL_MCLK); 360 DELAY(1); 361 MII_CLR(STE_PHYCTL_MCLK); 362 DELAY(1); 363 364 /* 365 * Turn off xmit. 366 */ 367 MII_CLR(STE_PHYCTL_MDIR); 368 369 STE_UNLOCK(sc); 370 371 return(0); 372} 373 374static int ste_miibus_readreg(dev, phy, reg) 375 device_t dev; 376 int phy, reg; 377{ 378 struct ste_softc *sc; 379 struct ste_mii_frame frame; 380 381 sc = device_get_softc(dev); 382 383 if ( sc->ste_one_phy && phy != 0 ) 384 return (0); 385 386 bzero((char *)&frame, sizeof(frame)); 387 388 frame.mii_phyaddr = phy; 389 frame.mii_regaddr = reg; 390 ste_mii_readreg(sc, &frame); 391 392 return(frame.mii_data); 393} 394 395static int ste_miibus_writereg(dev, phy, reg, data) 396 device_t dev; 397 int phy, reg, data; 398{ 399 struct ste_softc *sc; 400 struct ste_mii_frame frame; 401 402 sc = device_get_softc(dev); 403 bzero((char *)&frame, sizeof(frame)); 404 405 frame.mii_phyaddr = phy; 406 frame.mii_regaddr = reg; 407 frame.mii_data = data; 408 409 ste_mii_writereg(sc, &frame); 410 411 return(0); 412} 413 414static void ste_miibus_statchg(dev) 415 device_t dev; 416{ 417 struct ste_softc *sc; 418 struct mii_data *mii; 419 420 sc = device_get_softc(dev); 421 STE_LOCK(sc); 422 mii = device_get_softc(sc->ste_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 426 } else { 427 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } 429 STE_UNLOCK(sc); 430 431 return; 432} 433 434static int ste_ifmedia_upd(ifp) 435 struct ifnet *ifp; 436{ 437 struct ste_softc *sc; 438 struct mii_data *mii; 439 440 sc = ifp->if_softc; 441 mii = device_get_softc(sc->ste_miibus); 442 sc->ste_link = 0; 443 if (mii->mii_instance) { 444 struct mii_softc *miisc; 445 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 446 mii_phy_reset(miisc); 447 } 448 mii_mediachg(mii); 449 450 return(0); 451} 452 453static void ste_ifmedia_sts(ifp, ifmr) 454 struct ifnet *ifp; 455 struct ifmediareq *ifmr; 456{ 457 struct ste_softc *sc; 458 struct mii_data *mii; 459 460 sc = ifp->if_softc; 461 mii = device_get_softc(sc->ste_miibus); 462 463 mii_pollstat(mii); 464 ifmr->ifm_active = mii->mii_media_active; 465 ifmr->ifm_status = mii->mii_media_status; 466 467 return; 468} 469 470static void ste_wait(sc) 471 struct ste_softc *sc; 472{ 473 register int i; 474 475 for (i = 0; i < STE_TIMEOUT; i++) { 476 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 477 break; 478 } 479 480 if (i == STE_TIMEOUT) 481 printf("ste%d: command never completed!\n", sc->ste_unit); 482 483 return; 484} 485 486/* 487 * The EEPROM is slow: give it time to come ready after issuing 488 * it a command. 489 */ 490static int ste_eeprom_wait(sc) 491 struct ste_softc *sc; 492{ 493 int i; 494 495 DELAY(1000); 496 497 for (i = 0; i < 100; i++) { 498 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 499 DELAY(1000); 500 else 501 break; 502 } 503 504 if (i == 100) { 505 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 506 return(1); 507 } 508 509 return(0); 510} 511 512/* 513 * Read a sequence of words from the EEPROM. Note that ethernet address 514 * data is stored in the EEPROM in network byte order. 515 */ 516static int ste_read_eeprom(sc, dest, off, cnt, swap) 517 struct ste_softc *sc; 518 caddr_t dest; 519 int off; 520 int cnt; 521 int swap; 522{ 523 int err = 0, i; 524 u_int16_t word = 0, *ptr; 525 526 if (ste_eeprom_wait(sc)) 527 return(1); 528 529 for (i = 0; i < cnt; i++) { 530 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 531 err = ste_eeprom_wait(sc); 532 if (err) 533 break; 534 word = CSR_READ_2(sc, STE_EEPROM_DATA); 535 ptr = (u_int16_t *)(dest + (i * 2)); 536 if (swap) 537 *ptr = ntohs(word); 538 else 539 *ptr = word; 540 } 541 542 return(err ? 1 : 0); 543} 544 545static u_int8_t ste_calchash(addr) 546 caddr_t addr; 547{ 548 549 u_int32_t crc, carry; 550 int i, j; 551 u_int8_t c; 552 553 /* Compute CRC for the address value. */ 554 crc = 0xFFFFFFFF; /* initial value */ 555 556 for (i = 0; i < 6; i++) { 557 c = *(addr + i); 558 for (j = 0; j < 8; j++) { 559 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 560 crc <<= 1; 561 c >>= 1; 562 if (carry) 563 crc = (crc ^ 0x04c11db6) | carry; 564 } 565 } 566 567 /* return the filter bit position */ 568 return(crc & 0x0000003F); 569} 570 571static void ste_setmulti(sc) 572 struct ste_softc *sc; 573{ 574 struct ifnet *ifp; 575 int h = 0; 576 u_int32_t hashes[2] = { 0, 0 }; 577 struct ifmultiaddr *ifma; 578 579 ifp = &sc->arpcom.ac_if; 580 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 581 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 582 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 583 return; 584 } 585 586 /* first, zot all the existing hash bits */ 587 CSR_WRITE_2(sc, STE_MAR0, 0); 588 CSR_WRITE_2(sc, STE_MAR1, 0); 589 CSR_WRITE_2(sc, STE_MAR2, 0); 590 CSR_WRITE_2(sc, STE_MAR3, 0); 591 592 /* now program new ones */ 593 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 594 if (ifma->ifma_addr->sa_family != AF_LINK) 595 continue; 596 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 597 if (h < 32) 598 hashes[0] |= (1 << h); 599 else 600 hashes[1] |= (1 << (h - 32)); 601 } 602 603 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 604 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 605 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 606 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 607 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 608 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 609 610 return; 611} 612 613static void ste_intr(xsc) 614 void *xsc; 615{ 616 struct ste_softc *sc; 617 struct ifnet *ifp; 618 u_int16_t status; 619 620 sc = xsc; 621 STE_LOCK(sc); 622 ifp = &sc->arpcom.ac_if; 623 624 /* See if this is really our interrupt. */ 625 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 626 STE_UNLOCK(sc); 627 return; 628 } 629 630 for (;;) { 631 status = CSR_READ_2(sc, STE_ISR_ACK); 632 633 if (!(status & STE_INTRS)) 634 break; 635 636 if (status & STE_ISR_RX_DMADONE) 637 ste_rxeof(sc); 638 639 if (status & STE_ISR_TX_DMADONE) 640 ste_txeof(sc); 641 642 if (status & STE_ISR_TX_DONE) 643 ste_txeoc(sc); 644 645 if (status & STE_ISR_STATS_OFLOW) { 646 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 647 ste_stats_update(sc); 648 } 649 650 if (status & STE_ISR_LINKEVENT) 651 mii_pollstat(device_get_softc(sc->ste_miibus)); 652 653 654 if (status & STE_ISR_HOSTERR) { 655 ste_reset(sc); 656 ste_init(sc); 657 } 658 } 659 660 /* Re-enable interrupts */ 661 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 662 663 if (ifp->if_snd.ifq_head != NULL) 664 ste_start(ifp); 665 666 STE_UNLOCK(sc); 667 668 return; 669} 670 671/* 672 * A frame has been uploaded: pass the resulting mbuf chain up to 673 * the higher level protocols. 674 */ 675static void ste_rxeof(sc) 676 struct ste_softc *sc; 677{ 678 struct ether_header *eh; 679 struct mbuf *m; 680 struct ifnet *ifp; 681 struct ste_chain_onefrag *cur_rx; 682 int total_len = 0, count=0; 683 u_int32_t rxstat; 684 685 ifp = &sc->arpcom.ac_if; 686 687 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 688 & STE_RXSTAT_DMADONE) { 689 if ((STE_RX_LIST_CNT - count) < 3) { 690 break; 691 } 692 693 cur_rx = sc->ste_cdata.ste_rx_head; 694 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 695 696 /* 697 * If an error occurs, update stats, clear the 698 * status word and leave the mbuf cluster in place: 699 * it should simply get re-used next time this descriptor 700 * comes up in the ring. 701 */ 702 if (rxstat & STE_RXSTAT_FRAME_ERR) { 703 ifp->if_ierrors++; 704 cur_rx->ste_ptr->ste_status = 0; 705 continue; 706 } 707 708 /* 709 * If there error bit was not set, the upload complete 710 * bit should be set which means we have a valid packet. 711 * If not, something truly strange has happened. 712 */ 713 if (!(rxstat & STE_RXSTAT_DMADONE)) { 714 printf("ste%d: bad receive status -- packet dropped", 715 sc->ste_unit); 716 ifp->if_ierrors++; 717 cur_rx->ste_ptr->ste_status = 0; 718 continue; 719 } 720 721 /* No errors; receive the packet. */ 722 m = cur_rx->ste_mbuf; 723 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 724 725 /* 726 * Try to conjure up a new mbuf cluster. If that 727 * fails, it means we have an out of memory condition and 728 * should leave the buffer in place and continue. This will 729 * result in a lost packet, but there's little else we 730 * can do in this situation. 731 */ 732 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 733 ifp->if_ierrors++; 734 cur_rx->ste_ptr->ste_status = 0; 735 continue; 736 } 737 738 ifp->if_ipackets++; 739 eh = mtod(m, struct ether_header *); 740 m->m_pkthdr.rcvif = ifp; 741 m->m_pkthdr.len = m->m_len = total_len; 742 743 /* Remove header from mbuf and pass it on. */ 744 m_adj(m, sizeof(struct ether_header)); 745 ether_input(ifp, eh, m); 746 747 cur_rx->ste_ptr->ste_status = 0; 748 count++; 749 } 750 751 return; 752} 753 754static void ste_txeoc(sc) 755 struct ste_softc *sc; 756{ 757 u_int8_t txstat; 758 struct ifnet *ifp; 759 760 ifp = &sc->arpcom.ac_if; 761 762 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 763 STE_TXSTATUS_TXDONE) { 764 if (txstat & STE_TXSTATUS_UNDERRUN || 765 txstat & STE_TXSTATUS_EXCESSCOLLS || 766 txstat & STE_TXSTATUS_RECLAIMERR) { 767 ifp->if_oerrors++; 768 printf("ste%d: transmission error: %x\n", 769 sc->ste_unit, txstat); 770 771 ste_reset(sc); 772 ste_init(sc); 773 774 if (txstat & STE_TXSTATUS_UNDERRUN && 775 sc->ste_tx_thresh < STE_PACKET_SIZE) { 776 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 777 printf("ste%d: tx underrun, increasing tx" 778 " start threshold to %d bytes\n", 779 sc->ste_unit, sc->ste_tx_thresh); 780 } 781 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 782 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 783 (STE_PACKET_SIZE >> 4)); 784 } 785 ste_init(sc); 786 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 787 } 788 789 return; 790} 791 792static void ste_txeof(sc) 793 struct ste_softc *sc; 794{ 795 struct ste_chain *cur_tx = NULL; 796 struct ifnet *ifp; 797 int idx; 798 799 ifp = &sc->arpcom.ac_if; 800 801 idx = sc->ste_cdata.ste_tx_cons; 802 while(idx != sc->ste_cdata.ste_tx_prod) { 803 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 804 805 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 806 break; 807 808 if (cur_tx->ste_mbuf != NULL) { 809 m_freem(cur_tx->ste_mbuf); 810 cur_tx->ste_mbuf = NULL; 811 } 812 813 ifp->if_opackets++; 814 815 sc->ste_cdata.ste_tx_cnt--; 816 STE_INC(idx, STE_TX_LIST_CNT); 817 ifp->if_timer = 0; 818 } 819 820 sc->ste_cdata.ste_tx_cons = idx; 821 822 if (cur_tx != NULL) 823 ifp->if_flags &= ~IFF_OACTIVE; 824 825 return; 826} 827 828static void ste_stats_update(xsc) 829 void *xsc; 830{ 831 struct ste_softc *sc; 832 struct ifnet *ifp; 833 struct mii_data *mii; 834 835 sc = xsc; 836 STE_LOCK(sc); 837 838 ifp = &sc->arpcom.ac_if; 839 mii = device_get_softc(sc->ste_miibus); 840 841 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 842 + CSR_READ_1(sc, STE_MULTI_COLLS) 843 + CSR_READ_1(sc, STE_SINGLE_COLLS); 844 845 if (!sc->ste_link) { 846 mii_pollstat(mii); 847 if (mii->mii_media_status & IFM_ACTIVE && 848 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 849 sc->ste_link++; 850 /* 851 * we don't get a call-back on re-init so do it 852 * otherwise we get stuck in the wrong link state 853 */ 854 ste_miibus_statchg(sc->ste_dev); 855 if (ifp->if_snd.ifq_head != NULL) 856 ste_start(ifp); 857 } 858 } 859 860 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 861 STE_UNLOCK(sc); 862 863 return; 864} 865 866 867/* 868 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 869 * IDs against our list and return a device name if we find a match. 870 */ 871static int ste_probe(dev) 872 device_t dev; 873{ 874 struct ste_type *t; 875 876 t = ste_devs; 877 878 while(t->ste_name != NULL) { 879 if ((pci_get_vendor(dev) == t->ste_vid) && 880 (pci_get_device(dev) == t->ste_did)) { 881 device_set_desc(dev, t->ste_name); 882 return(0); 883 } 884 t++; 885 } 886 887 return(ENXIO); 888} 889 890/* 891 * Attach the interface. Allocate softc structures, do ifmedia 892 * setup and ethernet/BPF attach. 893 */ 894static int ste_attach(dev) 895 device_t dev; 896{ 897 u_int32_t command; 898 struct ste_softc *sc; 899 struct ifnet *ifp; 900 int unit, error = 0, rid; 901 902 sc = device_get_softc(dev); 903 unit = device_get_unit(dev); 904 bzero(sc, sizeof(struct ste_softc)); 905 sc->ste_dev = dev; 906 907 /* 908 * Only use the first PHY since this chip reports multiple 909 */ 910 if (pci_get_vendor(dev) == DL_VENDORID && 911 pci_get_device(dev) == DL_DEVICEID_550TX ) 912 sc->ste_one_phy = 1; 913 914 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 915 MTX_DEF | MTX_RECURSE); 916 STE_LOCK(sc); 917 918 /* 919 * Handle power management nonsense. 920 */ 921 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 922 u_int32_t iobase, membase, irq; 923 924 /* Save important PCI config data. */ 925 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 926 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 927 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 928 929 /* Reset the power state. */ 930 printf("ste%d: chip is in D%d power mode " 931 "-- setting to D0\n", unit, 932 pci_get_powerstate(dev)); 933 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 934 935 /* Restore PCI config data. */ 936 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 937 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 938 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 939 } 940 941 /* 942 * Map control/status registers. 943 */ 944 pci_enable_busmaster(dev); 945 pci_enable_io(dev, SYS_RES_IOPORT); 946 pci_enable_io(dev, SYS_RES_MEMORY); 947 command = pci_read_config(dev, PCIR_COMMAND, 4); 948 949#ifdef STE_USEIOSPACE 950 if (!(command & PCIM_CMD_PORTEN)) { 951 printf("ste%d: failed to enable I/O ports!\n", unit); 952 error = ENXIO; 953 goto fail; 954 } 955#else 956 if (!(command & PCIM_CMD_MEMEN)) { 957 printf("ste%d: failed to enable memory mapping!\n", unit); 958 error = ENXIO; 959 goto fail; 960 } 961#endif 962 963 rid = STE_RID; 964 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 965 0, ~0, 1, RF_ACTIVE); 966 967 if (sc->ste_res == NULL) { 968 printf ("ste%d: couldn't map ports/memory\n", unit); 969 error = ENXIO; 970 goto fail; 971 } 972 973 sc->ste_btag = rman_get_bustag(sc->ste_res); 974 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 975 976 rid = 0; 977 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 978 RF_SHAREABLE | RF_ACTIVE); 979 980 if (sc->ste_irq == NULL) { 981 printf("ste%d: couldn't map interrupt\n", unit); 982 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 983 error = ENXIO; 984 goto fail; 985 } 986 987 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 988 ste_intr, sc, &sc->ste_intrhand); 989 990 if (error) { 991 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 992 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 993 printf("ste%d: couldn't set up irq\n", unit); 994 goto fail; 995 } 996 997 callout_handle_init(&sc->ste_stat_ch); 998 999 /* Reset the adapter. */ 1000 ste_reset(sc); 1001 1002 /* 1003 * Get station address from the EEPROM. 1004 */ 1005 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1006 STE_EEADDR_NODE0, 3, 0)) { 1007 printf("ste%d: failed to read station address\n", unit); 1008 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1010 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1011 error = ENXIO;; 1012 goto fail; 1013 } 1014 1015 /* 1016 * A Sundance chip was detected. Inform the world. 1017 */ 1018 printf("ste%d: Ethernet address: %6D\n", unit, 1019 sc->arpcom.ac_enaddr, ":"); 1020 1021 sc->ste_unit = unit; 1022 1023 /* Allocate the descriptor queues. */ 1024 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1025 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1026 1027 if (sc->ste_ldata == NULL) { 1028 printf("ste%d: no memory for list buffers!\n", unit); 1029 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1030 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1031 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1037 1038 /* Do MII setup. */ 1039 if (mii_phy_probe(dev, &sc->ste_miibus, 1040 ste_ifmedia_upd, ste_ifmedia_sts)) { 1041 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1042 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1043 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1044 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1045 contigfree(sc->ste_ldata, 1046 sizeof(struct ste_list_data), M_DEVBUF); 1047 error = ENXIO; 1048 goto fail; 1049 } 1050 1051 ifp = &sc->arpcom.ac_if; 1052 ifp->if_softc = sc; 1053 ifp->if_unit = unit; 1054 ifp->if_name = "ste"; 1055 ifp->if_mtu = ETHERMTU; 1056 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1057 ifp->if_ioctl = ste_ioctl; 1058 ifp->if_output = ether_output; 1059 ifp->if_start = ste_start; 1060 ifp->if_watchdog = ste_watchdog; 1061 ifp->if_init = ste_init; 1062 ifp->if_baudrate = 10000000; 1063 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1064 1065 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1066 1067 /* 1068 * Call MI attach routine. 1069 */ 1070 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1071 1072 /* 1073 * Tell the upper layer(s) we support long frames. 1074 */ 1075 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1076 1077 STE_UNLOCK(sc); 1078 return(0); 1079 1080fail: 1081 STE_UNLOCK(sc); 1082 mtx_destroy(&sc->ste_mtx); 1083 return(error); 1084} 1085 1086static int ste_detach(dev) 1087 device_t dev; 1088{ 1089 struct ste_softc *sc; 1090 struct ifnet *ifp; 1091 1092 sc = device_get_softc(dev); 1093 STE_LOCK(sc); 1094 ifp = &sc->arpcom.ac_if; 1095 1096 ste_stop(sc); 1097 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1098 1099 bus_generic_detach(dev); 1100 device_delete_child(dev, sc->ste_miibus); 1101 1102 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1103 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1104 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1105 1106 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1107 1108 STE_UNLOCK(sc); 1109 mtx_destroy(&sc->ste_mtx); 1110 1111 return(0); 1112} 1113 1114static int ste_newbuf(sc, c, m) 1115 struct ste_softc *sc; 1116 struct ste_chain_onefrag *c; 1117 struct mbuf *m; 1118{ 1119 struct mbuf *m_new = NULL; 1120 1121 if (m == NULL) { 1122 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1123 if (m_new == NULL) 1124 return(ENOBUFS); 1125 MCLGET(m_new, M_DONTWAIT); 1126 if (!(m_new->m_flags & M_EXT)) { 1127 m_freem(m_new); 1128 return(ENOBUFS); 1129 } 1130 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1131 } else { 1132 m_new = m; 1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1134 m_new->m_data = m_new->m_ext.ext_buf; 1135 } 1136 1137 m_adj(m_new, ETHER_ALIGN); 1138 1139 c->ste_mbuf = m_new; 1140 c->ste_ptr->ste_status = 0; 1141 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1142 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1143 1144 return(0); 1145} 1146 1147static int ste_init_rx_list(sc) 1148 struct ste_softc *sc; 1149{ 1150 struct ste_chain_data *cd; 1151 struct ste_list_data *ld; 1152 int i; 1153 1154 cd = &sc->ste_cdata; 1155 ld = sc->ste_ldata; 1156 1157 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1158 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1159 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1160 return(ENOBUFS); 1161 if (i == (STE_RX_LIST_CNT - 1)) { 1162 cd->ste_rx_chain[i].ste_next = 1163 &cd->ste_rx_chain[0]; 1164 ld->ste_rx_list[i].ste_next = 1165 vtophys(&ld->ste_rx_list[0]); 1166 } else { 1167 cd->ste_rx_chain[i].ste_next = 1168 &cd->ste_rx_chain[i + 1]; 1169 ld->ste_rx_list[i].ste_next = 1170 vtophys(&ld->ste_rx_list[i + 1]); 1171 } 1172 ld->ste_rx_list[i].ste_status = 0; 1173 } 1174 1175 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1176 1177 return(0); 1178} 1179 1180static void ste_init_tx_list(sc) 1181 struct ste_softc *sc; 1182{ 1183 struct ste_chain_data *cd; 1184 struct ste_list_data *ld; 1185 int i; 1186 1187 cd = &sc->ste_cdata; 1188 ld = sc->ste_ldata; 1189 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1190 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1191 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1192 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1193 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1194 if (i == (STE_TX_LIST_CNT - 1)) 1195 cd->ste_tx_chain[i].ste_next = 1196 &cd->ste_tx_chain[0]; 1197 else 1198 cd->ste_tx_chain[i].ste_next = 1199 &cd->ste_tx_chain[i + 1]; 1200 if (i == 0) 1201 cd->ste_tx_chain[i].ste_prev = 1202 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1203 else 1204 cd->ste_tx_chain[i].ste_prev = 1205 &cd->ste_tx_chain[i - 1]; 1206 } 1207 1208 cd->ste_tx_prod = 0; 1209 cd->ste_tx_cons = 0; 1210 cd->ste_tx_cnt = 0; 1211 1212 return; 1213} 1214 1215static void ste_init(xsc) 1216 void *xsc; 1217{ 1218 struct ste_softc *sc; 1219 int i; 1220 struct ifnet *ifp; 1221 struct mii_data *mii; 1222 1223 sc = xsc; 1224 STE_LOCK(sc); 1225 ifp = &sc->arpcom.ac_if; 1226 mii = device_get_softc(sc->ste_miibus); 1227 1228 ste_stop(sc); 1229 1230 /* Init our MAC address */ 1231 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1232 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1233 } 1234 1235 /* Init RX list */ 1236 if (ste_init_rx_list(sc) == ENOBUFS) { 1237 printf("ste%d: initialization failed: no " 1238 "memory for RX buffers\n", sc->ste_unit); 1239 ste_stop(sc); 1240 STE_UNLOCK(sc); 1241 return; 1242 } 1243 1244 /* Set RX polling interval */ 1245 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1246 1247 /* Init TX descriptors */ 1248 ste_init_tx_list(sc); 1249 1250 /* Set the TX freethresh value */ 1251 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1252 1253 /* Set the TX start threshold for best performance. */ 1254 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1255 1256 /* Set the TX reclaim threshold. */ 1257 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1258 1259 /* Set up the RX filter. */ 1260 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1261 1262 /* If we want promiscuous mode, set the allframes bit. */ 1263 if (ifp->if_flags & IFF_PROMISC) { 1264 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1265 } else { 1266 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1267 } 1268 1269 /* Set capture broadcast bit to accept broadcast frames. */ 1270 if (ifp->if_flags & IFF_BROADCAST) { 1271 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1272 } else { 1273 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1274 } 1275 1276 ste_setmulti(sc); 1277 1278 /* Load the address of the RX list. */ 1279 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1280 ste_wait(sc); 1281 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1282 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1283 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1284 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1285 1286 /* Set TX polling interval (defer until we TX first packet */ 1287 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1288 1289 /* Load address of the TX list */ 1290 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1291 ste_wait(sc); 1292 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1293 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1295 ste_wait(sc); 1296 sc->ste_tx_prev_idx=-1; 1297 1298 /* Enable receiver and transmitter */ 1299 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1300 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1301 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1302 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1303 1304 /* Enable stats counters. */ 1305 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1306 1307 /* Enable interrupts. */ 1308 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1309 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1310 1311 /* Accept VLAN length packets */ 1312 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1313 1314 ste_ifmedia_upd(ifp); 1315 1316 ifp->if_flags |= IFF_RUNNING; 1317 ifp->if_flags &= ~IFF_OACTIVE; 1318 1319 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1320 STE_UNLOCK(sc); 1321 1322 return; 1323} 1324 1325static void ste_stop(sc) 1326 struct ste_softc *sc; 1327{ 1328 int i; 1329 struct ifnet *ifp; 1330 1331 STE_LOCK(sc); 1332 ifp = &sc->arpcom.ac_if; 1333 1334 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1335 1336 CSR_WRITE_2(sc, STE_IMR, 0); 1337 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1338 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1340 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1341 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1342 ste_wait(sc); 1343 /* 1344 * Try really hard to stop the RX engine or under heavy RX 1345 * data chip will write into de-allocated memory. 1346 */ 1347 ste_reset(sc); 1348 1349 sc->ste_link = 0; 1350 1351 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1352 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1353 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1354 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1355 } 1356 } 1357 1358 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1359 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1360 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1361 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1362 } 1363 } 1364 1365 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1366 1367 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1368 STE_UNLOCK(sc); 1369 1370 return; 1371} 1372 1373static void ste_reset(sc) 1374 struct ste_softc *sc; 1375{ 1376 int i; 1377 1378 STE_SETBIT4(sc, STE_ASICCTL, 1379 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1380 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1381 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1382 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1383 STE_ASICCTL_EXTRESET_RESET); 1384 1385 DELAY(100000); 1386 1387 for (i = 0; i < STE_TIMEOUT; i++) { 1388 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1389 break; 1390 } 1391 1392 if (i == STE_TIMEOUT) 1393 printf("ste%d: global reset never completed\n", sc->ste_unit); 1394 1395 return; 1396} 1397 1398static int ste_ioctl(ifp, command, data) 1399 struct ifnet *ifp; 1400 u_long command; 1401 caddr_t data; 1402{ 1403 struct ste_softc *sc; 1404 struct ifreq *ifr; 1405 struct mii_data *mii; 1406 int error = 0; 1407 1408 sc = ifp->if_softc; 1409 STE_LOCK(sc); 1410 ifr = (struct ifreq *)data; 1411 1412 switch(command) { 1413 case SIOCSIFADDR: 1414 case SIOCGIFADDR: 1415 case SIOCSIFMTU: 1416 error = ether_ioctl(ifp, command, data); 1417 break; 1418 case SIOCSIFFLAGS: 1419 if (ifp->if_flags & IFF_UP) { 1420 if (ifp->if_flags & IFF_RUNNING && 1421 ifp->if_flags & IFF_PROMISC && 1422 !(sc->ste_if_flags & IFF_PROMISC)) { 1423 STE_SETBIT1(sc, STE_RX_MODE, 1424 STE_RXMODE_PROMISC); 1425 } else if (ifp->if_flags & IFF_RUNNING && 1426 !(ifp->if_flags & IFF_PROMISC) && 1427 sc->ste_if_flags & IFF_PROMISC) { 1428 STE_CLRBIT1(sc, STE_RX_MODE, 1429 STE_RXMODE_PROMISC); 1430 } 1431 if (!(ifp->if_flags & IFF_RUNNING)) { 1432 sc->ste_tx_thresh = STE_MIN_FRAMELEN * 2; 1433 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1434 ste_init(sc); 1435 } 1436 } else { 1437 if (ifp->if_flags & IFF_RUNNING) 1438 ste_stop(sc); 1439 } 1440 sc->ste_if_flags = ifp->if_flags; 1441 error = 0; 1442 break; 1443 case SIOCADDMULTI: 1444 case SIOCDELMULTI: 1445 ste_setmulti(sc); 1446 error = 0; 1447 break; 1448 case SIOCGIFMEDIA: 1449 case SIOCSIFMEDIA: 1450 mii = device_get_softc(sc->ste_miibus); 1451 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1452 break; 1453 default: 1454 error = EINVAL; 1455 break; 1456 } 1457 1458 STE_UNLOCK(sc); 1459 1460 return(error); 1461} 1462 1463static int ste_encap(sc, c, m_head) 1464 struct ste_softc *sc; 1465 struct ste_chain *c; 1466 struct mbuf *m_head; 1467{ 1468 int frag = 0; 1469 struct ste_frag *f = NULL; 1470 struct mbuf *m; 1471 struct ste_desc *d; 1472 int total_len = 0; 1473 1474 d = c->ste_ptr; 1475 d->ste_ctl = 0; 1476 1477 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1478 if (m->m_len != 0) { 1479 if (frag == STE_MAXFRAGS) 1480 break; 1481 total_len += m->m_len; 1482 f = &d->ste_frags[frag]; 1483 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1484 f->ste_len = m->m_len; 1485 frag++; 1486 } 1487 } 1488 1489 c->ste_mbuf = m_head; 1490 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1491 d->ste_ctl = 1; 1492 1493 return(0); 1494} 1495 1496static void ste_start(ifp) 1497 struct ifnet *ifp; 1498{ 1499 struct ste_softc *sc; 1500 struct mbuf *m_head = NULL; 1501 struct ste_chain *cur_tx = NULL; 1502 int idx; 1503 1504 sc = ifp->if_softc; 1505 STE_LOCK(sc); 1506 1507 if (!sc->ste_link) { 1508 STE_UNLOCK(sc); 1509 return; 1510 } 1511 1512 if (ifp->if_flags & IFF_OACTIVE) { 1513 STE_UNLOCK(sc); 1514 return; 1515 } 1516 1517 idx = sc->ste_cdata.ste_tx_prod; 1518 1519 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1520 1521 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1522 ifp->if_flags |= IFF_OACTIVE; 1523 break; 1524 } 1525 1526 IF_DEQUEUE(&ifp->if_snd, m_head); 1527 if (m_head == NULL) 1528 break; 1529 1530 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1531 1532 ste_encap(sc, cur_tx, m_head); 1533 1534 cur_tx->ste_ptr->ste_next = 0; 1535 1536 if(sc->ste_tx_prev_idx < 0){ 1537 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1538 /* Load address of the TX list */ 1539 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1540 ste_wait(sc); 1541 1542 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1543 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1544 1545 /* Set TX polling interval to start TX engine */ 1546 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1547 1548 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1549 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1550 ste_wait(sc); 1551 1552 }else{ 1553 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1554 sc->ste_cdata.ste_tx_chain[ 1555 sc->ste_tx_prev_idx].ste_ptr->ste_next 1556 = cur_tx->ste_phys; 1557 } 1558 1559 sc->ste_tx_prev_idx=idx; 1560 1561 /* 1562 * If there's a BPF listener, bounce a copy of this frame 1563 * to him. 1564 */ 1565 if (ifp->if_bpf) 1566 bpf_mtap(ifp, cur_tx->ste_mbuf); 1567 1568 STE_INC(idx, STE_TX_LIST_CNT); 1569 sc->ste_cdata.ste_tx_cnt++; 1570 ifp->if_timer = 5; 1571 sc->ste_cdata.ste_tx_prod = idx; 1572 } 1573 1574 STE_UNLOCK(sc); 1575 1576 return; 1577} 1578 1579static void ste_watchdog(ifp) 1580 struct ifnet *ifp; 1581{ 1582 struct ste_softc *sc; 1583 1584 sc = ifp->if_softc; 1585 STE_LOCK(sc); 1586 1587 ifp->if_oerrors++; 1588 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1589 1590 ste_txeoc(sc); 1591 ste_txeof(sc); 1592 ste_rxeof(sc); 1593 ste_reset(sc); 1594 ste_init(sc); 1595 1596 if (ifp->if_snd.ifq_head != NULL) 1597 ste_start(ifp); 1598 STE_UNLOCK(sc); 1599 1600 return; 1601} 1602 1603static void ste_shutdown(dev) 1604 device_t dev; 1605{ 1606 struct ste_softc *sc; 1607 1608 sc = device_get_softc(dev); 1609 1610 ste_stop(sc); 1611 1612 return; 1613} 1614