if_ste.c revision 102000
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 102000 2002-08-16 23:19:16Z ambrisko $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48#include <net/if_vlan_var.h> 49 50#include <net/bpf.h> 51 52#include <vm/vm.h> /* for vtophys */ 53#include <vm/pmap.h> /* for vtophys */ 54#include <machine/bus_memio.h> 55#include <machine/bus_pio.h> 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <pci/pcireg.h> 65#include <pci/pcivar.h> 66 67/* "controller miibus0" required. See GENERIC if you get errors here. */ 68#include "miibus_if.h" 69 70#define STE_USEIOSPACE 71 72#include <pci/if_stereg.h> 73 74MODULE_DEPEND(ste, miibus, 1, 1, 1); 75 76#if !defined(lint) 77static const char rcsid[] = 78 "$FreeBSD: head/sys/pci/if_ste.c 102000 2002-08-16 23:19:16Z ambrisko $"; 79#endif 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 87 { 0, 0, NULL } 88}; 89 90static int ste_probe (device_t); 91static int ste_attach (device_t); 92static int ste_detach (device_t); 93static void ste_init (void *); 94static void ste_intr (void *); 95static void ste_rxeof (struct ste_softc *); 96static void ste_txeoc (struct ste_softc *); 97static void ste_txeof (struct ste_softc *); 98static void ste_stats_update (void *); 99static void ste_stop (struct ste_softc *); 100static void ste_reset (struct ste_softc *); 101static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104static void ste_start (struct ifnet *); 105static void ste_watchdog (struct ifnet *); 106static void ste_shutdown (device_t); 107static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd (struct ifnet *); 111static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113static void ste_mii_sync (struct ste_softc *); 114static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg (device_t, int, int); 118static int ste_miibus_writereg (device_t, int, int, int); 119static void ste_miibus_statchg (device_t); 120 121static int ste_eeprom_wait (struct ste_softc *); 122static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123static void ste_wait (struct ste_softc *); 124static u_int8_t ste_calchash (caddr_t); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167#define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170#define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173#define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 175 176#define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 178 179#define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 181 182#define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 184 185 186#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189/* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192static void ste_mii_sync(sc) 193 struct ste_softc *sc; 194{ 195 register int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205 206 return; 207} 208 209/* 210 * Clock a series of bits through the MII. 211 */ 212static void ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216{ 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232} 233 234/* 235 * Read an PHY register through the MII. 236 */ 237static int ste_mii_readreg(sc, frame) 238 struct ste_softc *sc; 239 struct ste_mii_frame *frame; 240 241{ 242 int i, ack; 243 244 STE_LOCK(sc); 245 246 /* 247 * Set up frame for RX. 248 */ 249 frame->mii_stdelim = STE_MII_STARTDELIM; 250 frame->mii_opcode = STE_MII_READOP; 251 frame->mii_turnaround = 0; 252 frame->mii_data = 0; 253 254 CSR_WRITE_2(sc, STE_PHYCTL, 0); 255 /* 256 * Turn on data xmit. 257 */ 258 MII_SET(STE_PHYCTL_MDIR); 259 260 ste_mii_sync(sc); 261 262 /* 263 * Send command/address info. 264 */ 265 ste_mii_send(sc, frame->mii_stdelim, 2); 266 ste_mii_send(sc, frame->mii_opcode, 2); 267 ste_mii_send(sc, frame->mii_phyaddr, 5); 268 ste_mii_send(sc, frame->mii_regaddr, 5); 269 270 /* Turn off xmit. */ 271 MII_CLR(STE_PHYCTL_MDIR); 272 273 /* Idle bit */ 274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 275 DELAY(1); 276 MII_SET(STE_PHYCTL_MCLK); 277 DELAY(1); 278 279 /* Check for ack */ 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 285 286 /* 287 * Now try reading data bits. If the ack failed, we still 288 * need to clock through 16 cycles to keep the PHY(s) in sync. 289 */ 290 if (ack) { 291 for(i = 0; i < 16; i++) { 292 MII_CLR(STE_PHYCTL_MCLK); 293 DELAY(1); 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 } 297 goto fail; 298 } 299 300 for (i = 0x8000; i; i >>= 1) { 301 MII_CLR(STE_PHYCTL_MCLK); 302 DELAY(1); 303 if (!ack) { 304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 305 frame->mii_data |= i; 306 DELAY(1); 307 } 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 } 311 312fail: 313 314 MII_CLR(STE_PHYCTL_MCLK); 315 DELAY(1); 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 319 STE_UNLOCK(sc); 320 321 if (ack) 322 return(1); 323 return(0); 324} 325 326/* 327 * Write to a PHY register through the MII. 328 */ 329static int ste_mii_writereg(sc, frame) 330 struct ste_softc *sc; 331 struct ste_mii_frame *frame; 332 333{ 334 STE_LOCK(sc); 335 336 /* 337 * Set up frame for TX. 338 */ 339 340 frame->mii_stdelim = STE_MII_STARTDELIM; 341 frame->mii_opcode = STE_MII_WRITEOP; 342 frame->mii_turnaround = STE_MII_TURNAROUND; 343 344 /* 345 * Turn on data output. 346 */ 347 MII_SET(STE_PHYCTL_MDIR); 348 349 ste_mii_sync(sc); 350 351 ste_mii_send(sc, frame->mii_stdelim, 2); 352 ste_mii_send(sc, frame->mii_opcode, 2); 353 ste_mii_send(sc, frame->mii_phyaddr, 5); 354 ste_mii_send(sc, frame->mii_regaddr, 5); 355 ste_mii_send(sc, frame->mii_turnaround, 2); 356 ste_mii_send(sc, frame->mii_data, 16); 357 358 /* Idle bit. */ 359 MII_SET(STE_PHYCTL_MCLK); 360 DELAY(1); 361 MII_CLR(STE_PHYCTL_MCLK); 362 DELAY(1); 363 364 /* 365 * Turn off xmit. 366 */ 367 MII_CLR(STE_PHYCTL_MDIR); 368 369 STE_UNLOCK(sc); 370 371 return(0); 372} 373 374static int ste_miibus_readreg(dev, phy, reg) 375 device_t dev; 376 int phy, reg; 377{ 378 struct ste_softc *sc; 379 struct ste_mii_frame frame; 380 381 sc = device_get_softc(dev); 382 383 if (pci_get_vendor(dev) == DL_VENDORID && 384 pci_get_device(dev) == DL_DEVICEID_550TX && 385 phy != 0) 386 return (0); 387 388 bzero((char *)&frame, sizeof(frame)); 389 390 frame.mii_phyaddr = phy; 391 frame.mii_regaddr = reg; 392 ste_mii_readreg(sc, &frame); 393 394 return(frame.mii_data); 395} 396 397static int ste_miibus_writereg(dev, phy, reg, data) 398 device_t dev; 399 int phy, reg, data; 400{ 401 struct ste_softc *sc; 402 struct ste_mii_frame frame; 403 404 sc = device_get_softc(dev); 405 bzero((char *)&frame, sizeof(frame)); 406 407 frame.mii_phyaddr = phy; 408 frame.mii_regaddr = reg; 409 frame.mii_data = data; 410 411 ste_mii_writereg(sc, &frame); 412 413 return(0); 414} 415 416static void ste_miibus_statchg(dev) 417 device_t dev; 418{ 419 struct ste_softc *sc; 420 struct mii_data *mii; 421 422 sc = device_get_softc(dev); 423 STE_LOCK(sc); 424 mii = device_get_softc(sc->ste_miibus); 425 426 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 427 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } else { 429 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 430 } 431 STE_UNLOCK(sc); 432 433 return; 434} 435 436static int ste_ifmedia_upd(ifp) 437 struct ifnet *ifp; 438{ 439 struct ste_softc *sc; 440 struct mii_data *mii; 441 442 sc = ifp->if_softc; 443 mii = device_get_softc(sc->ste_miibus); 444 sc->ste_link = 0; 445 if (mii->mii_instance) { 446 struct mii_softc *miisc; 447 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 448 mii_phy_reset(miisc); 449 } 450 mii_mediachg(mii); 451 452 return(0); 453} 454 455static void ste_ifmedia_sts(ifp, ifmr) 456 struct ifnet *ifp; 457 struct ifmediareq *ifmr; 458{ 459 struct ste_softc *sc; 460 struct mii_data *mii; 461 462 sc = ifp->if_softc; 463 mii = device_get_softc(sc->ste_miibus); 464 465 mii_pollstat(mii); 466 ifmr->ifm_active = mii->mii_media_active; 467 ifmr->ifm_status = mii->mii_media_status; 468 469 return; 470} 471 472static void ste_wait(sc) 473 struct ste_softc *sc; 474{ 475 register int i; 476 477 for (i = 0; i < STE_TIMEOUT; i++) { 478 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 479 break; 480 } 481 482 if (i == STE_TIMEOUT) 483 printf("ste%d: command never completed!\n", sc->ste_unit); 484 485 return; 486} 487 488/* 489 * The EEPROM is slow: give it time to come ready after issuing 490 * it a command. 491 */ 492static int ste_eeprom_wait(sc) 493 struct ste_softc *sc; 494{ 495 int i; 496 497 DELAY(1000); 498 499 for (i = 0; i < 100; i++) { 500 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 501 DELAY(1000); 502 else 503 break; 504 } 505 506 if (i == 100) { 507 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 508 return(1); 509 } 510 511 return(0); 512} 513 514/* 515 * Read a sequence of words from the EEPROM. Note that ethernet address 516 * data is stored in the EEPROM in network byte order. 517 */ 518static int ste_read_eeprom(sc, dest, off, cnt, swap) 519 struct ste_softc *sc; 520 caddr_t dest; 521 int off; 522 int cnt; 523 int swap; 524{ 525 int err = 0, i; 526 u_int16_t word = 0, *ptr; 527 528 if (ste_eeprom_wait(sc)) 529 return(1); 530 531 for (i = 0; i < cnt; i++) { 532 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 533 err = ste_eeprom_wait(sc); 534 if (err) 535 break; 536 word = CSR_READ_2(sc, STE_EEPROM_DATA); 537 ptr = (u_int16_t *)(dest + (i * 2)); 538 if (swap) 539 *ptr = ntohs(word); 540 else 541 *ptr = word; 542 } 543 544 return(err ? 1 : 0); 545} 546 547static u_int8_t ste_calchash(addr) 548 caddr_t addr; 549{ 550 551 u_int32_t crc, carry; 552 int i, j; 553 u_int8_t c; 554 555 /* Compute CRC for the address value. */ 556 crc = 0xFFFFFFFF; /* initial value */ 557 558 for (i = 0; i < 6; i++) { 559 c = *(addr + i); 560 for (j = 0; j < 8; j++) { 561 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 562 crc <<= 1; 563 c >>= 1; 564 if (carry) 565 crc = (crc ^ 0x04c11db6) | carry; 566 } 567 } 568 569 /* return the filter bit position */ 570 return(crc & 0x0000003F); 571} 572 573static void ste_setmulti(sc) 574 struct ste_softc *sc; 575{ 576 struct ifnet *ifp; 577 int h = 0; 578 u_int32_t hashes[2] = { 0, 0 }; 579 struct ifmultiaddr *ifma; 580 581 ifp = &sc->arpcom.ac_if; 582 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 583 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 584 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 585 return; 586 } 587 588 /* first, zot all the existing hash bits */ 589 CSR_WRITE_2(sc, STE_MAR0, 0); 590 CSR_WRITE_2(sc, STE_MAR1, 0); 591 CSR_WRITE_2(sc, STE_MAR2, 0); 592 CSR_WRITE_2(sc, STE_MAR3, 0); 593 594 /* now program new ones */ 595 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 596 if (ifma->ifma_addr->sa_family != AF_LINK) 597 continue; 598 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 599 if (h < 32) 600 hashes[0] |= (1 << h); 601 else 602 hashes[1] |= (1 << (h - 32)); 603 } 604 605 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 606 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 607 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 608 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 609 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 610 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 611 612 return; 613} 614 615static void ste_intr(xsc) 616 void *xsc; 617{ 618 struct ste_softc *sc; 619 struct ifnet *ifp; 620 u_int16_t status; 621 622 sc = xsc; 623 STE_LOCK(sc); 624 ifp = &sc->arpcom.ac_if; 625 626 /* See if this is really our interrupt. */ 627 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 628 STE_UNLOCK(sc); 629 return; 630 } 631 632 for (;;) { 633 status = CSR_READ_2(sc, STE_ISR_ACK); 634 635 if (!(status & STE_INTRS)) 636 break; 637 638 if (status & STE_ISR_RX_DMADONE) 639 ste_rxeof(sc); 640 641 if (status & STE_ISR_TX_DMADONE) 642 ste_txeof(sc); 643 644 if (status & STE_ISR_TX_DONE) 645 ste_txeoc(sc); 646 647 if (status & STE_ISR_STATS_OFLOW) { 648 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 649 ste_stats_update(sc); 650 } 651 652 if (status & STE_ISR_LINKEVENT) 653 mii_pollstat(device_get_softc(sc->ste_miibus)); 654 655 656 if (status & STE_ISR_HOSTERR) { 657 ste_reset(sc); 658 ste_init(sc); 659 } 660 } 661 662 /* Re-enable interrupts */ 663 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 664 665 if (ifp->if_snd.ifq_head != NULL) 666 ste_start(ifp); 667 668 STE_UNLOCK(sc); 669 670 return; 671} 672 673/* 674 * A frame has been uploaded: pass the resulting mbuf chain up to 675 * the higher level protocols. 676 */ 677static void ste_rxeof(sc) 678 struct ste_softc *sc; 679{ 680 struct ether_header *eh; 681 struct mbuf *m; 682 struct ifnet *ifp; 683 struct ste_chain_onefrag *cur_rx; 684 int total_len = 0, count=0; 685 u_int32_t rxstat; 686 687 ifp = &sc->arpcom.ac_if; 688 689 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 690 & STE_RXSTAT_DMADONE) { 691 if ((STE_RX_LIST_CNT - count) < 3) { 692 break; 693 } 694 695 cur_rx = sc->ste_cdata.ste_rx_head; 696 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 697 698 /* 699 * If an error occurs, update stats, clear the 700 * status word and leave the mbuf cluster in place: 701 * it should simply get re-used next time this descriptor 702 * comes up in the ring. 703 */ 704 if (rxstat & STE_RXSTAT_FRAME_ERR) { 705 ifp->if_ierrors++; 706 cur_rx->ste_ptr->ste_status = 0; 707 continue; 708 } 709 710 /* 711 * If there error bit was not set, the upload complete 712 * bit should be set which means we have a valid packet. 713 * If not, something truly strange has happened. 714 */ 715 if (!(rxstat & STE_RXSTAT_DMADONE)) { 716 printf("ste%d: bad receive status -- packet dropped", 717 sc->ste_unit); 718 ifp->if_ierrors++; 719 cur_rx->ste_ptr->ste_status = 0; 720 continue; 721 } 722 723 /* No errors; receive the packet. */ 724 m = cur_rx->ste_mbuf; 725 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 726 727 /* 728 * Try to conjure up a new mbuf cluster. If that 729 * fails, it means we have an out of memory condition and 730 * should leave the buffer in place and continue. This will 731 * result in a lost packet, but there's little else we 732 * can do in this situation. 733 */ 734 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 735 ifp->if_ierrors++; 736 cur_rx->ste_ptr->ste_status = 0; 737 continue; 738 } 739 740 ifp->if_ipackets++; 741 eh = mtod(m, struct ether_header *); 742 m->m_pkthdr.rcvif = ifp; 743 m->m_pkthdr.len = m->m_len = total_len; 744 745 /* Remove header from mbuf and pass it on. */ 746 m_adj(m, sizeof(struct ether_header)); 747 ether_input(ifp, eh, m); 748 749 cur_rx->ste_ptr->ste_status = 0; 750 count++; 751 } 752 753 return; 754} 755 756static void ste_txeoc(sc) 757 struct ste_softc *sc; 758{ 759 u_int8_t txstat; 760 struct ifnet *ifp; 761 762 ifp = &sc->arpcom.ac_if; 763 764 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 765 STE_TXSTATUS_TXDONE) { 766 if (txstat & STE_TXSTATUS_UNDERRUN || 767 txstat & STE_TXSTATUS_EXCESSCOLLS || 768 txstat & STE_TXSTATUS_RECLAIMERR) { 769 ifp->if_oerrors++; 770 printf("ste%d: transmission error: %x\n", 771 sc->ste_unit, txstat); 772 773 ste_reset(sc); 774 ste_init(sc); 775 776 if (txstat & STE_TXSTATUS_UNDERRUN && 777 sc->ste_tx_thresh < STE_PACKET_SIZE) { 778 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 779 printf("ste%d: tx underrun, increasing tx" 780 " start threshold to %d bytes\n", 781 sc->ste_unit, sc->ste_tx_thresh); 782 } 783 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 784 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 785 (STE_PACKET_SIZE >> 4)); 786 } 787 ste_init(sc); 788 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 789 } 790 791 return; 792} 793 794static void ste_txeof(sc) 795 struct ste_softc *sc; 796{ 797 struct ste_chain *cur_tx = NULL; 798 struct ifnet *ifp; 799 int idx; 800 801 ifp = &sc->arpcom.ac_if; 802 803 idx = sc->ste_cdata.ste_tx_cons; 804 while(idx != sc->ste_cdata.ste_tx_prod) { 805 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 806 807 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 808 break; 809 810 if (cur_tx->ste_mbuf != NULL) { 811 m_freem(cur_tx->ste_mbuf); 812 cur_tx->ste_mbuf = NULL; 813 } 814 815 ifp->if_opackets++; 816 817 sc->ste_cdata.ste_tx_cnt--; 818 STE_INC(idx, STE_TX_LIST_CNT); 819 ifp->if_timer = 0; 820 } 821 822 sc->ste_cdata.ste_tx_cons = idx; 823 824 if (cur_tx != NULL) 825 ifp->if_flags &= ~IFF_OACTIVE; 826 827 return; 828} 829 830static void ste_stats_update(xsc) 831 void *xsc; 832{ 833 struct ste_softc *sc; 834 struct ifnet *ifp; 835 struct mii_data *mii; 836 837 sc = xsc; 838 STE_LOCK(sc); 839 840 ifp = &sc->arpcom.ac_if; 841 mii = device_get_softc(sc->ste_miibus); 842 843 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 844 + CSR_READ_1(sc, STE_MULTI_COLLS) 845 + CSR_READ_1(sc, STE_SINGLE_COLLS); 846 847 if (!sc->ste_link) { 848 mii_pollstat(mii); 849 if (mii->mii_media_status & IFM_ACTIVE && 850 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 851 sc->ste_link++; 852 /* 853 * we don't get a call-back on re-init so do it 854 * otherwise we get stuck in the wrong link state 855 */ 856 ste_miibus_statchg(sc->ste_dev); 857 if (ifp->if_snd.ifq_head != NULL) 858 ste_start(ifp); 859 } 860 } 861 862 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 863 STE_UNLOCK(sc); 864 865 return; 866} 867 868 869/* 870 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 871 * IDs against our list and return a device name if we find a match. 872 */ 873static int ste_probe(dev) 874 device_t dev; 875{ 876 struct ste_type *t; 877 878 t = ste_devs; 879 880 while(t->ste_name != NULL) { 881 if ((pci_get_vendor(dev) == t->ste_vid) && 882 (pci_get_device(dev) == t->ste_did)) { 883 device_set_desc(dev, t->ste_name); 884 return(0); 885 } 886 t++; 887 } 888 889 return(ENXIO); 890} 891 892/* 893 * Attach the interface. Allocate softc structures, do ifmedia 894 * setup and ethernet/BPF attach. 895 */ 896static int ste_attach(dev) 897 device_t dev; 898{ 899 u_int32_t command; 900 struct ste_softc *sc; 901 struct ifnet *ifp; 902 int unit, error = 0, rid; 903 904 sc = device_get_softc(dev); 905 unit = device_get_unit(dev); 906 bzero(sc, sizeof(struct ste_softc)); 907 sc->ste_dev = dev; 908 909 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 910 MTX_DEF | MTX_RECURSE); 911 STE_LOCK(sc); 912 913 /* 914 * Handle power management nonsense. 915 */ 916 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 917 u_int32_t iobase, membase, irq; 918 919 /* Save important PCI config data. */ 920 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 921 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 922 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 923 924 /* Reset the power state. */ 925 printf("ste%d: chip is in D%d power mode " 926 "-- setting to D0\n", unit, 927 pci_get_powerstate(dev)); 928 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 929 930 /* Restore PCI config data. */ 931 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 932 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 933 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 934 } 935 936 /* 937 * Map control/status registers. 938 */ 939 pci_enable_busmaster(dev); 940 pci_enable_io(dev, SYS_RES_IOPORT); 941 pci_enable_io(dev, SYS_RES_MEMORY); 942 command = pci_read_config(dev, PCIR_COMMAND, 4); 943 944#ifdef STE_USEIOSPACE 945 if (!(command & PCIM_CMD_PORTEN)) { 946 printf("ste%d: failed to enable I/O ports!\n", unit); 947 error = ENXIO; 948 goto fail; 949 } 950#else 951 if (!(command & PCIM_CMD_MEMEN)) { 952 printf("ste%d: failed to enable memory mapping!\n", unit); 953 error = ENXIO; 954 goto fail; 955 } 956#endif 957 958 rid = STE_RID; 959 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 960 0, ~0, 1, RF_ACTIVE); 961 962 if (sc->ste_res == NULL) { 963 printf ("ste%d: couldn't map ports/memory\n", unit); 964 error = ENXIO; 965 goto fail; 966 } 967 968 sc->ste_btag = rman_get_bustag(sc->ste_res); 969 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 970 971 rid = 0; 972 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 973 RF_SHAREABLE | RF_ACTIVE); 974 975 if (sc->ste_irq == NULL) { 976 printf("ste%d: couldn't map interrupt\n", unit); 977 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 978 error = ENXIO; 979 goto fail; 980 } 981 982 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 983 ste_intr, sc, &sc->ste_intrhand); 984 985 if (error) { 986 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 987 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 988 printf("ste%d: couldn't set up irq\n", unit); 989 goto fail; 990 } 991 992 callout_handle_init(&sc->ste_stat_ch); 993 994 /* Reset the adapter. */ 995 ste_reset(sc); 996 997 /* 998 * Get station address from the EEPROM. 999 */ 1000 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1001 STE_EEADDR_NODE0, 3, 0)) { 1002 printf("ste%d: failed to read station address\n", unit); 1003 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1004 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1005 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1006 error = ENXIO;; 1007 goto fail; 1008 } 1009 1010 /* 1011 * A Sundance chip was detected. Inform the world. 1012 */ 1013 printf("ste%d: Ethernet address: %6D\n", unit, 1014 sc->arpcom.ac_enaddr, ":"); 1015 1016 sc->ste_unit = unit; 1017 1018 /* Allocate the descriptor queues. */ 1019 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1020 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1021 1022 if (sc->ste_ldata == NULL) { 1023 printf("ste%d: no memory for list buffers!\n", unit); 1024 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1025 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1026 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1027 error = ENXIO; 1028 goto fail; 1029 } 1030 1031 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1032 1033 /* Do MII setup. */ 1034 if (mii_phy_probe(dev, &sc->ste_miibus, 1035 ste_ifmedia_upd, ste_ifmedia_sts)) { 1036 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1037 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1038 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1039 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1040 contigfree(sc->ste_ldata, 1041 sizeof(struct ste_list_data), M_DEVBUF); 1042 error = ENXIO; 1043 goto fail; 1044 } 1045 1046 ifp = &sc->arpcom.ac_if; 1047 ifp->if_softc = sc; 1048 ifp->if_unit = unit; 1049 ifp->if_name = "ste"; 1050 ifp->if_mtu = ETHERMTU; 1051 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1052 ifp->if_ioctl = ste_ioctl; 1053 ifp->if_output = ether_output; 1054 ifp->if_start = ste_start; 1055 ifp->if_watchdog = ste_watchdog; 1056 ifp->if_init = ste_init; 1057 ifp->if_baudrate = 10000000; 1058 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1059 1060 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1061 1062 /* 1063 * Call MI attach routine. 1064 */ 1065 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1066 1067 /* 1068 * Tell the upper layer(s) we support long frames. 1069 */ 1070 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1071 1072 STE_UNLOCK(sc); 1073 return(0); 1074 1075fail: 1076 STE_UNLOCK(sc); 1077 mtx_destroy(&sc->ste_mtx); 1078 return(error); 1079} 1080 1081static int ste_detach(dev) 1082 device_t dev; 1083{ 1084 struct ste_softc *sc; 1085 struct ifnet *ifp; 1086 1087 sc = device_get_softc(dev); 1088 STE_LOCK(sc); 1089 ifp = &sc->arpcom.ac_if; 1090 1091 ste_stop(sc); 1092 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1093 1094 bus_generic_detach(dev); 1095 device_delete_child(dev, sc->ste_miibus); 1096 1097 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1098 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1099 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1100 1101 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1102 1103 STE_UNLOCK(sc); 1104 mtx_destroy(&sc->ste_mtx); 1105 1106 return(0); 1107} 1108 1109static int ste_newbuf(sc, c, m) 1110 struct ste_softc *sc; 1111 struct ste_chain_onefrag *c; 1112 struct mbuf *m; 1113{ 1114 struct mbuf *m_new = NULL; 1115 1116 if (m == NULL) { 1117 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1118 if (m_new == NULL) 1119 return(ENOBUFS); 1120 MCLGET(m_new, M_DONTWAIT); 1121 if (!(m_new->m_flags & M_EXT)) { 1122 m_freem(m_new); 1123 return(ENOBUFS); 1124 } 1125 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1126 } else { 1127 m_new = m; 1128 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1129 m_new->m_data = m_new->m_ext.ext_buf; 1130 } 1131 1132 m_adj(m_new, ETHER_ALIGN); 1133 1134 c->ste_mbuf = m_new; 1135 c->ste_ptr->ste_status = 0; 1136 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1137 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1138 1139 return(0); 1140} 1141 1142static int ste_init_rx_list(sc) 1143 struct ste_softc *sc; 1144{ 1145 struct ste_chain_data *cd; 1146 struct ste_list_data *ld; 1147 int i; 1148 1149 cd = &sc->ste_cdata; 1150 ld = sc->ste_ldata; 1151 1152 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1153 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1154 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1155 return(ENOBUFS); 1156 if (i == (STE_RX_LIST_CNT - 1)) { 1157 cd->ste_rx_chain[i].ste_next = 1158 &cd->ste_rx_chain[0]; 1159 ld->ste_rx_list[i].ste_next = 1160 vtophys(&ld->ste_rx_list[0]); 1161 } else { 1162 cd->ste_rx_chain[i].ste_next = 1163 &cd->ste_rx_chain[i + 1]; 1164 ld->ste_rx_list[i].ste_next = 1165 vtophys(&ld->ste_rx_list[i + 1]); 1166 } 1167 ld->ste_rx_list[i].ste_status = 0; 1168 } 1169 1170 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1171 1172 return(0); 1173} 1174 1175static void ste_init_tx_list(sc) 1176 struct ste_softc *sc; 1177{ 1178 struct ste_chain_data *cd; 1179 struct ste_list_data *ld; 1180 int i; 1181 1182 cd = &sc->ste_cdata; 1183 ld = sc->ste_ldata; 1184 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1185 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1186 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1187 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1188 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1189 if (i == (STE_TX_LIST_CNT - 1)) 1190 cd->ste_tx_chain[i].ste_next = 1191 &cd->ste_tx_chain[0]; 1192 else 1193 cd->ste_tx_chain[i].ste_next = 1194 &cd->ste_tx_chain[i + 1]; 1195 if (i == 0) 1196 cd->ste_tx_chain[i].ste_prev = 1197 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1198 else 1199 cd->ste_tx_chain[i].ste_prev = 1200 &cd->ste_tx_chain[i - 1]; 1201 } 1202 1203 cd->ste_tx_prod = 0; 1204 cd->ste_tx_cons = 0; 1205 cd->ste_tx_cnt = 0; 1206 1207 return; 1208} 1209 1210static void ste_init(xsc) 1211 void *xsc; 1212{ 1213 struct ste_softc *sc; 1214 int i; 1215 struct ifnet *ifp; 1216 struct mii_data *mii; 1217 1218 sc = xsc; 1219 STE_LOCK(sc); 1220 ifp = &sc->arpcom.ac_if; 1221 mii = device_get_softc(sc->ste_miibus); 1222 1223 ste_stop(sc); 1224 1225 /* Init our MAC address */ 1226 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1227 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1228 } 1229 1230 /* Init RX list */ 1231 if (ste_init_rx_list(sc) == ENOBUFS) { 1232 printf("ste%d: initialization failed: no " 1233 "memory for RX buffers\n", sc->ste_unit); 1234 ste_stop(sc); 1235 STE_UNLOCK(sc); 1236 return; 1237 } 1238 1239 /* Set RX polling interval */ 1240 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1241 1242 /* Init TX descriptors */ 1243 ste_init_tx_list(sc); 1244 1245 /* Set the TX freethresh value */ 1246 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1247 1248 /* Set the TX start threshold for best performance. */ 1249 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1250 1251 /* Set the TX reclaim threshold. */ 1252 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1253 1254 /* Set up the RX filter. */ 1255 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1256 1257 /* If we want promiscuous mode, set the allframes bit. */ 1258 if (ifp->if_flags & IFF_PROMISC) { 1259 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1260 } else { 1261 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1262 } 1263 1264 /* Set capture broadcast bit to accept broadcast frames. */ 1265 if (ifp->if_flags & IFF_BROADCAST) { 1266 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1267 } else { 1268 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1269 } 1270 1271 ste_setmulti(sc); 1272 1273 /* Load the address of the RX list. */ 1274 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1275 ste_wait(sc); 1276 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1277 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1278 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1279 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1280 1281 /* Set TX polling interval (defer until we TX first packet */ 1282 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1283 1284 /* Load address of the TX list */ 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1286 ste_wait(sc); 1287 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1288 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1289 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1290 ste_wait(sc); 1291 sc->ste_tx_prev_idx=-1; 1292 1293 /* Enable receiver and transmitter */ 1294 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1295 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1296 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1297 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1298 1299 /* Enable stats counters. */ 1300 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1301 1302 /* Enable interrupts. */ 1303 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1304 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1305 1306 /* Accept VLAN length packets */ 1307 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1308 1309 ste_ifmedia_upd(ifp); 1310 1311 ifp->if_flags |= IFF_RUNNING; 1312 ifp->if_flags &= ~IFF_OACTIVE; 1313 1314 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1315 STE_UNLOCK(sc); 1316 1317 return; 1318} 1319 1320static void ste_stop(sc) 1321 struct ste_softc *sc; 1322{ 1323 int i; 1324 struct ifnet *ifp; 1325 1326 STE_LOCK(sc); 1327 ifp = &sc->arpcom.ac_if; 1328 1329 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1330 1331 CSR_WRITE_2(sc, STE_IMR, 0); 1332 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1333 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1334 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1335 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1336 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1337 ste_wait(sc); 1338 /* 1339 * Try really hard to stop the RX engine or under heavy RX 1340 * data chip will write into de-allocated memory. 1341 */ 1342 ste_reset(sc); 1343 1344 sc->ste_link = 0; 1345 1346 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1347 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1348 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1349 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1350 } 1351 } 1352 1353 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1354 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1355 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1356 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1357 } 1358 } 1359 1360 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1361 1362 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1363 STE_UNLOCK(sc); 1364 1365 return; 1366} 1367 1368static void ste_reset(sc) 1369 struct ste_softc *sc; 1370{ 1371 int i; 1372 1373 STE_SETBIT4(sc, STE_ASICCTL, 1374 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1375 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1376 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1377 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1378 STE_ASICCTL_EXTRESET_RESET); 1379 1380 DELAY(100000); 1381 1382 for (i = 0; i < STE_TIMEOUT; i++) { 1383 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1384 break; 1385 } 1386 1387 if (i == STE_TIMEOUT) 1388 printf("ste%d: global reset never completed\n", sc->ste_unit); 1389 1390 return; 1391} 1392 1393static int ste_ioctl(ifp, command, data) 1394 struct ifnet *ifp; 1395 u_long command; 1396 caddr_t data; 1397{ 1398 struct ste_softc *sc; 1399 struct ifreq *ifr; 1400 struct mii_data *mii; 1401 int error = 0; 1402 1403 sc = ifp->if_softc; 1404 STE_LOCK(sc); 1405 ifr = (struct ifreq *)data; 1406 1407 switch(command) { 1408 case SIOCSIFADDR: 1409 case SIOCGIFADDR: 1410 case SIOCSIFMTU: 1411 error = ether_ioctl(ifp, command, data); 1412 break; 1413 case SIOCSIFFLAGS: 1414 if (ifp->if_flags & IFF_UP) { 1415 if (ifp->if_flags & IFF_RUNNING && 1416 ifp->if_flags & IFF_PROMISC && 1417 !(sc->ste_if_flags & IFF_PROMISC)) { 1418 STE_SETBIT1(sc, STE_RX_MODE, 1419 STE_RXMODE_PROMISC); 1420 } else if (ifp->if_flags & IFF_RUNNING && 1421 !(ifp->if_flags & IFF_PROMISC) && 1422 sc->ste_if_flags & IFF_PROMISC) { 1423 STE_CLRBIT1(sc, STE_RX_MODE, 1424 STE_RXMODE_PROMISC); 1425 } 1426 if (!(ifp->if_flags & IFF_RUNNING)) { 1427 sc->ste_tx_thresh = STE_MIN_FRAMELEN * 2; 1428 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1429 ste_init(sc); 1430 } 1431 } else { 1432 if (ifp->if_flags & IFF_RUNNING) 1433 ste_stop(sc); 1434 } 1435 sc->ste_if_flags = ifp->if_flags; 1436 error = 0; 1437 break; 1438 case SIOCADDMULTI: 1439 case SIOCDELMULTI: 1440 ste_setmulti(sc); 1441 error = 0; 1442 break; 1443 case SIOCGIFMEDIA: 1444 case SIOCSIFMEDIA: 1445 mii = device_get_softc(sc->ste_miibus); 1446 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1447 break; 1448 default: 1449 error = EINVAL; 1450 break; 1451 } 1452 1453 STE_UNLOCK(sc); 1454 1455 return(error); 1456} 1457 1458static int ste_encap(sc, c, m_head) 1459 struct ste_softc *sc; 1460 struct ste_chain *c; 1461 struct mbuf *m_head; 1462{ 1463 int frag = 0; 1464 struct ste_frag *f = NULL; 1465 struct mbuf *m; 1466 struct ste_desc *d; 1467 int total_len = 0; 1468 1469 d = c->ste_ptr; 1470 d->ste_ctl = 0; 1471 1472 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1473 if (m->m_len != 0) { 1474 if (frag == STE_MAXFRAGS) 1475 break; 1476 total_len += m->m_len; 1477 f = &d->ste_frags[frag]; 1478 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1479 f->ste_len = m->m_len; 1480 frag++; 1481 } 1482 } 1483 1484 c->ste_mbuf = m_head; 1485 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1486 d->ste_ctl = 1; 1487 1488 return(0); 1489} 1490 1491static void ste_start(ifp) 1492 struct ifnet *ifp; 1493{ 1494 struct ste_softc *sc; 1495 struct mbuf *m_head = NULL; 1496 struct ste_chain *cur_tx = NULL; 1497 int idx; 1498 1499 sc = ifp->if_softc; 1500 STE_LOCK(sc); 1501 1502 if (!sc->ste_link) { 1503 STE_UNLOCK(sc); 1504 return; 1505 } 1506 1507 if (ifp->if_flags & IFF_OACTIVE) { 1508 STE_UNLOCK(sc); 1509 return; 1510 } 1511 1512 idx = sc->ste_cdata.ste_tx_prod; 1513 1514 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1515 1516 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1517 ifp->if_flags |= IFF_OACTIVE; 1518 break; 1519 } 1520 1521 IF_DEQUEUE(&ifp->if_snd, m_head); 1522 if (m_head == NULL) 1523 break; 1524 1525 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1526 1527 ste_encap(sc, cur_tx, m_head); 1528 1529 cur_tx->ste_ptr->ste_next = 0; 1530 1531 if(sc->ste_tx_prev_idx < 0){ 1532 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1533 /* Load address of the TX list */ 1534 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1535 ste_wait(sc); 1536 1537 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1538 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1539 1540 /* Set TX polling interval to start TX engine */ 1541 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1542 1543 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1544 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1545 ste_wait(sc); 1546 1547 }else{ 1548 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1549 sc->ste_cdata.ste_tx_chain[ 1550 sc->ste_tx_prev_idx].ste_ptr->ste_next 1551 = cur_tx->ste_phys; 1552 } 1553 1554 sc->ste_tx_prev_idx=idx; 1555 1556 /* 1557 * If there's a BPF listener, bounce a copy of this frame 1558 * to him. 1559 */ 1560 if (ifp->if_bpf) 1561 bpf_mtap(ifp, cur_tx->ste_mbuf); 1562 1563 STE_INC(idx, STE_TX_LIST_CNT); 1564 sc->ste_cdata.ste_tx_cnt++; 1565 ifp->if_timer = 5; 1566 sc->ste_cdata.ste_tx_prod = idx; 1567 } 1568 1569 STE_UNLOCK(sc); 1570 1571 return; 1572} 1573 1574static void ste_watchdog(ifp) 1575 struct ifnet *ifp; 1576{ 1577 struct ste_softc *sc; 1578 1579 sc = ifp->if_softc; 1580 STE_LOCK(sc); 1581 1582 ifp->if_oerrors++; 1583 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1584 1585 ste_txeoc(sc); 1586 ste_txeof(sc); 1587 ste_rxeof(sc); 1588 ste_reset(sc); 1589 ste_init(sc); 1590 1591 if (ifp->if_snd.ifq_head != NULL) 1592 ste_start(ifp); 1593 STE_UNLOCK(sc); 1594 1595 return; 1596} 1597 1598static void ste_shutdown(dev) 1599 device_t dev; 1600{ 1601 struct ste_softc *sc; 1602 1603 sc = device_get_softc(dev); 1604 1605 ste_stop(sc); 1606 1607 return; 1608} 1609