if_ste.c revision 101493
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 101493 2002-08-07 22:31:27Z ambrisko $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48#include <net/if_vlan_var.h> 49 50#include <net/bpf.h> 51 52#include <vm/vm.h> /* for vtophys */ 53#include <vm/pmap.h> /* for vtophys */ 54#include <machine/bus_memio.h> 55#include <machine/bus_pio.h> 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <pci/pcireg.h> 65#include <pci/pcivar.h> 66 67/* "controller miibus0" required. See GENERIC if you get errors here. */ 68#include "miibus_if.h" 69 70#define STE_USEIOSPACE 71 72#include <pci/if_stereg.h> 73 74MODULE_DEPEND(ste, miibus, 1, 1, 1); 75 76#if !defined(lint) 77static const char rcsid[] = 78 "$FreeBSD: head/sys/pci/if_ste.c 101493 2002-08-07 22:31:27Z ambrisko $"; 79#endif 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 87 { 0, 0, NULL } 88}; 89 90static int ste_probe (device_t); 91static int ste_attach (device_t); 92static int ste_detach (device_t); 93static void ste_init (void *); 94static void ste_intr (void *); 95static void ste_rxeof (struct ste_softc *); 96static void ste_txeoc (struct ste_softc *); 97static void ste_txeof (struct ste_softc *); 98static void ste_stats_update (void *); 99static void ste_stop (struct ste_softc *); 100static void ste_reset (struct ste_softc *); 101static int ste_ioctl (struct ifnet *, u_long, caddr_t); 102static int ste_encap (struct ste_softc *, struct ste_chain *, 103 struct mbuf *); 104static void ste_start (struct ifnet *); 105static void ste_watchdog (struct ifnet *); 106static void ste_shutdown (device_t); 107static int ste_newbuf (struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *); 110static int ste_ifmedia_upd (struct ifnet *); 111static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 112 113static void ste_mii_sync (struct ste_softc *); 114static void ste_mii_send (struct ste_softc *, u_int32_t, int); 115static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg (device_t, int, int); 118static int ste_miibus_writereg (device_t, int, int, int); 119static void ste_miibus_statchg (device_t); 120 121static int ste_eeprom_wait (struct ste_softc *); 122static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 123static void ste_wait (struct ste_softc *); 124static u_int8_t ste_calchash (caddr_t); 125static void ste_setmulti (struct ste_softc *); 126static int ste_init_rx_list (struct ste_softc *); 127static void ste_init_tx_list (struct ste_softc *); 128 129#ifdef STE_USEIOSPACE 130#define STE_RES SYS_RES_IOPORT 131#define STE_RID STE_PCI_LOIO 132#else 133#define STE_RES SYS_RES_MEMORY 134#define STE_RID STE_PCI_LOMEM 135#endif 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167#define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 169 170#define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 172 173#define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 175 176#define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 178 179#define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 181 182#define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 184 185 186#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189/* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192static void ste_mii_sync(sc) 193 struct ste_softc *sc; 194{ 195 register int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205 206 return; 207} 208 209/* 210 * Clock a series of bits through the MII. 211 */ 212static void ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216{ 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232} 233 234/* 235 * Read an PHY register through the MII. 236 */ 237static int ste_mii_readreg(sc, frame) 238 struct ste_softc *sc; 239 struct ste_mii_frame *frame; 240 241{ 242 int i, ack; 243 244 STE_LOCK(sc); 245 246 /* 247 * Set up frame for RX. 248 */ 249 frame->mii_stdelim = STE_MII_STARTDELIM; 250 frame->mii_opcode = STE_MII_READOP; 251 frame->mii_turnaround = 0; 252 frame->mii_data = 0; 253 254 CSR_WRITE_2(sc, STE_PHYCTL, 0); 255 /* 256 * Turn on data xmit. 257 */ 258 MII_SET(STE_PHYCTL_MDIR); 259 260 ste_mii_sync(sc); 261 262 /* 263 * Send command/address info. 264 */ 265 ste_mii_send(sc, frame->mii_stdelim, 2); 266 ste_mii_send(sc, frame->mii_opcode, 2); 267 ste_mii_send(sc, frame->mii_phyaddr, 5); 268 ste_mii_send(sc, frame->mii_regaddr, 5); 269 270 /* Turn off xmit. */ 271 MII_CLR(STE_PHYCTL_MDIR); 272 273 /* Idle bit */ 274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 275 DELAY(1); 276 MII_SET(STE_PHYCTL_MCLK); 277 DELAY(1); 278 279 /* Check for ack */ 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 285 286 /* 287 * Now try reading data bits. If the ack failed, we still 288 * need to clock through 16 cycles to keep the PHY(s) in sync. 289 */ 290 if (ack) { 291 for(i = 0; i < 16; i++) { 292 MII_CLR(STE_PHYCTL_MCLK); 293 DELAY(1); 294 MII_SET(STE_PHYCTL_MCLK); 295 DELAY(1); 296 } 297 goto fail; 298 } 299 300 for (i = 0x8000; i; i >>= 1) { 301 MII_CLR(STE_PHYCTL_MCLK); 302 DELAY(1); 303 if (!ack) { 304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 305 frame->mii_data |= i; 306 DELAY(1); 307 } 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 } 311 312fail: 313 314 MII_CLR(STE_PHYCTL_MCLK); 315 DELAY(1); 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 319 STE_UNLOCK(sc); 320 321 if (ack) 322 return(1); 323 return(0); 324} 325 326/* 327 * Write to a PHY register through the MII. 328 */ 329static int ste_mii_writereg(sc, frame) 330 struct ste_softc *sc; 331 struct ste_mii_frame *frame; 332 333{ 334 STE_LOCK(sc); 335 336 /* 337 * Set up frame for TX. 338 */ 339 340 frame->mii_stdelim = STE_MII_STARTDELIM; 341 frame->mii_opcode = STE_MII_WRITEOP; 342 frame->mii_turnaround = STE_MII_TURNAROUND; 343 344 /* 345 * Turn on data output. 346 */ 347 MII_SET(STE_PHYCTL_MDIR); 348 349 ste_mii_sync(sc); 350 351 ste_mii_send(sc, frame->mii_stdelim, 2); 352 ste_mii_send(sc, frame->mii_opcode, 2); 353 ste_mii_send(sc, frame->mii_phyaddr, 5); 354 ste_mii_send(sc, frame->mii_regaddr, 5); 355 ste_mii_send(sc, frame->mii_turnaround, 2); 356 ste_mii_send(sc, frame->mii_data, 16); 357 358 /* Idle bit. */ 359 MII_SET(STE_PHYCTL_MCLK); 360 DELAY(1); 361 MII_CLR(STE_PHYCTL_MCLK); 362 DELAY(1); 363 364 /* 365 * Turn off xmit. 366 */ 367 MII_CLR(STE_PHYCTL_MDIR); 368 369 STE_UNLOCK(sc); 370 371 return(0); 372} 373 374static int ste_miibus_readreg(dev, phy, reg) 375 device_t dev; 376 int phy, reg; 377{ 378 struct ste_softc *sc; 379 struct ste_mii_frame frame; 380 381 sc = device_get_softc(dev); 382 383 bzero((char *)&frame, sizeof(frame)); 384 385 frame.mii_phyaddr = phy; 386 frame.mii_regaddr = reg; 387 ste_mii_readreg(sc, &frame); 388 389 return(frame.mii_data); 390} 391 392static int ste_miibus_writereg(dev, phy, reg, data) 393 device_t dev; 394 int phy, reg, data; 395{ 396 struct ste_softc *sc; 397 struct ste_mii_frame frame; 398 399 sc = device_get_softc(dev); 400 bzero((char *)&frame, sizeof(frame)); 401 402 frame.mii_phyaddr = phy; 403 frame.mii_regaddr = reg; 404 frame.mii_data = data; 405 406 ste_mii_writereg(sc, &frame); 407 408 return(0); 409} 410 411static void ste_miibus_statchg(dev) 412 device_t dev; 413{ 414 struct ste_softc *sc; 415 struct mii_data *mii; 416 417 sc = device_get_softc(dev); 418 STE_LOCK(sc); 419 mii = device_get_softc(sc->ste_miibus); 420 421 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 422 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 423 } else { 424 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 425 } 426 STE_UNLOCK(sc); 427 428 return; 429} 430 431static int ste_ifmedia_upd(ifp) 432 struct ifnet *ifp; 433{ 434 struct ste_softc *sc; 435 struct mii_data *mii; 436 437 sc = ifp->if_softc; 438 mii = device_get_softc(sc->ste_miibus); 439 sc->ste_link = 0; 440 if (mii->mii_instance) { 441 struct mii_softc *miisc; 442 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 443 mii_phy_reset(miisc); 444 } 445 mii_mediachg(mii); 446 447 return(0); 448} 449 450static void ste_ifmedia_sts(ifp, ifmr) 451 struct ifnet *ifp; 452 struct ifmediareq *ifmr; 453{ 454 struct ste_softc *sc; 455 struct mii_data *mii; 456 457 sc = ifp->if_softc; 458 mii = device_get_softc(sc->ste_miibus); 459 460 mii_pollstat(mii); 461 ifmr->ifm_active = mii->mii_media_active; 462 ifmr->ifm_status = mii->mii_media_status; 463 464 return; 465} 466 467static void ste_wait(sc) 468 struct ste_softc *sc; 469{ 470 register int i; 471 472 for (i = 0; i < STE_TIMEOUT; i++) { 473 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 474 break; 475 } 476 477 if (i == STE_TIMEOUT) 478 printf("ste%d: command never completed!\n", sc->ste_unit); 479 480 return; 481} 482 483/* 484 * The EEPROM is slow: give it time to come ready after issuing 485 * it a command. 486 */ 487static int ste_eeprom_wait(sc) 488 struct ste_softc *sc; 489{ 490 int i; 491 492 DELAY(1000); 493 494 for (i = 0; i < 100; i++) { 495 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 496 DELAY(1000); 497 else 498 break; 499 } 500 501 if (i == 100) { 502 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 503 return(1); 504 } 505 506 return(0); 507} 508 509/* 510 * Read a sequence of words from the EEPROM. Note that ethernet address 511 * data is stored in the EEPROM in network byte order. 512 */ 513static int ste_read_eeprom(sc, dest, off, cnt, swap) 514 struct ste_softc *sc; 515 caddr_t dest; 516 int off; 517 int cnt; 518 int swap; 519{ 520 int err = 0, i; 521 u_int16_t word = 0, *ptr; 522 523 if (ste_eeprom_wait(sc)) 524 return(1); 525 526 for (i = 0; i < cnt; i++) { 527 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 528 err = ste_eeprom_wait(sc); 529 if (err) 530 break; 531 word = CSR_READ_2(sc, STE_EEPROM_DATA); 532 ptr = (u_int16_t *)(dest + (i * 2)); 533 if (swap) 534 *ptr = ntohs(word); 535 else 536 *ptr = word; 537 } 538 539 return(err ? 1 : 0); 540} 541 542static u_int8_t ste_calchash(addr) 543 caddr_t addr; 544{ 545 546 u_int32_t crc, carry; 547 int i, j; 548 u_int8_t c; 549 550 /* Compute CRC for the address value. */ 551 crc = 0xFFFFFFFF; /* initial value */ 552 553 for (i = 0; i < 6; i++) { 554 c = *(addr + i); 555 for (j = 0; j < 8; j++) { 556 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 557 crc <<= 1; 558 c >>= 1; 559 if (carry) 560 crc = (crc ^ 0x04c11db6) | carry; 561 } 562 } 563 564 /* return the filter bit position */ 565 return(crc & 0x0000003F); 566} 567 568static void ste_setmulti(sc) 569 struct ste_softc *sc; 570{ 571 struct ifnet *ifp; 572 int h = 0; 573 u_int32_t hashes[2] = { 0, 0 }; 574 struct ifmultiaddr *ifma; 575 576 ifp = &sc->arpcom.ac_if; 577 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 578 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 579 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 580 return; 581 } 582 583 /* first, zot all the existing hash bits */ 584 CSR_WRITE_2(sc, STE_MAR0, 0); 585 CSR_WRITE_2(sc, STE_MAR1, 0); 586 CSR_WRITE_2(sc, STE_MAR2, 0); 587 CSR_WRITE_2(sc, STE_MAR3, 0); 588 589 /* now program new ones */ 590 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 591 if (ifma->ifma_addr->sa_family != AF_LINK) 592 continue; 593 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 594 if (h < 32) 595 hashes[0] |= (1 << h); 596 else 597 hashes[1] |= (1 << (h - 32)); 598 } 599 600 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 601 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 602 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 603 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 604 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 605 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 606 607 return; 608} 609 610static void ste_intr(xsc) 611 void *xsc; 612{ 613 struct ste_softc *sc; 614 struct ifnet *ifp; 615 u_int16_t status; 616 617 sc = xsc; 618 STE_LOCK(sc); 619 ifp = &sc->arpcom.ac_if; 620 621 /* See if this is really our interrupt. */ 622 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 623 STE_UNLOCK(sc); 624 return; 625 } 626 627 for (;;) { 628 status = CSR_READ_2(sc, STE_ISR_ACK); 629 630 if (!(status & STE_INTRS)) 631 break; 632 633 if (status & STE_ISR_RX_DMADONE) 634 ste_rxeof(sc); 635 636 if (status & STE_ISR_TX_DMADONE) 637 ste_txeof(sc); 638 639 if (status & STE_ISR_TX_DONE) 640 ste_txeoc(sc); 641 642 if (status & STE_ISR_STATS_OFLOW) { 643 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 644 ste_stats_update(sc); 645 } 646 647 if (status & STE_ISR_LINKEVENT) 648 mii_pollstat(device_get_softc(sc->ste_miibus)); 649 650 651 if (status & STE_ISR_HOSTERR) { 652 ste_reset(sc); 653 ste_init(sc); 654 } 655 } 656 657 /* Re-enable interrupts */ 658 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 659 660 if (ifp->if_snd.ifq_head != NULL) 661 ste_start(ifp); 662 663 STE_UNLOCK(sc); 664 665 return; 666} 667 668/* 669 * A frame has been uploaded: pass the resulting mbuf chain up to 670 * the higher level protocols. 671 */ 672static void ste_rxeof(sc) 673 struct ste_softc *sc; 674{ 675 struct ether_header *eh; 676 struct mbuf *m; 677 struct ifnet *ifp; 678 struct ste_chain_onefrag *cur_rx; 679 int total_len = 0, count=0; 680 u_int32_t rxstat; 681 682 ifp = &sc->arpcom.ac_if; 683 684 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 685 & STE_RXSTAT_DMADONE) { 686 if ((STE_RX_LIST_CNT - count) < 3) { 687 break; 688 } 689 690 cur_rx = sc->ste_cdata.ste_rx_head; 691 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 692 693 /* 694 * If an error occurs, update stats, clear the 695 * status word and leave the mbuf cluster in place: 696 * it should simply get re-used next time this descriptor 697 * comes up in the ring. 698 */ 699 if (rxstat & STE_RXSTAT_FRAME_ERR) { 700 ifp->if_ierrors++; 701 cur_rx->ste_ptr->ste_status = 0; 702 continue; 703 } 704 705 /* 706 * If there error bit was not set, the upload complete 707 * bit should be set which means we have a valid packet. 708 * If not, something truly strange has happened. 709 */ 710 if (!(rxstat & STE_RXSTAT_DMADONE)) { 711 printf("ste%d: bad receive status -- packet dropped", 712 sc->ste_unit); 713 ifp->if_ierrors++; 714 cur_rx->ste_ptr->ste_status = 0; 715 continue; 716 } 717 718 /* No errors; receive the packet. */ 719 m = cur_rx->ste_mbuf; 720 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 721 722 /* 723 * Try to conjure up a new mbuf cluster. If that 724 * fails, it means we have an out of memory condition and 725 * should leave the buffer in place and continue. This will 726 * result in a lost packet, but there's little else we 727 * can do in this situation. 728 */ 729 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 730 ifp->if_ierrors++; 731 cur_rx->ste_ptr->ste_status = 0; 732 continue; 733 } 734 735 ifp->if_ipackets++; 736 eh = mtod(m, struct ether_header *); 737 m->m_pkthdr.rcvif = ifp; 738 m->m_pkthdr.len = m->m_len = total_len; 739 740 /* Remove header from mbuf and pass it on. */ 741 m_adj(m, sizeof(struct ether_header)); 742 ether_input(ifp, eh, m); 743 744 cur_rx->ste_ptr->ste_status = 0; 745 count++; 746 } 747 748 return; 749} 750 751static void ste_txeoc(sc) 752 struct ste_softc *sc; 753{ 754 u_int8_t txstat; 755 struct ifnet *ifp; 756 757 ifp = &sc->arpcom.ac_if; 758 759 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 760 STE_TXSTATUS_TXDONE) { 761 if (txstat & STE_TXSTATUS_UNDERRUN || 762 txstat & STE_TXSTATUS_EXCESSCOLLS || 763 txstat & STE_TXSTATUS_RECLAIMERR) { 764 ifp->if_oerrors++; 765 printf("ste%d: transmission error: %x\n", 766 sc->ste_unit, txstat); 767 768 ste_reset(sc); 769 ste_init(sc); 770 771 if (txstat & STE_TXSTATUS_UNDERRUN && 772 sc->ste_tx_thresh < STE_PACKET_SIZE) { 773 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 774 printf("ste%d: tx underrun, increasing tx" 775 " start threshold to %d bytes\n", 776 sc->ste_unit, sc->ste_tx_thresh); 777 } 778 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 779 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 780 (STE_PACKET_SIZE >> 4)); 781 } 782 ste_init(sc); 783 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 784 } 785 786 return; 787} 788 789static void ste_txeof(sc) 790 struct ste_softc *sc; 791{ 792 struct ste_chain *cur_tx = NULL; 793 struct ifnet *ifp; 794 int idx; 795 796 ifp = &sc->arpcom.ac_if; 797 798 idx = sc->ste_cdata.ste_tx_cons; 799 while(idx != sc->ste_cdata.ste_tx_prod) { 800 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 801 802 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 803 break; 804 805 if (cur_tx->ste_mbuf != NULL) { 806 m_freem(cur_tx->ste_mbuf); 807 cur_tx->ste_mbuf = NULL; 808 } 809 810 ifp->if_opackets++; 811 812 sc->ste_cdata.ste_tx_cnt--; 813 STE_INC(idx, STE_TX_LIST_CNT); 814 ifp->if_timer = 0; 815 } 816 817 sc->ste_cdata.ste_tx_cons = idx; 818 819 if (cur_tx != NULL) 820 ifp->if_flags &= ~IFF_OACTIVE; 821 822 return; 823} 824 825static void ste_stats_update(xsc) 826 void *xsc; 827{ 828 struct ste_softc *sc; 829 struct ifnet *ifp; 830 struct mii_data *mii; 831 832 sc = xsc; 833 STE_LOCK(sc); 834 835 ifp = &sc->arpcom.ac_if; 836 mii = device_get_softc(sc->ste_miibus); 837 838 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 839 + CSR_READ_1(sc, STE_MULTI_COLLS) 840 + CSR_READ_1(sc, STE_SINGLE_COLLS); 841 842 if (!sc->ste_link) { 843 mii_pollstat(mii); 844 if (mii->mii_media_status & IFM_ACTIVE && 845 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 846 sc->ste_link++; 847 /* 848 * we don't get a call-back on re-init so do it 849 * otherwise we get stuck in the wrong link state 850 */ 851 ste_miibus_statchg(sc->ste_dev); 852 if (ifp->if_snd.ifq_head != NULL) 853 ste_start(ifp); 854 } 855 } 856 857 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 858 STE_UNLOCK(sc); 859 860 return; 861} 862 863 864/* 865 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 866 * IDs against our list and return a device name if we find a match. 867 */ 868static int ste_probe(dev) 869 device_t dev; 870{ 871 struct ste_type *t; 872 873 t = ste_devs; 874 875 while(t->ste_name != NULL) { 876 if ((pci_get_vendor(dev) == t->ste_vid) && 877 (pci_get_device(dev) == t->ste_did)) { 878 device_set_desc(dev, t->ste_name); 879 return(0); 880 } 881 t++; 882 } 883 884 return(ENXIO); 885} 886 887/* 888 * Attach the interface. Allocate softc structures, do ifmedia 889 * setup and ethernet/BPF attach. 890 */ 891static int ste_attach(dev) 892 device_t dev; 893{ 894 u_int32_t command; 895 struct ste_softc *sc; 896 struct ifnet *ifp; 897 int unit, error = 0, rid; 898 899 sc = device_get_softc(dev); 900 unit = device_get_unit(dev); 901 bzero(sc, sizeof(struct ste_softc)); 902 sc->ste_dev = dev; 903 904 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 905 MTX_DEF | MTX_RECURSE); 906 STE_LOCK(sc); 907 908 /* 909 * Handle power management nonsense. 910 */ 911 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 912 u_int32_t iobase, membase, irq; 913 914 /* Save important PCI config data. */ 915 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 916 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 917 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 918 919 /* Reset the power state. */ 920 printf("ste%d: chip is in D%d power mode " 921 "-- setting to D0\n", unit, 922 pci_get_powerstate(dev)); 923 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 924 925 /* Restore PCI config data. */ 926 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 927 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 928 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 929 } 930 931 /* 932 * Map control/status registers. 933 */ 934 pci_enable_busmaster(dev); 935 pci_enable_io(dev, SYS_RES_IOPORT); 936 pci_enable_io(dev, SYS_RES_MEMORY); 937 command = pci_read_config(dev, PCIR_COMMAND, 4); 938 939#ifdef STE_USEIOSPACE 940 if (!(command & PCIM_CMD_PORTEN)) { 941 printf("ste%d: failed to enable I/O ports!\n", unit); 942 error = ENXIO; 943 goto fail; 944 } 945#else 946 if (!(command & PCIM_CMD_MEMEN)) { 947 printf("ste%d: failed to enable memory mapping!\n", unit); 948 error = ENXIO; 949 goto fail; 950 } 951#endif 952 953 rid = STE_RID; 954 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 955 0, ~0, 1, RF_ACTIVE); 956 957 if (sc->ste_res == NULL) { 958 printf ("ste%d: couldn't map ports/memory\n", unit); 959 error = ENXIO; 960 goto fail; 961 } 962 963 sc->ste_btag = rman_get_bustag(sc->ste_res); 964 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 965 966 rid = 0; 967 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 968 RF_SHAREABLE | RF_ACTIVE); 969 970 if (sc->ste_irq == NULL) { 971 printf("ste%d: couldn't map interrupt\n", unit); 972 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 973 error = ENXIO; 974 goto fail; 975 } 976 977 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 978 ste_intr, sc, &sc->ste_intrhand); 979 980 if (error) { 981 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 982 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 983 printf("ste%d: couldn't set up irq\n", unit); 984 goto fail; 985 } 986 987 callout_handle_init(&sc->ste_stat_ch); 988 989 /* Reset the adapter. */ 990 ste_reset(sc); 991 992 /* 993 * Get station address from the EEPROM. 994 */ 995 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 996 STE_EEADDR_NODE0, 3, 0)) { 997 printf("ste%d: failed to read station address\n", unit); 998 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1000 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1001 error = ENXIO;; 1002 goto fail; 1003 } 1004 1005 /* 1006 * A Sundance chip was detected. Inform the world. 1007 */ 1008 printf("ste%d: Ethernet address: %6D\n", unit, 1009 sc->arpcom.ac_enaddr, ":"); 1010 1011 sc->ste_unit = unit; 1012 1013 /* Allocate the descriptor queues. */ 1014 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1015 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1016 1017 if (sc->ste_ldata == NULL) { 1018 printf("ste%d: no memory for list buffers!\n", unit); 1019 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1020 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1021 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1022 error = ENXIO; 1023 goto fail; 1024 } 1025 1026 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1027 1028 /* Do MII setup. */ 1029 if (mii_phy_probe(dev, &sc->ste_miibus, 1030 ste_ifmedia_upd, ste_ifmedia_sts)) { 1031 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1032 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1033 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1034 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1035 contigfree(sc->ste_ldata, 1036 sizeof(struct ste_list_data), M_DEVBUF); 1037 error = ENXIO; 1038 goto fail; 1039 } 1040 1041 ifp = &sc->arpcom.ac_if; 1042 ifp->if_softc = sc; 1043 ifp->if_unit = unit; 1044 ifp->if_name = "ste"; 1045 ifp->if_mtu = ETHERMTU; 1046 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1047 ifp->if_ioctl = ste_ioctl; 1048 ifp->if_output = ether_output; 1049 ifp->if_start = ste_start; 1050 ifp->if_watchdog = ste_watchdog; 1051 ifp->if_init = ste_init; 1052 ifp->if_baudrate = 10000000; 1053 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1054 1055 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1056 1057 /* 1058 * Call MI attach routine. 1059 */ 1060 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1061 1062 /* 1063 * Tell the upper layer(s) we support long frames. 1064 */ 1065 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1066 1067 STE_UNLOCK(sc); 1068 return(0); 1069 1070fail: 1071 STE_UNLOCK(sc); 1072 mtx_destroy(&sc->ste_mtx); 1073 return(error); 1074} 1075 1076static int ste_detach(dev) 1077 device_t dev; 1078{ 1079 struct ste_softc *sc; 1080 struct ifnet *ifp; 1081 1082 sc = device_get_softc(dev); 1083 STE_LOCK(sc); 1084 ifp = &sc->arpcom.ac_if; 1085 1086 ste_stop(sc); 1087 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1088 1089 bus_generic_detach(dev); 1090 device_delete_child(dev, sc->ste_miibus); 1091 1092 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1093 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1094 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1095 1096 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1097 1098 STE_UNLOCK(sc); 1099 mtx_destroy(&sc->ste_mtx); 1100 1101 return(0); 1102} 1103 1104static int ste_newbuf(sc, c, m) 1105 struct ste_softc *sc; 1106 struct ste_chain_onefrag *c; 1107 struct mbuf *m; 1108{ 1109 struct mbuf *m_new = NULL; 1110 1111 if (m == NULL) { 1112 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1113 if (m_new == NULL) 1114 return(ENOBUFS); 1115 MCLGET(m_new, M_DONTWAIT); 1116 if (!(m_new->m_flags & M_EXT)) { 1117 m_freem(m_new); 1118 return(ENOBUFS); 1119 } 1120 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1121 } else { 1122 m_new = m; 1123 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1124 m_new->m_data = m_new->m_ext.ext_buf; 1125 } 1126 1127 m_adj(m_new, ETHER_ALIGN); 1128 1129 c->ste_mbuf = m_new; 1130 c->ste_ptr->ste_status = 0; 1131 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1132 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; 1133 1134 return(0); 1135} 1136 1137static int ste_init_rx_list(sc) 1138 struct ste_softc *sc; 1139{ 1140 struct ste_chain_data *cd; 1141 struct ste_list_data *ld; 1142 int i; 1143 1144 cd = &sc->ste_cdata; 1145 ld = sc->ste_ldata; 1146 1147 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1148 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1149 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1150 return(ENOBUFS); 1151 if (i == (STE_RX_LIST_CNT - 1)) { 1152 cd->ste_rx_chain[i].ste_next = 1153 &cd->ste_rx_chain[0]; 1154 ld->ste_rx_list[i].ste_next = 1155 vtophys(&ld->ste_rx_list[0]); 1156 } else { 1157 cd->ste_rx_chain[i].ste_next = 1158 &cd->ste_rx_chain[i + 1]; 1159 ld->ste_rx_list[i].ste_next = 1160 vtophys(&ld->ste_rx_list[i + 1]); 1161 } 1162 ld->ste_rx_list[i].ste_status = 0; 1163 } 1164 1165 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1166 1167 return(0); 1168} 1169 1170static void ste_init_tx_list(sc) 1171 struct ste_softc *sc; 1172{ 1173 struct ste_chain_data *cd; 1174 struct ste_list_data *ld; 1175 int i; 1176 1177 cd = &sc->ste_cdata; 1178 ld = sc->ste_ldata; 1179 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1180 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1181 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1182 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1183 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1184 if (i == (STE_TX_LIST_CNT - 1)) 1185 cd->ste_tx_chain[i].ste_next = 1186 &cd->ste_tx_chain[0]; 1187 else 1188 cd->ste_tx_chain[i].ste_next = 1189 &cd->ste_tx_chain[i + 1]; 1190 if (i == 0) 1191 cd->ste_tx_chain[i].ste_prev = 1192 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1193 else 1194 cd->ste_tx_chain[i].ste_prev = 1195 &cd->ste_tx_chain[i - 1]; 1196 } 1197 1198 cd->ste_tx_prod = 0; 1199 cd->ste_tx_cons = 0; 1200 cd->ste_tx_cnt = 0; 1201 1202 return; 1203} 1204 1205static void ste_init(xsc) 1206 void *xsc; 1207{ 1208 struct ste_softc *sc; 1209 int i; 1210 struct ifnet *ifp; 1211 struct mii_data *mii; 1212 1213 sc = xsc; 1214 STE_LOCK(sc); 1215 ifp = &sc->arpcom.ac_if; 1216 mii = device_get_softc(sc->ste_miibus); 1217 1218 ste_stop(sc); 1219 1220 /* Init our MAC address */ 1221 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1222 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1223 } 1224 1225 /* Init RX list */ 1226 if (ste_init_rx_list(sc) == ENOBUFS) { 1227 printf("ste%d: initialization failed: no " 1228 "memory for RX buffers\n", sc->ste_unit); 1229 ste_stop(sc); 1230 STE_UNLOCK(sc); 1231 return; 1232 } 1233 1234 /* Set RX polling interval */ 1235 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1236 1237 /* Init TX descriptors */ 1238 ste_init_tx_list(sc); 1239 1240 /* Set the TX freethresh value */ 1241 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1242 1243 /* Set the TX start threshold for best performance. */ 1244 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1245 1246 /* Set the TX reclaim threshold. */ 1247 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1248 1249 /* Set up the RX filter. */ 1250 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1251 1252 /* If we want promiscuous mode, set the allframes bit. */ 1253 if (ifp->if_flags & IFF_PROMISC) { 1254 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1255 } else { 1256 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1257 } 1258 1259 /* Set capture broadcast bit to accept broadcast frames. */ 1260 if (ifp->if_flags & IFF_BROADCAST) { 1261 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1262 } else { 1263 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1264 } 1265 1266 ste_setmulti(sc); 1267 1268 /* Load the address of the RX list. */ 1269 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1270 ste_wait(sc); 1271 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1272 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1273 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1274 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1275 1276 /* Set TX polling interval (defer until we TX first packet */ 1277 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1278 1279 /* Load address of the TX list */ 1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1281 ste_wait(sc); 1282 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1283 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1284 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1285 ste_wait(sc); 1286 sc->ste_tx_prev_idx=-1; 1287 1288 /* Enable receiver and transmitter */ 1289 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1290 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1291 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1292 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1293 1294 /* Enable stats counters. */ 1295 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1296 1297 /* Enable interrupts. */ 1298 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1299 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1300 1301 /* Accept VLAN length packets */ 1302 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN); 1303 1304 ste_ifmedia_upd(ifp); 1305 1306 ifp->if_flags |= IFF_RUNNING; 1307 ifp->if_flags &= ~IFF_OACTIVE; 1308 1309 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1310 STE_UNLOCK(sc); 1311 1312 return; 1313} 1314 1315static void ste_stop(sc) 1316 struct ste_softc *sc; 1317{ 1318 int i; 1319 struct ifnet *ifp; 1320 1321 STE_LOCK(sc); 1322 ifp = &sc->arpcom.ac_if; 1323 1324 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1325 1326 CSR_WRITE_2(sc, STE_IMR, 0); 1327 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1328 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1329 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1330 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1331 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1332 ste_wait(sc); 1333 /* 1334 * Try really hard to stop the RX engine or under heavy RX 1335 * data chip will write into de-allocated memory. 1336 */ 1337 ste_reset(sc); 1338 1339 sc->ste_link = 0; 1340 1341 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1342 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1343 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1344 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1345 } 1346 } 1347 1348 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1349 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1350 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1351 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1352 } 1353 } 1354 1355 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1356 1357 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1358 STE_UNLOCK(sc); 1359 1360 return; 1361} 1362 1363static void ste_reset(sc) 1364 struct ste_softc *sc; 1365{ 1366 int i; 1367 1368 STE_SETBIT4(sc, STE_ASICCTL, 1369 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1370 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1371 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1372 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1373 STE_ASICCTL_EXTRESET_RESET); 1374 1375 DELAY(100000); 1376 1377 for (i = 0; i < STE_TIMEOUT; i++) { 1378 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1379 break; 1380 } 1381 1382 if (i == STE_TIMEOUT) 1383 printf("ste%d: global reset never completed\n", sc->ste_unit); 1384 1385 return; 1386} 1387 1388static int ste_ioctl(ifp, command, data) 1389 struct ifnet *ifp; 1390 u_long command; 1391 caddr_t data; 1392{ 1393 struct ste_softc *sc; 1394 struct ifreq *ifr; 1395 struct mii_data *mii; 1396 int error = 0; 1397 1398 sc = ifp->if_softc; 1399 STE_LOCK(sc); 1400 ifr = (struct ifreq *)data; 1401 1402 switch(command) { 1403 case SIOCSIFADDR: 1404 case SIOCGIFADDR: 1405 case SIOCSIFMTU: 1406 error = ether_ioctl(ifp, command, data); 1407 break; 1408 case SIOCSIFFLAGS: 1409 if (ifp->if_flags & IFF_UP) { 1410 if (ifp->if_flags & IFF_RUNNING && 1411 ifp->if_flags & IFF_PROMISC && 1412 !(sc->ste_if_flags & IFF_PROMISC)) { 1413 STE_SETBIT1(sc, STE_RX_MODE, 1414 STE_RXMODE_PROMISC); 1415 } else if (ifp->if_flags & IFF_RUNNING && 1416 !(ifp->if_flags & IFF_PROMISC) && 1417 sc->ste_if_flags & IFF_PROMISC) { 1418 STE_CLRBIT1(sc, STE_RX_MODE, 1419 STE_RXMODE_PROMISC); 1420 } 1421 if (!(ifp->if_flags & IFF_RUNNING)) { 1422 sc->ste_tx_thresh = STE_MIN_FRAMELEN * 2; 1423 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1424 ste_init(sc); 1425 } 1426 } else { 1427 if (ifp->if_flags & IFF_RUNNING) 1428 ste_stop(sc); 1429 } 1430 sc->ste_if_flags = ifp->if_flags; 1431 error = 0; 1432 break; 1433 case SIOCADDMULTI: 1434 case SIOCDELMULTI: 1435 ste_setmulti(sc); 1436 error = 0; 1437 break; 1438 case SIOCGIFMEDIA: 1439 case SIOCSIFMEDIA: 1440 mii = device_get_softc(sc->ste_miibus); 1441 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1442 break; 1443 default: 1444 error = EINVAL; 1445 break; 1446 } 1447 1448 STE_UNLOCK(sc); 1449 1450 return(error); 1451} 1452 1453static int ste_encap(sc, c, m_head) 1454 struct ste_softc *sc; 1455 struct ste_chain *c; 1456 struct mbuf *m_head; 1457{ 1458 int frag = 0; 1459 struct ste_frag *f = NULL; 1460 struct mbuf *m; 1461 struct ste_desc *d; 1462 int total_len = 0; 1463 1464 d = c->ste_ptr; 1465 d->ste_ctl = 0; 1466 1467 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1468 if (m->m_len != 0) { 1469 if (frag == STE_MAXFRAGS) 1470 break; 1471 total_len += m->m_len; 1472 f = &d->ste_frags[frag]; 1473 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1474 f->ste_len = m->m_len; 1475 frag++; 1476 } 1477 } 1478 1479 c->ste_mbuf = m_head; 1480 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1481 d->ste_ctl = 1; 1482 1483 return(0); 1484} 1485 1486static void ste_start(ifp) 1487 struct ifnet *ifp; 1488{ 1489 struct ste_softc *sc; 1490 struct mbuf *m_head = NULL; 1491 struct ste_chain *cur_tx = NULL; 1492 int idx; 1493 1494 sc = ifp->if_softc; 1495 STE_LOCK(sc); 1496 1497 if (!sc->ste_link) { 1498 STE_UNLOCK(sc); 1499 return; 1500 } 1501 1502 if (ifp->if_flags & IFF_OACTIVE) { 1503 STE_UNLOCK(sc); 1504 return; 1505 } 1506 1507 idx = sc->ste_cdata.ste_tx_prod; 1508 1509 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1510 1511 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1512 ifp->if_flags |= IFF_OACTIVE; 1513 break; 1514 } 1515 1516 IF_DEQUEUE(&ifp->if_snd, m_head); 1517 if (m_head == NULL) 1518 break; 1519 1520 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1521 1522 ste_encap(sc, cur_tx, m_head); 1523 1524 cur_tx->ste_ptr->ste_next = 0; 1525 1526 if(sc->ste_tx_prev_idx < 0){ 1527 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1528 /* Load address of the TX list */ 1529 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1530 ste_wait(sc); 1531 1532 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1533 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1534 1535 /* Set TX polling interval to start TX engine */ 1536 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1537 1538 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1539 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1540 ste_wait(sc); 1541 1542 }else{ 1543 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1544 sc->ste_cdata.ste_tx_chain[ 1545 sc->ste_tx_prev_idx].ste_ptr->ste_next 1546 = cur_tx->ste_phys; 1547 } 1548 1549 sc->ste_tx_prev_idx=idx; 1550 1551 /* 1552 * If there's a BPF listener, bounce a copy of this frame 1553 * to him. 1554 */ 1555 if (ifp->if_bpf) 1556 bpf_mtap(ifp, cur_tx->ste_mbuf); 1557 1558 STE_INC(idx, STE_TX_LIST_CNT); 1559 sc->ste_cdata.ste_tx_cnt++; 1560 ifp->if_timer = 5; 1561 sc->ste_cdata.ste_tx_prod = idx; 1562 } 1563 1564 STE_UNLOCK(sc); 1565 1566 return; 1567} 1568 1569static void ste_watchdog(ifp) 1570 struct ifnet *ifp; 1571{ 1572 struct ste_softc *sc; 1573 1574 sc = ifp->if_softc; 1575 STE_LOCK(sc); 1576 1577 ifp->if_oerrors++; 1578 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1579 1580 ste_txeoc(sc); 1581 ste_txeof(sc); 1582 ste_rxeof(sc); 1583 ste_reset(sc); 1584 ste_init(sc); 1585 1586 if (ifp->if_snd.ifq_head != NULL) 1587 ste_start(ifp); 1588 STE_UNLOCK(sc); 1589 1590 return; 1591} 1592 1593static void ste_shutdown(dev) 1594 device_t dev; 1595{ 1596 struct ste_softc *sc; 1597 1598 sc = device_get_softc(dev); 1599 1600 ste_stop(sc); 1601 1602 return; 1603} 1604