165543Scg/*- 265543Scg * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 365543Scg * All rights reserved. 465543Scg * 565543Scg * Redistribution and use in source and binary forms, with or without 665543Scg * modification, are permitted provided that the following conditions 765543Scg * are met: 865543Scg * 1. Redistributions of source code must retain the above copyright 965543Scg * notice, this list of conditions and the following disclaimer. 1065543Scg * 2. Redistributions in binary form must reproduce the above copyright 1165543Scg * notice, this list of conditions and the following disclaimer in the 1265543Scg * documentation and/or other materials provided with the distribution. 1365543Scg * 1465543Scg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1565543Scg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1665543Scg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1765543Scg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1865543Scg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1965543Scg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2065543Scg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2165543Scg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2265543Scg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2365543Scg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2465543Scg * SUCH DAMAGE. 2565543Scg * 26137500Sjulian * maestro_reg.h,v 1.13 2001/11/11 18:29:46 taku Exp 2765543Scg * $FreeBSD$ 2865543Scg */ 2965543Scg 3065543Scg#ifndef MAESTRO_REG_H_INCLUDED 3165543Scg#define MAESTRO_REG_H_INCLUDED 3265543Scg 3365543Scg/* ----------------------------- 3465543Scg * PCI config registers 3565543Scg */ 3665543Scg 3765543Scg/* Legacy emulation */ 3865543Scg#define CONF_LEGACY 0x40 3965543Scg 4065543Scg#define LEGACY_DISABLED 0x8000 4165543Scg 4265543Scg/* Chip configurations */ 4365543Scg#define CONF_MAESTRO 0x50 44137500Sjulian#define MAESTRO_PMC 0x08000000 45137500Sjulian#define MAESTRO_SPDIF 0x01000000 46137500Sjulian#define MAESTRO_HWVOL 0x00800000 4765543Scg#define MAESTRO_CHIBUS 0x00100000 4865543Scg#define MAESTRO_POSTEDWRITE 0x00000080 4965543Scg#define MAESTRO_DMA_PCITIMING 0x00000040 50137500Sjulian#define MAESTRO_SWAP_LR 0x00000020 5165543Scg 5265543Scg/* ACPI configurations */ 5365543Scg#define CONF_ACPI_STOPCLOCK 0x54 5465543Scg#define ACPI_PART_2ndC_CLOCK 15 5565543Scg#define ACPI_PART_CODEC_CLOCK 14 5665543Scg#define ACPI_PART_978 13 /* Docking station or something */ 5765543Scg#define ACPI_PART_SPDIF 12 5865543Scg#define ACPI_PART_GLUE 11 /* What? */ 5965543Scg#define ACPI_PART_DAA 10 6065543Scg#define ACPI_PART_PCI_IF 9 6165543Scg#define ACPI_PART_HW_VOL 8 6265543Scg#define ACPI_PART_GPIO 7 6365543Scg#define ACPI_PART_ASSP 6 6465543Scg#define ACPI_PART_SB 5 6565543Scg#define ACPI_PART_FM 4 6665543Scg#define ACPI_PART_RINGBUS 3 6765543Scg#define ACPI_PART_MIDI 2 6865543Scg#define ACPI_PART_GAME_PORT 1 6965543Scg#define ACPI_PART_WP 0 7065543Scg 7165543Scg/* Power management */ 7265543Scg#define CONF_PM_PTR 0x34 /* BYTE R */ 7365543Scg#define PM_CID 0 /* BYTE R */ 7465543Scg#define PPMI_CID 1 7565543Scg#define PM_CTRL 4 /* BYTE RW */ 7665543Scg#define PPMI_D0 0 /* Full power */ 7765543Scg#define PPMI_D1 1 /* Medium power */ 7865543Scg#define PPMI_D2 2 /* Low power */ 7965543Scg#define PPMI_D3 3 /* Turned off */ 8065543Scg 8165543Scg 8265543Scg/* ----------------------------- 8365543Scg * I/O ports 8465543Scg */ 8565543Scg 8665543Scg/* Direct Sound Processor (aka WP) */ 8765543Scg#define PORT_DSP_DATA 0x00 /* WORD RW */ 8865543Scg#define PORT_DSP_INDEX 0x02 /* WORD RW */ 8965543Scg#define PORT_INT_STAT 0x04 /* WORD RW */ 9065543Scg#define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 9165543Scg 9265543Scg/* WaveCache */ 9365543Scg#define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 9465543Scg#define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 9565543Scg#define WAVCACHE_PCMBAR 0x1fc 9665543Scg#define WAVCACHE_WTBAR 0x1f0 9765543Scg#define WAVCACHE_BASEADDR_SHIFT 12 9865543Scg 9965543Scg#define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 10065543Scg#define WAVCACHE_CHCTL_U8 0x0004 10165543Scg#define WAVCACHE_CHCTL_STEREO 0x0002 10265543Scg#define WAVCACHE_CHCTL_DECREMENTAL 0x0001 10365543Scg 10465543Scg#define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 10565543Scg#define WAVCACHE_EXTRA_CH_ENABLED 0x0200 10665543Scg#define WAVCACHE_ENABLED 0x0100 10765543Scg#define WAVCACHE_CH_60_ENABLED 0x0080 10865543Scg#define WAVCACHE_WTSIZE_MASK 0x0060 10965543Scg#define WAVCACHE_WTSIZE_1MB 0x0000 11065543Scg#define WAVCACHE_WTSIZE_2MB 0x0020 11165543Scg#define WAVCACHE_WTSIZE_4MB 0x0040 11265543Scg#define WAVCACHE_WTSIZE_8MB 0x0060 11365543Scg#define WAVCACHE_SGC_MASK 0x000c 11465543Scg#define WAVCACHE_SGC_DISABLED 0x0000 11565543Scg#define WAVCACHE_SGC_40_47 0x0004 11665543Scg#define WAVCACHE_SGC_32_47 0x0008 11765543Scg#define WAVCACHE_TESTMODE 0x0001 11865543Scg 11965543Scg/* Host Interruption */ 12065543Scg#define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 12165543Scg#define HOSTINT_CTRL_SOFT_RESET 0x8000 12265543Scg#define HOSTINT_CTRL_DSOUND_RESET 0x4000 12365543Scg#define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 12465543Scg#define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 12565543Scg#define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 12665543Scg#define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 12765543Scg#define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 12865543Scg#define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 12965543Scg#define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 13065543Scg#define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 13165543Scg 13265543Scg#define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 13365543Scg#define HOSTINT_STAT_HWVOL 0x40 13465543Scg#define HOSTINT_STAT_ASSP 0x10 13565543Scg#define HOSTINT_STAT_ISDN 0x08 13665543Scg#define HOSTINT_STAT_DSOUND 0x04 13765543Scg#define HOSTINT_STAT_MPU401 0x02 13865543Scg#define HOSTINT_STAT_SB 0x01 13965543Scg 14065543Scg/* Hardware volume */ 141137500Sjulian#define PORT_HWVOL_CTRL 0x1b /* BYTE RW */ 142137500Sjulian#define HWVOL_CTRL_SPLIT_SHADOW 0x01 143137500Sjulian 14465543Scg#define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 14565543Scg#define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 14665543Scg#define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 14765543Scg#define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 14870619Sjhb#define HWVOL_NOP 0x88 149137500Sjulian#define HWVOL_MUTE 0x11 15070619Sjhb#define HWVOL_UP 0xaa 15170619Sjhb#define HWVOL_DOWN 0x66 15265543Scg 15365543Scg/* CODEC */ 15465543Scg#define PORT_CODEC_CMD 0x30 /* BYTE W */ 15565543Scg#define CODEC_CMD_READ 0x80 15665543Scg#define CODEC_CMD_WRITE 0x00 15765543Scg#define CODEC_CMD_ADDR_MASK 0x7f 15865543Scg 15965543Scg#define PORT_CODEC_STAT 0x30 /* BYTE R */ 16065543Scg#define CODEC_STAT_MASK 0x01 16165543Scg#define CODEC_STAT_RW_DONE 0x00 16265543Scg#define CODEC_STAT_PROGLESS 0x01 16365543Scg 16465543Scg#define PORT_CODEC_REG 0x32 /* WORD RW */ 16565543Scg 16665543Scg/* Ring bus control */ 16765543Scg#define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 16865543Scg#define RINGBUS_CTRL_I2S_ENABLED 0x80000000 16965543Scg#define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 17065543Scg#define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 17165543Scg#define RINGBUS_CTRL_AC97_SWRESET 0x08000000 17265543Scg 17365543Scg#define RINGBUS_SRC_MIC 20 17465543Scg#define RINGBUS_SRC_I2S 16 17565543Scg#define RINGBUS_SRC_ADC 12 17665543Scg#define RINGBUS_SRC_MODEM 8 17765543Scg#define RINGBUS_SRC_DSOUND 4 17865543Scg#define RINGBUS_SRC_ASSP 0 17965543Scg 18065543Scg#define RINGBUS_DEST_MONORAL 000 18165543Scg#define RINGBUS_DEST_STEREO 010 18265543Scg#define RINGBUS_DEST_NONE 0 18365543Scg#define RINGBUS_DEST_DAC 1 18465543Scg#define RINGBUS_DEST_MODEM_IN 2 18565543Scg#define RINGBUS_DEST_RESERVED3 3 18665543Scg#define RINGBUS_DEST_DSOUND_IN 4 18765543Scg#define RINGBUS_DEST_ASSP_IN 5 18865543Scg 189137500Sjulian/* Ring bus control B */ 190137500Sjulian#define PORT_RINGBUS_CTRL_B 0x38 /* BYTE RW */ 191137500Sjulian#define RINGBUS_CTRL_SSPE 0x40 192137500Sjulian#define RINGBUS_CTRL_2ndCODEC 0x20 193137500Sjulian#define RINGBUS_CTRL_SPDIF 0x10 194137500Sjulian#define RINGBUS_CTRL_ITB_DISABLE 0x08 195137500Sjulian#define RINGBUS_CTRL_CODEC_ID_MASK 0x03 196137500Sjulian#define RINGBUS_CTRL_CODEC_ID_AC98 2 197137500Sjulian 19865543Scg/* General Purpose I/O */ 19965543Scg#define PORT_GPIO_DATA 0x60 /* WORD RW */ 20065543Scg#define PORT_GPIO_MASK 0x64 /* WORD RW */ 20165543Scg#define PORT_GPIO_DIR 0x68 /* WORD RW */ 20265543Scg 20365543Scg/* Application Specific Signal Processor */ 20465543Scg#define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 20565543Scg#define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 20665543Scg#define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 20765543Scg#define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 20865543Scg#define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 20965543Scg#define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 21065543Scg#define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 21165543Scg#define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 21265543Scg 21365543Scg 21465543Scg/* ----------------------------- 21565543Scg * Wave Processor Indexed Data Registers. 21665543Scg */ 21765543Scg 21865543Scg#define WPREG_DATA_PORT 0 21965543Scg#define WPREG_CRAM_PTR 1 22065543Scg#define WPREG_CRAM_DATA 2 22165543Scg#define WPREG_WAVE_DATA 3 22265543Scg#define WPREG_WAVE_PTR_LOW 4 22365543Scg#define WPREG_WAVE_PTR_HIGH 5 22465543Scg 22565543Scg#define WPREG_TIMER_FREQ 6 22665543Scg#define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 22765543Scg#define WP_TIMER_FREQ_PRESCALE_SHIFT 5 22865543Scg#define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 22965543Scg#define WP_TIMER_FREQ_DIVIDE_SHIFT 0 23065543Scg 23165543Scg#define WPREG_WAVE_ROMRAM 7 23265543Scg#define WP_WAVE_VIRTUAL_ENABLED 0x0400 23365543Scg#define WP_WAVE_8BITRAM_ENABLED 0x0200 23465543Scg#define WP_WAVE_DRAM_ENABLED 0x0100 23565543Scg#define WP_WAVE_RAMSPLIT_MASK 0x00ff 23665543Scg#define WP_WAVE_RAMSPLIT_SHIFT 0 23765543Scg 23865543Scg#define WPREG_BASE 12 23965543Scg#define WP_PARAOUT_BASE_MASK 0xf000 24065543Scg#define WP_PARAOUT_BASE_SHIFT 12 24165543Scg#define WP_PARAIN_BASE_MASK 0x0f00 24265543Scg#define WP_PARAIN_BASE_SHIFT 8 24365543Scg#define WP_SERIAL0_BASE_MASK 0x00f0 24465543Scg#define WP_SERIAL0_BASE_SHIFT 4 24565543Scg#define WP_SERIAL1_BASE_MASK 0x000f 24665543Scg#define WP_SERIAL1_BASE_SHIFT 0 24765543Scg 24865543Scg#define WPREG_TIMER_ENABLE 17 24965543Scg#define WPREG_TIMER_START 23 25065543Scg 25165543Scg 25265543Scg/* ----------------------------- 25365543Scg * Audio Processing Unit. 25465543Scg */ 25565543Scg#define APUREG_APUTYPE 0 25665543Scg#define APU_DMA_ENABLED 0x4000 25765543Scg#define APU_INT_ON_LOOP 0x2000 25865543Scg#define APU_ENDCURVE 0x1000 25965543Scg#define APU_APUTYPE_MASK 0x00f0 26065543Scg#define APU_FILTERTYPE_MASK 0x000c 26165543Scg#define APU_FILTERQ_MASK 0x0003 26265543Scg 26365543Scg/* APU types */ 26465543Scg#define APU_APUTYPE_SHIFT 4 26565543Scg 26665543Scg#define APUTYPE_INACTIVE 0 26765543Scg#define APUTYPE_16BITLINEAR 1 26865543Scg#define APUTYPE_16BITSTEREO 2 26965543Scg#define APUTYPE_8BITLINEAR 3 27065543Scg#define APUTYPE_8BITSTEREO 4 27165543Scg#define APUTYPE_8BITDIFF 5 27265543Scg#define APUTYPE_DIGITALDELAY 6 27365543Scg#define APUTYPE_DUALTAP_READER 7 27465543Scg#define APUTYPE_CORRELATOR 8 27565543Scg#define APUTYPE_INPUTMIXER 9 27665543Scg#define APUTYPE_WAVETABLE 10 27765543Scg#define APUTYPE_RATECONV 11 27865543Scg#define APUTYPE_16BITPINGPONG 12 27965543Scg/* APU type 13 through 15 are reserved. */ 28065543Scg 28165543Scg/* Filter types */ 28265543Scg#define APU_FILTERTYPE_SHIFT 2 28365543Scg 28465543Scg#define FILTERTYPE_2POLE_LOPASS 0 28565543Scg#define FILTERTYPE_2POLE_BANDPASS 1 28665543Scg#define FILTERTYPE_2POLE_HIPASS 2 28765543Scg#define FILTERTYPE_1POLE_LOPASS 3 28865543Scg#define FILTERTYPE_1POLE_HIPASS 4 28965543Scg#define FILTERTYPE_PASSTHROUGH 5 29065543Scg 29165543Scg/* Filter Q */ 29265543Scg#define APU_FILTERQ_SHIFT 0 29365543Scg 29465543Scg#define FILTERQ_LESSQ 0 29565543Scg#define FILTERQ_MOREQ 3 29665543Scg 29765543Scg/* APU register 2 */ 29865543Scg#define APUREG_FREQ_LOBYTE 2 29965543Scg#define APU_FREQ_LOBYTE_MASK 0xff00 30065543Scg#define APU_plus6dB 0x0010 30165543Scg 30265543Scg/* APU register 3 */ 30365543Scg#define APUREG_FREQ_HIWORD 3 30465543Scg#define APU_FREQ_HIWORD_MASK 0x0fff 30565543Scg 30665543Scg/* Frequency */ 30765543Scg#define APU_FREQ_LOBYTE_SHIFT 8 30865543Scg#define APU_FREQ_HIWORD_SHIFT 0 30965543Scg#define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 31065543Scg 31165543Scg/* APU register 4 */ 31265543Scg#define APUREG_WAVESPACE 4 31365543Scg#define APU_64KPAGE_MASK 0xff00 31465543Scg 31565543Scg/* 64KW (==128KB) Page */ 31665543Scg#define APU_64KPAGE_SHIFT 8 31765543Scg 318137500Sjulian/* Wave Processor Wavespace Address */ 319137500Sjulian#define WPWA_MAX ((1 << 22) - 1) 320137500Sjulian#define WPWA_STEREO (1 << 23) 321137500Sjulian#define WPWA_USE_SYSMEM (1 << 22) 322137500Sjulian 323137500Sjulian#define WPWA_WTBAR_SHIFT(wtsz) WPWA_WTBAR_SHIFT_##wtsz 324137500Sjulian#define WPWA_WTBAR_SHIFT_1 15 325137500Sjulian#define WPWA_WTBAR_SHIFT_2 16 326137500Sjulian#define WPWA_WTBAR_SHIFT_4 17 327137500Sjulian#define WPWA_WTBAR_SHIFT_8 18 328137500Sjulian 329137500Sjulian#define WPWA_PCMBAR_SHIFT 20 330137500Sjulian 33165543Scg/* APU register 5 - 7 */ 33265543Scg#define APUREG_CURPTR 5 33365543Scg#define APUREG_ENDPTR 6 33465543Scg#define APUREG_LOOPLEN 7 33565543Scg 336137500Sjulian/* APU register 8 */ 337137500Sjulian#define APUREG_EFFECT_GAIN 8 338137500Sjulian 339137500Sjulian/* Effect gain? */ 340137500Sjulian#define APUREG_EFFECT_GAIN_MASK 0x00ff 341137500Sjulian 34265543Scg/* APU register 9 */ 34365543Scg#define APUREG_AMPLITUDE 9 34465543Scg#define APU_AMPLITUDE_NOW_MASK 0xff00 34565543Scg#define APU_AMPLITUDE_DEST_MASK 0x00ff 34665543Scg 34765543Scg/* Amplitude now? */ 34865543Scg#define APU_AMPLITUDE_NOW_SHIFT 8 34965543Scg 35065543Scg/* APU register 10 */ 35165543Scg#define APUREG_POSITION 10 35265543Scg#define APU_RADIUS_MASK 0x00c0 35365543Scg#define APU_PAN_MASK 0x003f 35465543Scg 35565543Scg/* Radius control. */ 35665543Scg#define APU_RADIUS_SHIFT 6 35765543Scg#define RADIUS_CENTERCIRCLE 0 35865543Scg#define RADIUS_MIDDLE 1 35965543Scg#define RADIUS_OUTSIDE 2 36065543Scg 36165543Scg/* Polar pan. */ 36265543Scg#define APU_PAN_SHIFT 0 36365543Scg#define PAN_RIGHT 0x00 36465543Scg#define PAN_FRONT 0x08 36565543Scg#define PAN_LEFT 0x10 36665543Scg 367137500Sjulian/* Source routing. */ 368137500Sjulian#define APUREG_ROUTING 11 369137500Sjulian#define APU_INVERT_POLARITY_B 0x8000 370137500Sjulian#define APU_DATASRC_B_MASK 0x7f00 371137500Sjulian#define APU_INVERT_POLARITY_A 0x0080 372137500Sjulian#define APU_DATASRC_A_MASK 0x007f 37365543Scg 374137500Sjulian#define APU_DATASRC_A_SHIFT 0 375137500Sjulian#define APU_DATASRC_B_SHIFT 8 376137500Sjulian 377137500Sjulian 37865543Scg/* ----------------------------- 37965543Scg * Limits. 38065543Scg */ 38165543Scg#define WPWA_MAXADDR ((1 << 23) - 1) 38265543Scg#define MAESTRO_MAXADDR ((1 << 28) - 1) 38365543Scg 38465543Scg#endif /* MAESTRO_REG_H_INCLUDED */ 385