envy24ht.h revision 162886
1159687Snetchild/* 2162886Snetchild * Copyright (c) 2006 Konstantin Dimitrov <kosio.dimitrov@gmail.com> 3159687Snetchild * Copyright (c) 2001 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 4159687Snetchild * All rights reserved. 5159687Snetchild * 6159687Snetchild * Redistribution and use in source and binary forms, with or without 7159687Snetchild * modification, are permitted provided that the following conditions 8159687Snetchild * are met: 9159687Snetchild * 1. Redistributions of source code must retain the above copyright 10159687Snetchild * notice, this list of conditions and the following disclaimer. 11159687Snetchild * 2. Redistributions in binary form must reproduce the above copyright 12159687Snetchild * notice, this list of conditions and the following disclaimer in the 13159687Snetchild * documentation and/or other materials provided with the distribution. 14159687Snetchild * 15159687Snetchild * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16159687Snetchild * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17159687Snetchild * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18159687Snetchild * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19159687Snetchild * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20159687Snetchild * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21159687Snetchild * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22159687Snetchild * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23159687Snetchild * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24159687Snetchild * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25159687Snetchild * SUCH DAMAGE. 26159687Snetchild * 27159687Snetchild * $FreeBSD: head/sys/dev/sound/pci/envy24ht.h 162886 2006-09-30 17:52:28Z netchild $ 28159687Snetchild */ 29159687Snetchild 30159687Snetchild 31159687Snetchild/* -------------------------------------------------------------------- */ 32159687Snetchild 33159687Snetchild/* PCI device ID */ 34159687Snetchild#define PCIV_ENVY24 0x1412 35162886Snetchild#define PCID_ENVY24HT 0x1724 36159687Snetchild 37162886Snetchild#define PCIR_CCS 0x10 /* Controller I/O Base Address */ 38162886Snetchild#define ENVY24HT_PCIR_MT 0x14 /* Multi-Track I/O Base Address */ 39159687Snetchild 40159687Snetchild/* Controller Registers */ 41159687Snetchild 42162886Snetchild#define ENVY24HT_CCS_CTL 0x00 /* Control/Status Register */ 43162886Snetchild#define ENVY24HT_CCS_CTL_RESET 0x80 /* Entire Chip soft reset */ 44159687Snetchild 45162886Snetchild#define ENVY24HT_CCS_IMASK 0x01 /* Interrupt Mask Register */ 46162886Snetchild#define ENVY24HT_CCS_IMASK_PMT 0x10 /* Professional Multi-track */ 47159687Snetchild 48162886Snetchild#define ENVY24HT_CCS_I2CDEV 0x10 /* I2C Port Device Address Register */ 49162886Snetchild#define ENVY24HT_CCS_I2CDEV_ADDR 0xfe /* I2C device address */ 50162886Snetchild#define ENVY24HT_CCS_I2CDEV_ROM 0xa0 /* reserved for the external I2C E2PROM */ 51162886Snetchild#define ENVY24HT_CCS_I2CDEV_WR 0x01 /* write */ 52162886Snetchild#define ENVY24HT_CCS_I2CDEV_RD 0x00 /* read */ 53162886Snetchild 54162886Snetchild#define ENVY24HT_CCS_I2CADDR 0x11 /* I2C Port Byte Address Register */ 55162886Snetchild#define ENVY24HT_CCS_I2CDATA 0x12 /* I2C Port Read/Write Data Register */ 56159687Snetchild 57162886Snetchild#define ENVY24HT_CCS_I2CSTAT 0x13 /* I2C Port Control and Status Register */ 58162886Snetchild#define ENVY24HT_CCS_I2CSTAT_ROM 0x80 /* external E2PROM exists */ 59162886Snetchild#define ENVY24HT_CCS_I2CSTAT_BSY 0x01 /* I2C port read/write status busy */ 60159687Snetchild 61162886Snetchild#define ENVY24HT_CCS_SCFG 0x04 /* System Configuration Register */ 62162886Snetchild#define ENVY24HT_CCSM_SCFG_XIN2 0xc0 /* XIN2 Clock Source Configuration */ 63162886Snetchild /* 00: 24.576MHz(96kHz*256) */ 64162886Snetchild /* 01: 49.152MHz(192kHz*256) */ 65162886Snetchild /* 1x: Reserved */ 66162886Snetchild#define ENVY24HT_CCSM_SCFG_MPU 0x20 /* 0(not implemented)/1(1) MPU-401 UART */ 67162886Snetchild#define ENVY24HT_CCSM_SCFG_ADC 0x0c /* 1-2 stereo ADC connected, S/PDIF receiver connected */ 68162886Snetchild#define ENVY24HT_CCSM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */ 69159687Snetchild 70162886Snetchild#define ENVY24HT_CCS_ACL 0x05 /* AC-Link Configuration Register */ 71162886Snetchild#define ENVY24HT_CCSM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */ 72162886Snetchild#define ENVY24HT_CCSM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */ 73159687Snetchild 74162886Snetchild#define ENVY24HT_CCS_I2S 0x06 /* I2S Converters Features Register */ 75162886Snetchild#define ENVY24HT_CCSM_I2S_VOL 0x80 /* I2S codec Volume and mute */ 76162886Snetchild#define ENVY24HT_CCSM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */ 77162886Snetchild#define ENVY24HT_CCSM_I2S_192KHZ 0x08 /* I2S converter 192kHz sampling rate support */ 78162886Snetchild#define ENVY24HT_CCSM_I2S_RES 0x30 /* Converter resolution */ 79162886Snetchild#define ENVY24HT_CCSM_I2S_16BIT 0x00 /* 16bit */ 80162886Snetchild#define ENVY24HT_CCSM_I2S_18BIT 0x10 /* 18bit */ 81162886Snetchild#define ENVY24HT_CCSM_I2S_20BIT 0x20 /* 20bit */ 82162886Snetchild#define ENVY24HT_CCSM_I2S_24BIT 0x30 /* 24bit */ 83162886Snetchild#define ENVY24HT_CCSM_I2S_ID 0x07 /* Other I2S IDs */ 84159687Snetchild 85162886Snetchild#define ENVY24HT_CCS_SPDIF 0x07 /* S/PDIF Configuration Register */ 86162886Snetchild#define ENVY24HT_CCSM_SPDIF_INT_EN 0x80 /* Enable integrated S/PDIF transmitter */ 87162886Snetchild#define ENVY24HT_CCSM_SPDIF_INT_OUT 0x40 /* Internal S/PDIF Out implemented */ 88162886Snetchild#define ENVY24HT_CCSM_SPDIF_ID 0x3c /* S/PDIF chip ID */ 89162886Snetchild#define ENVY24HT_CCSM_SPDIF_IN 0x02 /* S/PDIF Stereo In is present */ 90162886Snetchild#define ENVY24HT_CCSM_SPDIF_OUT 0x01 /* External S/PDIF Out implemented */ 91159687Snetchild 92159687Snetchild/* Professional Multi-Track Control Registers */ 93162886Snetchild 94162886Snetchild#define ENVY24HT_MT_INT_STAT 0x00 /* DMA Interrupt Mask and Status Register */ 95162886Snetchild#define ENVY24HT_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */ 96162886Snetchild#define ENVY24HT_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */ 97162886Snetchild#define ENVY24HT_MT_INT_MASK 0x03 98162886Snetchild#define ENVY24HT_MT_INT_RMASK 0x02 /* Multi-track record interrupt mask */ 99162886Snetchild#define ENVY24HT_MT_INT_PMASK 0x01 /* Multi-track playback interrupt mask */ 100159687Snetchild 101162886Snetchild#define ENVY24HT_MT_RATE 0x01 /* Sampling Rate Select Register */ 102162886Snetchild#define ENVY24HT_MT_RATE_SPDIF 0x10 /* S/PDIF input clock as the master */ 103162886Snetchild#define ENVY24HT_MT_RATE_48000 0x00 104162886Snetchild#define ENVY24HT_MT_RATE_24000 0x01 105162886Snetchild#define ENVY24HT_MT_RATE_12000 0x02 106162886Snetchild#define ENVY24HT_MT_RATE_9600 0x03 107162886Snetchild#define ENVY24HT_MT_RATE_32000 0x04 108162886Snetchild#define ENVY24HT_MT_RATE_16000 0x05 109162886Snetchild#define ENVY24HT_MT_RATE_8000 0x06 110162886Snetchild#define ENVY24HT_MT_RATE_96000 0x07 111162886Snetchild#define ENVY24HT_MT_RATE_64000 0x0f 112162886Snetchild#define ENVY24HT_MT_RATE_44100 0x08 113162886Snetchild#define ENVY24HT_MT_RATE_22050 0x09 114162886Snetchild#define ENVY24HT_MT_RATE_11025 0x0a 115162886Snetchild#define ENVY24HT_MT_RATE_88200 0x0b 116162886Snetchild#define ENVY24HT_MT_RATE_MASK 0x0f 117159687Snetchild 118162886Snetchild#define ENVY24HT_MT_PADDR 0x10 /* Playback DMA Current/Base Address Register */ 119162886Snetchild#define ENVY24HT_MT_PCNT 0x14 /* Playback DMA Current/Base Count Register */ 120162886Snetchild#define ENVY24HT_MT_PTERM 0x1C /* Playback Current/Base Terminal Count Register */ 121159687Snetchild 122162886Snetchild#define ENVY24HT_MT_PCTL 0x18 /* Global Playback and Record DMA Start/Stop Register */ 123162886Snetchild#define ENVY24HT_MT_PCTL_RSTART 0x02 /* 1: Record start; 0: Record stop */ 124162886Snetchild#define ENVY24HT_MT_PCTL_PSTART 0x01 /* 1: Playback start; 0: Playback stop */ 125159687Snetchild 126162886Snetchild#define ENVY24HT_MT_RADDR 0x20 /* Record DMA Current/Base Address Register */ 127162886Snetchild#define ENVY24HT_MT_RCNT 0x24 /* Record DMA Current/Base Count Register */ 128162886Snetchild#define ENVY24HT_MT_RTERM 0x26 /* Record Current/Base Terminal Count Register */ 129159687Snetchild 130162886Snetchild/* 131162886Snetchild These map values are refferd from ALSA sound driver. 132162886Snetchild*/ 133162886Snetchild/* ENVY24 configuration E2PROM map */ 134162886Snetchild#define ENVY24HT_E2PROM_SUBVENDOR 0x02 135162886Snetchild#define ENVY24HT_E2PROM_SUBDEVICE 0x00 136162886Snetchild#define ENVY24HT_E2PROM_SIZE 0x04 137162886Snetchild#define ENVY24HT_E2PROM_VERSION 0x05 138162886Snetchild#define ENVY24HT_E2PROM_SCFG 0x06 139162886Snetchild#define ENVY24HT_E2PROM_ACL 0x07 140162886Snetchild#define ENVY24HT_E2PROM_I2S 0x08 141162886Snetchild#define ENVY24HT_E2PROM_SPDIF 0x09 142162886Snetchild#define ENVY24HT_E2PROM_GPIOMASK 0x0d 143162886Snetchild#define ENVY24HT_E2PROM_GPIOSTATE 0x10 144162886Snetchild#define ENVY24HT_E2PROM_GPIODIR 0x0a 145159687Snetchild 146159687Snetchild/* ENVY24 mixer channel defines */ 147159687Snetchild/* 148159687Snetchild ENVY24 mixer has original line matrix. So, general mixer command is not 149159687Snetchild able to use for this. If system has consumer AC'97 output, AC'97 line is 150159687Snetchild used as master mixer, and it is able to control. 151159687Snetchild*/ 152162886Snetchild#define ENVY24HT_CHAN_NUM 11 /* Play * 5 + Record * 5 + Mix * 1 */ 153159687Snetchild 154162886Snetchild#define ENVY24HT_CHAN_PLAY_DAC1 0 155162886Snetchild#define ENVY24HT_CHAN_PLAY_DAC2 1 156162886Snetchild#define ENVY24HT_CHAN_PLAY_DAC3 2 157162886Snetchild#define ENVY24HT_CHAN_PLAY_DAC4 3 158162886Snetchild#define ENVY24HT_CHAN_PLAY_SPDIF 4 159162886Snetchild#define ENVY24HT_CHAN_REC_ADC1 5 160162886Snetchild#define ENVY24HT_CHAN_REC_ADC2 6 161162886Snetchild#define ENVY24HT_CHAN_REC_ADC3 7 162162886Snetchild#define ENVY24HT_CHAN_REC_ADC4 8 163162886Snetchild#define ENVY24HT_CHAN_REC_SPDIF 9 164162886Snetchild#define ENVY24HT_CHAN_REC_MIX 10 165159687Snetchild 166162886Snetchild#define ENVY24HT_MIX_MASK 0x3ff 167162886Snetchild#define ENVY24HT_MIX_REC_MASK 0x3e0 168159687Snetchild 169159687Snetchild/* volume value constants */ 170162886Snetchild#define ENVY24HT_VOL_MAX 0 /* 0db(negate) */ 171162886Snetchild#define ENVY24HT_VOL_MIN 96 /* -144db(negate) */ 172162886Snetchild#define ENVY24HT_VOL_MUTE 127 /* mute */ 173159687Snetchild 174162886Snetchild#define BUS_SPACE_MAXADDR_ENVY24 0x0fffffff /* Address space beyond 256MB is not 175162886Snetchild supported */ 176162886Snetchild#define BUS_SPACE_MAXSIZE_ENVY24 0x3fffc /* 64k x 4byte(1dword) */ 177159687Snetchild 178162886Snetchild#define ENVY24HT_CCS_GPIO_HDATA 0x1E 179162886Snetchild#define ENVY24HT_CCS_GPIO_LDATA 0x14 180162886Snetchild#define ENVY24HT_CCS_GPIO_LMASK 0x16 181162886Snetchild#define ENVY24HT_CCS_GPIO_HMASK 0x1F 182162886Snetchild#define ENVY24HT_CCS_GPIO_CTLDIR 0x18 183159687Snetchild 184