1152851Sariff/*- 2152851Sariff * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org> 3152851Sariff * All rights reserved. 4152851Sariff * 5152851Sariff * Redistribution and use in source and binary forms, with or without 6152851Sariff * modification, are permitted provided that the following conditions 7152851Sariff * are met: 8152851Sariff * 1. Redistributions of source code must retain the above copyright 9152851Sariff * notice, this list of conditions and the following disclaimer. 10152851Sariff * 2. Redistributions in binary form must reproduce the above copyright 11152851Sariff * notice, this list of conditions and the following disclaimer in the 12152851Sariff * documentation and/or other materials provided with the distribution. 13152851Sariff * 14152851Sariff * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15152851Sariff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16152851Sariff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17152851Sariff * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18152851Sariff * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19152851Sariff * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20152851Sariff * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21152851Sariff * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22152851Sariff * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23152851Sariff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24152851Sariff * SUCH DAMAGE. 25152851Sariff * 26152851Sariff * $FreeBSD$ 27152851Sariff */ 28152851Sariff 29152851Sariff#ifndef _ATIIXP_H_ 30152851Sariff#define _ATIIXP_H_ 31152851Sariff 32152851Sariff/* 33152851Sariff * Constants, pretty much FreeBSD specific. 34152851Sariff */ 35152851Sariff 36152851Sariff/* Number of playback / recording channel */ 37152851Sariff#define ATI_IXP_NPCHAN 1 38152851Sariff#define ATI_IXP_NRCHAN 1 39152851Sariff#define ATI_IXP_NCHANS (ATI_IXP_NPCHAN + ATI_IXP_NRCHAN) 40152851Sariff 41152851Sariff/* 42152851Sariff * Maximum segments/descriptors is 256, but 2 for 43152851Sariff * each channel should be more than enough for us. 44152851Sariff */ 45152851Sariff#define ATI_IXP_DMA_CHSEGS 2 46152851Sariff#define ATI_IXP_DMA_CHSEGS_MIN 2 47152851Sariff#define ATI_IXP_DMA_CHSEGS_MAX 256 48152851Sariff 49162931Sariff#define ATI_VENDOR_ID 0x1002 /* ATI Technologies */ 50152851Sariff 51152851Sariff#define ATI_IXP_200_ID 0x4341 52152851Sariff#define ATI_IXP_300_ID 0x4361 53152851Sariff#define ATI_IXP_400_ID 0x4370 54180110Sdelphij#define ATI_IXP_SB600_ID 0x4382 55152851Sariff 56152851Sariff#define ATI_IXP_BASE_RATE 48000 57152851Sariff 58152851Sariff/* 59152851Sariff * Register definitions for ATI IXP 60152851Sariff * 61152851Sariff * References: ALSA snd-atiixp.c , OpenBSD/NetBSD auixp-*.h 62152851Sariff */ 63152851Sariff 64152851Sariff#define ATI_IXP_CODECS 3 65152851Sariff 66152851Sariff#define ATI_REG_ISR 0x00 /* interrupt source */ 67152851Sariff#define ATI_REG_ISR_IN_XRUN (1U<<0) 68152851Sariff#define ATI_REG_ISR_IN_STATUS (1U<<1) 69152851Sariff#define ATI_REG_ISR_OUT_XRUN (1U<<2) 70152851Sariff#define ATI_REG_ISR_OUT_STATUS (1U<<3) 71152851Sariff#define ATI_REG_ISR_SPDF_XRUN (1U<<4) 72152851Sariff#define ATI_REG_ISR_SPDF_STATUS (1U<<5) 73152851Sariff#define ATI_REG_ISR_PHYS_INTR (1U<<8) 74152851Sariff#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) 75152851Sariff#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) 76152851Sariff#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) 77152851Sariff#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) 78152851Sariff#define ATI_REG_ISR_NEW_FRAME (1U<<13) 79152851Sariff 80152851Sariff#define ATI_REG_IER 0x04 /* interrupt enable */ 81152851Sariff#define ATI_REG_IER_IN_XRUN_EN (1U<<0) 82152851Sariff#define ATI_REG_IER_IO_STATUS_EN (1U<<1) 83152851Sariff#define ATI_REG_IER_OUT_XRUN_EN (1U<<2) 84152851Sariff#define ATI_REG_IER_OUT_XRUN_COND (1U<<3) 85152851Sariff#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) 86152851Sariff#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) 87152851Sariff#define ATI_REG_IER_PHYS_INTR_EN (1U<<8) 88152851Sariff#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) 89152851Sariff#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) 90152851Sariff#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) 91152851Sariff#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) 92152851Sariff#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO) */ 93152851Sariff#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ 94152851Sariff 95152851Sariff#define ATI_REG_CMD 0x08 /* command */ 96152851Sariff#define ATI_REG_CMD_POWERDOWN (1U<<0) 97152851Sariff#define ATI_REG_CMD_RECEIVE_EN (1U<<1) 98152851Sariff#define ATI_REG_CMD_SEND_EN (1U<<2) 99152851Sariff#define ATI_REG_CMD_STATUS_MEM (1U<<3) 100152851Sariff#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) 101152851Sariff#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) 102152851Sariff#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) 103152851Sariff#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 104152851Sariff#define ATI_REG_CMD_IN_DMA_EN (1U<<8) 105152851Sariff#define ATI_REG_CMD_OUT_DMA_EN (1U<<9) 106152851Sariff#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) 107152851Sariff#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) 108152851Sariff#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) 109152851Sariff#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) 110152851Sariff#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) 111152851Sariff#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) 112152851Sariff#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) 113152851Sariff#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) 114152851Sariff#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) 115152851Sariff#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) 116152851Sariff#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) 117152851Sariff#define ATI_REG_CMD_LOOPBACK_EN (1U<<23) 118152851Sariff#define ATI_REG_CMD_PACKED_DIS (1U<<24) 119152851Sariff#define ATI_REG_CMD_BURST_EN (1U<<25) 120152851Sariff#define ATI_REG_CMD_PANIC_EN (1U<<26) 121152851Sariff#define ATI_REG_CMD_MODEM_PRESENT (1U<<27) 122152851Sariff#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) 123152851Sariff#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) 124152851Sariff#define ATI_REG_CMD_AC_SYNC (1U<<30) 125152851Sariff#define ATI_REG_CMD_AC_RESET (1U<<31) 126152851Sariff 127152851Sariff#define ATI_REG_PHYS_OUT_ADDR 0x0c 128152851Sariff#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) 129152851Sariff#define ATI_REG_PHYS_OUT_RW (1U<<2) 130152851Sariff#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) 131152851Sariff#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 132152851Sariff#define ATI_REG_PHYS_OUT_DATA_SHIFT 16 133152851Sariff 134152851Sariff#define ATI_REG_PHYS_IN_ADDR 0x10 135152851Sariff#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) 136152851Sariff#define ATI_REG_PHYS_IN_ADDR_SHIFT 9 137152851Sariff#define ATI_REG_PHYS_IN_DATA_SHIFT 16 138152851Sariff 139152851Sariff#define ATI_REG_SLOTREQ 0x14 140152851Sariff 141152851Sariff#define ATI_REG_COUNTER 0x18 142152851Sariff#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ 143152851Sariff#define ATI_REG_COUNTER_BITCLOCK (31U<<8) 144152851Sariff 145152851Sariff#define ATI_REG_IN_FIFO_THRESHOLD 0x1c 146152851Sariff 147152851Sariff#define ATI_REG_IN_DMA_LINKPTR 0x20 148152851Sariff#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ 149152851Sariff#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ 150152851Sariff#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ 151152851Sariff#define ATI_REG_IN_DMA_DT_SIZE 0x30 152152851Sariff 153152851Sariff#define ATI_REG_OUT_DMA_SLOT 0x34 154152851Sariff#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) 155152851Sariff#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff 156152851Sariff#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 157152851Sariff#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 158152851Sariff 159152851Sariff#define ATI_REG_OUT_DMA_LINKPTR 0x38 160152851Sariff#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ 161152851Sariff#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ 162152851Sariff#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ 163152851Sariff#define ATI_REG_OUT_DMA_DT_SIZE 0x48 164152851Sariff 165152851Sariff#define ATI_REG_SPDF_CMD 0x4c 166152851Sariff#define ATI_REG_SPDF_CMD_LFSR (1U<<4) 167152851Sariff#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) 168152851Sariff#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ 169152851Sariff 170152851Sariff#define ATI_REG_SPDF_DMA_LINKPTR 0x50 171152851Sariff#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ 172152851Sariff#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ 173152851Sariff#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ 174152851Sariff#define ATI_REG_SPDF_DMA_DT_SIZE 0x60 175152851Sariff 176152851Sariff#define ATI_REG_MODEM_MIRROR 0x7c 177152851Sariff#define ATI_REG_AUDIO_MIRROR 0x80 178152851Sariff 179152851Sariff#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ 180152851Sariff#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ 181152851Sariff 182152851Sariff#define ATI_REG_FIFO_FLUSH 0x88 183152851Sariff#define ATI_REG_FIFO_OUT_FLUSH (1U<<0) 184152851Sariff#define ATI_REG_FIFO_IN_FLUSH (1U<<1) 185152851Sariff 186152851Sariff/* LINKPTR */ 187152851Sariff#define ATI_REG_LINKPTR_EN (1U<<0) 188152851Sariff 189152851Sariff/* [INT|OUT|SPDIF]_DMA_DT_SIZE */ 190152851Sariff#define ATI_REG_DMA_DT_SIZE (0xffffU<<0) 191152851Sariff#define ATI_REG_DMA_FIFO_USED (0x1fU<<16) 192152851Sariff#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) 193152851Sariff#define ATI_REG_DMA_STATE (7U<<26) 194152851Sariff 195152851Sariff#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ 196152851Sariff 197152851Sariff/* codec detection constant indicating the interrupt flags */ 198152851Sariff#define ALL_CODECS_NOT_READY \ 199152851Sariff (ATI_REG_ISR_CODEC0_NOT_READY | ATI_REG_ISR_CODEC1_NOT_READY |\ 200152851Sariff ATI_REG_ISR_CODEC2_NOT_READY) 201152851Sariff#define CODEC_CHECK_BITS (ALL_CODECS_NOT_READY|ATI_REG_ISR_NEW_FRAME) 202152851Sariff 203152851Sariff#endif 204