efx_regs.h revision 256281
1/*- 2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/10/sys/dev/sfxge/common/efx_regs.h 228078 2011-11-28 17:19:05Z philip $ 26 */ 27 28#ifndef _SYS_EFX_REGS_H 29#define _SYS_EFX_REGS_H 30 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36 37/* 38 * FR_AB_EE_VPD_CFG0_REG_SF(128bit): 39 * SPI/VPD configuration register 0 40 */ 41#define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 42/* falcona0,falconb0=eeprom_flash */ 43/* 44 * FR_AB_EE_VPD_CFG0_REG(128bit): 45 * SPI/VPD configuration register 0 46 */ 47#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 48/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 49 50#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 51#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 52#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 53#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 54#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 55#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 56#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 57#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 58#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 59#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 60#define FRF_AB_EE_VPDW_LENGTH_LBN 80 61#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 62#define FRF_AB_EE_VPDW_BASE_LBN 64 63#define FRF_AB_EE_VPDW_BASE_WIDTH 15 64#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 65#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 66#define FRF_AB_EE_VPD_BASE_LBN 32 67#define FRF_AB_EE_VPD_BASE_WIDTH 24 68#define FRF_AB_EE_VPD_LENGTH_LBN 16 69#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 70#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 71#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 72#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 73#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 74#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 75#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 76#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 77#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 78#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 79#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 80#define FRF_AB_EE_VPD_EN_LBN 0 81#define FRF_AB_EE_VPD_EN_WIDTH 1 82 83 84/* 85 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): 86 * PCIE SerDes control register 0 to 3 87 */ 88#define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 89/* falcona0,falconb0=eeprom_flash */ 90/* 91 * FR_AB_PCIE_SD_CTL0123_REG(128bit): 92 * PCIE SerDes control register 0 to 3 93 */ 94#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 95/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 96 97#define FRF_AB_PCIE_TESTSIG_H_LBN 96 98#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 99#define FRF_AB_PCIE_TESTSIG_L_LBN 64 100#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 101#define FRF_AB_PCIE_OFFSET_LBN 56 102#define FRF_AB_PCIE_OFFSET_WIDTH 8 103#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 104#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 105#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 106#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 107#define FRF_AB_PCIE_HIVMODE_H_LBN 53 108#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 109#define FRF_AB_PCIE_HIVMODE_L_LBN 52 110#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 111#define FRF_AB_PCIE_PARRESET_H_LBN 51 112#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 113#define FRF_AB_PCIE_PARRESET_L_LBN 50 114#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 115#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 116#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 117#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 118#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 119#define FRF_AB_PCIE_LPBK_LBN 40 120#define FRF_AB_PCIE_LPBK_WIDTH 8 121#define FRF_AB_PCIE_PARLPBK_LBN 32 122#define FRF_AB_PCIE_PARLPBK_WIDTH 8 123#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 124#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 125#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 126#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 127#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 128#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 129#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 130#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 131#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 132#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 133#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 134#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 135#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 136#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 137#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 138#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 139#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 140#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 141#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 142#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 143#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 144#define FFE_AB_PCIE_RXEQCTL_OFF 2 145#define FFE_AB_PCIE_RXEQCTL_MIN 1 146#define FFE_AB_PCIE_RXEQCTL_MAX 0 147#define FRF_AB_PCIE_HIDRV_LBN 8 148#define FRF_AB_PCIE_HIDRV_WIDTH 8 149#define FRF_AB_PCIE_LODRV_LBN 0 150#define FRF_AB_PCIE_LODRV_WIDTH 8 151 152 153/* 154 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): 155 * PCIE SerDes control register 4 and 5 156 */ 157#define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 158/* falcona0,falconb0=eeprom_flash */ 159/* 160 * FR_AB_PCIE_SD_CTL45_REG(128bit): 161 * PCIE SerDes control register 4 and 5 162 */ 163#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 164/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 165 166#define FRF_AB_PCIE_DTX7_LBN 60 167#define FRF_AB_PCIE_DTX7_WIDTH 4 168#define FRF_AB_PCIE_DTX6_LBN 56 169#define FRF_AB_PCIE_DTX6_WIDTH 4 170#define FRF_AB_PCIE_DTX5_LBN 52 171#define FRF_AB_PCIE_DTX5_WIDTH 4 172#define FRF_AB_PCIE_DTX4_LBN 48 173#define FRF_AB_PCIE_DTX4_WIDTH 4 174#define FRF_AB_PCIE_DTX3_LBN 44 175#define FRF_AB_PCIE_DTX3_WIDTH 4 176#define FRF_AB_PCIE_DTX2_LBN 40 177#define FRF_AB_PCIE_DTX2_WIDTH 4 178#define FRF_AB_PCIE_DTX1_LBN 36 179#define FRF_AB_PCIE_DTX1_WIDTH 4 180#define FRF_AB_PCIE_DTX0_LBN 32 181#define FRF_AB_PCIE_DTX0_WIDTH 4 182#define FRF_AB_PCIE_DEQ7_LBN 28 183#define FRF_AB_PCIE_DEQ7_WIDTH 4 184#define FRF_AB_PCIE_DEQ6_LBN 24 185#define FRF_AB_PCIE_DEQ6_WIDTH 4 186#define FRF_AB_PCIE_DEQ5_LBN 20 187#define FRF_AB_PCIE_DEQ5_WIDTH 4 188#define FRF_AB_PCIE_DEQ4_LBN 16 189#define FRF_AB_PCIE_DEQ4_WIDTH 4 190#define FRF_AB_PCIE_DEQ3_LBN 12 191#define FRF_AB_PCIE_DEQ3_WIDTH 4 192#define FRF_AB_PCIE_DEQ2_LBN 8 193#define FRF_AB_PCIE_DEQ2_WIDTH 4 194#define FRF_AB_PCIE_DEQ1_LBN 4 195#define FRF_AB_PCIE_DEQ1_WIDTH 4 196#define FRF_AB_PCIE_DEQ0_LBN 0 197#define FRF_AB_PCIE_DEQ0_WIDTH 4 198 199 200/* 201 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): 202 * PCIE PCS control and status register 203 */ 204#define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 205/* falcona0,falconb0=eeprom_flash */ 206/* 207 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): 208 * PCIE PCS control and status register 209 */ 210#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 211/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 212 213#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 214#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 215#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 216#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 217#define FRF_AB_PCIE_PRBSERR_LBN 40 218#define FRF_AB_PCIE_PRBSERR_WIDTH 8 219#define FRF_AB_PCIE_PRBSERRH0_LBN 32 220#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 221#define FRF_AB_PCIE_FASTINIT_H_LBN 15 222#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 223#define FRF_AB_PCIE_FASTINIT_L_LBN 14 224#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 225#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 226#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 227#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 228#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 229#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 230#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 231#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 232#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 233#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 234#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 235#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 236#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 237#define FRF_AB_PCIE_PRBSSEL_LBN 0 238#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 239 240 241/* 242 * FR_AB_HW_INIT_REG_SF(128bit): 243 * Hardware initialization register 244 */ 245#define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 246/* falcona0,falconb0=eeprom_flash */ 247/* 248 * FR_AZ_HW_INIT_REG(128bit): 249 * Hardware initialization register 250 */ 251#define FR_AZ_HW_INIT_REG_OFST 0x000000c0 252/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 253 254#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 255#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 256#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 257#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 258#define FRF_CZ_TX_MRG_TAGS_LBN 120 259#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 260#define FRF_AZ_TRGT_MASK_ALL_LBN 100 261#define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 262#define FRF_AZ_DOORBELL_DROP_LBN 92 263#define FRF_AZ_DOORBELL_DROP_WIDTH 8 264#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 265#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 266#define FRF_AB_PE_EIDLE_DIS_LBN 75 267#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 268#define FRF_AZ_FC_BLOCKING_EN_LBN 45 269#define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 270#define FRF_AZ_B2B_REQ_EN_LBN 44 271#define FRF_AZ_B2B_REQ_EN_WIDTH 1 272#define FRF_AZ_POST_WR_MASK_LBN 40 273#define FRF_AZ_POST_WR_MASK_WIDTH 4 274#define FRF_AZ_TLP_TC_LBN 34 275#define FRF_AZ_TLP_TC_WIDTH 3 276#define FRF_AZ_TLP_ATTR_LBN 32 277#define FRF_AZ_TLP_ATTR_WIDTH 2 278#define FRF_AB_INTB_VEC_LBN 24 279#define FRF_AB_INTB_VEC_WIDTH 5 280#define FRF_AB_INTA_VEC_LBN 16 281#define FRF_AB_INTA_VEC_WIDTH 5 282#define FRF_AZ_WD_TIMER_LBN 8 283#define FRF_AZ_WD_TIMER_WIDTH 8 284#define FRF_AZ_US_DISABLE_LBN 5 285#define FRF_AZ_US_DISABLE_WIDTH 1 286#define FRF_AZ_TLP_EP_LBN 4 287#define FRF_AZ_TLP_EP_WIDTH 1 288#define FRF_AZ_ATTR_SEL_LBN 3 289#define FRF_AZ_ATTR_SEL_WIDTH 1 290#define FRF_AZ_TD_SEL_LBN 1 291#define FRF_AZ_TD_SEL_WIDTH 1 292#define FRF_AZ_TLP_TD_LBN 0 293#define FRF_AZ_TLP_TD_WIDTH 1 294 295 296/* 297 * FR_AB_NIC_STAT_REG_SF(128bit): 298 * NIC status register 299 */ 300#define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 301/* falcona0,falconb0=eeprom_flash */ 302/* 303 * FR_AB_NIC_STAT_REG(128bit): 304 * NIC status register 305 */ 306#define FR_AB_NIC_STAT_REG_OFST 0x00000200 307/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 308 309#define FRF_BB_AER_DIS_LBN 34 310#define FRF_BB_AER_DIS_WIDTH 1 311#define FRF_BB_EE_STRAP_EN_LBN 31 312#define FRF_BB_EE_STRAP_EN_WIDTH 1 313#define FRF_BB_EE_STRAP_LBN 24 314#define FRF_BB_EE_STRAP_WIDTH 4 315#define FRF_BB_REVISION_ID_LBN 17 316#define FRF_BB_REVISION_ID_WIDTH 7 317#define FRF_AB_ONCHIP_SRAM_LBN 16 318#define FRF_AB_ONCHIP_SRAM_WIDTH 1 319#define FRF_AB_SF_PRST_LBN 9 320#define FRF_AB_SF_PRST_WIDTH 1 321#define FRF_AB_EE_PRST_LBN 8 322#define FRF_AB_EE_PRST_WIDTH 1 323#define FRF_AB_ATE_MODE_LBN 3 324#define FRF_AB_ATE_MODE_WIDTH 1 325#define FRF_AB_STRAP_PINS_LBN 0 326#define FRF_AB_STRAP_PINS_WIDTH 3 327 328 329/* 330 * FR_AB_GLB_CTL_REG_SF(128bit): 331 * Global control register 332 */ 333#define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 334/* falcona0,falconb0=eeprom_flash */ 335/* 336 * FR_AB_GLB_CTL_REG(128bit): 337 * Global control register 338 */ 339#define FR_AB_GLB_CTL_REG_OFST 0x00000220 340/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 341 342#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 343#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 344#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 345#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 346#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 347#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 348#define FRF_AA_PCIX_RST_CTL_LBN 60 349#define FRF_AA_PCIX_RST_CTL_WIDTH 1 350#define FRF_BB_BIU_RST_CTL_LBN 60 351#define FRF_BB_BIU_RST_CTL_WIDTH 1 352#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 353#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 354#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 355#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 356#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 357#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 358#define FRF_AB_XGRX_RST_CTL_LBN 56 359#define FRF_AB_XGRX_RST_CTL_WIDTH 1 360#define FRF_AB_XGTX_RST_CTL_LBN 55 361#define FRF_AB_XGTX_RST_CTL_WIDTH 1 362#define FRF_AB_EM_RST_CTL_LBN 54 363#define FRF_AB_EM_RST_CTL_WIDTH 1 364#define FRF_AB_EV_RST_CTL_LBN 53 365#define FRF_AB_EV_RST_CTL_WIDTH 1 366#define FRF_AB_SR_RST_CTL_LBN 52 367#define FRF_AB_SR_RST_CTL_WIDTH 1 368#define FRF_AB_RX_RST_CTL_LBN 51 369#define FRF_AB_RX_RST_CTL_WIDTH 1 370#define FRF_AB_TX_RST_CTL_LBN 50 371#define FRF_AB_TX_RST_CTL_WIDTH 1 372#define FRF_AB_EE_RST_CTL_LBN 49 373#define FRF_AB_EE_RST_CTL_WIDTH 1 374#define FRF_AB_CS_RST_CTL_LBN 48 375#define FRF_AB_CS_RST_CTL_WIDTH 1 376#define FRF_AB_HOT_RST_CTL_LBN 40 377#define FRF_AB_HOT_RST_CTL_WIDTH 2 378#define FRF_AB_RST_EXT_PHY_LBN 31 379#define FRF_AB_RST_EXT_PHY_WIDTH 1 380#define FRF_AB_RST_XAUI_SD_LBN 30 381#define FRF_AB_RST_XAUI_SD_WIDTH 1 382#define FRF_AB_RST_PCIE_SD_LBN 29 383#define FRF_AB_RST_PCIE_SD_WIDTH 1 384#define FRF_AA_RST_PCIX_LBN 28 385#define FRF_AA_RST_PCIX_WIDTH 1 386#define FRF_BB_RST_BIU_LBN 28 387#define FRF_BB_RST_BIU_WIDTH 1 388#define FRF_AB_RST_PCIE_STKY_LBN 27 389#define FRF_AB_RST_PCIE_STKY_WIDTH 1 390#define FRF_AB_RST_PCIE_NSTKY_LBN 26 391#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 392#define FRF_AB_RST_PCIE_CORE_LBN 25 393#define FRF_AB_RST_PCIE_CORE_WIDTH 1 394#define FRF_AB_RST_XGRX_LBN 24 395#define FRF_AB_RST_XGRX_WIDTH 1 396#define FRF_AB_RST_XGTX_LBN 23 397#define FRF_AB_RST_XGTX_WIDTH 1 398#define FRF_AB_RST_EM_LBN 22 399#define FRF_AB_RST_EM_WIDTH 1 400#define FRF_AB_RST_EV_LBN 21 401#define FRF_AB_RST_EV_WIDTH 1 402#define FRF_AB_RST_SR_LBN 20 403#define FRF_AB_RST_SR_WIDTH 1 404#define FRF_AB_RST_RX_LBN 19 405#define FRF_AB_RST_RX_WIDTH 1 406#define FRF_AB_RST_TX_LBN 18 407#define FRF_AB_RST_TX_WIDTH 1 408#define FRF_AB_RST_SF_LBN 17 409#define FRF_AB_RST_SF_WIDTH 1 410#define FRF_AB_RST_CS_LBN 16 411#define FRF_AB_RST_CS_WIDTH 1 412#define FRF_AB_INT_RST_DUR_LBN 4 413#define FRF_AB_INT_RST_DUR_WIDTH 3 414#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 415#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 416#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 417#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 418#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 419#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 420#define FFE_AB_EXT_PHY_RST_DUR_640US 3 421#define FFE_AB_EXT_PHY_RST_DUR_320US 2 422#define FFE_AB_EXT_PHY_RST_DUR_160US 1 423#define FFE_AB_EXT_PHY_RST_DUR_80US 0 424#define FRF_AB_SWRST_LBN 0 425#define FRF_AB_SWRST_WIDTH 1 426 427 428/* 429 * FR_AZ_IOM_IND_ADR_REG(32bit): 430 * IO-mapped indirect access address register 431 */ 432#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 433/* falcona0,falconb0,sienaa0=net_func_bar0 */ 434 435#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 436#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 437#define FRF_AZ_IOM_IND_ADR_LBN 0 438#define FRF_AZ_IOM_IND_ADR_WIDTH 24 439 440 441/* 442 * FR_AZ_IOM_IND_DAT_REG(32bit): 443 * IO-mapped indirect access data register 444 */ 445#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 446/* falcona0,falconb0,sienaa0=net_func_bar0 */ 447 448#define FRF_AZ_IOM_IND_DAT_LBN 0 449#define FRF_AZ_IOM_IND_DAT_WIDTH 32 450 451 452/* 453 * FR_AZ_ADR_REGION_REG(128bit): 454 * Address region register 455 */ 456#define FR_AZ_ADR_REGION_REG_OFST 0x00000000 457/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 458 459#define FRF_AZ_ADR_REGION3_LBN 96 460#define FRF_AZ_ADR_REGION3_WIDTH 18 461#define FRF_AZ_ADR_REGION2_LBN 64 462#define FRF_AZ_ADR_REGION2_WIDTH 18 463#define FRF_AZ_ADR_REGION1_LBN 32 464#define FRF_AZ_ADR_REGION1_WIDTH 18 465#define FRF_AZ_ADR_REGION0_LBN 0 466#define FRF_AZ_ADR_REGION0_WIDTH 18 467 468 469/* 470 * FR_AZ_INT_EN_REG_KER(128bit): 471 * Kernel driver Interrupt enable register 472 */ 473#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 474/* falcona0,falconb0,sienaa0=net_func_bar2 */ 475 476#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 477#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 478#define FRF_AZ_KER_INT_CHAR_LBN 4 479#define FRF_AZ_KER_INT_CHAR_WIDTH 1 480#define FRF_AZ_KER_INT_KER_LBN 3 481#define FRF_AZ_KER_INT_KER_WIDTH 1 482#define FRF_AZ_DRV_INT_EN_KER_LBN 0 483#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 484 485 486/* 487 * FR_AZ_INT_EN_REG_CHAR(128bit): 488 * Char Driver interrupt enable register 489 */ 490#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 491/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 492 493#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 494#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 495#define FRF_AZ_CHAR_INT_CHAR_LBN 4 496#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 497#define FRF_AZ_CHAR_INT_KER_LBN 3 498#define FRF_AZ_CHAR_INT_KER_WIDTH 1 499#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 500#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 501 502 503/* 504 * FR_AZ_INT_ADR_REG_KER(128bit): 505 * Interrupt host address for Kernel driver 506 */ 507#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 508/* falcona0,falconb0,sienaa0=net_func_bar2 */ 509 510#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 511#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 512#define FRF_AZ_INT_ADR_KER_LBN 0 513#define FRF_AZ_INT_ADR_KER_WIDTH 64 514#define FRF_AZ_INT_ADR_KER_DW0_LBN 0 515#define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 516#define FRF_AZ_INT_ADR_KER_DW1_LBN 32 517#define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 518 519 520/* 521 * FR_AZ_INT_ADR_REG_CHAR(128bit): 522 * Interrupt host address for Char driver 523 */ 524#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 525/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 526 527#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 528#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 529#define FRF_AZ_INT_ADR_CHAR_LBN 0 530#define FRF_AZ_INT_ADR_CHAR_WIDTH 64 531#define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 532#define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 533#define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 534#define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 535 536 537/* 538 * FR_AA_INT_ACK_KER(32bit): 539 * Kernel interrupt acknowledge register 540 */ 541#define FR_AA_INT_ACK_KER_OFST 0x00000050 542/* falcona0=net_func_bar2 */ 543 544#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 545#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 546 547 548/* 549 * FR_BZ_INT_ISR0_REG(128bit): 550 * Function 0 Interrupt Acknowlege Status register 551 */ 552#define FR_BZ_INT_ISR0_REG_OFST 0x00000090 553/* falconb0,sienaa0=net_func_bar2 */ 554 555#define FRF_BZ_INT_ISR_REG_LBN 0 556#define FRF_BZ_INT_ISR_REG_WIDTH 64 557#define FRF_BZ_INT_ISR_REG_DW0_LBN 0 558#define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 559#define FRF_BZ_INT_ISR_REG_DW1_LBN 32 560#define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 561 562 563/* 564 * FR_AB_EE_SPI_HCMD_REG(128bit): 565 * SPI host command register 566 */ 567#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 568/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 569 570#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 571#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 572#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 573#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 574#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 575#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 576#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 577#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 578#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 579#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 580#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 581#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 582#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 583#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 584#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 585#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 586 587 588/* 589 * FR_CZ_USR_EV_CFG(32bit): 590 * User Level Event Configuration register 591 */ 592#define FR_CZ_USR_EV_CFG_OFST 0x00000100 593/* sienaa0=net_func_bar2 */ 594 595#define FRF_CZ_USREV_DIS_LBN 16 596#define FRF_CZ_USREV_DIS_WIDTH 1 597#define FRF_CZ_DFLT_EVQ_LBN 0 598#define FRF_CZ_DFLT_EVQ_WIDTH 10 599 600 601/* 602 * FR_AB_EE_SPI_HADR_REG(128bit): 603 * SPI host address register 604 */ 605#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 606/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 607 608#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 609#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 610#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 611#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 612 613 614/* 615 * FR_AB_EE_SPI_HDATA_REG(128bit): 616 * SPI host data register 617 */ 618#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 619/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 620 621#define FRF_AB_EE_SPI_HDATA3_LBN 96 622#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 623#define FRF_AB_EE_SPI_HDATA2_LBN 64 624#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 625#define FRF_AB_EE_SPI_HDATA1_LBN 32 626#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 627#define FRF_AB_EE_SPI_HDATA0_LBN 0 628#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 629 630 631/* 632 * FR_AB_EE_BASE_PAGE_REG(128bit): 633 * Expansion ROM base mirror register 634 */ 635#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 636/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 637 638#define FRF_AB_EE_EXPROM_MASK_LBN 16 639#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 640#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 641#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 642 643 644/* 645 * FR_AB_EE_VPD_SW_CNTL_REG(128bit): 646 * VPD access SW control register 647 */ 648#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 649/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 650 651#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 652#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 653#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 654#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 655#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 656#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 657 658 659/* 660 * FR_AB_EE_VPD_SW_DATA_REG(128bit): 661 * VPD access SW data register 662 */ 663#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 664/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 665 666#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 667#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 668 669 670/* 671 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): 672 * Indirect Access to PCIE Core registers 673 */ 674#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 675/* falconb0=net_func_bar2 */ 676 677#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 678#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 679#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 680#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 681#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 682#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 683 684 685/* 686 * FR_AB_GPIO_CTL_REG(128bit): 687 * GPIO control register 688 */ 689#define FR_AB_GPIO_CTL_REG_OFST 0x00000210 690/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 691 692#define FRF_AB_GPIO15_OEN_LBN 63 693#define FRF_AB_GPIO15_OEN_WIDTH 1 694#define FRF_AB_GPIO14_OEN_LBN 62 695#define FRF_AB_GPIO14_OEN_WIDTH 1 696#define FRF_AB_GPIO13_OEN_LBN 61 697#define FRF_AB_GPIO13_OEN_WIDTH 1 698#define FRF_AB_GPIO12_OEN_LBN 60 699#define FRF_AB_GPIO12_OEN_WIDTH 1 700#define FRF_AB_GPIO11_OEN_LBN 59 701#define FRF_AB_GPIO11_OEN_WIDTH 1 702#define FRF_AB_GPIO10_OEN_LBN 58 703#define FRF_AB_GPIO10_OEN_WIDTH 1 704#define FRF_AB_GPIO9_OEN_LBN 57 705#define FRF_AB_GPIO9_OEN_WIDTH 1 706#define FRF_AB_GPIO8_OEN_LBN 56 707#define FRF_AB_GPIO8_OEN_WIDTH 1 708#define FRF_AB_GPIO15_OUT_LBN 55 709#define FRF_AB_GPIO15_OUT_WIDTH 1 710#define FRF_AB_GPIO14_OUT_LBN 54 711#define FRF_AB_GPIO14_OUT_WIDTH 1 712#define FRF_AB_GPIO13_OUT_LBN 53 713#define FRF_AB_GPIO13_OUT_WIDTH 1 714#define FRF_AB_GPIO12_OUT_LBN 52 715#define FRF_AB_GPIO12_OUT_WIDTH 1 716#define FRF_AB_GPIO11_OUT_LBN 51 717#define FRF_AB_GPIO11_OUT_WIDTH 1 718#define FRF_AB_GPIO10_OUT_LBN 50 719#define FRF_AB_GPIO10_OUT_WIDTH 1 720#define FRF_AB_GPIO9_OUT_LBN 49 721#define FRF_AB_GPIO9_OUT_WIDTH 1 722#define FRF_AB_GPIO8_OUT_LBN 48 723#define FRF_AB_GPIO8_OUT_WIDTH 1 724#define FRF_AB_GPIO15_IN_LBN 47 725#define FRF_AB_GPIO15_IN_WIDTH 1 726#define FRF_AB_GPIO14_IN_LBN 46 727#define FRF_AB_GPIO14_IN_WIDTH 1 728#define FRF_AB_GPIO13_IN_LBN 45 729#define FRF_AB_GPIO13_IN_WIDTH 1 730#define FRF_AB_GPIO12_IN_LBN 44 731#define FRF_AB_GPIO12_IN_WIDTH 1 732#define FRF_AB_GPIO11_IN_LBN 43 733#define FRF_AB_GPIO11_IN_WIDTH 1 734#define FRF_AB_GPIO10_IN_LBN 42 735#define FRF_AB_GPIO10_IN_WIDTH 1 736#define FRF_AB_GPIO9_IN_LBN 41 737#define FRF_AB_GPIO9_IN_WIDTH 1 738#define FRF_AB_GPIO8_IN_LBN 40 739#define FRF_AB_GPIO8_IN_WIDTH 1 740#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 741#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 742#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 743#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 744#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 745#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 746#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 747#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 748#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 749#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 750#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 751#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 752#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 753#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 754#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 755#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 756#define FRF_BB_CLK156_OUT_EN_LBN 31 757#define FRF_BB_CLK156_OUT_EN_WIDTH 1 758#define FRF_BB_USE_NIC_CLK_LBN 30 759#define FRF_BB_USE_NIC_CLK_WIDTH 1 760#define FRF_AB_GPIO5_OEN_LBN 29 761#define FRF_AB_GPIO5_OEN_WIDTH 1 762#define FRF_AB_GPIO4_OEN_LBN 28 763#define FRF_AB_GPIO4_OEN_WIDTH 1 764#define FRF_AB_GPIO3_OEN_LBN 27 765#define FRF_AB_GPIO3_OEN_WIDTH 1 766#define FRF_AB_GPIO2_OEN_LBN 26 767#define FRF_AB_GPIO2_OEN_WIDTH 1 768#define FRF_AB_GPIO1_OEN_LBN 25 769#define FRF_AB_GPIO1_OEN_WIDTH 1 770#define FRF_AB_GPIO0_OEN_LBN 24 771#define FRF_AB_GPIO0_OEN_WIDTH 1 772#define FRF_AB_GPIO5_OUT_LBN 21 773#define FRF_AB_GPIO5_OUT_WIDTH 1 774#define FRF_AB_GPIO4_OUT_LBN 20 775#define FRF_AB_GPIO4_OUT_WIDTH 1 776#define FRF_AB_GPIO3_OUT_LBN 19 777#define FRF_AB_GPIO3_OUT_WIDTH 1 778#define FRF_AB_GPIO2_OUT_LBN 18 779#define FRF_AB_GPIO2_OUT_WIDTH 1 780#define FRF_AB_GPIO1_OUT_LBN 17 781#define FRF_AB_GPIO1_OUT_WIDTH 1 782#define FRF_AB_GPIO0_OUT_LBN 16 783#define FRF_AB_GPIO0_OUT_WIDTH 1 784#define FRF_AB_GPIO5_IN_LBN 13 785#define FRF_AB_GPIO5_IN_WIDTH 1 786#define FRF_AB_GPIO4_IN_LBN 12 787#define FRF_AB_GPIO4_IN_WIDTH 1 788#define FRF_AB_GPIO3_IN_LBN 11 789#define FRF_AB_GPIO3_IN_WIDTH 1 790#define FRF_AB_GPIO2_IN_LBN 10 791#define FRF_AB_GPIO2_IN_WIDTH 1 792#define FRF_AB_GPIO1_IN_LBN 9 793#define FRF_AB_GPIO1_IN_WIDTH 1 794#define FRF_AB_GPIO0_IN_LBN 8 795#define FRF_AB_GPIO0_IN_WIDTH 1 796#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 797#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 798#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 799#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 800#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 801#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 802#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 803#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 804#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 805#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 806#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 807#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 808 809 810/* 811 * FR_AZ_FATAL_INTR_REG_KER(128bit): 812 * Fatal interrupt register for Kernel 813 */ 814#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 815/* falcona0,falconb0,sienaa0=net_func_bar2 */ 816 817#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 818#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 819#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 820#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 821#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 822#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 823#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 824#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 825#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 826#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 827#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 828#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 829#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 830#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 831#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 832#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 833#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 834#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 835#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 836#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 837#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 838#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 839#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 840#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 841#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 842#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 843#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 844#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 845#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 846#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 847#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 848#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 849#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 850#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 851#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 852#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 853#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 854#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 855#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 856#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 857#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 858#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 859#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 860#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 861#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 862#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 863#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 864#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 865#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 866#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 867#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 868#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 869#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 870#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 871#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 872#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 873 874 875/* 876 * FR_AZ_FATAL_INTR_REG_CHAR(128bit): 877 * Fatal interrupt register for Char 878 */ 879#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 880/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 881 882#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 883#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 884#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 885#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 886#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 887#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 888#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 889#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 890#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 891#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 892#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 893#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 894#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 895#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 896#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 897#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 898#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 899#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 900#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 901#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 902#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 903#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 904#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 905#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 906#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 907#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 908#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 909#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 910#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 911#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 912#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 913#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 914#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 915#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 916#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 917#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 918#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 919#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 920#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 921#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 922#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 923#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 924#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 925#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 926#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 927#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 928#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 929#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 930#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 931#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 932#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 933#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 934#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 935#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 936#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 937#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 938 939 940/* 941 * FR_AZ_DP_CTRL_REG(128bit): 942 * Datapath control register 943 */ 944#define FR_AZ_DP_CTRL_REG_OFST 0x00000250 945/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 946 947#define FRF_AZ_FLS_EVQ_ID_LBN 0 948#define FRF_AZ_FLS_EVQ_ID_WIDTH 12 949 950 951/* 952 * FR_AZ_MEM_STAT_REG(128bit): 953 * Memory status register 954 */ 955#define FR_AZ_MEM_STAT_REG_OFST 0x00000260 956/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 957 958#define FRF_AB_MEM_PERR_VEC_LBN 53 959#define FRF_AB_MEM_PERR_VEC_WIDTH 40 960#define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 961#define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 962#define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 963#define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 964#define FRF_AB_MBIST_CORR_LBN 38 965#define FRF_AB_MBIST_CORR_WIDTH 15 966#define FRF_AB_MBIST_ERR_LBN 0 967#define FRF_AB_MBIST_ERR_WIDTH 40 968#define FRF_AB_MBIST_ERR_DW0_LBN 0 969#define FRF_AB_MBIST_ERR_DW0_WIDTH 32 970#define FRF_AB_MBIST_ERR_DW1_LBN 32 971#define FRF_AB_MBIST_ERR_DW1_WIDTH 6 972#define FRF_CZ_MEM_PERR_VEC_LBN 0 973#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 974#define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 975#define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 976#define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 977#define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 978 979 980/* 981 * FR_PORT0_CS_DEBUG_REG(128bit): 982 * Debug register 983 */ 984 985#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 986/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 987 988#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 989#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 990#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 991#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 992#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 993#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 994#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 995#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 996#define FRF_CZ_CS_PORT_NUM_LBN 40 997#define FRF_CZ_CS_PORT_NUM_WIDTH 2 998#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 999#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 1000#define FRF_CZ_CS_RESERVED_LBN 36 1001#define FRF_CZ_CS_RESERVED_WIDTH 4 1002#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 1003#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 1004#define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 1005#define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 1006#define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 1007#define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 1008#define FRF_CZ_CS_PORT_FPE_LBN 1 1009#define FRF_CZ_CS_PORT_FPE_WIDTH 35 1010#define FRF_AB_EM_DEBUG_ADDR_LBN 26 1011#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 1012#define FRF_AB_SR_DEBUG_ADDR_LBN 21 1013#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 1014#define FRF_AB_EV_DEBUG_ADDR_LBN 16 1015#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 1016#define FRF_AB_RX_DEBUG_ADDR_LBN 11 1017#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 1018#define FRF_AB_TX_DEBUG_ADDR_LBN 6 1019#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 1020#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 1021#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 1022#define FRF_AZ_CS_DEBUG_EN_LBN 0 1023#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 1024 1025 1026/* 1027 * FR_AZ_DRIVER_REG(128bit): 1028 * Driver scratch register [0-7] 1029 */ 1030#define FR_AZ_DRIVER_REG_OFST 0x00000280 1031/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1032#define FR_AZ_DRIVER_REG_STEP 16 1033#define FR_AZ_DRIVER_REG_ROWS 8 1034 1035#define FRF_AZ_DRIVER_DW0_LBN 0 1036#define FRF_AZ_DRIVER_DW0_WIDTH 32 1037 1038 1039/* 1040 * FR_AZ_ALTERA_BUILD_REG(128bit): 1041 * Altera build register 1042 */ 1043#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 1044/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1045 1046#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 1047#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 1048 1049 1050/* 1051 * FR_AZ_CSR_SPARE_REG(128bit): 1052 * Spare register 1053 */ 1054#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 1055/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1056 1057#define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 1058#define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 1059#define FRF_AZ_MEM_PERR_EN_LBN 64 1060#define FRF_AZ_MEM_PERR_EN_WIDTH 38 1061#define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 1062#define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 1063#define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 1064#define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 1065#define FRF_AZ_CSR_SPARE_BITS_LBN 0 1066#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 1067 1068 1069/* 1070 * FR_BZ_DEBUG_DATA_OUT_REG(128bit): 1071 * Live Debug and Debug 2 out ports 1072 */ 1073#define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 1074/* falconb0,sienaa0=net_func_bar2 */ 1075 1076#define FRF_BZ_DEBUG2_PORT_LBN 25 1077#define FRF_BZ_DEBUG2_PORT_WIDTH 15 1078#define FRF_BZ_DEBUG1_PORT_LBN 0 1079#define FRF_BZ_DEBUG1_PORT_WIDTH 25 1080 1081 1082/* 1083 * FR_BZ_EVQ_RPTR_REGP0(32bit): 1084 * Event queue read pointer register 1085 */ 1086#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 1087/* falconb0,sienaa0=net_func_bar2 */ 1088#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 1089#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 1090/* 1091 * FR_AA_EVQ_RPTR_REG_KER(32bit): 1092 * Event queue read pointer register 1093 */ 1094#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 1095/* falcona0=net_func_bar2 */ 1096#define FR_AA_EVQ_RPTR_REG_KER_STEP 4 1097#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 1098/* 1099 * FR_AZ_EVQ_RPTR_REG(32bit): 1100 * Event queue read pointer register 1101 */ 1102#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 1103/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1104#define FR_AZ_EVQ_RPTR_REG_STEP 16 1105#define FR_AB_EVQ_RPTR_REG_ROWS 4096 1106#define FR_CZ_EVQ_RPTR_REG_ROWS 1024 1107/* 1108 * FR_BB_EVQ_RPTR_REGP123(32bit): 1109 * Event queue read pointer register 1110 */ 1111#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 1112/* falconb0=net_func_bar2 */ 1113#define FR_BB_EVQ_RPTR_REGP123_STEP 8192 1114#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 1115 1116#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 1117#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 1118#define FRF_AZ_EVQ_RPTR_LBN 0 1119#define FRF_AZ_EVQ_RPTR_WIDTH 15 1120 1121 1122/* 1123 * FR_BZ_TIMER_COMMAND_REGP0(128bit): 1124 * Timer Command Registers 1125 */ 1126#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 1127/* falconb0,sienaa0=net_func_bar2 */ 1128#define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 1129#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 1130/* 1131 * FR_AA_TIMER_COMMAND_REG_KER(128bit): 1132 * Timer Command Registers 1133 */ 1134#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 1135/* falcona0=net_func_bar2 */ 1136#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 1137#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 1138/* 1139 * FR_AB_TIMER_COMMAND_REGP123(128bit): 1140 * Timer Command Registers 1141 */ 1142#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 1143/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1144#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 1145#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 1146/* 1147 * FR_AA_TIMER_COMMAND_REGP0(128bit): 1148 * Timer Command Registers 1149 */ 1150#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 1151/* falcona0=char_func_bar0 */ 1152#define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 1153#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 1154 1155#define FRF_CZ_TC_TIMER_MODE_LBN 14 1156#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 1157#define FRF_AB_TC_TIMER_MODE_LBN 12 1158#define FRF_AB_TC_TIMER_MODE_WIDTH 2 1159#define FRF_CZ_TC_TIMER_VAL_LBN 0 1160#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 1161#define FRF_AB_TC_TIMER_VAL_LBN 0 1162#define FRF_AB_TC_TIMER_VAL_WIDTH 12 1163 1164 1165/* 1166 * FR_AZ_DRV_EV_REG(128bit): 1167 * Driver generated event register 1168 */ 1169#define FR_AZ_DRV_EV_REG_OFST 0x00000440 1170/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1171 1172#define FRF_AZ_DRV_EV_QID_LBN 64 1173#define FRF_AZ_DRV_EV_QID_WIDTH 12 1174#define FRF_AZ_DRV_EV_DATA_LBN 0 1175#define FRF_AZ_DRV_EV_DATA_WIDTH 64 1176#define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 1177#define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 1178#define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 1179#define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 1180 1181 1182/* 1183 * FR_AZ_EVQ_CTL_REG(128bit): 1184 * Event queue control register 1185 */ 1186#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 1187/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1188 1189#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 1190#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 1191#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 1192#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 1193#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 1194#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 1195#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 1196#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 1197#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 1198#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 1199 1200 1201/* 1202 * FR_AZ_EVQ_CNT1_REG(128bit): 1203 * Event counter 1 register 1204 */ 1205#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 1206/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1207 1208#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 1209#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 1210#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 1211#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 1212#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 1213#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 1214#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 1215#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 1216#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 1217#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 1218#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 1219#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 1220#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 1221#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 1222 1223 1224/* 1225 * FR_AZ_EVQ_CNT2_REG(128bit): 1226 * Event counter 2 register 1227 */ 1228#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 1229/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1230 1231#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 1232#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 1233#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 1234#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 1235#define FRF_AZ_EVQ_RDY_CNT_LBN 80 1236#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 1237#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 1238#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 1239#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 1240#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 1241#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 1242#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 1243#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 1244#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 1245 1246 1247/* 1248 * FR_CZ_USR_EV_REG(32bit): 1249 * Event mailbox register 1250 */ 1251#define FR_CZ_USR_EV_REG_OFST 0x00000540 1252/* sienaa0=net_func_bar2 */ 1253#define FR_CZ_USR_EV_REG_STEP 8192 1254#define FR_CZ_USR_EV_REG_ROWS 1024 1255 1256#define FRF_CZ_USR_EV_DATA_LBN 0 1257#define FRF_CZ_USR_EV_DATA_WIDTH 32 1258 1259 1260/* 1261 * FR_AZ_BUF_TBL_CFG_REG(128bit): 1262 * Buffer table configuration register 1263 */ 1264#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 1265/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1266 1267#define FRF_AZ_BUF_TBL_MODE_LBN 3 1268#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 1269 1270 1271/* 1272 * FR_AZ_SRM_RX_DC_CFG_REG(128bit): 1273 * SRAM receive descriptor cache configuration register 1274 */ 1275#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 1276/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1277 1278#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 1279#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 1280#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 1281#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 1282 1283 1284/* 1285 * FR_AZ_SRM_TX_DC_CFG_REG(128bit): 1286 * SRAM transmit descriptor cache configuration register 1287 */ 1288#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 1289/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1290 1291#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 1292#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 1293 1294 1295/* 1296 * FR_AZ_SRM_CFG_REG(128bit): 1297 * SRAM configuration register 1298 */ 1299#define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 1300/* falcona0,falconb0=eeprom_flash */ 1301/* 1302 * FR_AZ_SRM_CFG_REG(128bit): 1303 * SRAM configuration register 1304 */ 1305#define FR_AZ_SRM_CFG_REG_OFST 0x00000630 1306/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1307 1308#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 1309#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 1310#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 1311#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 1312#define FRF_AZ_SRM_INIT_EN_LBN 3 1313#define FRF_AZ_SRM_INIT_EN_WIDTH 1 1314#define FRF_AZ_SRM_NUM_BANK_LBN 2 1315#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 1316#define FRF_AZ_SRM_BANK_SIZE_LBN 0 1317#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 1318 1319 1320/* 1321 * FR_AZ_BUF_TBL_UPD_REG(128bit): 1322 * Buffer table update register 1323 */ 1324#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 1325/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1326 1327#define FRF_AZ_BUF_UPD_CMD_LBN 63 1328#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 1329#define FRF_AZ_BUF_CLR_CMD_LBN 62 1330#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 1331#define FRF_AZ_BUF_CLR_END_ID_LBN 32 1332#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 1333#define FRF_AZ_BUF_CLR_START_ID_LBN 0 1334#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 1335 1336 1337/* 1338 * FR_AZ_SRM_UPD_EVQ_REG(128bit): 1339 * Buffer table update register 1340 */ 1341#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 1342/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1343 1344#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 1345#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 1346 1347 1348/* 1349 * FR_AZ_SRAM_PARITY_REG(128bit): 1350 * SRAM parity register. 1351 */ 1352#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 1353/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1354 1355#define FRF_CZ_BYPASS_ECC_LBN 3 1356#define FRF_CZ_BYPASS_ECC_WIDTH 1 1357#define FRF_CZ_SEC_INT_LBN 2 1358#define FRF_CZ_SEC_INT_WIDTH 1 1359#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 1360#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 1361#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 1362#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 1363#define FRF_AB_FORCE_SRAM_PERR_LBN 0 1364#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 1365 1366 1367/* 1368 * FR_AZ_RX_CFG_REG(128bit): 1369 * Receive configuration register 1370 */ 1371#define FR_AZ_RX_CFG_REG_OFST 0x00000800 1372/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1373 1374#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1375#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1376#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1377#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1378#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1379#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1380#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1381#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1382#define FRF_BZ_RX_TCP_SUP_LBN 48 1383#define FRF_BZ_RX_TCP_SUP_WIDTH 1 1384#define FRF_BZ_RX_INGR_EN_LBN 47 1385#define FRF_BZ_RX_INGR_EN_WIDTH 1 1386#define FRF_BZ_RX_IP_HASH_LBN 46 1387#define FRF_BZ_RX_IP_HASH_WIDTH 1 1388#define FRF_BZ_RX_HASH_ALG_LBN 45 1389#define FRF_BZ_RX_HASH_ALG_WIDTH 1 1390#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1391#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1392#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1393#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1394#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1395#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1396#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1397#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1398#define FRF_BZ_RX_OWNERR_CTL_LBN 38 1399#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1400#define FRF_BZ_RX_XON_TX_TH_LBN 33 1401#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1402#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1403#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1404#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1405#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1406#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1407#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1408#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1409#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1410#define FRF_AA_RX_OWNERR_CTL_LBN 30 1411#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1412#define FRF_AA_RX_XON_TX_TH_LBN 25 1413#define FRF_AA_RX_XON_TX_TH_WIDTH 5 1414#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1415#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1416#define FRF_AA_RX_XOFF_TX_TH_LBN 20 1417#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1418#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1419#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1420#define FRF_BZ_RX_XON_MAC_TH_LBN 10 1421#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1422#define FRF_AA_RX_XON_MAC_TH_LBN 6 1423#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1424#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1425#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1426#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1427#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1428#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1429#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1430 1431 1432/* 1433 * FR_AZ_RX_FILTER_CTL_REG(128bit): 1434 * Receive filter control registers 1435 */ 1436#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 1437/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1438 1439#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1440#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1441#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1442#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1443#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1444#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1445#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1446#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1447#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1448#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1449#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1450#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1451#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1452#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1453#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1454#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1455#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1456#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1457#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1458#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1459#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1460#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1461#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 1462#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1463#define FRF_AZ_NUM_KER_LBN 24 1464#define FRF_AZ_NUM_KER_WIDTH 2 1465#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 1466#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1467#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 1468#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1469#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 1470#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1471 1472 1473/* 1474 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): 1475 * Receive flush descriptor queue register 1476 */ 1477#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 1478/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1479 1480#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1481#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1482#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1483#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1484 1485 1486/* 1487 * FR_BZ_RX_DESC_UPD_REGP0(128bit): 1488 * Receive descriptor update register. 1489 */ 1490#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 1491/* falconb0,sienaa0=net_func_bar2 */ 1492#define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 1493#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 1494/* 1495 * FR_AA_RX_DESC_UPD_REG_KER(128bit): 1496 * Receive descriptor update register. 1497 */ 1498#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 1499/* falcona0=net_func_bar2 */ 1500#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 1501#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 1502/* 1503 * FR_AB_RX_DESC_UPD_REGP123(128bit): 1504 * Receive descriptor update register. 1505 */ 1506#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 1507/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1508#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 1509#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 1510/* 1511 * FR_AA_RX_DESC_UPD_REGP0(128bit): 1512 * Receive descriptor update register. 1513 */ 1514#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 1515/* falcona0=char_func_bar0 */ 1516#define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 1517#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 1518 1519#define FRF_AZ_RX_DESC_WPTR_LBN 96 1520#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1521#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1522#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1523#define FRF_AZ_RX_DESC_LBN 0 1524#define FRF_AZ_RX_DESC_WIDTH 64 1525#define FRF_AZ_RX_DESC_DW0_LBN 0 1526#define FRF_AZ_RX_DESC_DW0_WIDTH 32 1527#define FRF_AZ_RX_DESC_DW1_LBN 32 1528#define FRF_AZ_RX_DESC_DW1_WIDTH 32 1529 1530 1531/* 1532 * FR_AZ_RX_DC_CFG_REG(128bit): 1533 * Receive descriptor cache configuration register 1534 */ 1535#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 1536/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1537 1538#define FRF_AZ_RX_MAX_PF_LBN 2 1539#define FRF_AZ_RX_MAX_PF_WIDTH 2 1540#define FRF_AZ_RX_DC_SIZE_LBN 0 1541#define FRF_AZ_RX_DC_SIZE_WIDTH 2 1542#define FFE_AZ_RX_DC_SIZE_64 3 1543#define FFE_AZ_RX_DC_SIZE_32 2 1544#define FFE_AZ_RX_DC_SIZE_16 1 1545#define FFE_AZ_RX_DC_SIZE_8 0 1546 1547 1548/* 1549 * FR_AZ_RX_DC_PF_WM_REG(128bit): 1550 * Receive descriptor cache pre-fetch watermark register 1551 */ 1552#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 1553/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1554 1555#define FRF_AZ_RX_DC_PF_HWM_LBN 6 1556#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1557#define FRF_AZ_RX_DC_PF_LWM_LBN 0 1558#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1559 1560 1561/* 1562 * FR_BZ_RX_RSS_TKEY_REG(128bit): 1563 * RSS Toeplitz hash key 1564 */ 1565#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 1566/* falconb0,sienaa0=net_func_bar2 */ 1567 1568#define FRF_BZ_RX_RSS_TKEY_LBN 96 1569#define FRF_BZ_RX_RSS_TKEY_WIDTH 32 1570#define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 1571#define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 1572#define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 1573#define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 1574#define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 1575#define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 1576#define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 1577#define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 1578 1579 1580/* 1581 * FR_AZ_RX_NODESC_DROP_REG(128bit): 1582 * Receive dropped packet counter register 1583 */ 1584#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 1585/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1586 1587#define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 1588#define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 1589 1590 1591/* 1592 * FR_AZ_RX_SELF_RST_REG(128bit): 1593 * Receive self reset register 1594 */ 1595#define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 1596/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1597 1598#define FRF_AZ_RX_ISCSI_DIS_LBN 17 1599#define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 1600#define FRF_AB_RX_SW_RST_REG_LBN 16 1601#define FRF_AB_RX_SW_RST_REG_WIDTH 1 1602#define FRF_AB_RX_SELF_RST_EN_LBN 8 1603#define FRF_AB_RX_SELF_RST_EN_WIDTH 1 1604#define FRF_AZ_RX_MAX_PF_LAT_LBN 4 1605#define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 1606#define FRF_AZ_RX_MAX_LU_LAT_LBN 0 1607#define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 1608 1609 1610/* 1611 * FR_AZ_RX_DEBUG_REG(128bit): 1612 * undocumented register 1613 */ 1614#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 1615/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1616 1617#define FRF_AZ_RX_DEBUG_LBN 0 1618#define FRF_AZ_RX_DEBUG_WIDTH 64 1619#define FRF_AZ_RX_DEBUG_DW0_LBN 0 1620#define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 1621#define FRF_AZ_RX_DEBUG_DW1_LBN 32 1622#define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 1623 1624 1625/* 1626 * FR_AZ_RX_PUSH_DROP_REG(128bit): 1627 * Receive descriptor push dropped counter register 1628 */ 1629#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 1630/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1631 1632#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1633#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1634 1635 1636/* 1637 * FR_CZ_RX_RSS_IPV6_REG1(128bit): 1638 * IPv6 RSS Toeplitz hash key low bytes 1639 */ 1640#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 1641/* sienaa0=net_func_bar2 */ 1642 1643#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1644#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1645#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 1646#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 1647#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 1648#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 1649#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 1650#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 1651#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 1652#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 1653 1654 1655/* 1656 * FR_CZ_RX_RSS_IPV6_REG2(128bit): 1657 * IPv6 RSS Toeplitz hash key middle bytes 1658 */ 1659#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 1660/* sienaa0=net_func_bar2 */ 1661 1662#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1663#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1664#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 1665#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 1666#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 1667#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 1668#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 1669#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 1670#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 1671#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 1672 1673 1674/* 1675 * FR_CZ_RX_RSS_IPV6_REG3(128bit): 1676 * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings 1677 */ 1678#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 1679/* sienaa0=net_func_bar2 */ 1680 1681#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1682#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1683#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1684#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1685#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1686#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1687#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1688#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1689#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 1690#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 1691#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 1692#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 1693 1694 1695/* 1696 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): 1697 * Transmit flush descriptor queue register 1698 */ 1699#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 1700/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1701 1702#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1703#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1704#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1705#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1706 1707 1708/* 1709 * FR_BZ_TX_DESC_UPD_REGP0(128bit): 1710 * Transmit descriptor update register. 1711 */ 1712#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 1713/* falconb0,sienaa0=net_func_bar2 */ 1714#define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 1715#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 1716/* 1717 * FR_AA_TX_DESC_UPD_REG_KER(128bit): 1718 * Transmit descriptor update register. 1719 */ 1720#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 1721/* falcona0=net_func_bar2 */ 1722#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 1723#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 1724/* 1725 * FR_AB_TX_DESC_UPD_REGP123(128bit): 1726 * Transmit descriptor update register. 1727 */ 1728#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 1729/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1730#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 1731#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 1732/* 1733 * FR_AA_TX_DESC_UPD_REGP0(128bit): 1734 * Transmit descriptor update register. 1735 */ 1736#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 1737/* falcona0=char_func_bar0 */ 1738#define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 1739#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 1740 1741#define FRF_AZ_TX_DESC_WPTR_LBN 96 1742#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1743#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1744#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1745#define FRF_AZ_TX_DESC_LBN 0 1746#define FRF_AZ_TX_DESC_WIDTH 95 1747#define FRF_AZ_TX_DESC_DW0_LBN 0 1748#define FRF_AZ_TX_DESC_DW0_WIDTH 32 1749#define FRF_AZ_TX_DESC_DW1_LBN 32 1750#define FRF_AZ_TX_DESC_DW1_WIDTH 32 1751#define FRF_AZ_TX_DESC_DW2_LBN 64 1752#define FRF_AZ_TX_DESC_DW2_WIDTH 31 1753 1754 1755/* 1756 * FR_AZ_TX_DC_CFG_REG(128bit): 1757 * Transmit descriptor cache configuration register 1758 */ 1759#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 1760/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1761 1762#define FRF_AZ_TX_DC_SIZE_LBN 0 1763#define FRF_AZ_TX_DC_SIZE_WIDTH 2 1764#define FFE_AZ_TX_DC_SIZE_32 2 1765#define FFE_AZ_TX_DC_SIZE_16 1 1766#define FFE_AZ_TX_DC_SIZE_8 0 1767 1768 1769/* 1770 * FR_AA_TX_CHKSM_CFG_REG(128bit): 1771 * Transmit checksum configuration register 1772 */ 1773#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 1774/* falcona0=net_func_bar2,falcona0=char_func_bar0 */ 1775 1776#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1777#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1778#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1779#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1780#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1781#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1782#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1783#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1784 1785 1786/* 1787 * FR_AZ_TX_CFG_REG(128bit): 1788 * Transmit configuration register 1789 */ 1790#define FR_AZ_TX_CFG_REG_OFST 0x00000a50 1791/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1792 1793#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1794#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1795#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1796#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1797#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1798#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1799#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1800#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1801#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1802#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1803#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1804#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1805#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1806#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1807#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1808#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1809#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1810#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1811#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1812#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1813#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1814#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1815#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1816#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1817#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1818#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1819#define FRF_AZ_TX_P1_PRI_EN_LBN 4 1820#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1821#define FRF_AZ_TX_OWNERR_CTL_LBN 2 1822#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1823#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1824#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1825#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1826#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1827 1828 1829/* 1830 * FR_AZ_TX_PUSH_DROP_REG(128bit): 1831 * Transmit push dropped register 1832 */ 1833#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 1834/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1835 1836#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1837#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1838 1839 1840/* 1841 * FR_AZ_TX_RESERVED_REG(128bit): 1842 * Transmit configuration register 1843 */ 1844#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 1845/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1846 1847#define FRF_AZ_TX_EVT_CNT_LBN 121 1848#define FRF_AZ_TX_EVT_CNT_WIDTH 7 1849#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1850#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1851#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1852#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1853#define FRF_AZ_TX_PUSH_EN_LBN 89 1854#define FRF_AZ_TX_PUSH_EN_WIDTH 1 1855#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1856#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1857#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1858#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1859#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1860#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1861#define FRF_AZ_TX_DMAQ_ST_LBN 78 1862#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1863#define FRF_AZ_TX_RX_SPACER_LBN 64 1864#define FRF_AZ_TX_RX_SPACER_WIDTH 8 1865#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1866#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1867#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1868#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1869#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1870#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1871#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1872#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1873#define FRF_AZ_TX_XP_TIMER_LBN 52 1874#define FRF_AZ_TX_XP_TIMER_WIDTH 5 1875#define FRF_AZ_TX_PREF_SPACER_LBN 44 1876#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1877#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1878#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1879#define FRF_AZ_TX_ONLY1TAG_LBN 21 1880#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1881#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1882#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1883#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1884#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1885#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1886#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1887#define FRF_AA_TX_DMA_FF_THR_LBN 16 1888#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1889#define FRF_AZ_TX_DMA_SPACER_LBN 8 1890#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1891#define FRF_AA_TX_TCP_DIS_LBN 7 1892#define FRF_AA_TX_TCP_DIS_WIDTH 1 1893#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1894#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1895#define FRF_AA_TX_IP_DIS_LBN 6 1896#define FRF_AA_TX_IP_DIS_WIDTH 1 1897#define FRF_AZ_TX_MAX_CPL_LBN 2 1898#define FRF_AZ_TX_MAX_CPL_WIDTH 2 1899#define FFE_AZ_TX_MAX_CPL_16 3 1900#define FFE_AZ_TX_MAX_CPL_8 2 1901#define FFE_AZ_TX_MAX_CPL_4 1 1902#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1903#define FRF_AZ_TX_MAX_PREF_LBN 0 1904#define FRF_AZ_TX_MAX_PREF_WIDTH 2 1905#define FFE_AZ_TX_MAX_PREF_32 3 1906#define FFE_AZ_TX_MAX_PREF_16 2 1907#define FFE_AZ_TX_MAX_PREF_8 1 1908#define FFE_AZ_TX_MAX_PREF_OFF 0 1909 1910 1911/* 1912 * FR_BZ_TX_PACE_REG(128bit): 1913 * Transmit pace control register 1914 */ 1915#define FR_BZ_TX_PACE_REG_OFST 0x00000a90 1916/* falconb0,sienaa0=net_func_bar2 */ 1917/* 1918 * FR_AA_TX_PACE_REG(128bit): 1919 * Transmit pace control register 1920 */ 1921#define FR_AA_TX_PACE_REG_OFST 0x00f80000 1922/* falcona0=char_func_bar0 */ 1923 1924#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 1925#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 1926#define FRF_AZ_TX_PACE_SB_AF_LBN 9 1927#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 1928#define FRF_AZ_TX_PACE_FB_BASE_LBN 5 1929#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 1930#define FRF_AZ_TX_PACE_BIN_TH_LBN 0 1931#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 1932 1933 1934/* 1935 * FR_AZ_TX_PACE_DROP_QID_REG(128bit): 1936 * PACE Drop QID Counter 1937 */ 1938#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 1939/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1940 1941#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 1942#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1943 1944 1945/* 1946 * FR_AB_TX_VLAN_REG(128bit): 1947 * Transmit VLAN tag register 1948 */ 1949#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 1950/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1951 1952#define FRF_AB_TX_VLAN_EN_LBN 127 1953#define FRF_AB_TX_VLAN_EN_WIDTH 1 1954#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 1955#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 1956#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 1957#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 1958#define FRF_AB_TX_VLAN7_LBN 112 1959#define FRF_AB_TX_VLAN7_WIDTH 12 1960#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 1961#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 1962#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 1963#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 1964#define FRF_AB_TX_VLAN6_LBN 96 1965#define FRF_AB_TX_VLAN6_WIDTH 12 1966#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 1967#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 1968#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 1969#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 1970#define FRF_AB_TX_VLAN5_LBN 80 1971#define FRF_AB_TX_VLAN5_WIDTH 12 1972#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 1973#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 1974#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 1975#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 1976#define FRF_AB_TX_VLAN4_LBN 64 1977#define FRF_AB_TX_VLAN4_WIDTH 12 1978#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 1979#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 1980#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 1981#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 1982#define FRF_AB_TX_VLAN3_LBN 48 1983#define FRF_AB_TX_VLAN3_WIDTH 12 1984#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 1985#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 1986#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 1987#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 1988#define FRF_AB_TX_VLAN2_LBN 32 1989#define FRF_AB_TX_VLAN2_WIDTH 12 1990#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 1991#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 1992#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 1993#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 1994#define FRF_AB_TX_VLAN1_LBN 16 1995#define FRF_AB_TX_VLAN1_WIDTH 12 1996#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 1997#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 1998#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 1999#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 2000#define FRF_AB_TX_VLAN0_LBN 0 2001#define FRF_AB_TX_VLAN0_WIDTH 12 2002 2003 2004/* 2005 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): 2006 * Transmit filter control register 2007 */ 2008#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 2009/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 2010 2011#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 2012#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 2013#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 2014#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 2015#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 2016#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 2017#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 2018#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 2019#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 2020#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 2021#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 2022#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 2023#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 2024#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 2025#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 2026#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 2027#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 2028#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 2029#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 2030#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 2031#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 2032#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 2033#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 2034#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 2035#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 2036#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 2037#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 2038#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 2039#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 2040#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 2041#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 2042#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 2043#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 2044#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 2045#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 2046#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 2047#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 2048#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 2049#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 2050#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 2051#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 2052#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 2053#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 2054#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 2055#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 2056#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 2057#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 2058#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 2059#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 2060#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 2061#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 2062#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 2063#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 2064#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 2065#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 2066#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 2067#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 2068#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 2069#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 2070#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 2071#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 2072#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 2073#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 2074#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 2075#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 2076#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 2077 2078 2079/* 2080 * FR_AB_TX_IPFIL_TBL(128bit): 2081 * Transmit IP source address filter table 2082 */ 2083#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 2084/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2085#define FR_AB_TX_IPFIL_TBL_STEP 16 2086#define FR_AB_TX_IPFIL_TBL_ROWS 16 2087 2088#define FRF_AB_TX_IPFIL_MASK_1_LBN 96 2089#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 2090#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 2091#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 2092#define FRF_AB_TX_IPFIL_MASK_0_LBN 32 2093#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 2094#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 2095#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 2096 2097 2098/* 2099 * FR_AB_MD_TXD_REG(128bit): 2100 * PHY management transmit data register 2101 */ 2102#define FR_AB_MD_TXD_REG_OFST 0x00000c00 2103/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2104 2105#define FRF_AB_MD_TXD_LBN 0 2106#define FRF_AB_MD_TXD_WIDTH 16 2107 2108 2109/* 2110 * FR_AB_MD_RXD_REG(128bit): 2111 * PHY management receive data register 2112 */ 2113#define FR_AB_MD_RXD_REG_OFST 0x00000c10 2114/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2115 2116#define FRF_AB_MD_RXD_LBN 0 2117#define FRF_AB_MD_RXD_WIDTH 16 2118 2119 2120/* 2121 * FR_AB_MD_CS_REG(128bit): 2122 * PHY management configuration & status register 2123 */ 2124#define FR_AB_MD_CS_REG_OFST 0x00000c20 2125/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2126 2127#define FRF_AB_MD_RD_EN_LBN 15 2128#define FRF_AB_MD_RD_EN_WIDTH 1 2129#define FRF_AB_MD_WR_EN_LBN 14 2130#define FRF_AB_MD_WR_EN_WIDTH 1 2131#define FRF_AB_MD_ADDR_CMD_LBN 13 2132#define FRF_AB_MD_ADDR_CMD_WIDTH 1 2133#define FRF_AB_MD_PT_LBN 7 2134#define FRF_AB_MD_PT_WIDTH 3 2135#define FRF_AB_MD_PL_LBN 6 2136#define FRF_AB_MD_PL_WIDTH 1 2137#define FRF_AB_MD_INT_CLR_LBN 5 2138#define FRF_AB_MD_INT_CLR_WIDTH 1 2139#define FRF_AB_MD_GC_LBN 4 2140#define FRF_AB_MD_GC_WIDTH 1 2141#define FRF_AB_MD_PRSP_LBN 3 2142#define FRF_AB_MD_PRSP_WIDTH 1 2143#define FRF_AB_MD_RIC_LBN 2 2144#define FRF_AB_MD_RIC_WIDTH 1 2145#define FRF_AB_MD_RDC_LBN 1 2146#define FRF_AB_MD_RDC_WIDTH 1 2147#define FRF_AB_MD_WRC_LBN 0 2148#define FRF_AB_MD_WRC_WIDTH 1 2149 2150 2151/* 2152 * FR_AB_MD_PHY_ADR_REG(128bit): 2153 * PHY management PHY address register 2154 */ 2155#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 2156/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2157 2158#define FRF_AB_MD_PHY_ADR_LBN 0 2159#define FRF_AB_MD_PHY_ADR_WIDTH 16 2160 2161 2162/* 2163 * FR_AB_MD_ID_REG(128bit): 2164 * PHY management ID register 2165 */ 2166#define FR_AB_MD_ID_REG_OFST 0x00000c40 2167/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2168 2169#define FRF_AB_MD_PRT_ADR_LBN 11 2170#define FRF_AB_MD_PRT_ADR_WIDTH 5 2171#define FRF_AB_MD_DEV_ADR_LBN 6 2172#define FRF_AB_MD_DEV_ADR_WIDTH 5 2173 2174 2175/* 2176 * FR_AB_MD_STAT_REG(128bit): 2177 * PHY management status & mask register 2178 */ 2179#define FR_AB_MD_STAT_REG_OFST 0x00000c50 2180/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2181 2182#define FRF_AB_MD_PINT_LBN 4 2183#define FRF_AB_MD_PINT_WIDTH 1 2184#define FRF_AB_MD_DONE_LBN 3 2185#define FRF_AB_MD_DONE_WIDTH 1 2186#define FRF_AB_MD_BSERR_LBN 2 2187#define FRF_AB_MD_BSERR_WIDTH 1 2188#define FRF_AB_MD_LNFL_LBN 1 2189#define FRF_AB_MD_LNFL_WIDTH 1 2190#define FRF_AB_MD_BSY_LBN 0 2191#define FRF_AB_MD_BSY_WIDTH 1 2192 2193 2194/* 2195 * FR_AB_MAC_STAT_DMA_REG(128bit): 2196 * Port MAC statistical counter DMA register 2197 */ 2198#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 2199/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2200 2201#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 2202#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 2203#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 2204#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 2205#define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 2206#define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 2207#define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 2208#define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 2209 2210 2211/* 2212 * FR_AB_MAC_CTRL_REG(128bit): 2213 * Port MAC control register 2214 */ 2215#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 2216/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2217 2218#define FRF_AB_MAC_XOFF_VAL_LBN 16 2219#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 2220#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 2221#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 2222#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 2223#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 2224#define FRF_AB_MAC_BCAD_ACPT_LBN 4 2225#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 2226#define FRF_AB_MAC_UC_PROM_LBN 3 2227#define FRF_AB_MAC_UC_PROM_WIDTH 1 2228#define FRF_AB_MAC_LINK_STATUS_LBN 2 2229#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 2230#define FRF_AB_MAC_SPEED_LBN 0 2231#define FRF_AB_MAC_SPEED_WIDTH 2 2232#define FRF_AB_MAC_SPEED_10M 0 2233#define FRF_AB_MAC_SPEED_100M 1 2234#define FRF_AB_MAC_SPEED_1G 2 2235#define FRF_AB_MAC_SPEED_10G 3 2236 2237/* 2238 * FR_BB_GEN_MODE_REG(128bit): 2239 * General Purpose mode register (external interrupt mask) 2240 */ 2241#define FR_BB_GEN_MODE_REG_OFST 0x00000c90 2242/* falconb0=net_func_bar2 */ 2243 2244#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 2245#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 2246#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 2247#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 2248#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 2249#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 2250#define FRF_BB_XG_PHY_INT_MASK_LBN 0 2251#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 2252 2253 2254/* 2255 * FR_AB_MAC_MC_HASH_REG0(128bit): 2256 * Multicast address hash table 2257 */ 2258#define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 2259/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2260 2261#define FRF_AB_MAC_MCAST_HASH0_LBN 0 2262#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 2263#define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 2264#define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 2265#define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 2266#define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 2267#define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 2268#define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 2269#define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 2270#define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 2271 2272 2273/* 2274 * FR_AB_MAC_MC_HASH_REG1(128bit): 2275 * Multicast address hash table 2276 */ 2277#define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 2278/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2279 2280#define FRF_AB_MAC_MCAST_HASH1_LBN 0 2281#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 2282#define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 2283#define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 2284#define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 2285#define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 2286#define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 2287#define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 2288#define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 2289#define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 2290 2291 2292/* 2293 * FR_AB_GM_CFG1_REG(32bit): 2294 * GMAC configuration register 1 2295 */ 2296#define FR_AB_GM_CFG1_REG_OFST 0x00000e00 2297/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2298 2299#define FRF_AB_GM_SW_RST_LBN 31 2300#define FRF_AB_GM_SW_RST_WIDTH 1 2301#define FRF_AB_GM_SIM_RST_LBN 30 2302#define FRF_AB_GM_SIM_RST_WIDTH 1 2303#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 2304#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 2305#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 2306#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 2307#define FRF_AB_GM_RST_RX_FUNC_LBN 17 2308#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 2309#define FRF_AB_GM_RST_TX_FUNC_LBN 16 2310#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 2311#define FRF_AB_GM_LOOP_LBN 8 2312#define FRF_AB_GM_LOOP_WIDTH 1 2313#define FRF_AB_GM_RX_FC_EN_LBN 5 2314#define FRF_AB_GM_RX_FC_EN_WIDTH 1 2315#define FRF_AB_GM_TX_FC_EN_LBN 4 2316#define FRF_AB_GM_TX_FC_EN_WIDTH 1 2317#define FRF_AB_GM_SYNC_RXEN_LBN 3 2318#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 2319#define FRF_AB_GM_RX_EN_LBN 2 2320#define FRF_AB_GM_RX_EN_WIDTH 1 2321#define FRF_AB_GM_SYNC_TXEN_LBN 1 2322#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 2323#define FRF_AB_GM_TX_EN_LBN 0 2324#define FRF_AB_GM_TX_EN_WIDTH 1 2325 2326 2327/* 2328 * FR_AB_GM_CFG2_REG(32bit): 2329 * GMAC configuration register 2 2330 */ 2331#define FR_AB_GM_CFG2_REG_OFST 0x00000e10 2332/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2333 2334#define FRF_AB_GM_PAMBL_LEN_LBN 12 2335#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 2336#define FRF_AB_GM_IF_MODE_LBN 8 2337#define FRF_AB_GM_IF_MODE_WIDTH 2 2338#define FRF_AB_GM_IF_MODE_BYTE_MODE 2 2339#define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 2340#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 2341#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 2342#define FRF_AB_GM_LEN_CHK_LBN 4 2343#define FRF_AB_GM_LEN_CHK_WIDTH 1 2344#define FRF_AB_GM_PAD_CRC_EN_LBN 2 2345#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 2346#define FRF_AB_GM_CRC_EN_LBN 1 2347#define FRF_AB_GM_CRC_EN_WIDTH 1 2348#define FRF_AB_GM_FD_LBN 0 2349#define FRF_AB_GM_FD_WIDTH 1 2350 2351 2352/* 2353 * FR_AB_GM_IPG_REG(32bit): 2354 * GMAC IPG register 2355 */ 2356#define FR_AB_GM_IPG_REG_OFST 0x00000e20 2357/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2358 2359#define FRF_AB_GM_NONB2B_IPG1_LBN 24 2360#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 2361#define FRF_AB_GM_NONB2B_IPG2_LBN 16 2362#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 2363#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 2364#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 2365#define FRF_AB_GM_B2B_IPG_LBN 0 2366#define FRF_AB_GM_B2B_IPG_WIDTH 7 2367 2368 2369/* 2370 * FR_AB_GM_HD_REG(32bit): 2371 * GMAC half duplex register 2372 */ 2373#define FR_AB_GM_HD_REG_OFST 0x00000e30 2374/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2375 2376#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 2377#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 2378#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 2379#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 2380#define FRF_AB_GM_BP_NO_BOFF_LBN 18 2381#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 2382#define FRF_AB_GM_DIS_BOFF_LBN 17 2383#define FRF_AB_GM_DIS_BOFF_WIDTH 1 2384#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 2385#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 2386#define FRF_AB_GM_RTRY_LIMIT_LBN 12 2387#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 2388#define FRF_AB_GM_COL_WIN_LBN 0 2389#define FRF_AB_GM_COL_WIN_WIDTH 10 2390 2391 2392/* 2393 * FR_AB_GM_MAX_FLEN_REG(32bit): 2394 * GMAC maximum frame length register 2395 */ 2396#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 2397/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2398 2399#define FRF_AB_GM_MAX_FLEN_LBN 0 2400#define FRF_AB_GM_MAX_FLEN_WIDTH 16 2401 2402 2403/* 2404 * FR_AB_GM_TEST_REG(32bit): 2405 * GMAC test register 2406 */ 2407#define FR_AB_GM_TEST_REG_OFST 0x00000e70 2408/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2409 2410#define FRF_AB_GM_MAX_BOFF_LBN 3 2411#define FRF_AB_GM_MAX_BOFF_WIDTH 1 2412#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 2413#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 2414#define FRF_AB_GM_TEST_PAUSE_LBN 1 2415#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 2416#define FRF_AB_GM_SHORT_SLOT_LBN 0 2417#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 2418 2419 2420/* 2421 * FR_AB_GM_ADR1_REG(32bit): 2422 * GMAC station address register 1 2423 */ 2424#define FR_AB_GM_ADR1_REG_OFST 0x00000f00 2425/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2426 2427#define FRF_AB_GM_ADR_B0_LBN 24 2428#define FRF_AB_GM_ADR_B0_WIDTH 8 2429#define FRF_AB_GM_ADR_B1_LBN 16 2430#define FRF_AB_GM_ADR_B1_WIDTH 8 2431#define FRF_AB_GM_ADR_B2_LBN 8 2432#define FRF_AB_GM_ADR_B2_WIDTH 8 2433#define FRF_AB_GM_ADR_B3_LBN 0 2434#define FRF_AB_GM_ADR_B3_WIDTH 8 2435 2436 2437/* 2438 * FR_AB_GM_ADR2_REG(32bit): 2439 * GMAC station address register 2 2440 */ 2441#define FR_AB_GM_ADR2_REG_OFST 0x00000f10 2442/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2443 2444#define FRF_AB_GM_ADR_B4_LBN 24 2445#define FRF_AB_GM_ADR_B4_WIDTH 8 2446#define FRF_AB_GM_ADR_B5_LBN 16 2447#define FRF_AB_GM_ADR_B5_WIDTH 8 2448 2449 2450/* 2451 * FR_AB_GMF_CFG0_REG(32bit): 2452 * GMAC FIFO configuration register 0 2453 */ 2454#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 2455/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2456 2457#define FRF_AB_GMF_FTFENRPLY_LBN 20 2458#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 2459#define FRF_AB_GMF_STFENRPLY_LBN 19 2460#define FRF_AB_GMF_STFENRPLY_WIDTH 1 2461#define FRF_AB_GMF_FRFENRPLY_LBN 18 2462#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 2463#define FRF_AB_GMF_SRFENRPLY_LBN 17 2464#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 2465#define FRF_AB_GMF_WTMENRPLY_LBN 16 2466#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 2467#define FRF_AB_GMF_FTFENREQ_LBN 12 2468#define FRF_AB_GMF_FTFENREQ_WIDTH 1 2469#define FRF_AB_GMF_STFENREQ_LBN 11 2470#define FRF_AB_GMF_STFENREQ_WIDTH 1 2471#define FRF_AB_GMF_FRFENREQ_LBN 10 2472#define FRF_AB_GMF_FRFENREQ_WIDTH 1 2473#define FRF_AB_GMF_SRFENREQ_LBN 9 2474#define FRF_AB_GMF_SRFENREQ_WIDTH 1 2475#define FRF_AB_GMF_WTMENREQ_LBN 8 2476#define FRF_AB_GMF_WTMENREQ_WIDTH 1 2477#define FRF_AB_GMF_HSTRSTFT_LBN 4 2478#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 2479#define FRF_AB_GMF_HSTRSTST_LBN 3 2480#define FRF_AB_GMF_HSTRSTST_WIDTH 1 2481#define FRF_AB_GMF_HSTRSTFR_LBN 2 2482#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 2483#define FRF_AB_GMF_HSTRSTSR_LBN 1 2484#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 2485#define FRF_AB_GMF_HSTRSTWT_LBN 0 2486#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 2487 2488 2489/* 2490 * FR_AB_GMF_CFG1_REG(32bit): 2491 * GMAC FIFO configuration register 1 2492 */ 2493#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 2494/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2495 2496#define FRF_AB_GMF_CFGFRTH_LBN 16 2497#define FRF_AB_GMF_CFGFRTH_WIDTH 5 2498#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 2499#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 2500 2501 2502/* 2503 * FR_AB_GMF_CFG2_REG(32bit): 2504 * GMAC FIFO configuration register 2 2505 */ 2506#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 2507/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2508 2509#define FRF_AB_GMF_CFGHWM_LBN 16 2510#define FRF_AB_GMF_CFGHWM_WIDTH 6 2511#define FRF_AB_GMF_CFGLWM_LBN 0 2512#define FRF_AB_GMF_CFGLWM_WIDTH 6 2513 2514 2515/* 2516 * FR_AB_GMF_CFG3_REG(32bit): 2517 * GMAC FIFO configuration register 3 2518 */ 2519#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 2520/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2521 2522#define FRF_AB_GMF_CFGHWMFT_LBN 16 2523#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 2524#define FRF_AB_GMF_CFGFTTH_LBN 0 2525#define FRF_AB_GMF_CFGFTTH_WIDTH 6 2526 2527 2528/* 2529 * FR_AB_GMF_CFG4_REG(32bit): 2530 * GMAC FIFO configuration register 4 2531 */ 2532#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 2533/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2534 2535#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 2536#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 2537 2538 2539/* 2540 * FR_AB_GMF_CFG5_REG(32bit): 2541 * GMAC FIFO configuration register 5 2542 */ 2543#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 2544/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2545 2546#define FRF_AB_GMF_CFGHDPLX_LBN 22 2547#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 2548#define FRF_AB_GMF_SRFULL_LBN 21 2549#define FRF_AB_GMF_SRFULL_WIDTH 1 2550#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 2551#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 2552#define FRF_AB_GMF_CFGBYTMODE_LBN 19 2553#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 2554#define FRF_AB_GMF_HSTDRPLT64_LBN 18 2555#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 2556#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 2557#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 2558 2559 2560/* 2561 * FR_BB_TX_SRC_MAC_TBL(128bit): 2562 * Transmit IP source address filter table 2563 */ 2564#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 2565/* falconb0=net_func_bar2 */ 2566#define FR_BB_TX_SRC_MAC_TBL_STEP 16 2567#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 2568 2569#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 2570#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 2571#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 2572#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 2573#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 2574#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 2575#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 2576#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 2577#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 2578#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 2579#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 2580#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 2581 2582 2583/* 2584 * FR_BB_TX_SRC_MAC_CTL_REG(128bit): 2585 * Transmit MAC source address filter control 2586 */ 2587#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 2588/* falconb0=net_func_bar2 */ 2589 2590#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 2591#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 2592#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 2593#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 2594#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 2595#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 2596#define FRF_BB_TX_MAC_QID_SEL_LBN 0 2597#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 2598 2599 2600/* 2601 * FR_AB_XM_ADR_LO_REG(128bit): 2602 * XGMAC address register low 2603 */ 2604#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 2605/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2606 2607#define FRF_AB_XM_ADR_LO_LBN 0 2608#define FRF_AB_XM_ADR_LO_WIDTH 32 2609 2610 2611/* 2612 * FR_AB_XM_ADR_HI_REG(128bit): 2613 * XGMAC address register high 2614 */ 2615#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 2616/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2617 2618#define FRF_AB_XM_ADR_HI_LBN 0 2619#define FRF_AB_XM_ADR_HI_WIDTH 16 2620 2621 2622/* 2623 * FR_AB_XM_GLB_CFG_REG(128bit): 2624 * XGMAC global configuration 2625 */ 2626#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 2627/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2628 2629#define FRF_AB_XM_RMTFLT_GEN_LBN 17 2630#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 2631#define FRF_AB_XM_DEBUG_MODE_LBN 16 2632#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 2633#define FRF_AB_XM_RX_STAT_EN_LBN 11 2634#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 2635#define FRF_AB_XM_TX_STAT_EN_LBN 10 2636#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 2637#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 2638#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 2639#define FRF_AB_XM_WAN_MODE_LBN 5 2640#define FRF_AB_XM_WAN_MODE_WIDTH 1 2641#define FRF_AB_XM_INTCLR_MODE_LBN 3 2642#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 2643#define FRF_AB_XM_CORE_RST_LBN 0 2644#define FRF_AB_XM_CORE_RST_WIDTH 1 2645 2646 2647/* 2648 * FR_AB_XM_TX_CFG_REG(128bit): 2649 * XGMAC transmit configuration 2650 */ 2651#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 2652/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2653 2654#define FRF_AB_XM_TX_PROG_LBN 24 2655#define FRF_AB_XM_TX_PROG_WIDTH 1 2656#define FRF_AB_XM_IPG_LBN 16 2657#define FRF_AB_XM_IPG_WIDTH 4 2658#define FRF_AB_XM_FCNTL_LBN 10 2659#define FRF_AB_XM_FCNTL_WIDTH 1 2660#define FRF_AB_XM_TXCRC_LBN 8 2661#define FRF_AB_XM_TXCRC_WIDTH 1 2662#define FRF_AB_XM_EDRC_LBN 6 2663#define FRF_AB_XM_EDRC_WIDTH 1 2664#define FRF_AB_XM_AUTO_PAD_LBN 5 2665#define FRF_AB_XM_AUTO_PAD_WIDTH 1 2666#define FRF_AB_XM_TX_PRMBL_LBN 2 2667#define FRF_AB_XM_TX_PRMBL_WIDTH 1 2668#define FRF_AB_XM_TXEN_LBN 1 2669#define FRF_AB_XM_TXEN_WIDTH 1 2670#define FRF_AB_XM_TX_RST_LBN 0 2671#define FRF_AB_XM_TX_RST_WIDTH 1 2672 2673 2674/* 2675 * FR_AB_XM_RX_CFG_REG(128bit): 2676 * XGMAC receive configuration 2677 */ 2678#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 2679/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2680 2681#define FRF_AB_XM_PASS_LENERR_LBN 26 2682#define FRF_AB_XM_PASS_LENERR_WIDTH 1 2683#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 2684#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 2685#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 2686#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 2687#define FRF_AB_XM_REJ_BCAST_LBN 20 2688#define FRF_AB_XM_REJ_BCAST_WIDTH 1 2689#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 2690#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 2691#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 2692#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 2693#define FRF_AB_XM_AUTO_DEPAD_LBN 8 2694#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 2695#define FRF_AB_XM_RXCRC_LBN 3 2696#define FRF_AB_XM_RXCRC_WIDTH 1 2697#define FRF_AB_XM_RX_PRMBL_LBN 2 2698#define FRF_AB_XM_RX_PRMBL_WIDTH 1 2699#define FRF_AB_XM_RXEN_LBN 1 2700#define FRF_AB_XM_RXEN_WIDTH 1 2701#define FRF_AB_XM_RX_RST_LBN 0 2702#define FRF_AB_XM_RX_RST_WIDTH 1 2703 2704 2705/* 2706 * FR_AB_XM_MGT_INT_MASK(128bit): 2707 * documentation to be written for sum_XM_MGT_INT_MASK 2708 */ 2709#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 2710/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2711 2712#define FRF_AB_XM_MSK_STA_INTR_LBN 16 2713#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 2714#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 2715#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 2716#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 2717#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 2718#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 2719#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 2720#define FRF_AB_XM_MSK_RMTFLT_LBN 1 2721#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 2722#define FRF_AB_XM_MSK_LCLFLT_LBN 0 2723#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 2724 2725 2726/* 2727 * FR_AB_XM_FC_REG(128bit): 2728 * XGMAC flow control register 2729 */ 2730#define FR_AB_XM_FC_REG_OFST 0x00001270 2731/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2732 2733#define FRF_AB_XM_PAUSE_TIME_LBN 16 2734#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 2735#define FRF_AB_XM_RX_MAC_STAT_LBN 11 2736#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 2737#define FRF_AB_XM_TX_MAC_STAT_LBN 10 2738#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 2739#define FRF_AB_XM_MCNTL_PASS_LBN 8 2740#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 2741#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 2742#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 2743#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 2744#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 2745#define FRF_AB_XM_ZPAUSE_LBN 2 2746#define FRF_AB_XM_ZPAUSE_WIDTH 1 2747#define FRF_AB_XM_XMIT_PAUSE_LBN 1 2748#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 2749#define FRF_AB_XM_DIS_FCNTL_LBN 0 2750#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 2751 2752 2753/* 2754 * FR_AB_XM_PAUSE_TIME_REG(128bit): 2755 * XGMAC pause time register 2756 */ 2757#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 2758/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2759 2760#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 2761#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 2762#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 2763#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 2764 2765 2766/* 2767 * FR_AB_XM_TX_PARAM_REG(128bit): 2768 * XGMAC transmit parameter register 2769 */ 2770#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 2771/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2772 2773#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 2774#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 2775#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 2776#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 2777#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 2778#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 2779#define FRF_AB_XM_PAD_CHAR_LBN 0 2780#define FRF_AB_XM_PAD_CHAR_WIDTH 8 2781 2782 2783/* 2784 * FR_AB_XM_RX_PARAM_REG(128bit): 2785 * XGMAC receive parameter register 2786 */ 2787#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 2788/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2789 2790#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 2791#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 2792#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 2793#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 2794 2795 2796/* 2797 * FR_AB_XM_MGT_INT_MSK_REG(128bit): 2798 * XGMAC management interrupt mask register 2799 */ 2800#define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 2801/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2802 2803#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 2804#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 2805#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 2806#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 2807#define FRF_AB_XM_PRMBLE_ERR_LBN 2 2808#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 2809#define FRF_AB_XM_RMTFLT_LBN 1 2810#define FRF_AB_XM_RMTFLT_WIDTH 1 2811#define FRF_AB_XM_LCLFLT_LBN 0 2812#define FRF_AB_XM_LCLFLT_WIDTH 1 2813 2814 2815/* 2816 * FR_AB_XX_PWR_RST_REG(128bit): 2817 * XGXS/XAUI powerdown/reset register 2818 */ 2819#define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 2820/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2821 2822#define FRF_AB_XX_PWRDND_SIG_LBN 31 2823#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 2824#define FRF_AB_XX_PWRDNC_SIG_LBN 30 2825#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 2826#define FRF_AB_XX_PWRDNB_SIG_LBN 29 2827#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 2828#define FRF_AB_XX_PWRDNA_SIG_LBN 28 2829#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 2830#define FRF_AB_XX_SIM_MODE_LBN 27 2831#define FRF_AB_XX_SIM_MODE_WIDTH 1 2832#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 2833#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 2834#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 2835#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 2836#define FRF_AB_XX_RESETD_SIG_LBN 23 2837#define FRF_AB_XX_RESETD_SIG_WIDTH 1 2838#define FRF_AB_XX_RESETC_SIG_LBN 22 2839#define FRF_AB_XX_RESETC_SIG_WIDTH 1 2840#define FRF_AB_XX_RESETB_SIG_LBN 21 2841#define FRF_AB_XX_RESETB_SIG_WIDTH 1 2842#define FRF_AB_XX_RESETA_SIG_LBN 20 2843#define FRF_AB_XX_RESETA_SIG_WIDTH 1 2844#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 2845#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 2846#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 2847#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 2848#define FRF_AB_XX_SD_RST_ACT_LBN 16 2849#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 2850#define FRF_AB_XX_PWRDND_EN_LBN 15 2851#define FRF_AB_XX_PWRDND_EN_WIDTH 1 2852#define FRF_AB_XX_PWRDNC_EN_LBN 14 2853#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 2854#define FRF_AB_XX_PWRDNB_EN_LBN 13 2855#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 2856#define FRF_AB_XX_PWRDNA_EN_LBN 12 2857#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2858#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2859#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2860#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2861#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2862#define FRF_AB_XX_RESETD_EN_LBN 7 2863#define FRF_AB_XX_RESETD_EN_WIDTH 1 2864#define FRF_AB_XX_RESETC_EN_LBN 6 2865#define FRF_AB_XX_RESETC_EN_WIDTH 1 2866#define FRF_AB_XX_RESETB_EN_LBN 5 2867#define FRF_AB_XX_RESETB_EN_WIDTH 1 2868#define FRF_AB_XX_RESETA_EN_LBN 4 2869#define FRF_AB_XX_RESETA_EN_WIDTH 1 2870#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2871#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2872#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2873#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2874#define FRF_AB_XX_RST_XX_EN_LBN 0 2875#define FRF_AB_XX_RST_XX_EN_WIDTH 1 2876 2877 2878/* 2879 * FR_AB_XX_SD_CTL_REG(128bit): 2880 * XGXS/XAUI powerdown/reset control register 2881 */ 2882#define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 2883/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2884 2885#define FRF_AB_XX_TERMADJ1_LBN 17 2886#define FRF_AB_XX_TERMADJ1_WIDTH 1 2887#define FRF_AB_XX_TERMADJ0_LBN 16 2888#define FRF_AB_XX_TERMADJ0_WIDTH 1 2889#define FRF_AB_XX_HIDRVD_LBN 15 2890#define FRF_AB_XX_HIDRVD_WIDTH 1 2891#define FRF_AB_XX_LODRVD_LBN 14 2892#define FRF_AB_XX_LODRVD_WIDTH 1 2893#define FRF_AB_XX_HIDRVC_LBN 13 2894#define FRF_AB_XX_HIDRVC_WIDTH 1 2895#define FRF_AB_XX_LODRVC_LBN 12 2896#define FRF_AB_XX_LODRVC_WIDTH 1 2897#define FRF_AB_XX_HIDRVB_LBN 11 2898#define FRF_AB_XX_HIDRVB_WIDTH 1 2899#define FRF_AB_XX_LODRVB_LBN 10 2900#define FRF_AB_XX_LODRVB_WIDTH 1 2901#define FRF_AB_XX_HIDRVA_LBN 9 2902#define FRF_AB_XX_HIDRVA_WIDTH 1 2903#define FRF_AB_XX_LODRVA_LBN 8 2904#define FRF_AB_XX_LODRVA_WIDTH 1 2905#define FRF_AB_XX_LPBKD_LBN 3 2906#define FRF_AB_XX_LPBKD_WIDTH 1 2907#define FRF_AB_XX_LPBKC_LBN 2 2908#define FRF_AB_XX_LPBKC_WIDTH 1 2909#define FRF_AB_XX_LPBKB_LBN 1 2910#define FRF_AB_XX_LPBKB_WIDTH 1 2911#define FRF_AB_XX_LPBKA_LBN 0 2912#define FRF_AB_XX_LPBKA_WIDTH 1 2913 2914 2915/* 2916 * FR_AB_XX_TXDRV_CTL_REG(128bit): 2917 * XAUI SerDes transmit drive control register 2918 */ 2919#define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 2920/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2921 2922#define FRF_AB_XX_DEQD_LBN 28 2923#define FRF_AB_XX_DEQD_WIDTH 4 2924#define FRF_AB_XX_DEQC_LBN 24 2925#define FRF_AB_XX_DEQC_WIDTH 4 2926#define FRF_AB_XX_DEQB_LBN 20 2927#define FRF_AB_XX_DEQB_WIDTH 4 2928#define FRF_AB_XX_DEQA_LBN 16 2929#define FRF_AB_XX_DEQA_WIDTH 4 2930#define FRF_AB_XX_DTXD_LBN 12 2931#define FRF_AB_XX_DTXD_WIDTH 4 2932#define FRF_AB_XX_DTXC_LBN 8 2933#define FRF_AB_XX_DTXC_WIDTH 4 2934#define FRF_AB_XX_DTXB_LBN 4 2935#define FRF_AB_XX_DTXB_WIDTH 4 2936#define FRF_AB_XX_DTXA_LBN 0 2937#define FRF_AB_XX_DTXA_WIDTH 4 2938 2939 2940/* 2941 * FR_AB_XX_PRBS_CTL_REG(128bit): 2942 * documentation to be written for sum_XX_PRBS_CTL_REG 2943 */ 2944#define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 2945/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2946 2947#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2948#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2949#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2950#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2951#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2952#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2953#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2954#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2955#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2956#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2957#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2958#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2959#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2960#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2961#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2962#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2963#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2964#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2965#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2966#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2967#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2968#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2969#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2970#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2971#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2972#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2973#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2974#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2975#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2976#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2977#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2978#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2979#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2980#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2981#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2982#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2983#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2984#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2985#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 2986#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 2987#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 2988#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 2989#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 2990#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 2991#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 2992#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 2993#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 2994#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 2995 2996 2997/* 2998 * FR_AB_XX_PRBS_CHK_REG(128bit): 2999 * documentation to be written for sum_XX_PRBS_CHK_REG 3000 */ 3001#define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 3002/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3003 3004#define FRF_AB_XX_REV_LB_EN_LBN 16 3005#define FRF_AB_XX_REV_LB_EN_WIDTH 1 3006#define FRF_AB_XX_CH3_DEG_DET_LBN 15 3007#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 3008#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 3009#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 3010#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 3011#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 3012#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 3013#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 3014#define FRF_AB_XX_CH2_DEG_DET_LBN 11 3015#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 3016#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 3017#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 3018#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 3019#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 3020#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 3021#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 3022#define FRF_AB_XX_CH1_DEG_DET_LBN 7 3023#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 3024#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 3025#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 3026#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 3027#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 3028#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 3029#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 3030#define FRF_AB_XX_CH0_DEG_DET_LBN 3 3031#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 3032#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 3033#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 3034#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 3035#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 3036#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 3037#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 3038 3039 3040/* 3041 * FR_AB_XX_PRBS_ERR_REG(128bit): 3042 * documentation to be written for sum_XX_PRBS_ERR_REG 3043 */ 3044#define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 3045/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3046 3047#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 3048#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 3049#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 3050#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 3051#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 3052#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 3053#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 3054#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 3055 3056 3057/* 3058 * FR_AB_XX_CORE_STAT_REG(128bit): 3059 * XAUI XGXS core status register 3060 */ 3061#define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 3062/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3063 3064#define FRF_AB_XX_FORCE_SIG3_LBN 31 3065#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 3066#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 3067#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 3068#define FRF_AB_XX_FORCE_SIG2_LBN 29 3069#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 3070#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 3071#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 3072#define FRF_AB_XX_FORCE_SIG1_LBN 27 3073#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 3074#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 3075#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 3076#define FRF_AB_XX_FORCE_SIG0_LBN 25 3077#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 3078#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 3079#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 3080#define FRF_AB_XX_XGXS_LB_EN_LBN 23 3081#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 3082#define FRF_AB_XX_XGMII_LB_EN_LBN 22 3083#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 3084#define FRF_AB_XX_MATCH_FAULT_LBN 21 3085#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 3086#define FRF_AB_XX_ALIGN_DONE_LBN 20 3087#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 3088#define FRF_AB_XX_SYNC_STAT3_LBN 19 3089#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 3090#define FRF_AB_XX_SYNC_STAT2_LBN 18 3091#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 3092#define FRF_AB_XX_SYNC_STAT1_LBN 17 3093#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 3094#define FRF_AB_XX_SYNC_STAT0_LBN 16 3095#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 3096#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 3097#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 3098#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 3099#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 3100#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 3101#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 3102#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 3103#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 3104#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 3105#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 3106#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 3107#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 3108#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 3109#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 3110#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 3111#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 3112#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 3113#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 3114#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 3115#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 3116#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 3117#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 3118#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 3119#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 3120#define FRF_AB_XX_DISPERR_CH3_LBN 3 3121#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 3122#define FRF_AB_XX_DISPERR_CH2_LBN 2 3123#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 3124#define FRF_AB_XX_DISPERR_CH1_LBN 1 3125#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 3126#define FRF_AB_XX_DISPERR_CH0_LBN 0 3127#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 3128 3129 3130/* 3131 * FR_AA_RX_DESC_PTR_TBL_KER(128bit): 3132 * Receive descriptor pointer table 3133 */ 3134#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 3135/* falcona0=net_func_bar2 */ 3136#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 3137#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 3138/* 3139 * FR_AZ_RX_DESC_PTR_TBL(128bit): 3140 * Receive descriptor pointer table 3141 */ 3142#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 3143/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3144#define FR_AZ_RX_DESC_PTR_TBL_STEP 16 3145#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 3146#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 3147 3148#define FRF_CZ_RX_HDR_SPLIT_LBN 90 3149#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 3150#define FRF_AZ_RX_RESET_LBN 89 3151#define FRF_AZ_RX_RESET_WIDTH 1 3152#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 3153#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 3154#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 3155#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 3156#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 3157#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 3158#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 3159#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 3160#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 3161#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 3162#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 3163#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 3164#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 3165#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 3166#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 3167#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 3168#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 3169#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 3170#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 3171#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 3172#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 3173#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 3174#define FFE_AZ_RX_DESCQ_SIZE_4K 3 3175#define FFE_AZ_RX_DESCQ_SIZE_2K 2 3176#define FFE_AZ_RX_DESCQ_SIZE_1K 1 3177#define FFE_AZ_RX_DESCQ_SIZE_512 0 3178#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 3179#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 3180#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 3181#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 3182#define FRF_AZ_RX_DESCQ_EN_LBN 0 3183#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 3184 3185 3186/* 3187 * FR_AA_TX_DESC_PTR_TBL_KER(128bit): 3188 * Transmit descriptor pointer 3189 */ 3190#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 3191/* falcona0=net_func_bar2 */ 3192#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 3193#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 3194/* 3195 * FR_AZ_TX_DESC_PTR_TBL(128bit): 3196 * Transmit descriptor pointer 3197 */ 3198#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 3199/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3200#define FR_AZ_TX_DESC_PTR_TBL_STEP 16 3201#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 3202#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 3203 3204#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 3205#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 3206#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 3207#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 3208#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 3209#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 3210#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 3211#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 3212#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 3213#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 3214#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 3215#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 3216#define FRF_AZ_TX_DESCQ_EN_LBN 88 3217#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 3218#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 3219#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 3220#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 3221#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 3222#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 3223#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 3224#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 3225#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 3226#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 3227#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 3228#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 3229#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 3230#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 3231#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 3232#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 3233#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 3234#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 3235#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 3236#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 3237#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 3238#define FFE_AZ_TX_DESCQ_SIZE_4K 3 3239#define FFE_AZ_TX_DESCQ_SIZE_2K 2 3240#define FFE_AZ_TX_DESCQ_SIZE_1K 1 3241#define FFE_AZ_TX_DESCQ_SIZE_512 0 3242#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 3243#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 3244#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 3245#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 3246 3247 3248/* 3249 * FR_AA_EVQ_PTR_TBL_KER(128bit): 3250 * Event queue pointer table 3251 */ 3252#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 3253/* falcona0=net_func_bar2 */ 3254#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 3255#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 3256/* 3257 * FR_AZ_EVQ_PTR_TBL(128bit): 3258 * Event queue pointer table 3259 */ 3260#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 3261/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3262#define FR_AZ_EVQ_PTR_TBL_STEP 16 3263#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 3264#define FR_AB_EVQ_PTR_TBL_ROWS 4096 3265 3266#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 3267#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 3268#define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 3269#define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 3270#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 3271#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 3272#define FRF_AZ_EVQ_EN_LBN 23 3273#define FRF_AZ_EVQ_EN_WIDTH 1 3274#define FRF_AZ_EVQ_SIZE_LBN 20 3275#define FRF_AZ_EVQ_SIZE_WIDTH 3 3276#define FFE_AZ_EVQ_SIZE_32K 6 3277#define FFE_AZ_EVQ_SIZE_16K 5 3278#define FFE_AZ_EVQ_SIZE_8K 4 3279#define FFE_AZ_EVQ_SIZE_4K 3 3280#define FFE_AZ_EVQ_SIZE_2K 2 3281#define FFE_AZ_EVQ_SIZE_1K 1 3282#define FFE_AZ_EVQ_SIZE_512 0 3283#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 3284#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 3285 3286 3287/* 3288 * FR_AA_BUF_HALF_TBL_KER(64bit): 3289 * Buffer table in half buffer table mode direct access by driver 3290 */ 3291#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 3292/* falcona0=net_func_bar2 */ 3293#define FR_AA_BUF_HALF_TBL_KER_STEP 8 3294#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 3295/* 3296 * FR_AZ_BUF_HALF_TBL(64bit): 3297 * Buffer table in half buffer table mode direct access by driver 3298 */ 3299#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 3300/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3301#define FR_AZ_BUF_HALF_TBL_STEP 8 3302#define FR_CZ_BUF_HALF_TBL_ROWS 147456 3303#define FR_AB_BUF_HALF_TBL_ROWS 524288 3304 3305#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 3306#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 3307#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 3308#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 3309#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 3310#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 3311#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 3312#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 3313 3314 3315/* 3316 * FR_AA_BUF_FULL_TBL_KER(64bit): 3317 * Buffer table in full buffer table mode direct access by driver 3318 */ 3319#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 3320/* falcona0=net_func_bar2 */ 3321#define FR_AA_BUF_FULL_TBL_KER_STEP 8 3322#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 3323/* 3324 * FR_AZ_BUF_FULL_TBL(64bit): 3325 * Buffer table in full buffer table mode direct access by driver 3326 */ 3327#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 3328/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3329#define FR_AZ_BUF_FULL_TBL_STEP 8 3330 3331#define FR_CZ_BUF_FULL_TBL_ROWS 147456 3332#define FR_AB_BUF_FULL_TBL_ROWS 917504 3333 3334#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 3335#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 3336#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 3337#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 3338#define FRF_AZ_BUF_ADR_REGION_LBN 48 3339#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 3340#define FFE_AZ_BUF_ADR_REGN3 3 3341#define FFE_AZ_BUF_ADR_REGN2 2 3342#define FFE_AZ_BUF_ADR_REGN1 1 3343#define FFE_AZ_BUF_ADR_REGN0 0 3344#define FRF_AZ_BUF_ADR_FBUF_LBN 14 3345#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 3346#define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 3347#define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 3348#define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 3349#define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 3350#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 3351#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 3352 3353 3354/* 3355 * FR_AZ_RX_FILTER_TBL0(128bit): 3356 * TCP/IPv4 Receive filter table 3357 */ 3358#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 3359/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3360#define FR_AZ_RX_FILTER_TBL0_STEP 32 3361#define FR_AZ_RX_FILTER_TBL0_ROWS 8192 3362/* 3363 * FR_AB_RX_FILTER_TBL1(128bit): 3364 * TCP/IPv4 Receive filter table 3365 */ 3366#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 3367/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3368#define FR_AB_RX_FILTER_TBL1_STEP 32 3369#define FR_AB_RX_FILTER_TBL1_ROWS 8192 3370 3371#define FRF_BZ_RSS_EN_LBN 110 3372#define FRF_BZ_RSS_EN_WIDTH 1 3373#define FRF_BZ_SCATTER_EN_LBN 109 3374#define FRF_BZ_SCATTER_EN_WIDTH 1 3375#define FRF_AZ_TCP_UDP_LBN 108 3376#define FRF_AZ_TCP_UDP_WIDTH 1 3377#define FRF_AZ_RXQ_ID_LBN 96 3378#define FRF_AZ_RXQ_ID_WIDTH 12 3379#define FRF_AZ_DEST_IP_LBN 64 3380#define FRF_AZ_DEST_IP_WIDTH 32 3381#define FRF_AZ_DEST_PORT_TCP_LBN 48 3382#define FRF_AZ_DEST_PORT_TCP_WIDTH 16 3383#define FRF_AZ_SRC_IP_LBN 16 3384#define FRF_AZ_SRC_IP_WIDTH 32 3385#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 3386#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 3387 3388 3389/* 3390 * FR_CZ_RX_MAC_FILTER_TBL0(128bit): 3391 * Receive Ethernet filter table 3392 */ 3393#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 3394/* sienaa0=net_func_bar2 */ 3395#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 3396#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 3397 3398#define FRF_CZ_RMFT_RSS_EN_LBN 75 3399#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 3400#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 3401#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 3402#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 3403#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 3404#define FRF_CZ_RMFT_RXQ_ID_LBN 61 3405#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 3406#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 3407#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 3408#define FRF_CZ_RMFT_DEST_MAC_LBN 12 3409#define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 3410#define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 3411#define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 3412#define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 3413#define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 3414#define FRF_CZ_RMFT_VLAN_ID_LBN 0 3415#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 3416 3417 3418/* 3419 * FR_AZ_TIMER_TBL(128bit): 3420 * Timer table 3421 */ 3422#define FR_AZ_TIMER_TBL_OFST 0x00f70000 3423/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3424#define FR_AZ_TIMER_TBL_STEP 16 3425#define FR_CZ_TIMER_TBL_ROWS 1024 3426#define FR_AB_TIMER_TBL_ROWS 4096 3427 3428#define FRF_CZ_TIMER_Q_EN_LBN 33 3429#define FRF_CZ_TIMER_Q_EN_WIDTH 1 3430#define FRF_CZ_INT_ARMD_LBN 32 3431#define FRF_CZ_INT_ARMD_WIDTH 1 3432#define FRF_CZ_INT_PEND_LBN 31 3433#define FRF_CZ_INT_PEND_WIDTH 1 3434#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 3435#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 3436#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 3437#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 3438#define FRF_CZ_TIMER_MODE_LBN 14 3439#define FRF_CZ_TIMER_MODE_WIDTH 2 3440#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 3441#define FFE_CZ_TIMER_MODE_TRIG_START 2 3442#define FFE_CZ_TIMER_MODE_IMMED_START 1 3443#define FFE_CZ_TIMER_MODE_DIS 0 3444#define FRF_AB_TIMER_MODE_LBN 12 3445#define FRF_AB_TIMER_MODE_WIDTH 2 3446#define FFE_AB_TIMER_MODE_INT_HLDOFF 2 3447#define FFE_AB_TIMER_MODE_TRIG_START 2 3448#define FFE_AB_TIMER_MODE_IMMED_START 1 3449#define FFE_AB_TIMER_MODE_DIS 0 3450#define FRF_CZ_TIMER_VAL_LBN 0 3451#define FRF_CZ_TIMER_VAL_WIDTH 14 3452#define FRF_AB_TIMER_VAL_LBN 0 3453#define FRF_AB_TIMER_VAL_WIDTH 12 3454 3455 3456/* 3457 * FR_BZ_TX_PACE_TBL(128bit): 3458 * Transmit pacing table 3459 */ 3460#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 3461/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ 3462#define FR_AZ_TX_PACE_TBL_STEP 16 3463#define FR_CZ_TX_PACE_TBL_ROWS 1024 3464#define FR_BB_TX_PACE_TBL_ROWS 4096 3465/* 3466 * FR_AA_TX_PACE_TBL(128bit): 3467 * Transmit pacing table 3468 */ 3469#define FR_AA_TX_PACE_TBL_OFST 0x00f80040 3470/* falcona0=char_func_bar0 */ 3471/* FR_AZ_TX_PACE_TBL_STEP 16 */ 3472#define FR_AA_TX_PACE_TBL_ROWS 4092 3473 3474#define FRF_AZ_TX_PACE_LBN 0 3475#define FRF_AZ_TX_PACE_WIDTH 5 3476 3477 3478/* 3479 * FR_BZ_RX_INDIRECTION_TBL(7bit): 3480 * RX Indirection Table 3481 */ 3482#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 3483/* falconb0,sienaa0=net_func_bar2 */ 3484#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 3485#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 3486 3487#define FRF_BZ_IT_QUEUE_LBN 0 3488#define FRF_BZ_IT_QUEUE_WIDTH 6 3489 3490 3491/* 3492 * FR_CZ_TX_FILTER_TBL0(128bit): 3493 * TCP/IPv4 Transmit filter table 3494 */ 3495#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 3496/* sienaa0=net_func_bar2 */ 3497#define FR_CZ_TX_FILTER_TBL0_STEP 16 3498#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 3499 3500#define FRF_CZ_TIFT_TCP_UDP_LBN 108 3501#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 3502#define FRF_CZ_TIFT_TXQ_ID_LBN 96 3503#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 3504#define FRF_CZ_TIFT_DEST_IP_LBN 64 3505#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 3506#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 3507#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 3508#define FRF_CZ_TIFT_SRC_IP_LBN 16 3509#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 3510#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 3511#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 3512 3513 3514/* 3515 * FR_CZ_TX_MAC_FILTER_TBL0(128bit): 3516 * Transmit Ethernet filter table 3517 */ 3518#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 3519/* sienaa0=net_func_bar2 */ 3520#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 3521#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 3522 3523#define FRF_CZ_TMFT_TXQ_ID_LBN 61 3524#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 3525#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 3526#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 3527#define FRF_CZ_TMFT_SRC_MAC_LBN 12 3528#define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 3529#define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 3530#define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 3531#define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 3532#define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 3533#define FRF_CZ_TMFT_VLAN_ID_LBN 0 3534#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 3535 3536 3537/* 3538 * FR_CZ_MC_TREG_SMEM(32bit): 3539 * MC Shared Memory 3540 */ 3541#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 3542/* sienaa0=net_func_bar2 */ 3543#define FR_CZ_MC_TREG_SMEM_STEP 4 3544#define FR_CZ_MC_TREG_SMEM_ROWS 512 3545 3546#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 3547#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 3548 3549 3550/* 3551 * FR_BB_MSIX_VECTOR_TABLE(128bit): 3552 * MSIX Vector Table 3553 */ 3554#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 3555/* falconb0=net_func_bar2 */ 3556#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 3557#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 3558/* 3559 * FR_CZ_MSIX_VECTOR_TABLE(128bit): 3560 * MSIX Vector Table 3561 */ 3562#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 3563/* sienaa0=pci_f0_bar4 */ 3564/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 3565#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 3566 3567#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 3568#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 3569#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 3570#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 3571#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 3572#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 3573#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 3574#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 3575#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 3576#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 3577 3578 3579/* 3580 * FR_BB_MSIX_PBA_TABLE(32bit): 3581 * MSIX Pending Bit Array 3582 */ 3583#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 3584/* falconb0=net_func_bar2 */ 3585#define FR_BZ_MSIX_PBA_TABLE_STEP 4 3586#define FR_BB_MSIX_PBA_TABLE_ROWS 2 3587/* 3588 * FR_CZ_MSIX_PBA_TABLE(32bit): 3589 * MSIX Pending Bit Array 3590 */ 3591#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 3592/* sienaa0=pci_f0_bar4 */ 3593/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 3594#define FR_CZ_MSIX_PBA_TABLE_ROWS 32 3595 3596#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 3597#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 3598 3599 3600/* 3601 * FR_AZ_SRM_DBG_REG(64bit): 3602 * SRAM debug access 3603 */ 3604#define FR_AZ_SRM_DBG_REG_OFST 0x03000000 3605/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3606#define FR_AZ_SRM_DBG_REG_STEP 8 3607 3608#define FR_CZ_SRM_DBG_REG_ROWS 262144 3609#define FR_AB_SRM_DBG_REG_ROWS 2097152 3610 3611#define FRF_AZ_SRM_DBG_LBN 0 3612#define FRF_AZ_SRM_DBG_WIDTH 64 3613#define FRF_AZ_SRM_DBG_DW0_LBN 0 3614#define FRF_AZ_SRM_DBG_DW0_WIDTH 32 3615#define FRF_AZ_SRM_DBG_DW1_LBN 32 3616#define FRF_AZ_SRM_DBG_DW1_WIDTH 32 3617 3618 3619/* 3620 * FR_AA_INT_ACK_CHAR(32bit): 3621 * CHAR interrupt acknowledge register 3622 */ 3623#define FR_AA_INT_ACK_CHAR_OFST 0x00000060 3624/* falcona0=char_func_bar0 */ 3625 3626#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 3627#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 3628 3629 3630/* FS_DRIVER_EV */ 3631#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 3632#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 3633#define FSE_AZ_TX_DSC_ERROR_EV 15 3634#define FSE_AZ_RX_DSC_ERROR_EV 14 3635#define FSE_AZ_RX_RECOVER_EV 11 3636#define FSE_AZ_TIMER_EV 10 3637#define FSE_AZ_TX_PKT_NON_TCP_UDP 9 3638#define FSE_AZ_WAKE_UP_EV 6 3639#define FSE_AZ_SRM_UPD_DONE_EV 5 3640#define FSE_AZ_EVQ_NOT_EN_EV 3 3641#define FSE_AZ_EVQ_INIT_DONE_EV 2 3642#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 3643#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 3644#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 3645#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 3646 3647 3648/* FS_EVENT_ENTRY */ 3649#define FSF_AZ_EV_CODE_LBN 60 3650#define FSF_AZ_EV_CODE_WIDTH 4 3651#define FSE_AZ_EV_CODE_USER_EV 8 3652#define FSE_AZ_EV_CODE_DRV_GEN_EV 7 3653#define FSE_AZ_EV_CODE_GLOBAL_EV 6 3654#define FSE_AZ_EV_CODE_DRIVER_EV 5 3655#define FSE_AZ_EV_CODE_TX_EV 2 3656#define FSE_AZ_EV_CODE_RX_EV 0 3657#define FSF_AZ_EV_DATA_LBN 0 3658#define FSF_AZ_EV_DATA_WIDTH 60 3659#define FSF_AZ_EV_DATA_DW0_LBN 0 3660#define FSF_AZ_EV_DATA_DW0_WIDTH 32 3661#define FSF_AZ_EV_DATA_DW1_LBN 32 3662#define FSF_AZ_EV_DATA_DW1_WIDTH 28 3663 3664 3665/* FS_GLOBAL_EV */ 3666#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 3667#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 3668#define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 3669#define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 3670#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 3671#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 3672#define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 3673#define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 3674#define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 3675#define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 3676 3677 3678/* FS_RX_EV */ 3679#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 3680#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 3681#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 3682#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 3683#define FSF_AZ_RX_EV_PKT_OK_LBN 56 3684#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 3685#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 3686#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 3687#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 3688#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3689#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 3690#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 3691#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 3692#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 3693#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 3694#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 3695#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 3696#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 3697#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 3698#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 3699#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 3700#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 3701#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 3702#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 3703#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 3704#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 3705#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 3706#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 3707#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 3708#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 3709#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 3710#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 3711#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 3712#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 3713#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 3714#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 3715#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 3716#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 3717#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 3718#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 3719#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 3720#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 3721#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 3722#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 3723#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 3724#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 3725#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 3726#define FSF_AZ_RX_EV_Q_LABEL_LBN 32 3727#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 3728#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 3729#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 3730#define FSF_AZ_RX_EV_PORT_LBN 30 3731#define FSF_AZ_RX_EV_PORT_WIDTH 1 3732#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 3733#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 3734#define FSF_AZ_RX_EV_SOP_LBN 15 3735#define FSF_AZ_RX_EV_SOP_WIDTH 1 3736#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 3737#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 3738#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 3739#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 3740#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 3741#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 3742#define FSF_AZ_RX_EV_DESC_PTR_LBN 0 3743#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 3744 3745 3746/* FS_RX_KER_DESC */ 3747#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 3748#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 3749#define FSF_AZ_RX_KER_BUF_REGION_LBN 46 3750#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 3751#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 3752#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 3753#define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 3754#define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 3755#define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 3756#define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 3757 3758 3759/* FS_RX_USER_DESC */ 3760#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 3761#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 3762#define FSF_AZ_RX_USER_BUF_ID_LBN 0 3763#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 3764 3765 3766/* FS_TX_EV */ 3767#define FSF_AZ_TX_EV_PKT_ERR_LBN 38 3768#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 3769#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 3770#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 3771#define FSF_AZ_TX_EV_Q_LABEL_LBN 32 3772#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 3773#define FSF_AZ_TX_EV_PORT_LBN 16 3774#define FSF_AZ_TX_EV_PORT_WIDTH 1 3775#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 3776#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 3777#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 3778#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3779#define FSF_AZ_TX_EV_COMP_LBN 12 3780#define FSF_AZ_TX_EV_COMP_WIDTH 1 3781#define FSF_AZ_TX_EV_DESC_PTR_LBN 0 3782#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 3783 3784 3785/* FS_TX_KER_DESC */ 3786#define FSF_AZ_TX_KER_CONT_LBN 62 3787#define FSF_AZ_TX_KER_CONT_WIDTH 1 3788#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 3789#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 3790#define FSF_AZ_TX_KER_BUF_REGION_LBN 46 3791#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 3792#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 3793#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 3794#define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 3795#define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 3796#define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 3797#define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 3798 3799 3800/* FS_TX_USER_DESC */ 3801#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 3802#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 3803#define FSF_AZ_TX_USER_CONT_LBN 46 3804#define FSF_AZ_TX_USER_CONT_WIDTH 1 3805#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 3806#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 3807#define FSF_AZ_TX_USER_BUF_ID_LBN 13 3808#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 3809#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 3810#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 3811 3812 3813/* FS_USER_EV */ 3814#define FSF_CZ_USER_QID_LBN 32 3815#define FSF_CZ_USER_QID_WIDTH 10 3816#define FSF_CZ_USER_EV_REG_VALUE_LBN 0 3817#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 3818 3819 3820/* FS_NET_IVEC */ 3821#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 3822#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 3823#define FSF_AZ_NET_IVEC_INT_Q_LBN 40 3824#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 3825#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 3826#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 3827#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 3828#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 3829#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 3830#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 3831 3832 3833/* DRIVER_EV */ 3834/* Sub-fields of an RX flush completion event */ 3835#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 3836#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 3837#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 3838#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 3839 3840 3841#ifdef __cplusplus 3842} 3843#endif 3844 3845 3846 3847 3848#endif /* _SYS_EFX_REGS_H */ 3849