efx_regs.h revision 227569
1227569Sphilip/*- 2227569Sphilip * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3227569Sphilip * 4227569Sphilip * Redistribution and use in source and binary forms, with or without 5227569Sphilip * modification, are permitted provided that the following conditions 6227569Sphilip * are met: 7227569Sphilip * 1. Redistributions of source code must retain the above copyright 8227569Sphilip * notice, this list of conditions and the following disclaimer. 9227569Sphilip * 2. Redistributions in binary form must reproduce the above copyright 10227569Sphilip * notice, this list of conditions and the following disclaimer in the 11227569Sphilip * documentation and/or other materials provided with the distribution. 12227569Sphilip * 13227569Sphilip * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14227569Sphilip * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15227569Sphilip * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16227569Sphilip * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17227569Sphilip * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18227569Sphilip * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19227569Sphilip * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20227569Sphilip * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21227569Sphilip * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22227569Sphilip * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23227569Sphilip * SUCH DAMAGE. 24227569Sphilip */ 25227569Sphilip 26227569Sphilip#ifndef _SYS_EFX_REGS_H 27227569Sphilip#define _SYS_EFX_REGS_H 28227569Sphilip 29227569Sphilip 30227569Sphilip#ifdef __cplusplus 31227569Sphilipextern "C" { 32227569Sphilip#endif 33227569Sphilip 34227569Sphilip 35227569Sphilip/* 36227569Sphilip * FR_AB_EE_VPD_CFG0_REG_SF(128bit): 37227569Sphilip * SPI/VPD configuration register 0 38227569Sphilip */ 39227569Sphilip#define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 40227569Sphilip/* falcona0,falconb0=eeprom_flash */ 41227569Sphilip/* 42227569Sphilip * FR_AB_EE_VPD_CFG0_REG(128bit): 43227569Sphilip * SPI/VPD configuration register 0 44227569Sphilip */ 45227569Sphilip#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 46227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 47227569Sphilip 48227569Sphilip#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 49227569Sphilip#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 50227569Sphilip#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 51227569Sphilip#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 52227569Sphilip#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 53227569Sphilip#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 54227569Sphilip#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 55227569Sphilip#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 56227569Sphilip#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 57227569Sphilip#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 58227569Sphilip#define FRF_AB_EE_VPDW_LENGTH_LBN 80 59227569Sphilip#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 60227569Sphilip#define FRF_AB_EE_VPDW_BASE_LBN 64 61227569Sphilip#define FRF_AB_EE_VPDW_BASE_WIDTH 15 62227569Sphilip#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 63227569Sphilip#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 64227569Sphilip#define FRF_AB_EE_VPD_BASE_LBN 32 65227569Sphilip#define FRF_AB_EE_VPD_BASE_WIDTH 24 66227569Sphilip#define FRF_AB_EE_VPD_LENGTH_LBN 16 67227569Sphilip#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 68227569Sphilip#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 69227569Sphilip#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 70227569Sphilip#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 71227569Sphilip#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 72227569Sphilip#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 73227569Sphilip#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 74227569Sphilip#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 75227569Sphilip#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 76227569Sphilip#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 77227569Sphilip#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 78227569Sphilip#define FRF_AB_EE_VPD_EN_LBN 0 79227569Sphilip#define FRF_AB_EE_VPD_EN_WIDTH 1 80227569Sphilip 81227569Sphilip 82227569Sphilip/* 83227569Sphilip * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): 84227569Sphilip * PCIE SerDes control register 0 to 3 85227569Sphilip */ 86227569Sphilip#define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 87227569Sphilip/* falcona0,falconb0=eeprom_flash */ 88227569Sphilip/* 89227569Sphilip * FR_AB_PCIE_SD_CTL0123_REG(128bit): 90227569Sphilip * PCIE SerDes control register 0 to 3 91227569Sphilip */ 92227569Sphilip#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 93227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 94227569Sphilip 95227569Sphilip#define FRF_AB_PCIE_TESTSIG_H_LBN 96 96227569Sphilip#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 97227569Sphilip#define FRF_AB_PCIE_TESTSIG_L_LBN 64 98227569Sphilip#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 99227569Sphilip#define FRF_AB_PCIE_OFFSET_LBN 56 100227569Sphilip#define FRF_AB_PCIE_OFFSET_WIDTH 8 101227569Sphilip#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 102227569Sphilip#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 103227569Sphilip#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 104227569Sphilip#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 105227569Sphilip#define FRF_AB_PCIE_HIVMODE_H_LBN 53 106227569Sphilip#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 107227569Sphilip#define FRF_AB_PCIE_HIVMODE_L_LBN 52 108227569Sphilip#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 109227569Sphilip#define FRF_AB_PCIE_PARRESET_H_LBN 51 110227569Sphilip#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 111227569Sphilip#define FRF_AB_PCIE_PARRESET_L_LBN 50 112227569Sphilip#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 113227569Sphilip#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 114227569Sphilip#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 115227569Sphilip#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 116227569Sphilip#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 117227569Sphilip#define FRF_AB_PCIE_LPBK_LBN 40 118227569Sphilip#define FRF_AB_PCIE_LPBK_WIDTH 8 119227569Sphilip#define FRF_AB_PCIE_PARLPBK_LBN 32 120227569Sphilip#define FRF_AB_PCIE_PARLPBK_WIDTH 8 121227569Sphilip#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 122227569Sphilip#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 123227569Sphilip#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 124227569Sphilip#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 125227569Sphilip#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 126227569Sphilip#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 127227569Sphilip#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 128227569Sphilip#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 129227569Sphilip#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 130227569Sphilip#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 131227569Sphilip#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 132227569Sphilip#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 133227569Sphilip#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 134227569Sphilip#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 135227569Sphilip#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 136227569Sphilip#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 137227569Sphilip#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 138227569Sphilip#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 139227569Sphilip#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 140227569Sphilip#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 141227569Sphilip#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 142227569Sphilip#define FFE_AB_PCIE_RXEQCTL_OFF 2 143227569Sphilip#define FFE_AB_PCIE_RXEQCTL_MIN 1 144227569Sphilip#define FFE_AB_PCIE_RXEQCTL_MAX 0 145227569Sphilip#define FRF_AB_PCIE_HIDRV_LBN 8 146227569Sphilip#define FRF_AB_PCIE_HIDRV_WIDTH 8 147227569Sphilip#define FRF_AB_PCIE_LODRV_LBN 0 148227569Sphilip#define FRF_AB_PCIE_LODRV_WIDTH 8 149227569Sphilip 150227569Sphilip 151227569Sphilip/* 152227569Sphilip * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): 153227569Sphilip * PCIE SerDes control register 4 and 5 154227569Sphilip */ 155227569Sphilip#define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 156227569Sphilip/* falcona0,falconb0=eeprom_flash */ 157227569Sphilip/* 158227569Sphilip * FR_AB_PCIE_SD_CTL45_REG(128bit): 159227569Sphilip * PCIE SerDes control register 4 and 5 160227569Sphilip */ 161227569Sphilip#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 162227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 163227569Sphilip 164227569Sphilip#define FRF_AB_PCIE_DTX7_LBN 60 165227569Sphilip#define FRF_AB_PCIE_DTX7_WIDTH 4 166227569Sphilip#define FRF_AB_PCIE_DTX6_LBN 56 167227569Sphilip#define FRF_AB_PCIE_DTX6_WIDTH 4 168227569Sphilip#define FRF_AB_PCIE_DTX5_LBN 52 169227569Sphilip#define FRF_AB_PCIE_DTX5_WIDTH 4 170227569Sphilip#define FRF_AB_PCIE_DTX4_LBN 48 171227569Sphilip#define FRF_AB_PCIE_DTX4_WIDTH 4 172227569Sphilip#define FRF_AB_PCIE_DTX3_LBN 44 173227569Sphilip#define FRF_AB_PCIE_DTX3_WIDTH 4 174227569Sphilip#define FRF_AB_PCIE_DTX2_LBN 40 175227569Sphilip#define FRF_AB_PCIE_DTX2_WIDTH 4 176227569Sphilip#define FRF_AB_PCIE_DTX1_LBN 36 177227569Sphilip#define FRF_AB_PCIE_DTX1_WIDTH 4 178227569Sphilip#define FRF_AB_PCIE_DTX0_LBN 32 179227569Sphilip#define FRF_AB_PCIE_DTX0_WIDTH 4 180227569Sphilip#define FRF_AB_PCIE_DEQ7_LBN 28 181227569Sphilip#define FRF_AB_PCIE_DEQ7_WIDTH 4 182227569Sphilip#define FRF_AB_PCIE_DEQ6_LBN 24 183227569Sphilip#define FRF_AB_PCIE_DEQ6_WIDTH 4 184227569Sphilip#define FRF_AB_PCIE_DEQ5_LBN 20 185227569Sphilip#define FRF_AB_PCIE_DEQ5_WIDTH 4 186227569Sphilip#define FRF_AB_PCIE_DEQ4_LBN 16 187227569Sphilip#define FRF_AB_PCIE_DEQ4_WIDTH 4 188227569Sphilip#define FRF_AB_PCIE_DEQ3_LBN 12 189227569Sphilip#define FRF_AB_PCIE_DEQ3_WIDTH 4 190227569Sphilip#define FRF_AB_PCIE_DEQ2_LBN 8 191227569Sphilip#define FRF_AB_PCIE_DEQ2_WIDTH 4 192227569Sphilip#define FRF_AB_PCIE_DEQ1_LBN 4 193227569Sphilip#define FRF_AB_PCIE_DEQ1_WIDTH 4 194227569Sphilip#define FRF_AB_PCIE_DEQ0_LBN 0 195227569Sphilip#define FRF_AB_PCIE_DEQ0_WIDTH 4 196227569Sphilip 197227569Sphilip 198227569Sphilip/* 199227569Sphilip * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): 200227569Sphilip * PCIE PCS control and status register 201227569Sphilip */ 202227569Sphilip#define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 203227569Sphilip/* falcona0,falconb0=eeprom_flash */ 204227569Sphilip/* 205227569Sphilip * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): 206227569Sphilip * PCIE PCS control and status register 207227569Sphilip */ 208227569Sphilip#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 209227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 210227569Sphilip 211227569Sphilip#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 212227569Sphilip#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 213227569Sphilip#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 214227569Sphilip#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 215227569Sphilip#define FRF_AB_PCIE_PRBSERR_LBN 40 216227569Sphilip#define FRF_AB_PCIE_PRBSERR_WIDTH 8 217227569Sphilip#define FRF_AB_PCIE_PRBSERRH0_LBN 32 218227569Sphilip#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 219227569Sphilip#define FRF_AB_PCIE_FASTINIT_H_LBN 15 220227569Sphilip#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 221227569Sphilip#define FRF_AB_PCIE_FASTINIT_L_LBN 14 222227569Sphilip#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 223227569Sphilip#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 224227569Sphilip#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 225227569Sphilip#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 226227569Sphilip#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 227227569Sphilip#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 228227569Sphilip#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 229227569Sphilip#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 230227569Sphilip#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 231227569Sphilip#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 232227569Sphilip#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 233227569Sphilip#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 234227569Sphilip#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 235227569Sphilip#define FRF_AB_PCIE_PRBSSEL_LBN 0 236227569Sphilip#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 237227569Sphilip 238227569Sphilip 239227569Sphilip/* 240227569Sphilip * FR_AB_HW_INIT_REG_SF(128bit): 241227569Sphilip * Hardware initialization register 242227569Sphilip */ 243227569Sphilip#define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 244227569Sphilip/* falcona0,falconb0=eeprom_flash */ 245227569Sphilip/* 246227569Sphilip * FR_AZ_HW_INIT_REG(128bit): 247227569Sphilip * Hardware initialization register 248227569Sphilip */ 249227569Sphilip#define FR_AZ_HW_INIT_REG_OFST 0x000000c0 250227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 251227569Sphilip 252227569Sphilip#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 253227569Sphilip#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 254227569Sphilip#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 255227569Sphilip#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 256227569Sphilip#define FRF_CZ_TX_MRG_TAGS_LBN 120 257227569Sphilip#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 258227569Sphilip#define FRF_AZ_TRGT_MASK_ALL_LBN 100 259227569Sphilip#define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 260227569Sphilip#define FRF_AZ_DOORBELL_DROP_LBN 92 261227569Sphilip#define FRF_AZ_DOORBELL_DROP_WIDTH 8 262227569Sphilip#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 263227569Sphilip#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 264227569Sphilip#define FRF_AB_PE_EIDLE_DIS_LBN 75 265227569Sphilip#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 266227569Sphilip#define FRF_AZ_FC_BLOCKING_EN_LBN 45 267227569Sphilip#define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 268227569Sphilip#define FRF_AZ_B2B_REQ_EN_LBN 44 269227569Sphilip#define FRF_AZ_B2B_REQ_EN_WIDTH 1 270227569Sphilip#define FRF_AZ_POST_WR_MASK_LBN 40 271227569Sphilip#define FRF_AZ_POST_WR_MASK_WIDTH 4 272227569Sphilip#define FRF_AZ_TLP_TC_LBN 34 273227569Sphilip#define FRF_AZ_TLP_TC_WIDTH 3 274227569Sphilip#define FRF_AZ_TLP_ATTR_LBN 32 275227569Sphilip#define FRF_AZ_TLP_ATTR_WIDTH 2 276227569Sphilip#define FRF_AB_INTB_VEC_LBN 24 277227569Sphilip#define FRF_AB_INTB_VEC_WIDTH 5 278227569Sphilip#define FRF_AB_INTA_VEC_LBN 16 279227569Sphilip#define FRF_AB_INTA_VEC_WIDTH 5 280227569Sphilip#define FRF_AZ_WD_TIMER_LBN 8 281227569Sphilip#define FRF_AZ_WD_TIMER_WIDTH 8 282227569Sphilip#define FRF_AZ_US_DISABLE_LBN 5 283227569Sphilip#define FRF_AZ_US_DISABLE_WIDTH 1 284227569Sphilip#define FRF_AZ_TLP_EP_LBN 4 285227569Sphilip#define FRF_AZ_TLP_EP_WIDTH 1 286227569Sphilip#define FRF_AZ_ATTR_SEL_LBN 3 287227569Sphilip#define FRF_AZ_ATTR_SEL_WIDTH 1 288227569Sphilip#define FRF_AZ_TD_SEL_LBN 1 289227569Sphilip#define FRF_AZ_TD_SEL_WIDTH 1 290227569Sphilip#define FRF_AZ_TLP_TD_LBN 0 291227569Sphilip#define FRF_AZ_TLP_TD_WIDTH 1 292227569Sphilip 293227569Sphilip 294227569Sphilip/* 295227569Sphilip * FR_AB_NIC_STAT_REG_SF(128bit): 296227569Sphilip * NIC status register 297227569Sphilip */ 298227569Sphilip#define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 299227569Sphilip/* falcona0,falconb0=eeprom_flash */ 300227569Sphilip/* 301227569Sphilip * FR_AB_NIC_STAT_REG(128bit): 302227569Sphilip * NIC status register 303227569Sphilip */ 304227569Sphilip#define FR_AB_NIC_STAT_REG_OFST 0x00000200 305227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 306227569Sphilip 307227569Sphilip#define FRF_BB_AER_DIS_LBN 34 308227569Sphilip#define FRF_BB_AER_DIS_WIDTH 1 309227569Sphilip#define FRF_BB_EE_STRAP_EN_LBN 31 310227569Sphilip#define FRF_BB_EE_STRAP_EN_WIDTH 1 311227569Sphilip#define FRF_BB_EE_STRAP_LBN 24 312227569Sphilip#define FRF_BB_EE_STRAP_WIDTH 4 313227569Sphilip#define FRF_BB_REVISION_ID_LBN 17 314227569Sphilip#define FRF_BB_REVISION_ID_WIDTH 7 315227569Sphilip#define FRF_AB_ONCHIP_SRAM_LBN 16 316227569Sphilip#define FRF_AB_ONCHIP_SRAM_WIDTH 1 317227569Sphilip#define FRF_AB_SF_PRST_LBN 9 318227569Sphilip#define FRF_AB_SF_PRST_WIDTH 1 319227569Sphilip#define FRF_AB_EE_PRST_LBN 8 320227569Sphilip#define FRF_AB_EE_PRST_WIDTH 1 321227569Sphilip#define FRF_AB_ATE_MODE_LBN 3 322227569Sphilip#define FRF_AB_ATE_MODE_WIDTH 1 323227569Sphilip#define FRF_AB_STRAP_PINS_LBN 0 324227569Sphilip#define FRF_AB_STRAP_PINS_WIDTH 3 325227569Sphilip 326227569Sphilip 327227569Sphilip/* 328227569Sphilip * FR_AB_GLB_CTL_REG_SF(128bit): 329227569Sphilip * Global control register 330227569Sphilip */ 331227569Sphilip#define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 332227569Sphilip/* falcona0,falconb0=eeprom_flash */ 333227569Sphilip/* 334227569Sphilip * FR_AB_GLB_CTL_REG(128bit): 335227569Sphilip * Global control register 336227569Sphilip */ 337227569Sphilip#define FR_AB_GLB_CTL_REG_OFST 0x00000220 338227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 339227569Sphilip 340227569Sphilip#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 341227569Sphilip#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 342227569Sphilip#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 343227569Sphilip#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 344227569Sphilip#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 345227569Sphilip#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 346227569Sphilip#define FRF_AA_PCIX_RST_CTL_LBN 60 347227569Sphilip#define FRF_AA_PCIX_RST_CTL_WIDTH 1 348227569Sphilip#define FRF_BB_BIU_RST_CTL_LBN 60 349227569Sphilip#define FRF_BB_BIU_RST_CTL_WIDTH 1 350227569Sphilip#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 351227569Sphilip#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 352227569Sphilip#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 353227569Sphilip#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 354227569Sphilip#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 355227569Sphilip#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 356227569Sphilip#define FRF_AB_XGRX_RST_CTL_LBN 56 357227569Sphilip#define FRF_AB_XGRX_RST_CTL_WIDTH 1 358227569Sphilip#define FRF_AB_XGTX_RST_CTL_LBN 55 359227569Sphilip#define FRF_AB_XGTX_RST_CTL_WIDTH 1 360227569Sphilip#define FRF_AB_EM_RST_CTL_LBN 54 361227569Sphilip#define FRF_AB_EM_RST_CTL_WIDTH 1 362227569Sphilip#define FRF_AB_EV_RST_CTL_LBN 53 363227569Sphilip#define FRF_AB_EV_RST_CTL_WIDTH 1 364227569Sphilip#define FRF_AB_SR_RST_CTL_LBN 52 365227569Sphilip#define FRF_AB_SR_RST_CTL_WIDTH 1 366227569Sphilip#define FRF_AB_RX_RST_CTL_LBN 51 367227569Sphilip#define FRF_AB_RX_RST_CTL_WIDTH 1 368227569Sphilip#define FRF_AB_TX_RST_CTL_LBN 50 369227569Sphilip#define FRF_AB_TX_RST_CTL_WIDTH 1 370227569Sphilip#define FRF_AB_EE_RST_CTL_LBN 49 371227569Sphilip#define FRF_AB_EE_RST_CTL_WIDTH 1 372227569Sphilip#define FRF_AB_CS_RST_CTL_LBN 48 373227569Sphilip#define FRF_AB_CS_RST_CTL_WIDTH 1 374227569Sphilip#define FRF_AB_HOT_RST_CTL_LBN 40 375227569Sphilip#define FRF_AB_HOT_RST_CTL_WIDTH 2 376227569Sphilip#define FRF_AB_RST_EXT_PHY_LBN 31 377227569Sphilip#define FRF_AB_RST_EXT_PHY_WIDTH 1 378227569Sphilip#define FRF_AB_RST_XAUI_SD_LBN 30 379227569Sphilip#define FRF_AB_RST_XAUI_SD_WIDTH 1 380227569Sphilip#define FRF_AB_RST_PCIE_SD_LBN 29 381227569Sphilip#define FRF_AB_RST_PCIE_SD_WIDTH 1 382227569Sphilip#define FRF_AA_RST_PCIX_LBN 28 383227569Sphilip#define FRF_AA_RST_PCIX_WIDTH 1 384227569Sphilip#define FRF_BB_RST_BIU_LBN 28 385227569Sphilip#define FRF_BB_RST_BIU_WIDTH 1 386227569Sphilip#define FRF_AB_RST_PCIE_STKY_LBN 27 387227569Sphilip#define FRF_AB_RST_PCIE_STKY_WIDTH 1 388227569Sphilip#define FRF_AB_RST_PCIE_NSTKY_LBN 26 389227569Sphilip#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 390227569Sphilip#define FRF_AB_RST_PCIE_CORE_LBN 25 391227569Sphilip#define FRF_AB_RST_PCIE_CORE_WIDTH 1 392227569Sphilip#define FRF_AB_RST_XGRX_LBN 24 393227569Sphilip#define FRF_AB_RST_XGRX_WIDTH 1 394227569Sphilip#define FRF_AB_RST_XGTX_LBN 23 395227569Sphilip#define FRF_AB_RST_XGTX_WIDTH 1 396227569Sphilip#define FRF_AB_RST_EM_LBN 22 397227569Sphilip#define FRF_AB_RST_EM_WIDTH 1 398227569Sphilip#define FRF_AB_RST_EV_LBN 21 399227569Sphilip#define FRF_AB_RST_EV_WIDTH 1 400227569Sphilip#define FRF_AB_RST_SR_LBN 20 401227569Sphilip#define FRF_AB_RST_SR_WIDTH 1 402227569Sphilip#define FRF_AB_RST_RX_LBN 19 403227569Sphilip#define FRF_AB_RST_RX_WIDTH 1 404227569Sphilip#define FRF_AB_RST_TX_LBN 18 405227569Sphilip#define FRF_AB_RST_TX_WIDTH 1 406227569Sphilip#define FRF_AB_RST_SF_LBN 17 407227569Sphilip#define FRF_AB_RST_SF_WIDTH 1 408227569Sphilip#define FRF_AB_RST_CS_LBN 16 409227569Sphilip#define FRF_AB_RST_CS_WIDTH 1 410227569Sphilip#define FRF_AB_INT_RST_DUR_LBN 4 411227569Sphilip#define FRF_AB_INT_RST_DUR_WIDTH 3 412227569Sphilip#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 413227569Sphilip#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 414227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 415227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 416227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 417227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 418227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_640US 3 419227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_320US 2 420227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_160US 1 421227569Sphilip#define FFE_AB_EXT_PHY_RST_DUR_80US 0 422227569Sphilip#define FRF_AB_SWRST_LBN 0 423227569Sphilip#define FRF_AB_SWRST_WIDTH 1 424227569Sphilip 425227569Sphilip 426227569Sphilip/* 427227569Sphilip * FR_AZ_IOM_IND_ADR_REG(32bit): 428227569Sphilip * IO-mapped indirect access address register 429227569Sphilip */ 430227569Sphilip#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 431227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar0 */ 432227569Sphilip 433227569Sphilip#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 434227569Sphilip#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 435227569Sphilip#define FRF_AZ_IOM_IND_ADR_LBN 0 436227569Sphilip#define FRF_AZ_IOM_IND_ADR_WIDTH 24 437227569Sphilip 438227569Sphilip 439227569Sphilip/* 440227569Sphilip * FR_AZ_IOM_IND_DAT_REG(32bit): 441227569Sphilip * IO-mapped indirect access data register 442227569Sphilip */ 443227569Sphilip#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 444227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar0 */ 445227569Sphilip 446227569Sphilip#define FRF_AZ_IOM_IND_DAT_LBN 0 447227569Sphilip#define FRF_AZ_IOM_IND_DAT_WIDTH 32 448227569Sphilip 449227569Sphilip 450227569Sphilip/* 451227569Sphilip * FR_AZ_ADR_REGION_REG(128bit): 452227569Sphilip * Address region register 453227569Sphilip */ 454227569Sphilip#define FR_AZ_ADR_REGION_REG_OFST 0x00000000 455227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 456227569Sphilip 457227569Sphilip#define FRF_AZ_ADR_REGION3_LBN 96 458227569Sphilip#define FRF_AZ_ADR_REGION3_WIDTH 18 459227569Sphilip#define FRF_AZ_ADR_REGION2_LBN 64 460227569Sphilip#define FRF_AZ_ADR_REGION2_WIDTH 18 461227569Sphilip#define FRF_AZ_ADR_REGION1_LBN 32 462227569Sphilip#define FRF_AZ_ADR_REGION1_WIDTH 18 463227569Sphilip#define FRF_AZ_ADR_REGION0_LBN 0 464227569Sphilip#define FRF_AZ_ADR_REGION0_WIDTH 18 465227569Sphilip 466227569Sphilip 467227569Sphilip/* 468227569Sphilip * FR_AZ_INT_EN_REG_KER(128bit): 469227569Sphilip * Kernel driver Interrupt enable register 470227569Sphilip */ 471227569Sphilip#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 472227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2 */ 473227569Sphilip 474227569Sphilip#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 475227569Sphilip#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 476227569Sphilip#define FRF_AZ_KER_INT_CHAR_LBN 4 477227569Sphilip#define FRF_AZ_KER_INT_CHAR_WIDTH 1 478227569Sphilip#define FRF_AZ_KER_INT_KER_LBN 3 479227569Sphilip#define FRF_AZ_KER_INT_KER_WIDTH 1 480227569Sphilip#define FRF_AZ_DRV_INT_EN_KER_LBN 0 481227569Sphilip#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 482227569Sphilip 483227569Sphilip 484227569Sphilip/* 485227569Sphilip * FR_AZ_INT_EN_REG_CHAR(128bit): 486227569Sphilip * Char Driver interrupt enable register 487227569Sphilip */ 488227569Sphilip#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 489227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 490227569Sphilip 491227569Sphilip#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 492227569Sphilip#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 493227569Sphilip#define FRF_AZ_CHAR_INT_CHAR_LBN 4 494227569Sphilip#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 495227569Sphilip#define FRF_AZ_CHAR_INT_KER_LBN 3 496227569Sphilip#define FRF_AZ_CHAR_INT_KER_WIDTH 1 497227569Sphilip#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 498227569Sphilip#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 499227569Sphilip 500227569Sphilip 501227569Sphilip/* 502227569Sphilip * FR_AZ_INT_ADR_REG_KER(128bit): 503227569Sphilip * Interrupt host address for Kernel driver 504227569Sphilip */ 505227569Sphilip#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 506227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2 */ 507227569Sphilip 508227569Sphilip#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 509227569Sphilip#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 510227569Sphilip#define FRF_AZ_INT_ADR_KER_LBN 0 511227569Sphilip#define FRF_AZ_INT_ADR_KER_WIDTH 64 512227569Sphilip#define FRF_AZ_INT_ADR_KER_DW0_LBN 0 513227569Sphilip#define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 514227569Sphilip#define FRF_AZ_INT_ADR_KER_DW1_LBN 32 515227569Sphilip#define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 516227569Sphilip 517227569Sphilip 518227569Sphilip/* 519227569Sphilip * FR_AZ_INT_ADR_REG_CHAR(128bit): 520227569Sphilip * Interrupt host address for Char driver 521227569Sphilip */ 522227569Sphilip#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 523227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 524227569Sphilip 525227569Sphilip#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 526227569Sphilip#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 527227569Sphilip#define FRF_AZ_INT_ADR_CHAR_LBN 0 528227569Sphilip#define FRF_AZ_INT_ADR_CHAR_WIDTH 64 529227569Sphilip#define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 530227569Sphilip#define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 531227569Sphilip#define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 532227569Sphilip#define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 533227569Sphilip 534227569Sphilip 535227569Sphilip/* 536227569Sphilip * FR_AA_INT_ACK_KER(32bit): 537227569Sphilip * Kernel interrupt acknowledge register 538227569Sphilip */ 539227569Sphilip#define FR_AA_INT_ACK_KER_OFST 0x00000050 540227569Sphilip/* falcona0=net_func_bar2 */ 541227569Sphilip 542227569Sphilip#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 543227569Sphilip#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 544227569Sphilip 545227569Sphilip 546227569Sphilip/* 547227569Sphilip * FR_BZ_INT_ISR0_REG(128bit): 548227569Sphilip * Function 0 Interrupt Acknowlege Status register 549227569Sphilip */ 550227569Sphilip#define FR_BZ_INT_ISR0_REG_OFST 0x00000090 551227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 552227569Sphilip 553227569Sphilip#define FRF_BZ_INT_ISR_REG_LBN 0 554227569Sphilip#define FRF_BZ_INT_ISR_REG_WIDTH 64 555227569Sphilip#define FRF_BZ_INT_ISR_REG_DW0_LBN 0 556227569Sphilip#define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 557227569Sphilip#define FRF_BZ_INT_ISR_REG_DW1_LBN 32 558227569Sphilip#define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 559227569Sphilip 560227569Sphilip 561227569Sphilip/* 562227569Sphilip * FR_AB_EE_SPI_HCMD_REG(128bit): 563227569Sphilip * SPI host command register 564227569Sphilip */ 565227569Sphilip#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 566227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 567227569Sphilip 568227569Sphilip#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 569227569Sphilip#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 570227569Sphilip#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 571227569Sphilip#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 572227569Sphilip#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 573227569Sphilip#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 574227569Sphilip#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 575227569Sphilip#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 576227569Sphilip#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 577227569Sphilip#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 578227569Sphilip#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 579227569Sphilip#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 580227569Sphilip#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 581227569Sphilip#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 582227569Sphilip#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 583227569Sphilip#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 584227569Sphilip 585227569Sphilip 586227569Sphilip/* 587227569Sphilip * FR_CZ_USR_EV_CFG(32bit): 588227569Sphilip * User Level Event Configuration register 589227569Sphilip */ 590227569Sphilip#define FR_CZ_USR_EV_CFG_OFST 0x00000100 591227569Sphilip/* sienaa0=net_func_bar2 */ 592227569Sphilip 593227569Sphilip#define FRF_CZ_USREV_DIS_LBN 16 594227569Sphilip#define FRF_CZ_USREV_DIS_WIDTH 1 595227569Sphilip#define FRF_CZ_DFLT_EVQ_LBN 0 596227569Sphilip#define FRF_CZ_DFLT_EVQ_WIDTH 10 597227569Sphilip 598227569Sphilip 599227569Sphilip/* 600227569Sphilip * FR_AB_EE_SPI_HADR_REG(128bit): 601227569Sphilip * SPI host address register 602227569Sphilip */ 603227569Sphilip#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 604227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 605227569Sphilip 606227569Sphilip#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 607227569Sphilip#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 608227569Sphilip#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 609227569Sphilip#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 610227569Sphilip 611227569Sphilip 612227569Sphilip/* 613227569Sphilip * FR_AB_EE_SPI_HDATA_REG(128bit): 614227569Sphilip * SPI host data register 615227569Sphilip */ 616227569Sphilip#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 617227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 618227569Sphilip 619227569Sphilip#define FRF_AB_EE_SPI_HDATA3_LBN 96 620227569Sphilip#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 621227569Sphilip#define FRF_AB_EE_SPI_HDATA2_LBN 64 622227569Sphilip#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 623227569Sphilip#define FRF_AB_EE_SPI_HDATA1_LBN 32 624227569Sphilip#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 625227569Sphilip#define FRF_AB_EE_SPI_HDATA0_LBN 0 626227569Sphilip#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 627227569Sphilip 628227569Sphilip 629227569Sphilip/* 630227569Sphilip * FR_AB_EE_BASE_PAGE_REG(128bit): 631227569Sphilip * Expansion ROM base mirror register 632227569Sphilip */ 633227569Sphilip#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 634227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 635227569Sphilip 636227569Sphilip#define FRF_AB_EE_EXPROM_MASK_LBN 16 637227569Sphilip#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 638227569Sphilip#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 639227569Sphilip#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 640227569Sphilip 641227569Sphilip 642227569Sphilip/* 643227569Sphilip * FR_AB_EE_VPD_SW_CNTL_REG(128bit): 644227569Sphilip * VPD access SW control register 645227569Sphilip */ 646227569Sphilip#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 647227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 648227569Sphilip 649227569Sphilip#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 650227569Sphilip#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 651227569Sphilip#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 652227569Sphilip#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 653227569Sphilip#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 654227569Sphilip#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 655227569Sphilip 656227569Sphilip 657227569Sphilip/* 658227569Sphilip * FR_AB_EE_VPD_SW_DATA_REG(128bit): 659227569Sphilip * VPD access SW data register 660227569Sphilip */ 661227569Sphilip#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 662227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 663227569Sphilip 664227569Sphilip#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 665227569Sphilip#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 666227569Sphilip 667227569Sphilip 668227569Sphilip/* 669227569Sphilip * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): 670227569Sphilip * Indirect Access to PCIE Core registers 671227569Sphilip */ 672227569Sphilip#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 673227569Sphilip/* falconb0=net_func_bar2 */ 674227569Sphilip 675227569Sphilip#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 676227569Sphilip#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 677227569Sphilip#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 678227569Sphilip#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 679227569Sphilip#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 680227569Sphilip#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 681227569Sphilip 682227569Sphilip 683227569Sphilip/* 684227569Sphilip * FR_AB_GPIO_CTL_REG(128bit): 685227569Sphilip * GPIO control register 686227569Sphilip */ 687227569Sphilip#define FR_AB_GPIO_CTL_REG_OFST 0x00000210 688227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 689227569Sphilip 690227569Sphilip#define FRF_AB_GPIO15_OEN_LBN 63 691227569Sphilip#define FRF_AB_GPIO15_OEN_WIDTH 1 692227569Sphilip#define FRF_AB_GPIO14_OEN_LBN 62 693227569Sphilip#define FRF_AB_GPIO14_OEN_WIDTH 1 694227569Sphilip#define FRF_AB_GPIO13_OEN_LBN 61 695227569Sphilip#define FRF_AB_GPIO13_OEN_WIDTH 1 696227569Sphilip#define FRF_AB_GPIO12_OEN_LBN 60 697227569Sphilip#define FRF_AB_GPIO12_OEN_WIDTH 1 698227569Sphilip#define FRF_AB_GPIO11_OEN_LBN 59 699227569Sphilip#define FRF_AB_GPIO11_OEN_WIDTH 1 700227569Sphilip#define FRF_AB_GPIO10_OEN_LBN 58 701227569Sphilip#define FRF_AB_GPIO10_OEN_WIDTH 1 702227569Sphilip#define FRF_AB_GPIO9_OEN_LBN 57 703227569Sphilip#define FRF_AB_GPIO9_OEN_WIDTH 1 704227569Sphilip#define FRF_AB_GPIO8_OEN_LBN 56 705227569Sphilip#define FRF_AB_GPIO8_OEN_WIDTH 1 706227569Sphilip#define FRF_AB_GPIO15_OUT_LBN 55 707227569Sphilip#define FRF_AB_GPIO15_OUT_WIDTH 1 708227569Sphilip#define FRF_AB_GPIO14_OUT_LBN 54 709227569Sphilip#define FRF_AB_GPIO14_OUT_WIDTH 1 710227569Sphilip#define FRF_AB_GPIO13_OUT_LBN 53 711227569Sphilip#define FRF_AB_GPIO13_OUT_WIDTH 1 712227569Sphilip#define FRF_AB_GPIO12_OUT_LBN 52 713227569Sphilip#define FRF_AB_GPIO12_OUT_WIDTH 1 714227569Sphilip#define FRF_AB_GPIO11_OUT_LBN 51 715227569Sphilip#define FRF_AB_GPIO11_OUT_WIDTH 1 716227569Sphilip#define FRF_AB_GPIO10_OUT_LBN 50 717227569Sphilip#define FRF_AB_GPIO10_OUT_WIDTH 1 718227569Sphilip#define FRF_AB_GPIO9_OUT_LBN 49 719227569Sphilip#define FRF_AB_GPIO9_OUT_WIDTH 1 720227569Sphilip#define FRF_AB_GPIO8_OUT_LBN 48 721227569Sphilip#define FRF_AB_GPIO8_OUT_WIDTH 1 722227569Sphilip#define FRF_AB_GPIO15_IN_LBN 47 723227569Sphilip#define FRF_AB_GPIO15_IN_WIDTH 1 724227569Sphilip#define FRF_AB_GPIO14_IN_LBN 46 725227569Sphilip#define FRF_AB_GPIO14_IN_WIDTH 1 726227569Sphilip#define FRF_AB_GPIO13_IN_LBN 45 727227569Sphilip#define FRF_AB_GPIO13_IN_WIDTH 1 728227569Sphilip#define FRF_AB_GPIO12_IN_LBN 44 729227569Sphilip#define FRF_AB_GPIO12_IN_WIDTH 1 730227569Sphilip#define FRF_AB_GPIO11_IN_LBN 43 731227569Sphilip#define FRF_AB_GPIO11_IN_WIDTH 1 732227569Sphilip#define FRF_AB_GPIO10_IN_LBN 42 733227569Sphilip#define FRF_AB_GPIO10_IN_WIDTH 1 734227569Sphilip#define FRF_AB_GPIO9_IN_LBN 41 735227569Sphilip#define FRF_AB_GPIO9_IN_WIDTH 1 736227569Sphilip#define FRF_AB_GPIO8_IN_LBN 40 737227569Sphilip#define FRF_AB_GPIO8_IN_WIDTH 1 738227569Sphilip#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 739227569Sphilip#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 740227569Sphilip#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 741227569Sphilip#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 742227569Sphilip#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 743227569Sphilip#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 744227569Sphilip#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 745227569Sphilip#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 746227569Sphilip#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 747227569Sphilip#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 748227569Sphilip#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 749227569Sphilip#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 750227569Sphilip#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 751227569Sphilip#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 752227569Sphilip#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 753227569Sphilip#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 754227569Sphilip#define FRF_BB_CLK156_OUT_EN_LBN 31 755227569Sphilip#define FRF_BB_CLK156_OUT_EN_WIDTH 1 756227569Sphilip#define FRF_BB_USE_NIC_CLK_LBN 30 757227569Sphilip#define FRF_BB_USE_NIC_CLK_WIDTH 1 758227569Sphilip#define FRF_AB_GPIO5_OEN_LBN 29 759227569Sphilip#define FRF_AB_GPIO5_OEN_WIDTH 1 760227569Sphilip#define FRF_AB_GPIO4_OEN_LBN 28 761227569Sphilip#define FRF_AB_GPIO4_OEN_WIDTH 1 762227569Sphilip#define FRF_AB_GPIO3_OEN_LBN 27 763227569Sphilip#define FRF_AB_GPIO3_OEN_WIDTH 1 764227569Sphilip#define FRF_AB_GPIO2_OEN_LBN 26 765227569Sphilip#define FRF_AB_GPIO2_OEN_WIDTH 1 766227569Sphilip#define FRF_AB_GPIO1_OEN_LBN 25 767227569Sphilip#define FRF_AB_GPIO1_OEN_WIDTH 1 768227569Sphilip#define FRF_AB_GPIO0_OEN_LBN 24 769227569Sphilip#define FRF_AB_GPIO0_OEN_WIDTH 1 770227569Sphilip#define FRF_AB_GPIO5_OUT_LBN 21 771227569Sphilip#define FRF_AB_GPIO5_OUT_WIDTH 1 772227569Sphilip#define FRF_AB_GPIO4_OUT_LBN 20 773227569Sphilip#define FRF_AB_GPIO4_OUT_WIDTH 1 774227569Sphilip#define FRF_AB_GPIO3_OUT_LBN 19 775227569Sphilip#define FRF_AB_GPIO3_OUT_WIDTH 1 776227569Sphilip#define FRF_AB_GPIO2_OUT_LBN 18 777227569Sphilip#define FRF_AB_GPIO2_OUT_WIDTH 1 778227569Sphilip#define FRF_AB_GPIO1_OUT_LBN 17 779227569Sphilip#define FRF_AB_GPIO1_OUT_WIDTH 1 780227569Sphilip#define FRF_AB_GPIO0_OUT_LBN 16 781227569Sphilip#define FRF_AB_GPIO0_OUT_WIDTH 1 782227569Sphilip#define FRF_AB_GPIO5_IN_LBN 13 783227569Sphilip#define FRF_AB_GPIO5_IN_WIDTH 1 784227569Sphilip#define FRF_AB_GPIO4_IN_LBN 12 785227569Sphilip#define FRF_AB_GPIO4_IN_WIDTH 1 786227569Sphilip#define FRF_AB_GPIO3_IN_LBN 11 787227569Sphilip#define FRF_AB_GPIO3_IN_WIDTH 1 788227569Sphilip#define FRF_AB_GPIO2_IN_LBN 10 789227569Sphilip#define FRF_AB_GPIO2_IN_WIDTH 1 790227569Sphilip#define FRF_AB_GPIO1_IN_LBN 9 791227569Sphilip#define FRF_AB_GPIO1_IN_WIDTH 1 792227569Sphilip#define FRF_AB_GPIO0_IN_LBN 8 793227569Sphilip#define FRF_AB_GPIO0_IN_WIDTH 1 794227569Sphilip#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 795227569Sphilip#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 796227569Sphilip#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 797227569Sphilip#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 798227569Sphilip#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 799227569Sphilip#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 800227569Sphilip#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 801227569Sphilip#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 802227569Sphilip#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 803227569Sphilip#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 804227569Sphilip#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 805227569Sphilip#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 806227569Sphilip 807227569Sphilip 808227569Sphilip/* 809227569Sphilip * FR_AZ_FATAL_INTR_REG_KER(128bit): 810227569Sphilip * Fatal interrupt register for Kernel 811227569Sphilip */ 812227569Sphilip#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 813227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2 */ 814227569Sphilip 815227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 816227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 817227569Sphilip#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 818227569Sphilip#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 819227569Sphilip#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 820227569Sphilip#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 821227569Sphilip#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 822227569Sphilip#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 823227569Sphilip#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 824227569Sphilip#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 825227569Sphilip#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 826227569Sphilip#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 827227569Sphilip#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 828227569Sphilip#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 829227569Sphilip#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 830227569Sphilip#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 831227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 832227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 833227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 834227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 835227569Sphilip#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 836227569Sphilip#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 837227569Sphilip#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 838227569Sphilip#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 839227569Sphilip#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 840227569Sphilip#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 841227569Sphilip#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 842227569Sphilip#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 843227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 844227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 845227569Sphilip#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 846227569Sphilip#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 847227569Sphilip#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 848227569Sphilip#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 849227569Sphilip#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 850227569Sphilip#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 851227569Sphilip#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 852227569Sphilip#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 853227569Sphilip#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 854227569Sphilip#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 855227569Sphilip#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 856227569Sphilip#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 857227569Sphilip#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 858227569Sphilip#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 859227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 860227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 861227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 862227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 863227569Sphilip#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 864227569Sphilip#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 865227569Sphilip#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 866227569Sphilip#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 867227569Sphilip#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 868227569Sphilip#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 869227569Sphilip#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 870227569Sphilip#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 871227569Sphilip 872227569Sphilip 873227569Sphilip/* 874227569Sphilip * FR_AZ_FATAL_INTR_REG_CHAR(128bit): 875227569Sphilip * Fatal interrupt register for Char 876227569Sphilip */ 877227569Sphilip#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 878227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 879227569Sphilip 880227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 881227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 882227569Sphilip#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 883227569Sphilip#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 884227569Sphilip#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 885227569Sphilip#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 886227569Sphilip#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 887227569Sphilip#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 888227569Sphilip#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 889227569Sphilip#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 890227569Sphilip#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 891227569Sphilip#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 892227569Sphilip#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 893227569Sphilip#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 894227569Sphilip#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 895227569Sphilip#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 896227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 897227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 898227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 899227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 900227569Sphilip#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 901227569Sphilip#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 902227569Sphilip#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 903227569Sphilip#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 904227569Sphilip#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 905227569Sphilip#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 906227569Sphilip#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 907227569Sphilip#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 908227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 909227569Sphilip#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 910227569Sphilip#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 911227569Sphilip#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 912227569Sphilip#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 913227569Sphilip#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 914227569Sphilip#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 915227569Sphilip#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 916227569Sphilip#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 917227569Sphilip#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 918227569Sphilip#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 919227569Sphilip#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 920227569Sphilip#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 921227569Sphilip#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 922227569Sphilip#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 923227569Sphilip#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 924227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 925227569Sphilip#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 926227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 927227569Sphilip#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 928227569Sphilip#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 929227569Sphilip#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 930227569Sphilip#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 931227569Sphilip#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 932227569Sphilip#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 933227569Sphilip#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 934227569Sphilip#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 935227569Sphilip#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 936227569Sphilip 937227569Sphilip 938227569Sphilip/* 939227569Sphilip * FR_AZ_DP_CTRL_REG(128bit): 940227569Sphilip * Datapath control register 941227569Sphilip */ 942227569Sphilip#define FR_AZ_DP_CTRL_REG_OFST 0x00000250 943227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 944227569Sphilip 945227569Sphilip#define FRF_AZ_FLS_EVQ_ID_LBN 0 946227569Sphilip#define FRF_AZ_FLS_EVQ_ID_WIDTH 12 947227569Sphilip 948227569Sphilip 949227569Sphilip/* 950227569Sphilip * FR_AZ_MEM_STAT_REG(128bit): 951227569Sphilip * Memory status register 952227569Sphilip */ 953227569Sphilip#define FR_AZ_MEM_STAT_REG_OFST 0x00000260 954227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 955227569Sphilip 956227569Sphilip#define FRF_AB_MEM_PERR_VEC_LBN 53 957227569Sphilip#define FRF_AB_MEM_PERR_VEC_WIDTH 40 958227569Sphilip#define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 959227569Sphilip#define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 960227569Sphilip#define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 961227569Sphilip#define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 962227569Sphilip#define FRF_AB_MBIST_CORR_LBN 38 963227569Sphilip#define FRF_AB_MBIST_CORR_WIDTH 15 964227569Sphilip#define FRF_AB_MBIST_ERR_LBN 0 965227569Sphilip#define FRF_AB_MBIST_ERR_WIDTH 40 966227569Sphilip#define FRF_AB_MBIST_ERR_DW0_LBN 0 967227569Sphilip#define FRF_AB_MBIST_ERR_DW0_WIDTH 32 968227569Sphilip#define FRF_AB_MBIST_ERR_DW1_LBN 32 969227569Sphilip#define FRF_AB_MBIST_ERR_DW1_WIDTH 6 970227569Sphilip#define FRF_CZ_MEM_PERR_VEC_LBN 0 971227569Sphilip#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 972227569Sphilip#define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 973227569Sphilip#define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 974227569Sphilip#define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 975227569Sphilip#define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 976227569Sphilip 977227569Sphilip 978227569Sphilip/* 979227569Sphilip * FR_PORT0_CS_DEBUG_REG(128bit): 980227569Sphilip * Debug register 981227569Sphilip */ 982227569Sphilip 983227569Sphilip#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 984227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 985227569Sphilip 986227569Sphilip#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 987227569Sphilip#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 988227569Sphilip#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 989227569Sphilip#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 990227569Sphilip#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 991227569Sphilip#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 992227569Sphilip#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 993227569Sphilip#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 994227569Sphilip#define FRF_CZ_CS_PORT_NUM_LBN 40 995227569Sphilip#define FRF_CZ_CS_PORT_NUM_WIDTH 2 996227569Sphilip#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 997227569Sphilip#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 998227569Sphilip#define FRF_CZ_CS_RESERVED_LBN 36 999227569Sphilip#define FRF_CZ_CS_RESERVED_WIDTH 4 1000227569Sphilip#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 1001227569Sphilip#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 1002227569Sphilip#define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 1003227569Sphilip#define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 1004227569Sphilip#define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 1005227569Sphilip#define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 1006227569Sphilip#define FRF_CZ_CS_PORT_FPE_LBN 1 1007227569Sphilip#define FRF_CZ_CS_PORT_FPE_WIDTH 35 1008227569Sphilip#define FRF_AB_EM_DEBUG_ADDR_LBN 26 1009227569Sphilip#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 1010227569Sphilip#define FRF_AB_SR_DEBUG_ADDR_LBN 21 1011227569Sphilip#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 1012227569Sphilip#define FRF_AB_EV_DEBUG_ADDR_LBN 16 1013227569Sphilip#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 1014227569Sphilip#define FRF_AB_RX_DEBUG_ADDR_LBN 11 1015227569Sphilip#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 1016227569Sphilip#define FRF_AB_TX_DEBUG_ADDR_LBN 6 1017227569Sphilip#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 1018227569Sphilip#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 1019227569Sphilip#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 1020227569Sphilip#define FRF_AZ_CS_DEBUG_EN_LBN 0 1021227569Sphilip#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 1022227569Sphilip 1023227569Sphilip 1024227569Sphilip/* 1025227569Sphilip * FR_AZ_DRIVER_REG(128bit): 1026227569Sphilip * Driver scratch register [0-7] 1027227569Sphilip */ 1028227569Sphilip#define FR_AZ_DRIVER_REG_OFST 0x00000280 1029227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1030227569Sphilip#define FR_AZ_DRIVER_REG_STEP 16 1031227569Sphilip#define FR_AZ_DRIVER_REG_ROWS 8 1032227569Sphilip 1033227569Sphilip#define FRF_AZ_DRIVER_DW0_LBN 0 1034227569Sphilip#define FRF_AZ_DRIVER_DW0_WIDTH 32 1035227569Sphilip 1036227569Sphilip 1037227569Sphilip/* 1038227569Sphilip * FR_AZ_ALTERA_BUILD_REG(128bit): 1039227569Sphilip * Altera build register 1040227569Sphilip */ 1041227569Sphilip#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 1042227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1043227569Sphilip 1044227569Sphilip#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 1045227569Sphilip#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 1046227569Sphilip 1047227569Sphilip 1048227569Sphilip/* 1049227569Sphilip * FR_AZ_CSR_SPARE_REG(128bit): 1050227569Sphilip * Spare register 1051227569Sphilip */ 1052227569Sphilip#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 1053227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1054227569Sphilip 1055227569Sphilip#define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 1056227569Sphilip#define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 1057227569Sphilip#define FRF_AZ_MEM_PERR_EN_LBN 64 1058227569Sphilip#define FRF_AZ_MEM_PERR_EN_WIDTH 38 1059227569Sphilip#define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 1060227569Sphilip#define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 1061227569Sphilip#define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 1062227569Sphilip#define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 1063227569Sphilip#define FRF_AZ_CSR_SPARE_BITS_LBN 0 1064227569Sphilip#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 1065227569Sphilip 1066227569Sphilip 1067227569Sphilip/* 1068227569Sphilip * FR_BZ_DEBUG_DATA_OUT_REG(128bit): 1069227569Sphilip * Live Debug and Debug 2 out ports 1070227569Sphilip */ 1071227569Sphilip#define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 1072227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 1073227569Sphilip 1074227569Sphilip#define FRF_BZ_DEBUG2_PORT_LBN 25 1075227569Sphilip#define FRF_BZ_DEBUG2_PORT_WIDTH 15 1076227569Sphilip#define FRF_BZ_DEBUG1_PORT_LBN 0 1077227569Sphilip#define FRF_BZ_DEBUG1_PORT_WIDTH 25 1078227569Sphilip 1079227569Sphilip 1080227569Sphilip/* 1081227569Sphilip * FR_BZ_EVQ_RPTR_REGP0(32bit): 1082227569Sphilip * Event queue read pointer register 1083227569Sphilip */ 1084227569Sphilip#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 1085227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 1086227569Sphilip#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 1087227569Sphilip#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 1088227569Sphilip/* 1089227569Sphilip * FR_AA_EVQ_RPTR_REG_KER(32bit): 1090227569Sphilip * Event queue read pointer register 1091227569Sphilip */ 1092227569Sphilip#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 1093227569Sphilip/* falcona0=net_func_bar2 */ 1094227569Sphilip#define FR_AA_EVQ_RPTR_REG_KER_STEP 4 1095227569Sphilip#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 1096227569Sphilip/* 1097227569Sphilip * FR_AZ_EVQ_RPTR_REG(32bit): 1098227569Sphilip * Event queue read pointer register 1099227569Sphilip */ 1100227569Sphilip#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 1101227569Sphilip/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1102227569Sphilip#define FR_AZ_EVQ_RPTR_REG_STEP 16 1103227569Sphilip#define FR_AB_EVQ_RPTR_REG_ROWS 4096 1104227569Sphilip#define FR_CZ_EVQ_RPTR_REG_ROWS 1024 1105227569Sphilip/* 1106227569Sphilip * FR_BB_EVQ_RPTR_REGP123(32bit): 1107227569Sphilip * Event queue read pointer register 1108227569Sphilip */ 1109227569Sphilip#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 1110227569Sphilip/* falconb0=net_func_bar2 */ 1111227569Sphilip#define FR_BB_EVQ_RPTR_REGP123_STEP 8192 1112227569Sphilip#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 1113227569Sphilip 1114227569Sphilip#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 1115227569Sphilip#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 1116227569Sphilip#define FRF_AZ_EVQ_RPTR_LBN 0 1117227569Sphilip#define FRF_AZ_EVQ_RPTR_WIDTH 15 1118227569Sphilip 1119227569Sphilip 1120227569Sphilip/* 1121227569Sphilip * FR_BZ_TIMER_COMMAND_REGP0(128bit): 1122227569Sphilip * Timer Command Registers 1123227569Sphilip */ 1124227569Sphilip#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 1125227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 1126227569Sphilip#define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 1127227569Sphilip#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 1128227569Sphilip/* 1129227569Sphilip * FR_AA_TIMER_COMMAND_REG_KER(128bit): 1130227569Sphilip * Timer Command Registers 1131227569Sphilip */ 1132227569Sphilip#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 1133227569Sphilip/* falcona0=net_func_bar2 */ 1134227569Sphilip#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 1135227569Sphilip#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 1136227569Sphilip/* 1137227569Sphilip * FR_AB_TIMER_COMMAND_REGP123(128bit): 1138227569Sphilip * Timer Command Registers 1139227569Sphilip */ 1140227569Sphilip#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 1141227569Sphilip/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1142227569Sphilip#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 1143227569Sphilip#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 1144227569Sphilip/* 1145227569Sphilip * FR_AA_TIMER_COMMAND_REGP0(128bit): 1146227569Sphilip * Timer Command Registers 1147227569Sphilip */ 1148227569Sphilip#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 1149227569Sphilip/* falcona0=char_func_bar0 */ 1150227569Sphilip#define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 1151227569Sphilip#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 1152227569Sphilip 1153227569Sphilip#define FRF_CZ_TC_TIMER_MODE_LBN 14 1154227569Sphilip#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 1155227569Sphilip#define FRF_AB_TC_TIMER_MODE_LBN 12 1156227569Sphilip#define FRF_AB_TC_TIMER_MODE_WIDTH 2 1157227569Sphilip#define FRF_CZ_TC_TIMER_VAL_LBN 0 1158227569Sphilip#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 1159227569Sphilip#define FRF_AB_TC_TIMER_VAL_LBN 0 1160227569Sphilip#define FRF_AB_TC_TIMER_VAL_WIDTH 12 1161227569Sphilip 1162227569Sphilip 1163227569Sphilip/* 1164227569Sphilip * FR_AZ_DRV_EV_REG(128bit): 1165227569Sphilip * Driver generated event register 1166227569Sphilip */ 1167227569Sphilip#define FR_AZ_DRV_EV_REG_OFST 0x00000440 1168227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1169227569Sphilip 1170227569Sphilip#define FRF_AZ_DRV_EV_QID_LBN 64 1171227569Sphilip#define FRF_AZ_DRV_EV_QID_WIDTH 12 1172227569Sphilip#define FRF_AZ_DRV_EV_DATA_LBN 0 1173227569Sphilip#define FRF_AZ_DRV_EV_DATA_WIDTH 64 1174227569Sphilip#define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 1175227569Sphilip#define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 1176227569Sphilip#define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 1177227569Sphilip#define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 1178227569Sphilip 1179227569Sphilip 1180227569Sphilip/* 1181227569Sphilip * FR_AZ_EVQ_CTL_REG(128bit): 1182227569Sphilip * Event queue control register 1183227569Sphilip */ 1184227569Sphilip#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 1185227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1186227569Sphilip 1187227569Sphilip#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 1188227569Sphilip#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 1189227569Sphilip#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 1190227569Sphilip#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 1191227569Sphilip#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 1192227569Sphilip#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 1193227569Sphilip#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 1194227569Sphilip#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 1195227569Sphilip#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 1196227569Sphilip#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 1197227569Sphilip 1198227569Sphilip 1199227569Sphilip/* 1200227569Sphilip * FR_AZ_EVQ_CNT1_REG(128bit): 1201227569Sphilip * Event counter 1 register 1202227569Sphilip */ 1203227569Sphilip#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 1204227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1205227569Sphilip 1206227569Sphilip#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 1207227569Sphilip#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 1208227569Sphilip#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 1209227569Sphilip#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 1210227569Sphilip#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 1211227569Sphilip#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 1212227569Sphilip#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 1213227569Sphilip#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 1214227569Sphilip#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 1215227569Sphilip#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 1216227569Sphilip#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 1217227569Sphilip#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 1218227569Sphilip#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 1219227569Sphilip#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 1220227569Sphilip 1221227569Sphilip 1222227569Sphilip/* 1223227569Sphilip * FR_AZ_EVQ_CNT2_REG(128bit): 1224227569Sphilip * Event counter 2 register 1225227569Sphilip */ 1226227569Sphilip#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 1227227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1228227569Sphilip 1229227569Sphilip#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 1230227569Sphilip#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 1231227569Sphilip#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 1232227569Sphilip#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 1233227569Sphilip#define FRF_AZ_EVQ_RDY_CNT_LBN 80 1234227569Sphilip#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 1235227569Sphilip#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 1236227569Sphilip#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 1237227569Sphilip#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 1238227569Sphilip#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 1239227569Sphilip#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 1240227569Sphilip#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 1241227569Sphilip#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 1242227569Sphilip#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 1243227569Sphilip 1244227569Sphilip 1245227569Sphilip/* 1246227569Sphilip * FR_CZ_USR_EV_REG(32bit): 1247227569Sphilip * Event mailbox register 1248227569Sphilip */ 1249227569Sphilip#define FR_CZ_USR_EV_REG_OFST 0x00000540 1250227569Sphilip/* sienaa0=net_func_bar2 */ 1251227569Sphilip#define FR_CZ_USR_EV_REG_STEP 8192 1252227569Sphilip#define FR_CZ_USR_EV_REG_ROWS 1024 1253227569Sphilip 1254227569Sphilip#define FRF_CZ_USR_EV_DATA_LBN 0 1255227569Sphilip#define FRF_CZ_USR_EV_DATA_WIDTH 32 1256227569Sphilip 1257227569Sphilip 1258227569Sphilip/* 1259227569Sphilip * FR_AZ_BUF_TBL_CFG_REG(128bit): 1260227569Sphilip * Buffer table configuration register 1261227569Sphilip */ 1262227569Sphilip#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 1263227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1264227569Sphilip 1265227569Sphilip#define FRF_AZ_BUF_TBL_MODE_LBN 3 1266227569Sphilip#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 1267227569Sphilip 1268227569Sphilip 1269227569Sphilip/* 1270227569Sphilip * FR_AZ_SRM_RX_DC_CFG_REG(128bit): 1271227569Sphilip * SRAM receive descriptor cache configuration register 1272227569Sphilip */ 1273227569Sphilip#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 1274227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1275227569Sphilip 1276227569Sphilip#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 1277227569Sphilip#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 1278227569Sphilip#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 1279227569Sphilip#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 1280227569Sphilip 1281227569Sphilip 1282227569Sphilip/* 1283227569Sphilip * FR_AZ_SRM_TX_DC_CFG_REG(128bit): 1284227569Sphilip * SRAM transmit descriptor cache configuration register 1285227569Sphilip */ 1286227569Sphilip#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 1287227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1288227569Sphilip 1289227569Sphilip#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 1290227569Sphilip#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 1291227569Sphilip 1292227569Sphilip 1293227569Sphilip/* 1294227569Sphilip * FR_AZ_SRM_CFG_REG(128bit): 1295227569Sphilip * SRAM configuration register 1296227569Sphilip */ 1297227569Sphilip#define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 1298227569Sphilip/* falcona0,falconb0=eeprom_flash */ 1299227569Sphilip/* 1300227569Sphilip * FR_AZ_SRM_CFG_REG(128bit): 1301227569Sphilip * SRAM configuration register 1302227569Sphilip */ 1303227569Sphilip#define FR_AZ_SRM_CFG_REG_OFST 0x00000630 1304227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1305227569Sphilip 1306227569Sphilip#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 1307227569Sphilip#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 1308227569Sphilip#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 1309227569Sphilip#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 1310227569Sphilip#define FRF_AZ_SRM_INIT_EN_LBN 3 1311227569Sphilip#define FRF_AZ_SRM_INIT_EN_WIDTH 1 1312227569Sphilip#define FRF_AZ_SRM_NUM_BANK_LBN 2 1313227569Sphilip#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 1314227569Sphilip#define FRF_AZ_SRM_BANK_SIZE_LBN 0 1315227569Sphilip#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 1316227569Sphilip 1317227569Sphilip 1318227569Sphilip/* 1319227569Sphilip * FR_AZ_BUF_TBL_UPD_REG(128bit): 1320227569Sphilip * Buffer table update register 1321227569Sphilip */ 1322227569Sphilip#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 1323227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1324227569Sphilip 1325227569Sphilip#define FRF_AZ_BUF_UPD_CMD_LBN 63 1326227569Sphilip#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 1327227569Sphilip#define FRF_AZ_BUF_CLR_CMD_LBN 62 1328227569Sphilip#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 1329227569Sphilip#define FRF_AZ_BUF_CLR_END_ID_LBN 32 1330227569Sphilip#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 1331227569Sphilip#define FRF_AZ_BUF_CLR_START_ID_LBN 0 1332227569Sphilip#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 1333227569Sphilip 1334227569Sphilip 1335227569Sphilip/* 1336227569Sphilip * FR_AZ_SRM_UPD_EVQ_REG(128bit): 1337227569Sphilip * Buffer table update register 1338227569Sphilip */ 1339227569Sphilip#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 1340227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1341227569Sphilip 1342227569Sphilip#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 1343227569Sphilip#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 1344227569Sphilip 1345227569Sphilip 1346227569Sphilip/* 1347227569Sphilip * FR_AZ_SRAM_PARITY_REG(128bit): 1348227569Sphilip * SRAM parity register. 1349227569Sphilip */ 1350227569Sphilip#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 1351227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1352227569Sphilip 1353227569Sphilip#define FRF_CZ_BYPASS_ECC_LBN 3 1354227569Sphilip#define FRF_CZ_BYPASS_ECC_WIDTH 1 1355227569Sphilip#define FRF_CZ_SEC_INT_LBN 2 1356227569Sphilip#define FRF_CZ_SEC_INT_WIDTH 1 1357227569Sphilip#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 1358227569Sphilip#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 1359227569Sphilip#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 1360227569Sphilip#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 1361227569Sphilip#define FRF_AB_FORCE_SRAM_PERR_LBN 0 1362227569Sphilip#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 1363227569Sphilip 1364227569Sphilip 1365227569Sphilip/* 1366227569Sphilip * FR_AZ_RX_CFG_REG(128bit): 1367227569Sphilip * Receive configuration register 1368227569Sphilip */ 1369227569Sphilip#define FR_AZ_RX_CFG_REG_OFST 0x00000800 1370227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1371227569Sphilip 1372227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1373227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1374227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1375227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1376227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1377227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1378227569Sphilip#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1379227569Sphilip#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1380227569Sphilip#define FRF_BZ_RX_TCP_SUP_LBN 48 1381227569Sphilip#define FRF_BZ_RX_TCP_SUP_WIDTH 1 1382227569Sphilip#define FRF_BZ_RX_INGR_EN_LBN 47 1383227569Sphilip#define FRF_BZ_RX_INGR_EN_WIDTH 1 1384227569Sphilip#define FRF_BZ_RX_IP_HASH_LBN 46 1385227569Sphilip#define FRF_BZ_RX_IP_HASH_WIDTH 1 1386227569Sphilip#define FRF_BZ_RX_HASH_ALG_LBN 45 1387227569Sphilip#define FRF_BZ_RX_HASH_ALG_WIDTH 1 1388227569Sphilip#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1389227569Sphilip#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1390227569Sphilip#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1391227569Sphilip#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1392227569Sphilip#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1393227569Sphilip#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1394227569Sphilip#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1395227569Sphilip#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1396227569Sphilip#define FRF_BZ_RX_OWNERR_CTL_LBN 38 1397227569Sphilip#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1398227569Sphilip#define FRF_BZ_RX_XON_TX_TH_LBN 33 1399227569Sphilip#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1400227569Sphilip#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1401227569Sphilip#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1402227569Sphilip#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1403227569Sphilip#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1404227569Sphilip#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1405227569Sphilip#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1406227569Sphilip#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1407227569Sphilip#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1408227569Sphilip#define FRF_AA_RX_OWNERR_CTL_LBN 30 1409227569Sphilip#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1410227569Sphilip#define FRF_AA_RX_XON_TX_TH_LBN 25 1411227569Sphilip#define FRF_AA_RX_XON_TX_TH_WIDTH 5 1412227569Sphilip#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1413227569Sphilip#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1414227569Sphilip#define FRF_AA_RX_XOFF_TX_TH_LBN 20 1415227569Sphilip#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1416227569Sphilip#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1417227569Sphilip#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1418227569Sphilip#define FRF_BZ_RX_XON_MAC_TH_LBN 10 1419227569Sphilip#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1420227569Sphilip#define FRF_AA_RX_XON_MAC_TH_LBN 6 1421227569Sphilip#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1422227569Sphilip#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1423227569Sphilip#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1424227569Sphilip#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1425227569Sphilip#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1426227569Sphilip#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1427227569Sphilip#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1428227569Sphilip 1429227569Sphilip 1430227569Sphilip/* 1431227569Sphilip * FR_AZ_RX_FILTER_CTL_REG(128bit): 1432227569Sphilip * Receive filter control registers 1433227569Sphilip */ 1434227569Sphilip#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 1435227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1436227569Sphilip 1437227569Sphilip#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1438227569Sphilip#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1439227569Sphilip#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1440227569Sphilip#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1441227569Sphilip#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1442227569Sphilip#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1443227569Sphilip#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1444227569Sphilip#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1445227569Sphilip#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1446227569Sphilip#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1447227569Sphilip#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1448227569Sphilip#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1449227569Sphilip#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1450227569Sphilip#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1451227569Sphilip#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1452227569Sphilip#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1453227569Sphilip#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1454227569Sphilip#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1455227569Sphilip#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1456227569Sphilip#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1457227569Sphilip#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1458227569Sphilip#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1459227569Sphilip#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 1460227569Sphilip#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1461227569Sphilip#define FRF_AZ_NUM_KER_LBN 24 1462227569Sphilip#define FRF_AZ_NUM_KER_WIDTH 2 1463227569Sphilip#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 1464227569Sphilip#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1465227569Sphilip#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 1466227569Sphilip#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1467227569Sphilip#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 1468227569Sphilip#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1469227569Sphilip 1470227569Sphilip 1471227569Sphilip/* 1472227569Sphilip * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): 1473227569Sphilip * Receive flush descriptor queue register 1474227569Sphilip */ 1475227569Sphilip#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 1476227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1477227569Sphilip 1478227569Sphilip#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1479227569Sphilip#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1480227569Sphilip#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1481227569Sphilip#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1482227569Sphilip 1483227569Sphilip 1484227569Sphilip/* 1485227569Sphilip * FR_BZ_RX_DESC_UPD_REGP0(128bit): 1486227569Sphilip * Receive descriptor update register. 1487227569Sphilip */ 1488227569Sphilip#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 1489227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 1490227569Sphilip#define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 1491227569Sphilip#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 1492227569Sphilip/* 1493227569Sphilip * FR_AA_RX_DESC_UPD_REG_KER(128bit): 1494227569Sphilip * Receive descriptor update register. 1495227569Sphilip */ 1496227569Sphilip#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 1497227569Sphilip/* falcona0=net_func_bar2 */ 1498227569Sphilip#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 1499227569Sphilip#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 1500227569Sphilip/* 1501227569Sphilip * FR_AB_RX_DESC_UPD_REGP123(128bit): 1502227569Sphilip * Receive descriptor update register. 1503227569Sphilip */ 1504227569Sphilip#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 1505227569Sphilip/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1506227569Sphilip#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 1507227569Sphilip#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 1508227569Sphilip/* 1509227569Sphilip * FR_AA_RX_DESC_UPD_REGP0(128bit): 1510227569Sphilip * Receive descriptor update register. 1511227569Sphilip */ 1512227569Sphilip#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 1513227569Sphilip/* falcona0=char_func_bar0 */ 1514227569Sphilip#define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 1515227569Sphilip#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 1516227569Sphilip 1517227569Sphilip#define FRF_AZ_RX_DESC_WPTR_LBN 96 1518227569Sphilip#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1519227569Sphilip#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1520227569Sphilip#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1521227569Sphilip#define FRF_AZ_RX_DESC_LBN 0 1522227569Sphilip#define FRF_AZ_RX_DESC_WIDTH 64 1523227569Sphilip#define FRF_AZ_RX_DESC_DW0_LBN 0 1524227569Sphilip#define FRF_AZ_RX_DESC_DW0_WIDTH 32 1525227569Sphilip#define FRF_AZ_RX_DESC_DW1_LBN 32 1526227569Sphilip#define FRF_AZ_RX_DESC_DW1_WIDTH 32 1527227569Sphilip 1528227569Sphilip 1529227569Sphilip/* 1530227569Sphilip * FR_AZ_RX_DC_CFG_REG(128bit): 1531227569Sphilip * Receive descriptor cache configuration register 1532227569Sphilip */ 1533227569Sphilip#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 1534227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1535227569Sphilip 1536227569Sphilip#define FRF_AZ_RX_MAX_PF_LBN 2 1537227569Sphilip#define FRF_AZ_RX_MAX_PF_WIDTH 2 1538227569Sphilip#define FRF_AZ_RX_DC_SIZE_LBN 0 1539227569Sphilip#define FRF_AZ_RX_DC_SIZE_WIDTH 2 1540227569Sphilip#define FFE_AZ_RX_DC_SIZE_64 3 1541227569Sphilip#define FFE_AZ_RX_DC_SIZE_32 2 1542227569Sphilip#define FFE_AZ_RX_DC_SIZE_16 1 1543227569Sphilip#define FFE_AZ_RX_DC_SIZE_8 0 1544227569Sphilip 1545227569Sphilip 1546227569Sphilip/* 1547227569Sphilip * FR_AZ_RX_DC_PF_WM_REG(128bit): 1548227569Sphilip * Receive descriptor cache pre-fetch watermark register 1549227569Sphilip */ 1550227569Sphilip#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 1551227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1552227569Sphilip 1553227569Sphilip#define FRF_AZ_RX_DC_PF_HWM_LBN 6 1554227569Sphilip#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1555227569Sphilip#define FRF_AZ_RX_DC_PF_LWM_LBN 0 1556227569Sphilip#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1557227569Sphilip 1558227569Sphilip 1559227569Sphilip/* 1560227569Sphilip * FR_BZ_RX_RSS_TKEY_REG(128bit): 1561227569Sphilip * RSS Toeplitz hash key 1562227569Sphilip */ 1563227569Sphilip#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 1564227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 1565227569Sphilip 1566227569Sphilip#define FRF_BZ_RX_RSS_TKEY_LBN 96 1567227569Sphilip#define FRF_BZ_RX_RSS_TKEY_WIDTH 32 1568227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 1569227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 1570227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 1571227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 1572227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 1573227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 1574227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 1575227569Sphilip#define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 1576227569Sphilip 1577227569Sphilip 1578227569Sphilip/* 1579227569Sphilip * FR_AZ_RX_NODESC_DROP_REG(128bit): 1580227569Sphilip * Receive dropped packet counter register 1581227569Sphilip */ 1582227569Sphilip#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 1583227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1584227569Sphilip 1585227569Sphilip#define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 1586227569Sphilip#define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 1587227569Sphilip 1588227569Sphilip 1589227569Sphilip/* 1590227569Sphilip * FR_AZ_RX_SELF_RST_REG(128bit): 1591227569Sphilip * Receive self reset register 1592227569Sphilip */ 1593227569Sphilip#define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 1594227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1595227569Sphilip 1596227569Sphilip#define FRF_AZ_RX_ISCSI_DIS_LBN 17 1597227569Sphilip#define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 1598227569Sphilip#define FRF_AB_RX_SW_RST_REG_LBN 16 1599227569Sphilip#define FRF_AB_RX_SW_RST_REG_WIDTH 1 1600227569Sphilip#define FRF_AB_RX_SELF_RST_EN_LBN 8 1601227569Sphilip#define FRF_AB_RX_SELF_RST_EN_WIDTH 1 1602227569Sphilip#define FRF_AZ_RX_MAX_PF_LAT_LBN 4 1603227569Sphilip#define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 1604227569Sphilip#define FRF_AZ_RX_MAX_LU_LAT_LBN 0 1605227569Sphilip#define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 1606227569Sphilip 1607227569Sphilip 1608227569Sphilip/* 1609227569Sphilip * FR_AZ_RX_DEBUG_REG(128bit): 1610227569Sphilip * undocumented register 1611227569Sphilip */ 1612227569Sphilip#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 1613227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1614227569Sphilip 1615227569Sphilip#define FRF_AZ_RX_DEBUG_LBN 0 1616227569Sphilip#define FRF_AZ_RX_DEBUG_WIDTH 64 1617227569Sphilip#define FRF_AZ_RX_DEBUG_DW0_LBN 0 1618227569Sphilip#define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 1619227569Sphilip#define FRF_AZ_RX_DEBUG_DW1_LBN 32 1620227569Sphilip#define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 1621227569Sphilip 1622227569Sphilip 1623227569Sphilip/* 1624227569Sphilip * FR_AZ_RX_PUSH_DROP_REG(128bit): 1625227569Sphilip * Receive descriptor push dropped counter register 1626227569Sphilip */ 1627227569Sphilip#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 1628227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1629227569Sphilip 1630227569Sphilip#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1631227569Sphilip#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1632227569Sphilip 1633227569Sphilip 1634227569Sphilip/* 1635227569Sphilip * FR_CZ_RX_RSS_IPV6_REG1(128bit): 1636227569Sphilip * IPv6 RSS Toeplitz hash key low bytes 1637227569Sphilip */ 1638227569Sphilip#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 1639227569Sphilip/* sienaa0=net_func_bar2 */ 1640227569Sphilip 1641227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1642227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1643227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 1644227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 1645227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 1646227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 1647227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 1648227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 1649227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 1650227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 1651227569Sphilip 1652227569Sphilip 1653227569Sphilip/* 1654227569Sphilip * FR_CZ_RX_RSS_IPV6_REG2(128bit): 1655227569Sphilip * IPv6 RSS Toeplitz hash key middle bytes 1656227569Sphilip */ 1657227569Sphilip#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 1658227569Sphilip/* sienaa0=net_func_bar2 */ 1659227569Sphilip 1660227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1661227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1662227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 1663227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 1664227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 1665227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 1666227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 1667227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 1668227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 1669227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 1670227569Sphilip 1671227569Sphilip 1672227569Sphilip/* 1673227569Sphilip * FR_CZ_RX_RSS_IPV6_REG3(128bit): 1674227569Sphilip * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings 1675227569Sphilip */ 1676227569Sphilip#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 1677227569Sphilip/* sienaa0=net_func_bar2 */ 1678227569Sphilip 1679227569Sphilip#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1680227569Sphilip#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1681227569Sphilip#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1682227569Sphilip#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1683227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1684227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1685227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1686227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1687227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 1688227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 1689227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 1690227569Sphilip#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 1691227569Sphilip 1692227569Sphilip 1693227569Sphilip/* 1694227569Sphilip * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): 1695227569Sphilip * Transmit flush descriptor queue register 1696227569Sphilip */ 1697227569Sphilip#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 1698227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1699227569Sphilip 1700227569Sphilip#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1701227569Sphilip#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1702227569Sphilip#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1703227569Sphilip#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1704227569Sphilip 1705227569Sphilip 1706227569Sphilip/* 1707227569Sphilip * FR_BZ_TX_DESC_UPD_REGP0(128bit): 1708227569Sphilip * Transmit descriptor update register. 1709227569Sphilip */ 1710227569Sphilip#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 1711227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 1712227569Sphilip#define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 1713227569Sphilip#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 1714227569Sphilip/* 1715227569Sphilip * FR_AA_TX_DESC_UPD_REG_KER(128bit): 1716227569Sphilip * Transmit descriptor update register. 1717227569Sphilip */ 1718227569Sphilip#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 1719227569Sphilip/* falcona0=net_func_bar2 */ 1720227569Sphilip#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 1721227569Sphilip#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 1722227569Sphilip/* 1723227569Sphilip * FR_AB_TX_DESC_UPD_REGP123(128bit): 1724227569Sphilip * Transmit descriptor update register. 1725227569Sphilip */ 1726227569Sphilip#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 1727227569Sphilip/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1728227569Sphilip#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 1729227569Sphilip#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 1730227569Sphilip/* 1731227569Sphilip * FR_AA_TX_DESC_UPD_REGP0(128bit): 1732227569Sphilip * Transmit descriptor update register. 1733227569Sphilip */ 1734227569Sphilip#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 1735227569Sphilip/* falcona0=char_func_bar0 */ 1736227569Sphilip#define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 1737227569Sphilip#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 1738227569Sphilip 1739227569Sphilip#define FRF_AZ_TX_DESC_WPTR_LBN 96 1740227569Sphilip#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1741227569Sphilip#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1742227569Sphilip#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1743227569Sphilip#define FRF_AZ_TX_DESC_LBN 0 1744227569Sphilip#define FRF_AZ_TX_DESC_WIDTH 95 1745227569Sphilip#define FRF_AZ_TX_DESC_DW0_LBN 0 1746227569Sphilip#define FRF_AZ_TX_DESC_DW0_WIDTH 32 1747227569Sphilip#define FRF_AZ_TX_DESC_DW1_LBN 32 1748227569Sphilip#define FRF_AZ_TX_DESC_DW1_WIDTH 32 1749227569Sphilip#define FRF_AZ_TX_DESC_DW2_LBN 64 1750227569Sphilip#define FRF_AZ_TX_DESC_DW2_WIDTH 31 1751227569Sphilip 1752227569Sphilip 1753227569Sphilip/* 1754227569Sphilip * FR_AZ_TX_DC_CFG_REG(128bit): 1755227569Sphilip * Transmit descriptor cache configuration register 1756227569Sphilip */ 1757227569Sphilip#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 1758227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1759227569Sphilip 1760227569Sphilip#define FRF_AZ_TX_DC_SIZE_LBN 0 1761227569Sphilip#define FRF_AZ_TX_DC_SIZE_WIDTH 2 1762227569Sphilip#define FFE_AZ_TX_DC_SIZE_32 2 1763227569Sphilip#define FFE_AZ_TX_DC_SIZE_16 1 1764227569Sphilip#define FFE_AZ_TX_DC_SIZE_8 0 1765227569Sphilip 1766227569Sphilip 1767227569Sphilip/* 1768227569Sphilip * FR_AA_TX_CHKSM_CFG_REG(128bit): 1769227569Sphilip * Transmit checksum configuration register 1770227569Sphilip */ 1771227569Sphilip#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 1772227569Sphilip/* falcona0=net_func_bar2,falcona0=char_func_bar0 */ 1773227569Sphilip 1774227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1775227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1776227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1777227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1778227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1779227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1780227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1781227569Sphilip#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1782227569Sphilip 1783227569Sphilip 1784227569Sphilip/* 1785227569Sphilip * FR_AZ_TX_CFG_REG(128bit): 1786227569Sphilip * Transmit configuration register 1787227569Sphilip */ 1788227569Sphilip#define FR_AZ_TX_CFG_REG_OFST 0x00000a50 1789227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1790227569Sphilip 1791227569Sphilip#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1792227569Sphilip#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1793227569Sphilip#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1794227569Sphilip#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1795227569Sphilip#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1796227569Sphilip#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1797227569Sphilip#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1798227569Sphilip#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1799227569Sphilip#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1800227569Sphilip#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1801227569Sphilip#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1802227569Sphilip#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1803227569Sphilip#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1804227569Sphilip#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1805227569Sphilip#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1806227569Sphilip#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1807227569Sphilip#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1808227569Sphilip#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1809227569Sphilip#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1810227569Sphilip#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1811227569Sphilip#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1812227569Sphilip#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1813227569Sphilip#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1814227569Sphilip#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1815227569Sphilip#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1816227569Sphilip#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1817227569Sphilip#define FRF_AZ_TX_P1_PRI_EN_LBN 4 1818227569Sphilip#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1819227569Sphilip#define FRF_AZ_TX_OWNERR_CTL_LBN 2 1820227569Sphilip#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1821227569Sphilip#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1822227569Sphilip#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1823227569Sphilip#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1824227569Sphilip#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1825227569Sphilip 1826227569Sphilip 1827227569Sphilip/* 1828227569Sphilip * FR_AZ_TX_PUSH_DROP_REG(128bit): 1829227569Sphilip * Transmit push dropped register 1830227569Sphilip */ 1831227569Sphilip#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 1832227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1833227569Sphilip 1834227569Sphilip#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1835227569Sphilip#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1836227569Sphilip 1837227569Sphilip 1838227569Sphilip/* 1839227569Sphilip * FR_AZ_TX_RESERVED_REG(128bit): 1840227569Sphilip * Transmit configuration register 1841227569Sphilip */ 1842227569Sphilip#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 1843227569Sphilip/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1844227569Sphilip 1845227569Sphilip#define FRF_AZ_TX_EVT_CNT_LBN 121 1846227569Sphilip#define FRF_AZ_TX_EVT_CNT_WIDTH 7 1847227569Sphilip#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1848227569Sphilip#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1849227569Sphilip#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1850227569Sphilip#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1851227569Sphilip#define FRF_AZ_TX_PUSH_EN_LBN 89 1852227569Sphilip#define FRF_AZ_TX_PUSH_EN_WIDTH 1 1853227569Sphilip#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1854227569Sphilip#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1855227569Sphilip#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1856227569Sphilip#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1857227569Sphilip#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1858227569Sphilip#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1859227569Sphilip#define FRF_AZ_TX_DMAQ_ST_LBN 78 1860227569Sphilip#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1861227569Sphilip#define FRF_AZ_TX_RX_SPACER_LBN 64 1862227569Sphilip#define FRF_AZ_TX_RX_SPACER_WIDTH 8 1863227569Sphilip#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1864227569Sphilip#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1865227569Sphilip#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1866227569Sphilip#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1867227569Sphilip#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1868227569Sphilip#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1869227569Sphilip#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1870227569Sphilip#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1871227569Sphilip#define FRF_AZ_TX_XP_TIMER_LBN 52 1872227569Sphilip#define FRF_AZ_TX_XP_TIMER_WIDTH 5 1873227569Sphilip#define FRF_AZ_TX_PREF_SPACER_LBN 44 1874227569Sphilip#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1875227569Sphilip#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1876227569Sphilip#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1877227569Sphilip#define FRF_AZ_TX_ONLY1TAG_LBN 21 1878227569Sphilip#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1879227569Sphilip#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1880227569Sphilip#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1881227569Sphilip#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1882227569Sphilip#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1883227569Sphilip#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1884227569Sphilip#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1885227569Sphilip#define FRF_AA_TX_DMA_FF_THR_LBN 16 1886227569Sphilip#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1887227569Sphilip#define FRF_AZ_TX_DMA_SPACER_LBN 8 1888227569Sphilip#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1889227569Sphilip#define FRF_AA_TX_TCP_DIS_LBN 7 1890227569Sphilip#define FRF_AA_TX_TCP_DIS_WIDTH 1 1891227569Sphilip#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1892227569Sphilip#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1893227569Sphilip#define FRF_AA_TX_IP_DIS_LBN 6 1894227569Sphilip#define FRF_AA_TX_IP_DIS_WIDTH 1 1895227569Sphilip#define FRF_AZ_TX_MAX_CPL_LBN 2 1896227569Sphilip#define FRF_AZ_TX_MAX_CPL_WIDTH 2 1897227569Sphilip#define FFE_AZ_TX_MAX_CPL_16 3 1898227569Sphilip#define FFE_AZ_TX_MAX_CPL_8 2 1899227569Sphilip#define FFE_AZ_TX_MAX_CPL_4 1 1900227569Sphilip#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1901227569Sphilip#define FRF_AZ_TX_MAX_PREF_LBN 0 1902227569Sphilip#define FRF_AZ_TX_MAX_PREF_WIDTH 2 1903227569Sphilip#define FFE_AZ_TX_MAX_PREF_32 3 1904227569Sphilip#define FFE_AZ_TX_MAX_PREF_16 2 1905227569Sphilip#define FFE_AZ_TX_MAX_PREF_8 1 1906227569Sphilip#define FFE_AZ_TX_MAX_PREF_OFF 0 1907227569Sphilip 1908227569Sphilip 1909227569Sphilip/* 1910227569Sphilip * FR_BZ_TX_PACE_REG(128bit): 1911227569Sphilip * Transmit pace control register 1912227569Sphilip */ 1913227569Sphilip#define FR_BZ_TX_PACE_REG_OFST 0x00000a90 1914227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 1915227569Sphilip/* 1916227569Sphilip * FR_AA_TX_PACE_REG(128bit): 1917227569Sphilip * Transmit pace control register 1918227569Sphilip */ 1919227569Sphilip#define FR_AA_TX_PACE_REG_OFST 0x00f80000 1920227569Sphilip/* falcona0=char_func_bar0 */ 1921227569Sphilip 1922227569Sphilip#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 1923227569Sphilip#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 1924227569Sphilip#define FRF_AZ_TX_PACE_SB_AF_LBN 9 1925227569Sphilip#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 1926227569Sphilip#define FRF_AZ_TX_PACE_FB_BASE_LBN 5 1927227569Sphilip#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 1928227569Sphilip#define FRF_AZ_TX_PACE_BIN_TH_LBN 0 1929227569Sphilip#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 1930227569Sphilip 1931227569Sphilip 1932227569Sphilip/* 1933227569Sphilip * FR_AZ_TX_PACE_DROP_QID_REG(128bit): 1934227569Sphilip * PACE Drop QID Counter 1935227569Sphilip */ 1936227569Sphilip#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 1937227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1938227569Sphilip 1939227569Sphilip#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 1940227569Sphilip#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1941227569Sphilip 1942227569Sphilip 1943227569Sphilip/* 1944227569Sphilip * FR_AB_TX_VLAN_REG(128bit): 1945227569Sphilip * Transmit VLAN tag register 1946227569Sphilip */ 1947227569Sphilip#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 1948227569Sphilip/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1949227569Sphilip 1950227569Sphilip#define FRF_AB_TX_VLAN_EN_LBN 127 1951227569Sphilip#define FRF_AB_TX_VLAN_EN_WIDTH 1 1952227569Sphilip#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 1953227569Sphilip#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 1954227569Sphilip#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 1955227569Sphilip#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 1956227569Sphilip#define FRF_AB_TX_VLAN7_LBN 112 1957227569Sphilip#define FRF_AB_TX_VLAN7_WIDTH 12 1958227569Sphilip#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 1959227569Sphilip#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 1960227569Sphilip#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 1961227569Sphilip#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 1962227569Sphilip#define FRF_AB_TX_VLAN6_LBN 96 1963227569Sphilip#define FRF_AB_TX_VLAN6_WIDTH 12 1964227569Sphilip#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 1965227569Sphilip#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 1966227569Sphilip#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 1967227569Sphilip#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 1968227569Sphilip#define FRF_AB_TX_VLAN5_LBN 80 1969227569Sphilip#define FRF_AB_TX_VLAN5_WIDTH 12 1970227569Sphilip#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 1971227569Sphilip#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 1972227569Sphilip#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 1973227569Sphilip#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 1974227569Sphilip#define FRF_AB_TX_VLAN4_LBN 64 1975227569Sphilip#define FRF_AB_TX_VLAN4_WIDTH 12 1976227569Sphilip#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 1977227569Sphilip#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 1978227569Sphilip#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 1979227569Sphilip#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 1980227569Sphilip#define FRF_AB_TX_VLAN3_LBN 48 1981227569Sphilip#define FRF_AB_TX_VLAN3_WIDTH 12 1982227569Sphilip#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 1983227569Sphilip#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 1984227569Sphilip#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 1985227569Sphilip#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 1986227569Sphilip#define FRF_AB_TX_VLAN2_LBN 32 1987227569Sphilip#define FRF_AB_TX_VLAN2_WIDTH 12 1988227569Sphilip#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 1989227569Sphilip#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 1990227569Sphilip#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 1991227569Sphilip#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 1992227569Sphilip#define FRF_AB_TX_VLAN1_LBN 16 1993227569Sphilip#define FRF_AB_TX_VLAN1_WIDTH 12 1994227569Sphilip#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 1995227569Sphilip#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 1996227569Sphilip#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 1997227569Sphilip#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 1998227569Sphilip#define FRF_AB_TX_VLAN0_LBN 0 1999227569Sphilip#define FRF_AB_TX_VLAN0_WIDTH 12 2000227569Sphilip 2001227569Sphilip 2002227569Sphilip/* 2003227569Sphilip * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): 2004227569Sphilip * Transmit filter control register 2005227569Sphilip */ 2006227569Sphilip#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 2007227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 2008227569Sphilip 2009227569Sphilip#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 2010227569Sphilip#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 2011227569Sphilip#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 2012227569Sphilip#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 2013227569Sphilip#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 2014227569Sphilip#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 2015227569Sphilip#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 2016227569Sphilip#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 2017227569Sphilip#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 2018227569Sphilip#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 2019227569Sphilip#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 2020227569Sphilip#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 2021227569Sphilip#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 2022227569Sphilip#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 2023227569Sphilip#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 2024227569Sphilip#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 2025227569Sphilip#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 2026227569Sphilip#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 2027227569Sphilip#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 2028227569Sphilip#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 2029227569Sphilip#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 2030227569Sphilip#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 2031227569Sphilip#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 2032227569Sphilip#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 2033227569Sphilip#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 2034227569Sphilip#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 2035227569Sphilip#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 2036227569Sphilip#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 2037227569Sphilip#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 2038227569Sphilip#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 2039227569Sphilip#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 2040227569Sphilip#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 2041227569Sphilip#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 2042227569Sphilip#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 2043227569Sphilip#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 2044227569Sphilip#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 2045227569Sphilip#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 2046227569Sphilip#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 2047227569Sphilip#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 2048227569Sphilip#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 2049227569Sphilip#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 2050227569Sphilip#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 2051227569Sphilip#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 2052227569Sphilip#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 2053227569Sphilip#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 2054227569Sphilip#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 2055227569Sphilip#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 2056227569Sphilip#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 2057227569Sphilip#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 2058227569Sphilip#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 2059227569Sphilip#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 2060227569Sphilip#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 2061227569Sphilip#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 2062227569Sphilip#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 2063227569Sphilip#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 2064227569Sphilip#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 2065227569Sphilip#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 2066227569Sphilip#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 2067227569Sphilip#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 2068227569Sphilip#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 2069227569Sphilip#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 2070227569Sphilip#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 2071227569Sphilip#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 2072227569Sphilip#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 2073227569Sphilip#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 2074227569Sphilip#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 2075227569Sphilip 2076227569Sphilip 2077227569Sphilip/* 2078227569Sphilip * FR_AB_TX_IPFIL_TBL(128bit): 2079227569Sphilip * Transmit IP source address filter table 2080227569Sphilip */ 2081227569Sphilip#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 2082227569Sphilip/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2083227569Sphilip#define FR_AB_TX_IPFIL_TBL_STEP 16 2084227569Sphilip#define FR_AB_TX_IPFIL_TBL_ROWS 16 2085227569Sphilip 2086227569Sphilip#define FRF_AB_TX_IPFIL_MASK_1_LBN 96 2087227569Sphilip#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 2088227569Sphilip#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 2089227569Sphilip#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 2090227569Sphilip#define FRF_AB_TX_IPFIL_MASK_0_LBN 32 2091227569Sphilip#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 2092227569Sphilip#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 2093227569Sphilip#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 2094227569Sphilip 2095227569Sphilip 2096227569Sphilip/* 2097227569Sphilip * FR_AB_MD_TXD_REG(128bit): 2098227569Sphilip * PHY management transmit data register 2099227569Sphilip */ 2100227569Sphilip#define FR_AB_MD_TXD_REG_OFST 0x00000c00 2101227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2102227569Sphilip 2103227569Sphilip#define FRF_AB_MD_TXD_LBN 0 2104227569Sphilip#define FRF_AB_MD_TXD_WIDTH 16 2105227569Sphilip 2106227569Sphilip 2107227569Sphilip/* 2108227569Sphilip * FR_AB_MD_RXD_REG(128bit): 2109227569Sphilip * PHY management receive data register 2110227569Sphilip */ 2111227569Sphilip#define FR_AB_MD_RXD_REG_OFST 0x00000c10 2112227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2113227569Sphilip 2114227569Sphilip#define FRF_AB_MD_RXD_LBN 0 2115227569Sphilip#define FRF_AB_MD_RXD_WIDTH 16 2116227569Sphilip 2117227569Sphilip 2118227569Sphilip/* 2119227569Sphilip * FR_AB_MD_CS_REG(128bit): 2120227569Sphilip * PHY management configuration & status register 2121227569Sphilip */ 2122227569Sphilip#define FR_AB_MD_CS_REG_OFST 0x00000c20 2123227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2124227569Sphilip 2125227569Sphilip#define FRF_AB_MD_RD_EN_LBN 15 2126227569Sphilip#define FRF_AB_MD_RD_EN_WIDTH 1 2127227569Sphilip#define FRF_AB_MD_WR_EN_LBN 14 2128227569Sphilip#define FRF_AB_MD_WR_EN_WIDTH 1 2129227569Sphilip#define FRF_AB_MD_ADDR_CMD_LBN 13 2130227569Sphilip#define FRF_AB_MD_ADDR_CMD_WIDTH 1 2131227569Sphilip#define FRF_AB_MD_PT_LBN 7 2132227569Sphilip#define FRF_AB_MD_PT_WIDTH 3 2133227569Sphilip#define FRF_AB_MD_PL_LBN 6 2134227569Sphilip#define FRF_AB_MD_PL_WIDTH 1 2135227569Sphilip#define FRF_AB_MD_INT_CLR_LBN 5 2136227569Sphilip#define FRF_AB_MD_INT_CLR_WIDTH 1 2137227569Sphilip#define FRF_AB_MD_GC_LBN 4 2138227569Sphilip#define FRF_AB_MD_GC_WIDTH 1 2139227569Sphilip#define FRF_AB_MD_PRSP_LBN 3 2140227569Sphilip#define FRF_AB_MD_PRSP_WIDTH 1 2141227569Sphilip#define FRF_AB_MD_RIC_LBN 2 2142227569Sphilip#define FRF_AB_MD_RIC_WIDTH 1 2143227569Sphilip#define FRF_AB_MD_RDC_LBN 1 2144227569Sphilip#define FRF_AB_MD_RDC_WIDTH 1 2145227569Sphilip#define FRF_AB_MD_WRC_LBN 0 2146227569Sphilip#define FRF_AB_MD_WRC_WIDTH 1 2147227569Sphilip 2148227569Sphilip 2149227569Sphilip/* 2150227569Sphilip * FR_AB_MD_PHY_ADR_REG(128bit): 2151227569Sphilip * PHY management PHY address register 2152227569Sphilip */ 2153227569Sphilip#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 2154227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2155227569Sphilip 2156227569Sphilip#define FRF_AB_MD_PHY_ADR_LBN 0 2157227569Sphilip#define FRF_AB_MD_PHY_ADR_WIDTH 16 2158227569Sphilip 2159227569Sphilip 2160227569Sphilip/* 2161227569Sphilip * FR_AB_MD_ID_REG(128bit): 2162227569Sphilip * PHY management ID register 2163227569Sphilip */ 2164227569Sphilip#define FR_AB_MD_ID_REG_OFST 0x00000c40 2165227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2166227569Sphilip 2167227569Sphilip#define FRF_AB_MD_PRT_ADR_LBN 11 2168227569Sphilip#define FRF_AB_MD_PRT_ADR_WIDTH 5 2169227569Sphilip#define FRF_AB_MD_DEV_ADR_LBN 6 2170227569Sphilip#define FRF_AB_MD_DEV_ADR_WIDTH 5 2171227569Sphilip 2172227569Sphilip 2173227569Sphilip/* 2174227569Sphilip * FR_AB_MD_STAT_REG(128bit): 2175227569Sphilip * PHY management status & mask register 2176227569Sphilip */ 2177227569Sphilip#define FR_AB_MD_STAT_REG_OFST 0x00000c50 2178227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2179227569Sphilip 2180227569Sphilip#define FRF_AB_MD_PINT_LBN 4 2181227569Sphilip#define FRF_AB_MD_PINT_WIDTH 1 2182227569Sphilip#define FRF_AB_MD_DONE_LBN 3 2183227569Sphilip#define FRF_AB_MD_DONE_WIDTH 1 2184227569Sphilip#define FRF_AB_MD_BSERR_LBN 2 2185227569Sphilip#define FRF_AB_MD_BSERR_WIDTH 1 2186227569Sphilip#define FRF_AB_MD_LNFL_LBN 1 2187227569Sphilip#define FRF_AB_MD_LNFL_WIDTH 1 2188227569Sphilip#define FRF_AB_MD_BSY_LBN 0 2189227569Sphilip#define FRF_AB_MD_BSY_WIDTH 1 2190227569Sphilip 2191227569Sphilip 2192227569Sphilip/* 2193227569Sphilip * FR_AB_MAC_STAT_DMA_REG(128bit): 2194227569Sphilip * Port MAC statistical counter DMA register 2195227569Sphilip */ 2196227569Sphilip#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 2197227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2198227569Sphilip 2199227569Sphilip#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 2200227569Sphilip#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 2201227569Sphilip#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 2202227569Sphilip#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 2203227569Sphilip#define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 2204227569Sphilip#define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 2205227569Sphilip#define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 2206227569Sphilip#define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 2207227569Sphilip 2208227569Sphilip 2209227569Sphilip/* 2210227569Sphilip * FR_AB_MAC_CTRL_REG(128bit): 2211227569Sphilip * Port MAC control register 2212227569Sphilip */ 2213227569Sphilip#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 2214227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2215227569Sphilip 2216227569Sphilip#define FRF_AB_MAC_XOFF_VAL_LBN 16 2217227569Sphilip#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 2218227569Sphilip#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 2219227569Sphilip#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 2220227569Sphilip#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 2221227569Sphilip#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 2222227569Sphilip#define FRF_AB_MAC_BCAD_ACPT_LBN 4 2223227569Sphilip#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 2224227569Sphilip#define FRF_AB_MAC_UC_PROM_LBN 3 2225227569Sphilip#define FRF_AB_MAC_UC_PROM_WIDTH 1 2226227569Sphilip#define FRF_AB_MAC_LINK_STATUS_LBN 2 2227227569Sphilip#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 2228227569Sphilip#define FRF_AB_MAC_SPEED_LBN 0 2229227569Sphilip#define FRF_AB_MAC_SPEED_WIDTH 2 2230227569Sphilip#define FRF_AB_MAC_SPEED_10M 0 2231227569Sphilip#define FRF_AB_MAC_SPEED_100M 1 2232227569Sphilip#define FRF_AB_MAC_SPEED_1G 2 2233227569Sphilip#define FRF_AB_MAC_SPEED_10G 3 2234227569Sphilip 2235227569Sphilip/* 2236227569Sphilip * FR_BB_GEN_MODE_REG(128bit): 2237227569Sphilip * General Purpose mode register (external interrupt mask) 2238227569Sphilip */ 2239227569Sphilip#define FR_BB_GEN_MODE_REG_OFST 0x00000c90 2240227569Sphilip/* falconb0=net_func_bar2 */ 2241227569Sphilip 2242227569Sphilip#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 2243227569Sphilip#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 2244227569Sphilip#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 2245227569Sphilip#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 2246227569Sphilip#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 2247227569Sphilip#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 2248227569Sphilip#define FRF_BB_XG_PHY_INT_MASK_LBN 0 2249227569Sphilip#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 2250227569Sphilip 2251227569Sphilip 2252227569Sphilip/* 2253227569Sphilip * FR_AB_MAC_MC_HASH_REG0(128bit): 2254227569Sphilip * Multicast address hash table 2255227569Sphilip */ 2256227569Sphilip#define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 2257227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2258227569Sphilip 2259227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_LBN 0 2260227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 2261227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 2262227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 2263227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 2264227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 2265227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 2266227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 2267227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 2268227569Sphilip#define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 2269227569Sphilip 2270227569Sphilip 2271227569Sphilip/* 2272227569Sphilip * FR_AB_MAC_MC_HASH_REG1(128bit): 2273227569Sphilip * Multicast address hash table 2274227569Sphilip */ 2275227569Sphilip#define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 2276227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2277227569Sphilip 2278227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_LBN 0 2279227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 2280227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 2281227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 2282227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 2283227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 2284227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 2285227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 2286227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 2287227569Sphilip#define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 2288227569Sphilip 2289227569Sphilip 2290227569Sphilip/* 2291227569Sphilip * FR_AB_GM_CFG1_REG(32bit): 2292227569Sphilip * GMAC configuration register 1 2293227569Sphilip */ 2294227569Sphilip#define FR_AB_GM_CFG1_REG_OFST 0x00000e00 2295227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2296227569Sphilip 2297227569Sphilip#define FRF_AB_GM_SW_RST_LBN 31 2298227569Sphilip#define FRF_AB_GM_SW_RST_WIDTH 1 2299227569Sphilip#define FRF_AB_GM_SIM_RST_LBN 30 2300227569Sphilip#define FRF_AB_GM_SIM_RST_WIDTH 1 2301227569Sphilip#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 2302227569Sphilip#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 2303227569Sphilip#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 2304227569Sphilip#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 2305227569Sphilip#define FRF_AB_GM_RST_RX_FUNC_LBN 17 2306227569Sphilip#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 2307227569Sphilip#define FRF_AB_GM_RST_TX_FUNC_LBN 16 2308227569Sphilip#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 2309227569Sphilip#define FRF_AB_GM_LOOP_LBN 8 2310227569Sphilip#define FRF_AB_GM_LOOP_WIDTH 1 2311227569Sphilip#define FRF_AB_GM_RX_FC_EN_LBN 5 2312227569Sphilip#define FRF_AB_GM_RX_FC_EN_WIDTH 1 2313227569Sphilip#define FRF_AB_GM_TX_FC_EN_LBN 4 2314227569Sphilip#define FRF_AB_GM_TX_FC_EN_WIDTH 1 2315227569Sphilip#define FRF_AB_GM_SYNC_RXEN_LBN 3 2316227569Sphilip#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 2317227569Sphilip#define FRF_AB_GM_RX_EN_LBN 2 2318227569Sphilip#define FRF_AB_GM_RX_EN_WIDTH 1 2319227569Sphilip#define FRF_AB_GM_SYNC_TXEN_LBN 1 2320227569Sphilip#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 2321227569Sphilip#define FRF_AB_GM_TX_EN_LBN 0 2322227569Sphilip#define FRF_AB_GM_TX_EN_WIDTH 1 2323227569Sphilip 2324227569Sphilip 2325227569Sphilip/* 2326227569Sphilip * FR_AB_GM_CFG2_REG(32bit): 2327227569Sphilip * GMAC configuration register 2 2328227569Sphilip */ 2329227569Sphilip#define FR_AB_GM_CFG2_REG_OFST 0x00000e10 2330227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2331227569Sphilip 2332227569Sphilip#define FRF_AB_GM_PAMBL_LEN_LBN 12 2333227569Sphilip#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 2334227569Sphilip#define FRF_AB_GM_IF_MODE_LBN 8 2335227569Sphilip#define FRF_AB_GM_IF_MODE_WIDTH 2 2336227569Sphilip#define FRF_AB_GM_IF_MODE_BYTE_MODE 2 2337227569Sphilip#define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 2338227569Sphilip#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 2339227569Sphilip#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 2340227569Sphilip#define FRF_AB_GM_LEN_CHK_LBN 4 2341227569Sphilip#define FRF_AB_GM_LEN_CHK_WIDTH 1 2342227569Sphilip#define FRF_AB_GM_PAD_CRC_EN_LBN 2 2343227569Sphilip#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 2344227569Sphilip#define FRF_AB_GM_CRC_EN_LBN 1 2345227569Sphilip#define FRF_AB_GM_CRC_EN_WIDTH 1 2346227569Sphilip#define FRF_AB_GM_FD_LBN 0 2347227569Sphilip#define FRF_AB_GM_FD_WIDTH 1 2348227569Sphilip 2349227569Sphilip 2350227569Sphilip/* 2351227569Sphilip * FR_AB_GM_IPG_REG(32bit): 2352227569Sphilip * GMAC IPG register 2353227569Sphilip */ 2354227569Sphilip#define FR_AB_GM_IPG_REG_OFST 0x00000e20 2355227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2356227569Sphilip 2357227569Sphilip#define FRF_AB_GM_NONB2B_IPG1_LBN 24 2358227569Sphilip#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 2359227569Sphilip#define FRF_AB_GM_NONB2B_IPG2_LBN 16 2360227569Sphilip#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 2361227569Sphilip#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 2362227569Sphilip#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 2363227569Sphilip#define FRF_AB_GM_B2B_IPG_LBN 0 2364227569Sphilip#define FRF_AB_GM_B2B_IPG_WIDTH 7 2365227569Sphilip 2366227569Sphilip 2367227569Sphilip/* 2368227569Sphilip * FR_AB_GM_HD_REG(32bit): 2369227569Sphilip * GMAC half duplex register 2370227569Sphilip */ 2371227569Sphilip#define FR_AB_GM_HD_REG_OFST 0x00000e30 2372227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2373227569Sphilip 2374227569Sphilip#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 2375227569Sphilip#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 2376227569Sphilip#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 2377227569Sphilip#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 2378227569Sphilip#define FRF_AB_GM_BP_NO_BOFF_LBN 18 2379227569Sphilip#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 2380227569Sphilip#define FRF_AB_GM_DIS_BOFF_LBN 17 2381227569Sphilip#define FRF_AB_GM_DIS_BOFF_WIDTH 1 2382227569Sphilip#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 2383227569Sphilip#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 2384227569Sphilip#define FRF_AB_GM_RTRY_LIMIT_LBN 12 2385227569Sphilip#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 2386227569Sphilip#define FRF_AB_GM_COL_WIN_LBN 0 2387227569Sphilip#define FRF_AB_GM_COL_WIN_WIDTH 10 2388227569Sphilip 2389227569Sphilip 2390227569Sphilip/* 2391227569Sphilip * FR_AB_GM_MAX_FLEN_REG(32bit): 2392227569Sphilip * GMAC maximum frame length register 2393227569Sphilip */ 2394227569Sphilip#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 2395227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2396227569Sphilip 2397227569Sphilip#define FRF_AB_GM_MAX_FLEN_LBN 0 2398227569Sphilip#define FRF_AB_GM_MAX_FLEN_WIDTH 16 2399227569Sphilip 2400227569Sphilip 2401227569Sphilip/* 2402227569Sphilip * FR_AB_GM_TEST_REG(32bit): 2403227569Sphilip * GMAC test register 2404227569Sphilip */ 2405227569Sphilip#define FR_AB_GM_TEST_REG_OFST 0x00000e70 2406227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2407227569Sphilip 2408227569Sphilip#define FRF_AB_GM_MAX_BOFF_LBN 3 2409227569Sphilip#define FRF_AB_GM_MAX_BOFF_WIDTH 1 2410227569Sphilip#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 2411227569Sphilip#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 2412227569Sphilip#define FRF_AB_GM_TEST_PAUSE_LBN 1 2413227569Sphilip#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 2414227569Sphilip#define FRF_AB_GM_SHORT_SLOT_LBN 0 2415227569Sphilip#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 2416227569Sphilip 2417227569Sphilip 2418227569Sphilip/* 2419227569Sphilip * FR_AB_GM_ADR1_REG(32bit): 2420227569Sphilip * GMAC station address register 1 2421227569Sphilip */ 2422227569Sphilip#define FR_AB_GM_ADR1_REG_OFST 0x00000f00 2423227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2424227569Sphilip 2425227569Sphilip#define FRF_AB_GM_ADR_B0_LBN 24 2426227569Sphilip#define FRF_AB_GM_ADR_B0_WIDTH 8 2427227569Sphilip#define FRF_AB_GM_ADR_B1_LBN 16 2428227569Sphilip#define FRF_AB_GM_ADR_B1_WIDTH 8 2429227569Sphilip#define FRF_AB_GM_ADR_B2_LBN 8 2430227569Sphilip#define FRF_AB_GM_ADR_B2_WIDTH 8 2431227569Sphilip#define FRF_AB_GM_ADR_B3_LBN 0 2432227569Sphilip#define FRF_AB_GM_ADR_B3_WIDTH 8 2433227569Sphilip 2434227569Sphilip 2435227569Sphilip/* 2436227569Sphilip * FR_AB_GM_ADR2_REG(32bit): 2437227569Sphilip * GMAC station address register 2 2438227569Sphilip */ 2439227569Sphilip#define FR_AB_GM_ADR2_REG_OFST 0x00000f10 2440227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2441227569Sphilip 2442227569Sphilip#define FRF_AB_GM_ADR_B4_LBN 24 2443227569Sphilip#define FRF_AB_GM_ADR_B4_WIDTH 8 2444227569Sphilip#define FRF_AB_GM_ADR_B5_LBN 16 2445227569Sphilip#define FRF_AB_GM_ADR_B5_WIDTH 8 2446227569Sphilip 2447227569Sphilip 2448227569Sphilip/* 2449227569Sphilip * FR_AB_GMF_CFG0_REG(32bit): 2450227569Sphilip * GMAC FIFO configuration register 0 2451227569Sphilip */ 2452227569Sphilip#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 2453227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2454227569Sphilip 2455227569Sphilip#define FRF_AB_GMF_FTFENRPLY_LBN 20 2456227569Sphilip#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 2457227569Sphilip#define FRF_AB_GMF_STFENRPLY_LBN 19 2458227569Sphilip#define FRF_AB_GMF_STFENRPLY_WIDTH 1 2459227569Sphilip#define FRF_AB_GMF_FRFENRPLY_LBN 18 2460227569Sphilip#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 2461227569Sphilip#define FRF_AB_GMF_SRFENRPLY_LBN 17 2462227569Sphilip#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 2463227569Sphilip#define FRF_AB_GMF_WTMENRPLY_LBN 16 2464227569Sphilip#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 2465227569Sphilip#define FRF_AB_GMF_FTFENREQ_LBN 12 2466227569Sphilip#define FRF_AB_GMF_FTFENREQ_WIDTH 1 2467227569Sphilip#define FRF_AB_GMF_STFENREQ_LBN 11 2468227569Sphilip#define FRF_AB_GMF_STFENREQ_WIDTH 1 2469227569Sphilip#define FRF_AB_GMF_FRFENREQ_LBN 10 2470227569Sphilip#define FRF_AB_GMF_FRFENREQ_WIDTH 1 2471227569Sphilip#define FRF_AB_GMF_SRFENREQ_LBN 9 2472227569Sphilip#define FRF_AB_GMF_SRFENREQ_WIDTH 1 2473227569Sphilip#define FRF_AB_GMF_WTMENREQ_LBN 8 2474227569Sphilip#define FRF_AB_GMF_WTMENREQ_WIDTH 1 2475227569Sphilip#define FRF_AB_GMF_HSTRSTFT_LBN 4 2476227569Sphilip#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 2477227569Sphilip#define FRF_AB_GMF_HSTRSTST_LBN 3 2478227569Sphilip#define FRF_AB_GMF_HSTRSTST_WIDTH 1 2479227569Sphilip#define FRF_AB_GMF_HSTRSTFR_LBN 2 2480227569Sphilip#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 2481227569Sphilip#define FRF_AB_GMF_HSTRSTSR_LBN 1 2482227569Sphilip#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 2483227569Sphilip#define FRF_AB_GMF_HSTRSTWT_LBN 0 2484227569Sphilip#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 2485227569Sphilip 2486227569Sphilip 2487227569Sphilip/* 2488227569Sphilip * FR_AB_GMF_CFG1_REG(32bit): 2489227569Sphilip * GMAC FIFO configuration register 1 2490227569Sphilip */ 2491227569Sphilip#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 2492227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2493227569Sphilip 2494227569Sphilip#define FRF_AB_GMF_CFGFRTH_LBN 16 2495227569Sphilip#define FRF_AB_GMF_CFGFRTH_WIDTH 5 2496227569Sphilip#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 2497227569Sphilip#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 2498227569Sphilip 2499227569Sphilip 2500227569Sphilip/* 2501227569Sphilip * FR_AB_GMF_CFG2_REG(32bit): 2502227569Sphilip * GMAC FIFO configuration register 2 2503227569Sphilip */ 2504227569Sphilip#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 2505227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2506227569Sphilip 2507227569Sphilip#define FRF_AB_GMF_CFGHWM_LBN 16 2508227569Sphilip#define FRF_AB_GMF_CFGHWM_WIDTH 6 2509227569Sphilip#define FRF_AB_GMF_CFGLWM_LBN 0 2510227569Sphilip#define FRF_AB_GMF_CFGLWM_WIDTH 6 2511227569Sphilip 2512227569Sphilip 2513227569Sphilip/* 2514227569Sphilip * FR_AB_GMF_CFG3_REG(32bit): 2515227569Sphilip * GMAC FIFO configuration register 3 2516227569Sphilip */ 2517227569Sphilip#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 2518227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2519227569Sphilip 2520227569Sphilip#define FRF_AB_GMF_CFGHWMFT_LBN 16 2521227569Sphilip#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 2522227569Sphilip#define FRF_AB_GMF_CFGFTTH_LBN 0 2523227569Sphilip#define FRF_AB_GMF_CFGFTTH_WIDTH 6 2524227569Sphilip 2525227569Sphilip 2526227569Sphilip/* 2527227569Sphilip * FR_AB_GMF_CFG4_REG(32bit): 2528227569Sphilip * GMAC FIFO configuration register 4 2529227569Sphilip */ 2530227569Sphilip#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 2531227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2532227569Sphilip 2533227569Sphilip#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 2534227569Sphilip#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 2535227569Sphilip 2536227569Sphilip 2537227569Sphilip/* 2538227569Sphilip * FR_AB_GMF_CFG5_REG(32bit): 2539227569Sphilip * GMAC FIFO configuration register 5 2540227569Sphilip */ 2541227569Sphilip#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 2542227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2543227569Sphilip 2544227569Sphilip#define FRF_AB_GMF_CFGHDPLX_LBN 22 2545227569Sphilip#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 2546227569Sphilip#define FRF_AB_GMF_SRFULL_LBN 21 2547227569Sphilip#define FRF_AB_GMF_SRFULL_WIDTH 1 2548227569Sphilip#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 2549227569Sphilip#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 2550227569Sphilip#define FRF_AB_GMF_CFGBYTMODE_LBN 19 2551227569Sphilip#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 2552227569Sphilip#define FRF_AB_GMF_HSTDRPLT64_LBN 18 2553227569Sphilip#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 2554227569Sphilip#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 2555227569Sphilip#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 2556227569Sphilip 2557227569Sphilip 2558227569Sphilip/* 2559227569Sphilip * FR_BB_TX_SRC_MAC_TBL(128bit): 2560227569Sphilip * Transmit IP source address filter table 2561227569Sphilip */ 2562227569Sphilip#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 2563227569Sphilip/* falconb0=net_func_bar2 */ 2564227569Sphilip#define FR_BB_TX_SRC_MAC_TBL_STEP 16 2565227569Sphilip#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 2566227569Sphilip 2567227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 2568227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 2569227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 2570227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 2571227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 2572227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 2573227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 2574227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 2575227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 2576227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 2577227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 2578227569Sphilip#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 2579227569Sphilip 2580227569Sphilip 2581227569Sphilip/* 2582227569Sphilip * FR_BB_TX_SRC_MAC_CTL_REG(128bit): 2583227569Sphilip * Transmit MAC source address filter control 2584227569Sphilip */ 2585227569Sphilip#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 2586227569Sphilip/* falconb0=net_func_bar2 */ 2587227569Sphilip 2588227569Sphilip#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 2589227569Sphilip#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 2590227569Sphilip#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 2591227569Sphilip#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 2592227569Sphilip#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 2593227569Sphilip#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 2594227569Sphilip#define FRF_BB_TX_MAC_QID_SEL_LBN 0 2595227569Sphilip#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 2596227569Sphilip 2597227569Sphilip 2598227569Sphilip/* 2599227569Sphilip * FR_AB_XM_ADR_LO_REG(128bit): 2600227569Sphilip * XGMAC address register low 2601227569Sphilip */ 2602227569Sphilip#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 2603227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2604227569Sphilip 2605227569Sphilip#define FRF_AB_XM_ADR_LO_LBN 0 2606227569Sphilip#define FRF_AB_XM_ADR_LO_WIDTH 32 2607227569Sphilip 2608227569Sphilip 2609227569Sphilip/* 2610227569Sphilip * FR_AB_XM_ADR_HI_REG(128bit): 2611227569Sphilip * XGMAC address register high 2612227569Sphilip */ 2613227569Sphilip#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 2614227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2615227569Sphilip 2616227569Sphilip#define FRF_AB_XM_ADR_HI_LBN 0 2617227569Sphilip#define FRF_AB_XM_ADR_HI_WIDTH 16 2618227569Sphilip 2619227569Sphilip 2620227569Sphilip/* 2621227569Sphilip * FR_AB_XM_GLB_CFG_REG(128bit): 2622227569Sphilip * XGMAC global configuration 2623227569Sphilip */ 2624227569Sphilip#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 2625227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2626227569Sphilip 2627227569Sphilip#define FRF_AB_XM_RMTFLT_GEN_LBN 17 2628227569Sphilip#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 2629227569Sphilip#define FRF_AB_XM_DEBUG_MODE_LBN 16 2630227569Sphilip#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 2631227569Sphilip#define FRF_AB_XM_RX_STAT_EN_LBN 11 2632227569Sphilip#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 2633227569Sphilip#define FRF_AB_XM_TX_STAT_EN_LBN 10 2634227569Sphilip#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 2635227569Sphilip#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 2636227569Sphilip#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 2637227569Sphilip#define FRF_AB_XM_WAN_MODE_LBN 5 2638227569Sphilip#define FRF_AB_XM_WAN_MODE_WIDTH 1 2639227569Sphilip#define FRF_AB_XM_INTCLR_MODE_LBN 3 2640227569Sphilip#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 2641227569Sphilip#define FRF_AB_XM_CORE_RST_LBN 0 2642227569Sphilip#define FRF_AB_XM_CORE_RST_WIDTH 1 2643227569Sphilip 2644227569Sphilip 2645227569Sphilip/* 2646227569Sphilip * FR_AB_XM_TX_CFG_REG(128bit): 2647227569Sphilip * XGMAC transmit configuration 2648227569Sphilip */ 2649227569Sphilip#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 2650227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2651227569Sphilip 2652227569Sphilip#define FRF_AB_XM_TX_PROG_LBN 24 2653227569Sphilip#define FRF_AB_XM_TX_PROG_WIDTH 1 2654227569Sphilip#define FRF_AB_XM_IPG_LBN 16 2655227569Sphilip#define FRF_AB_XM_IPG_WIDTH 4 2656227569Sphilip#define FRF_AB_XM_FCNTL_LBN 10 2657227569Sphilip#define FRF_AB_XM_FCNTL_WIDTH 1 2658227569Sphilip#define FRF_AB_XM_TXCRC_LBN 8 2659227569Sphilip#define FRF_AB_XM_TXCRC_WIDTH 1 2660227569Sphilip#define FRF_AB_XM_EDRC_LBN 6 2661227569Sphilip#define FRF_AB_XM_EDRC_WIDTH 1 2662227569Sphilip#define FRF_AB_XM_AUTO_PAD_LBN 5 2663227569Sphilip#define FRF_AB_XM_AUTO_PAD_WIDTH 1 2664227569Sphilip#define FRF_AB_XM_TX_PRMBL_LBN 2 2665227569Sphilip#define FRF_AB_XM_TX_PRMBL_WIDTH 1 2666227569Sphilip#define FRF_AB_XM_TXEN_LBN 1 2667227569Sphilip#define FRF_AB_XM_TXEN_WIDTH 1 2668227569Sphilip#define FRF_AB_XM_TX_RST_LBN 0 2669227569Sphilip#define FRF_AB_XM_TX_RST_WIDTH 1 2670227569Sphilip 2671227569Sphilip 2672227569Sphilip/* 2673227569Sphilip * FR_AB_XM_RX_CFG_REG(128bit): 2674227569Sphilip * XGMAC receive configuration 2675227569Sphilip */ 2676227569Sphilip#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 2677227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2678227569Sphilip 2679227569Sphilip#define FRF_AB_XM_PASS_LENERR_LBN 26 2680227569Sphilip#define FRF_AB_XM_PASS_LENERR_WIDTH 1 2681227569Sphilip#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 2682227569Sphilip#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 2683227569Sphilip#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 2684227569Sphilip#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 2685227569Sphilip#define FRF_AB_XM_REJ_BCAST_LBN 20 2686227569Sphilip#define FRF_AB_XM_REJ_BCAST_WIDTH 1 2687227569Sphilip#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 2688227569Sphilip#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 2689227569Sphilip#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 2690227569Sphilip#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 2691227569Sphilip#define FRF_AB_XM_AUTO_DEPAD_LBN 8 2692227569Sphilip#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 2693227569Sphilip#define FRF_AB_XM_RXCRC_LBN 3 2694227569Sphilip#define FRF_AB_XM_RXCRC_WIDTH 1 2695227569Sphilip#define FRF_AB_XM_RX_PRMBL_LBN 2 2696227569Sphilip#define FRF_AB_XM_RX_PRMBL_WIDTH 1 2697227569Sphilip#define FRF_AB_XM_RXEN_LBN 1 2698227569Sphilip#define FRF_AB_XM_RXEN_WIDTH 1 2699227569Sphilip#define FRF_AB_XM_RX_RST_LBN 0 2700227569Sphilip#define FRF_AB_XM_RX_RST_WIDTH 1 2701227569Sphilip 2702227569Sphilip 2703227569Sphilip/* 2704227569Sphilip * FR_AB_XM_MGT_INT_MASK(128bit): 2705227569Sphilip * documentation to be written for sum_XM_MGT_INT_MASK 2706227569Sphilip */ 2707227569Sphilip#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 2708227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2709227569Sphilip 2710227569Sphilip#define FRF_AB_XM_MSK_STA_INTR_LBN 16 2711227569Sphilip#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 2712227569Sphilip#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 2713227569Sphilip#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 2714227569Sphilip#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 2715227569Sphilip#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 2716227569Sphilip#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 2717227569Sphilip#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 2718227569Sphilip#define FRF_AB_XM_MSK_RMTFLT_LBN 1 2719227569Sphilip#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 2720227569Sphilip#define FRF_AB_XM_MSK_LCLFLT_LBN 0 2721227569Sphilip#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 2722227569Sphilip 2723227569Sphilip 2724227569Sphilip/* 2725227569Sphilip * FR_AB_XM_FC_REG(128bit): 2726227569Sphilip * XGMAC flow control register 2727227569Sphilip */ 2728227569Sphilip#define FR_AB_XM_FC_REG_OFST 0x00001270 2729227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2730227569Sphilip 2731227569Sphilip#define FRF_AB_XM_PAUSE_TIME_LBN 16 2732227569Sphilip#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 2733227569Sphilip#define FRF_AB_XM_RX_MAC_STAT_LBN 11 2734227569Sphilip#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 2735227569Sphilip#define FRF_AB_XM_TX_MAC_STAT_LBN 10 2736227569Sphilip#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 2737227569Sphilip#define FRF_AB_XM_MCNTL_PASS_LBN 8 2738227569Sphilip#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 2739227569Sphilip#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 2740227569Sphilip#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 2741227569Sphilip#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 2742227569Sphilip#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 2743227569Sphilip#define FRF_AB_XM_ZPAUSE_LBN 2 2744227569Sphilip#define FRF_AB_XM_ZPAUSE_WIDTH 1 2745227569Sphilip#define FRF_AB_XM_XMIT_PAUSE_LBN 1 2746227569Sphilip#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 2747227569Sphilip#define FRF_AB_XM_DIS_FCNTL_LBN 0 2748227569Sphilip#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 2749227569Sphilip 2750227569Sphilip 2751227569Sphilip/* 2752227569Sphilip * FR_AB_XM_PAUSE_TIME_REG(128bit): 2753227569Sphilip * XGMAC pause time register 2754227569Sphilip */ 2755227569Sphilip#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 2756227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2757227569Sphilip 2758227569Sphilip#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 2759227569Sphilip#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 2760227569Sphilip#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 2761227569Sphilip#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 2762227569Sphilip 2763227569Sphilip 2764227569Sphilip/* 2765227569Sphilip * FR_AB_XM_TX_PARAM_REG(128bit): 2766227569Sphilip * XGMAC transmit parameter register 2767227569Sphilip */ 2768227569Sphilip#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 2769227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2770227569Sphilip 2771227569Sphilip#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 2772227569Sphilip#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 2773227569Sphilip#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 2774227569Sphilip#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 2775227569Sphilip#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 2776227569Sphilip#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 2777227569Sphilip#define FRF_AB_XM_PAD_CHAR_LBN 0 2778227569Sphilip#define FRF_AB_XM_PAD_CHAR_WIDTH 8 2779227569Sphilip 2780227569Sphilip 2781227569Sphilip/* 2782227569Sphilip * FR_AB_XM_RX_PARAM_REG(128bit): 2783227569Sphilip * XGMAC receive parameter register 2784227569Sphilip */ 2785227569Sphilip#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 2786227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2787227569Sphilip 2788227569Sphilip#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 2789227569Sphilip#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 2790227569Sphilip#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 2791227569Sphilip#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 2792227569Sphilip 2793227569Sphilip 2794227569Sphilip/* 2795227569Sphilip * FR_AB_XM_MGT_INT_MSK_REG(128bit): 2796227569Sphilip * XGMAC management interrupt mask register 2797227569Sphilip */ 2798227569Sphilip#define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 2799227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2800227569Sphilip 2801227569Sphilip#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 2802227569Sphilip#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 2803227569Sphilip#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 2804227569Sphilip#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 2805227569Sphilip#define FRF_AB_XM_PRMBLE_ERR_LBN 2 2806227569Sphilip#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 2807227569Sphilip#define FRF_AB_XM_RMTFLT_LBN 1 2808227569Sphilip#define FRF_AB_XM_RMTFLT_WIDTH 1 2809227569Sphilip#define FRF_AB_XM_LCLFLT_LBN 0 2810227569Sphilip#define FRF_AB_XM_LCLFLT_WIDTH 1 2811227569Sphilip 2812227569Sphilip 2813227569Sphilip/* 2814227569Sphilip * FR_AB_XX_PWR_RST_REG(128bit): 2815227569Sphilip * XGXS/XAUI powerdown/reset register 2816227569Sphilip */ 2817227569Sphilip#define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 2818227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2819227569Sphilip 2820227569Sphilip#define FRF_AB_XX_PWRDND_SIG_LBN 31 2821227569Sphilip#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 2822227569Sphilip#define FRF_AB_XX_PWRDNC_SIG_LBN 30 2823227569Sphilip#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 2824227569Sphilip#define FRF_AB_XX_PWRDNB_SIG_LBN 29 2825227569Sphilip#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 2826227569Sphilip#define FRF_AB_XX_PWRDNA_SIG_LBN 28 2827227569Sphilip#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 2828227569Sphilip#define FRF_AB_XX_SIM_MODE_LBN 27 2829227569Sphilip#define FRF_AB_XX_SIM_MODE_WIDTH 1 2830227569Sphilip#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 2831227569Sphilip#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 2832227569Sphilip#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 2833227569Sphilip#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 2834227569Sphilip#define FRF_AB_XX_RESETD_SIG_LBN 23 2835227569Sphilip#define FRF_AB_XX_RESETD_SIG_WIDTH 1 2836227569Sphilip#define FRF_AB_XX_RESETC_SIG_LBN 22 2837227569Sphilip#define FRF_AB_XX_RESETC_SIG_WIDTH 1 2838227569Sphilip#define FRF_AB_XX_RESETB_SIG_LBN 21 2839227569Sphilip#define FRF_AB_XX_RESETB_SIG_WIDTH 1 2840227569Sphilip#define FRF_AB_XX_RESETA_SIG_LBN 20 2841227569Sphilip#define FRF_AB_XX_RESETA_SIG_WIDTH 1 2842227569Sphilip#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 2843227569Sphilip#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 2844227569Sphilip#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 2845227569Sphilip#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 2846227569Sphilip#define FRF_AB_XX_SD_RST_ACT_LBN 16 2847227569Sphilip#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 2848227569Sphilip#define FRF_AB_XX_PWRDND_EN_LBN 15 2849227569Sphilip#define FRF_AB_XX_PWRDND_EN_WIDTH 1 2850227569Sphilip#define FRF_AB_XX_PWRDNC_EN_LBN 14 2851227569Sphilip#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 2852227569Sphilip#define FRF_AB_XX_PWRDNB_EN_LBN 13 2853227569Sphilip#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 2854227569Sphilip#define FRF_AB_XX_PWRDNA_EN_LBN 12 2855227569Sphilip#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2856227569Sphilip#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2857227569Sphilip#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2858227569Sphilip#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2859227569Sphilip#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2860227569Sphilip#define FRF_AB_XX_RESETD_EN_LBN 7 2861227569Sphilip#define FRF_AB_XX_RESETD_EN_WIDTH 1 2862227569Sphilip#define FRF_AB_XX_RESETC_EN_LBN 6 2863227569Sphilip#define FRF_AB_XX_RESETC_EN_WIDTH 1 2864227569Sphilip#define FRF_AB_XX_RESETB_EN_LBN 5 2865227569Sphilip#define FRF_AB_XX_RESETB_EN_WIDTH 1 2866227569Sphilip#define FRF_AB_XX_RESETA_EN_LBN 4 2867227569Sphilip#define FRF_AB_XX_RESETA_EN_WIDTH 1 2868227569Sphilip#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2869227569Sphilip#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2870227569Sphilip#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2871227569Sphilip#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2872227569Sphilip#define FRF_AB_XX_RST_XX_EN_LBN 0 2873227569Sphilip#define FRF_AB_XX_RST_XX_EN_WIDTH 1 2874227569Sphilip 2875227569Sphilip 2876227569Sphilip/* 2877227569Sphilip * FR_AB_XX_SD_CTL_REG(128bit): 2878227569Sphilip * XGXS/XAUI powerdown/reset control register 2879227569Sphilip */ 2880227569Sphilip#define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 2881227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2882227569Sphilip 2883227569Sphilip#define FRF_AB_XX_TERMADJ1_LBN 17 2884227569Sphilip#define FRF_AB_XX_TERMADJ1_WIDTH 1 2885227569Sphilip#define FRF_AB_XX_TERMADJ0_LBN 16 2886227569Sphilip#define FRF_AB_XX_TERMADJ0_WIDTH 1 2887227569Sphilip#define FRF_AB_XX_HIDRVD_LBN 15 2888227569Sphilip#define FRF_AB_XX_HIDRVD_WIDTH 1 2889227569Sphilip#define FRF_AB_XX_LODRVD_LBN 14 2890227569Sphilip#define FRF_AB_XX_LODRVD_WIDTH 1 2891227569Sphilip#define FRF_AB_XX_HIDRVC_LBN 13 2892227569Sphilip#define FRF_AB_XX_HIDRVC_WIDTH 1 2893227569Sphilip#define FRF_AB_XX_LODRVC_LBN 12 2894227569Sphilip#define FRF_AB_XX_LODRVC_WIDTH 1 2895227569Sphilip#define FRF_AB_XX_HIDRVB_LBN 11 2896227569Sphilip#define FRF_AB_XX_HIDRVB_WIDTH 1 2897227569Sphilip#define FRF_AB_XX_LODRVB_LBN 10 2898227569Sphilip#define FRF_AB_XX_LODRVB_WIDTH 1 2899227569Sphilip#define FRF_AB_XX_HIDRVA_LBN 9 2900227569Sphilip#define FRF_AB_XX_HIDRVA_WIDTH 1 2901227569Sphilip#define FRF_AB_XX_LODRVA_LBN 8 2902227569Sphilip#define FRF_AB_XX_LODRVA_WIDTH 1 2903227569Sphilip#define FRF_AB_XX_LPBKD_LBN 3 2904227569Sphilip#define FRF_AB_XX_LPBKD_WIDTH 1 2905227569Sphilip#define FRF_AB_XX_LPBKC_LBN 2 2906227569Sphilip#define FRF_AB_XX_LPBKC_WIDTH 1 2907227569Sphilip#define FRF_AB_XX_LPBKB_LBN 1 2908227569Sphilip#define FRF_AB_XX_LPBKB_WIDTH 1 2909227569Sphilip#define FRF_AB_XX_LPBKA_LBN 0 2910227569Sphilip#define FRF_AB_XX_LPBKA_WIDTH 1 2911227569Sphilip 2912227569Sphilip 2913227569Sphilip/* 2914227569Sphilip * FR_AB_XX_TXDRV_CTL_REG(128bit): 2915227569Sphilip * XAUI SerDes transmit drive control register 2916227569Sphilip */ 2917227569Sphilip#define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 2918227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2919227569Sphilip 2920227569Sphilip#define FRF_AB_XX_DEQD_LBN 28 2921227569Sphilip#define FRF_AB_XX_DEQD_WIDTH 4 2922227569Sphilip#define FRF_AB_XX_DEQC_LBN 24 2923227569Sphilip#define FRF_AB_XX_DEQC_WIDTH 4 2924227569Sphilip#define FRF_AB_XX_DEQB_LBN 20 2925227569Sphilip#define FRF_AB_XX_DEQB_WIDTH 4 2926227569Sphilip#define FRF_AB_XX_DEQA_LBN 16 2927227569Sphilip#define FRF_AB_XX_DEQA_WIDTH 4 2928227569Sphilip#define FRF_AB_XX_DTXD_LBN 12 2929227569Sphilip#define FRF_AB_XX_DTXD_WIDTH 4 2930227569Sphilip#define FRF_AB_XX_DTXC_LBN 8 2931227569Sphilip#define FRF_AB_XX_DTXC_WIDTH 4 2932227569Sphilip#define FRF_AB_XX_DTXB_LBN 4 2933227569Sphilip#define FRF_AB_XX_DTXB_WIDTH 4 2934227569Sphilip#define FRF_AB_XX_DTXA_LBN 0 2935227569Sphilip#define FRF_AB_XX_DTXA_WIDTH 4 2936227569Sphilip 2937227569Sphilip 2938227569Sphilip/* 2939227569Sphilip * FR_AB_XX_PRBS_CTL_REG(128bit): 2940227569Sphilip * documentation to be written for sum_XX_PRBS_CTL_REG 2941227569Sphilip */ 2942227569Sphilip#define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 2943227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2944227569Sphilip 2945227569Sphilip#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2946227569Sphilip#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2947227569Sphilip#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2948227569Sphilip#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2949227569Sphilip#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2950227569Sphilip#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2951227569Sphilip#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2952227569Sphilip#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2953227569Sphilip#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2954227569Sphilip#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2955227569Sphilip#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2956227569Sphilip#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2957227569Sphilip#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2958227569Sphilip#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2959227569Sphilip#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2960227569Sphilip#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2961227569Sphilip#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2962227569Sphilip#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2963227569Sphilip#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2964227569Sphilip#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2965227569Sphilip#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2966227569Sphilip#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2967227569Sphilip#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2968227569Sphilip#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2969227569Sphilip#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2970227569Sphilip#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2971227569Sphilip#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2972227569Sphilip#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2973227569Sphilip#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2974227569Sphilip#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2975227569Sphilip#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2976227569Sphilip#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2977227569Sphilip#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2978227569Sphilip#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2979227569Sphilip#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2980227569Sphilip#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2981227569Sphilip#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2982227569Sphilip#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2983227569Sphilip#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 2984227569Sphilip#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 2985227569Sphilip#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 2986227569Sphilip#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 2987227569Sphilip#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 2988227569Sphilip#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 2989227569Sphilip#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 2990227569Sphilip#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 2991227569Sphilip#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 2992227569Sphilip#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 2993227569Sphilip 2994227569Sphilip 2995227569Sphilip/* 2996227569Sphilip * FR_AB_XX_PRBS_CHK_REG(128bit): 2997227569Sphilip * documentation to be written for sum_XX_PRBS_CHK_REG 2998227569Sphilip */ 2999227569Sphilip#define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 3000227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3001227569Sphilip 3002227569Sphilip#define FRF_AB_XX_REV_LB_EN_LBN 16 3003227569Sphilip#define FRF_AB_XX_REV_LB_EN_WIDTH 1 3004227569Sphilip#define FRF_AB_XX_CH3_DEG_DET_LBN 15 3005227569Sphilip#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 3006227569Sphilip#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 3007227569Sphilip#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 3008227569Sphilip#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 3009227569Sphilip#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 3010227569Sphilip#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 3011227569Sphilip#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 3012227569Sphilip#define FRF_AB_XX_CH2_DEG_DET_LBN 11 3013227569Sphilip#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 3014227569Sphilip#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 3015227569Sphilip#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 3016227569Sphilip#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 3017227569Sphilip#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 3018227569Sphilip#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 3019227569Sphilip#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 3020227569Sphilip#define FRF_AB_XX_CH1_DEG_DET_LBN 7 3021227569Sphilip#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 3022227569Sphilip#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 3023227569Sphilip#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 3024227569Sphilip#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 3025227569Sphilip#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 3026227569Sphilip#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 3027227569Sphilip#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 3028227569Sphilip#define FRF_AB_XX_CH0_DEG_DET_LBN 3 3029227569Sphilip#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 3030227569Sphilip#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 3031227569Sphilip#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 3032227569Sphilip#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 3033227569Sphilip#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 3034227569Sphilip#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 3035227569Sphilip#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 3036227569Sphilip 3037227569Sphilip 3038227569Sphilip/* 3039227569Sphilip * FR_AB_XX_PRBS_ERR_REG(128bit): 3040227569Sphilip * documentation to be written for sum_XX_PRBS_ERR_REG 3041227569Sphilip */ 3042227569Sphilip#define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 3043227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3044227569Sphilip 3045227569Sphilip#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 3046227569Sphilip#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 3047227569Sphilip#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 3048227569Sphilip#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 3049227569Sphilip#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 3050227569Sphilip#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 3051227569Sphilip#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 3052227569Sphilip#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 3053227569Sphilip 3054227569Sphilip 3055227569Sphilip/* 3056227569Sphilip * FR_AB_XX_CORE_STAT_REG(128bit): 3057227569Sphilip * XAUI XGXS core status register 3058227569Sphilip */ 3059227569Sphilip#define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 3060227569Sphilip/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3061227569Sphilip 3062227569Sphilip#define FRF_AB_XX_FORCE_SIG3_LBN 31 3063227569Sphilip#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 3064227569Sphilip#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 3065227569Sphilip#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 3066227569Sphilip#define FRF_AB_XX_FORCE_SIG2_LBN 29 3067227569Sphilip#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 3068227569Sphilip#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 3069227569Sphilip#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 3070227569Sphilip#define FRF_AB_XX_FORCE_SIG1_LBN 27 3071227569Sphilip#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 3072227569Sphilip#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 3073227569Sphilip#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 3074227569Sphilip#define FRF_AB_XX_FORCE_SIG0_LBN 25 3075227569Sphilip#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 3076227569Sphilip#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 3077227569Sphilip#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 3078227569Sphilip#define FRF_AB_XX_XGXS_LB_EN_LBN 23 3079227569Sphilip#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 3080227569Sphilip#define FRF_AB_XX_XGMII_LB_EN_LBN 22 3081227569Sphilip#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 3082227569Sphilip#define FRF_AB_XX_MATCH_FAULT_LBN 21 3083227569Sphilip#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 3084227569Sphilip#define FRF_AB_XX_ALIGN_DONE_LBN 20 3085227569Sphilip#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 3086227569Sphilip#define FRF_AB_XX_SYNC_STAT3_LBN 19 3087227569Sphilip#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 3088227569Sphilip#define FRF_AB_XX_SYNC_STAT2_LBN 18 3089227569Sphilip#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 3090227569Sphilip#define FRF_AB_XX_SYNC_STAT1_LBN 17 3091227569Sphilip#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 3092227569Sphilip#define FRF_AB_XX_SYNC_STAT0_LBN 16 3093227569Sphilip#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 3094227569Sphilip#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 3095227569Sphilip#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 3096227569Sphilip#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 3097227569Sphilip#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 3098227569Sphilip#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 3099227569Sphilip#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 3100227569Sphilip#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 3101227569Sphilip#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 3102227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 3103227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 3104227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 3105227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 3106227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 3107227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 3108227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 3109227569Sphilip#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 3110227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 3111227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 3112227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 3113227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 3114227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 3115227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 3116227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 3117227569Sphilip#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 3118227569Sphilip#define FRF_AB_XX_DISPERR_CH3_LBN 3 3119227569Sphilip#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 3120227569Sphilip#define FRF_AB_XX_DISPERR_CH2_LBN 2 3121227569Sphilip#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 3122227569Sphilip#define FRF_AB_XX_DISPERR_CH1_LBN 1 3123227569Sphilip#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 3124227569Sphilip#define FRF_AB_XX_DISPERR_CH0_LBN 0 3125227569Sphilip#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 3126227569Sphilip 3127227569Sphilip 3128227569Sphilip/* 3129227569Sphilip * FR_AA_RX_DESC_PTR_TBL_KER(128bit): 3130227569Sphilip * Receive descriptor pointer table 3131227569Sphilip */ 3132227569Sphilip#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 3133227569Sphilip/* falcona0=net_func_bar2 */ 3134227569Sphilip#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 3135227569Sphilip#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 3136227569Sphilip/* 3137227569Sphilip * FR_AZ_RX_DESC_PTR_TBL(128bit): 3138227569Sphilip * Receive descriptor pointer table 3139227569Sphilip */ 3140227569Sphilip#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 3141227569Sphilip/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3142227569Sphilip#define FR_AZ_RX_DESC_PTR_TBL_STEP 16 3143227569Sphilip#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 3144227569Sphilip#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 3145227569Sphilip 3146227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_LBN 90 3147227569Sphilip#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 3148227569Sphilip#define FRF_AZ_RX_RESET_LBN 89 3149227569Sphilip#define FRF_AZ_RX_RESET_WIDTH 1 3150227569Sphilip#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 3151227569Sphilip#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 3152227569Sphilip#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 3153227569Sphilip#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 3154227569Sphilip#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 3155227569Sphilip#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 3156227569Sphilip#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 3157227569Sphilip#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 3158227569Sphilip#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 3159227569Sphilip#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 3160227569Sphilip#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 3161227569Sphilip#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 3162227569Sphilip#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 3163227569Sphilip#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 3164227569Sphilip#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 3165227569Sphilip#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 3166227569Sphilip#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 3167227569Sphilip#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 3168227569Sphilip#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 3169227569Sphilip#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 3170227569Sphilip#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 3171227569Sphilip#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 3172227569Sphilip#define FFE_AZ_RX_DESCQ_SIZE_4K 3 3173227569Sphilip#define FFE_AZ_RX_DESCQ_SIZE_2K 2 3174227569Sphilip#define FFE_AZ_RX_DESCQ_SIZE_1K 1 3175227569Sphilip#define FFE_AZ_RX_DESCQ_SIZE_512 0 3176227569Sphilip#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 3177227569Sphilip#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 3178227569Sphilip#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 3179227569Sphilip#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 3180227569Sphilip#define FRF_AZ_RX_DESCQ_EN_LBN 0 3181227569Sphilip#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 3182227569Sphilip 3183227569Sphilip 3184227569Sphilip/* 3185227569Sphilip * FR_AA_TX_DESC_PTR_TBL_KER(128bit): 3186227569Sphilip * Transmit descriptor pointer 3187227569Sphilip */ 3188227569Sphilip#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 3189227569Sphilip/* falcona0=net_func_bar2 */ 3190227569Sphilip#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 3191227569Sphilip#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 3192227569Sphilip/* 3193227569Sphilip * FR_AZ_TX_DESC_PTR_TBL(128bit): 3194227569Sphilip * Transmit descriptor pointer 3195227569Sphilip */ 3196227569Sphilip#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 3197227569Sphilip/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3198227569Sphilip#define FR_AZ_TX_DESC_PTR_TBL_STEP 16 3199227569Sphilip#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 3200227569Sphilip#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 3201227569Sphilip 3202227569Sphilip#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 3203227569Sphilip#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 3204227569Sphilip#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 3205227569Sphilip#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 3206227569Sphilip#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 3207227569Sphilip#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 3208227569Sphilip#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 3209227569Sphilip#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 3210227569Sphilip#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 3211227569Sphilip#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 3212227569Sphilip#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 3213227569Sphilip#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 3214227569Sphilip#define FRF_AZ_TX_DESCQ_EN_LBN 88 3215227569Sphilip#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 3216227569Sphilip#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 3217227569Sphilip#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 3218227569Sphilip#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 3219227569Sphilip#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 3220227569Sphilip#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 3221227569Sphilip#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 3222227569Sphilip#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 3223227569Sphilip#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 3224227569Sphilip#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 3225227569Sphilip#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 3226227569Sphilip#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 3227227569Sphilip#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 3228227569Sphilip#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 3229227569Sphilip#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 3230227569Sphilip#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 3231227569Sphilip#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 3232227569Sphilip#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 3233227569Sphilip#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 3234227569Sphilip#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 3235227569Sphilip#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 3236227569Sphilip#define FFE_AZ_TX_DESCQ_SIZE_4K 3 3237227569Sphilip#define FFE_AZ_TX_DESCQ_SIZE_2K 2 3238227569Sphilip#define FFE_AZ_TX_DESCQ_SIZE_1K 1 3239227569Sphilip#define FFE_AZ_TX_DESCQ_SIZE_512 0 3240227569Sphilip#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 3241227569Sphilip#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 3242227569Sphilip#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 3243227569Sphilip#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 3244227569Sphilip 3245227569Sphilip 3246227569Sphilip/* 3247227569Sphilip * FR_AA_EVQ_PTR_TBL_KER(128bit): 3248227569Sphilip * Event queue pointer table 3249227569Sphilip */ 3250227569Sphilip#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 3251227569Sphilip/* falcona0=net_func_bar2 */ 3252227569Sphilip#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 3253227569Sphilip#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 3254227569Sphilip/* 3255227569Sphilip * FR_AZ_EVQ_PTR_TBL(128bit): 3256227569Sphilip * Event queue pointer table 3257227569Sphilip */ 3258227569Sphilip#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 3259227569Sphilip/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3260227569Sphilip#define FR_AZ_EVQ_PTR_TBL_STEP 16 3261227569Sphilip#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 3262227569Sphilip#define FR_AB_EVQ_PTR_TBL_ROWS 4096 3263227569Sphilip 3264227569Sphilip#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 3265227569Sphilip#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 3266227569Sphilip#define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 3267227569Sphilip#define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 3268227569Sphilip#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 3269227569Sphilip#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 3270227569Sphilip#define FRF_AZ_EVQ_EN_LBN 23 3271227569Sphilip#define FRF_AZ_EVQ_EN_WIDTH 1 3272227569Sphilip#define FRF_AZ_EVQ_SIZE_LBN 20 3273227569Sphilip#define FRF_AZ_EVQ_SIZE_WIDTH 3 3274227569Sphilip#define FFE_AZ_EVQ_SIZE_32K 6 3275227569Sphilip#define FFE_AZ_EVQ_SIZE_16K 5 3276227569Sphilip#define FFE_AZ_EVQ_SIZE_8K 4 3277227569Sphilip#define FFE_AZ_EVQ_SIZE_4K 3 3278227569Sphilip#define FFE_AZ_EVQ_SIZE_2K 2 3279227569Sphilip#define FFE_AZ_EVQ_SIZE_1K 1 3280227569Sphilip#define FFE_AZ_EVQ_SIZE_512 0 3281227569Sphilip#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 3282227569Sphilip#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 3283227569Sphilip 3284227569Sphilip 3285227569Sphilip/* 3286227569Sphilip * FR_AA_BUF_HALF_TBL_KER(64bit): 3287227569Sphilip * Buffer table in half buffer table mode direct access by driver 3288227569Sphilip */ 3289227569Sphilip#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 3290227569Sphilip/* falcona0=net_func_bar2 */ 3291227569Sphilip#define FR_AA_BUF_HALF_TBL_KER_STEP 8 3292227569Sphilip#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 3293227569Sphilip/* 3294227569Sphilip * FR_AZ_BUF_HALF_TBL(64bit): 3295227569Sphilip * Buffer table in half buffer table mode direct access by driver 3296227569Sphilip */ 3297227569Sphilip#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 3298227569Sphilip/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3299227569Sphilip#define FR_AZ_BUF_HALF_TBL_STEP 8 3300227569Sphilip#define FR_CZ_BUF_HALF_TBL_ROWS 147456 3301227569Sphilip#define FR_AB_BUF_HALF_TBL_ROWS 524288 3302227569Sphilip 3303227569Sphilip#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 3304227569Sphilip#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 3305227569Sphilip#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 3306227569Sphilip#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 3307227569Sphilip#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 3308227569Sphilip#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 3309227569Sphilip#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 3310227569Sphilip#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 3311227569Sphilip 3312227569Sphilip 3313227569Sphilip/* 3314227569Sphilip * FR_AA_BUF_FULL_TBL_KER(64bit): 3315227569Sphilip * Buffer table in full buffer table mode direct access by driver 3316227569Sphilip */ 3317227569Sphilip#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 3318227569Sphilip/* falcona0=net_func_bar2 */ 3319227569Sphilip#define FR_AA_BUF_FULL_TBL_KER_STEP 8 3320227569Sphilip#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 3321227569Sphilip/* 3322227569Sphilip * FR_AZ_BUF_FULL_TBL(64bit): 3323227569Sphilip * Buffer table in full buffer table mode direct access by driver 3324227569Sphilip */ 3325227569Sphilip#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 3326227569Sphilip/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3327227569Sphilip#define FR_AZ_BUF_FULL_TBL_STEP 8 3328227569Sphilip 3329227569Sphilip#define FR_CZ_BUF_FULL_TBL_ROWS 147456 3330227569Sphilip#define FR_AB_BUF_FULL_TBL_ROWS 917504 3331227569Sphilip 3332227569Sphilip#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 3333227569Sphilip#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 3334227569Sphilip#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 3335227569Sphilip#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 3336227569Sphilip#define FRF_AZ_BUF_ADR_REGION_LBN 48 3337227569Sphilip#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 3338227569Sphilip#define FFE_AZ_BUF_ADR_REGN3 3 3339227569Sphilip#define FFE_AZ_BUF_ADR_REGN2 2 3340227569Sphilip#define FFE_AZ_BUF_ADR_REGN1 1 3341227569Sphilip#define FFE_AZ_BUF_ADR_REGN0 0 3342227569Sphilip#define FRF_AZ_BUF_ADR_FBUF_LBN 14 3343227569Sphilip#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 3344227569Sphilip#define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 3345227569Sphilip#define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 3346227569Sphilip#define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 3347227569Sphilip#define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 3348227569Sphilip#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 3349227569Sphilip#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 3350227569Sphilip 3351227569Sphilip 3352227569Sphilip/* 3353227569Sphilip * FR_AZ_RX_FILTER_TBL0(128bit): 3354227569Sphilip * TCP/IPv4 Receive filter table 3355227569Sphilip */ 3356227569Sphilip#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 3357227569Sphilip/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3358227569Sphilip#define FR_AZ_RX_FILTER_TBL0_STEP 32 3359227569Sphilip#define FR_AZ_RX_FILTER_TBL0_ROWS 8192 3360227569Sphilip/* 3361227569Sphilip * FR_AB_RX_FILTER_TBL1(128bit): 3362227569Sphilip * TCP/IPv4 Receive filter table 3363227569Sphilip */ 3364227569Sphilip#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 3365227569Sphilip/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3366227569Sphilip#define FR_AB_RX_FILTER_TBL1_STEP 32 3367227569Sphilip#define FR_AB_RX_FILTER_TBL1_ROWS 8192 3368227569Sphilip 3369227569Sphilip#define FRF_BZ_RSS_EN_LBN 110 3370227569Sphilip#define FRF_BZ_RSS_EN_WIDTH 1 3371227569Sphilip#define FRF_BZ_SCATTER_EN_LBN 109 3372227569Sphilip#define FRF_BZ_SCATTER_EN_WIDTH 1 3373227569Sphilip#define FRF_AZ_TCP_UDP_LBN 108 3374227569Sphilip#define FRF_AZ_TCP_UDP_WIDTH 1 3375227569Sphilip#define FRF_AZ_RXQ_ID_LBN 96 3376227569Sphilip#define FRF_AZ_RXQ_ID_WIDTH 12 3377227569Sphilip#define FRF_AZ_DEST_IP_LBN 64 3378227569Sphilip#define FRF_AZ_DEST_IP_WIDTH 32 3379227569Sphilip#define FRF_AZ_DEST_PORT_TCP_LBN 48 3380227569Sphilip#define FRF_AZ_DEST_PORT_TCP_WIDTH 16 3381227569Sphilip#define FRF_AZ_SRC_IP_LBN 16 3382227569Sphilip#define FRF_AZ_SRC_IP_WIDTH 32 3383227569Sphilip#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 3384227569Sphilip#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 3385227569Sphilip 3386227569Sphilip 3387227569Sphilip/* 3388227569Sphilip * FR_CZ_RX_MAC_FILTER_TBL0(128bit): 3389227569Sphilip * Receive Ethernet filter table 3390227569Sphilip */ 3391227569Sphilip#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 3392227569Sphilip/* sienaa0=net_func_bar2 */ 3393227569Sphilip#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 3394227569Sphilip#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 3395227569Sphilip 3396227569Sphilip#define FRF_CZ_RMFT_RSS_EN_LBN 75 3397227569Sphilip#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 3398227569Sphilip#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 3399227569Sphilip#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 3400227569Sphilip#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 3401227569Sphilip#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 3402227569Sphilip#define FRF_CZ_RMFT_RXQ_ID_LBN 61 3403227569Sphilip#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 3404227569Sphilip#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 3405227569Sphilip#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 3406227569Sphilip#define FRF_CZ_RMFT_DEST_MAC_LBN 12 3407227569Sphilip#define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 3408227569Sphilip#define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 3409227569Sphilip#define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 3410227569Sphilip#define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 3411227569Sphilip#define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 3412227569Sphilip#define FRF_CZ_RMFT_VLAN_ID_LBN 0 3413227569Sphilip#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 3414227569Sphilip 3415227569Sphilip 3416227569Sphilip/* 3417227569Sphilip * FR_AZ_TIMER_TBL(128bit): 3418227569Sphilip * Timer table 3419227569Sphilip */ 3420227569Sphilip#define FR_AZ_TIMER_TBL_OFST 0x00f70000 3421227569Sphilip/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3422227569Sphilip#define FR_AZ_TIMER_TBL_STEP 16 3423227569Sphilip#define FR_CZ_TIMER_TBL_ROWS 1024 3424227569Sphilip#define FR_AB_TIMER_TBL_ROWS 4096 3425227569Sphilip 3426227569Sphilip#define FRF_CZ_TIMER_Q_EN_LBN 33 3427227569Sphilip#define FRF_CZ_TIMER_Q_EN_WIDTH 1 3428227569Sphilip#define FRF_CZ_INT_ARMD_LBN 32 3429227569Sphilip#define FRF_CZ_INT_ARMD_WIDTH 1 3430227569Sphilip#define FRF_CZ_INT_PEND_LBN 31 3431227569Sphilip#define FRF_CZ_INT_PEND_WIDTH 1 3432227569Sphilip#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 3433227569Sphilip#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 3434227569Sphilip#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 3435227569Sphilip#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 3436227569Sphilip#define FRF_CZ_TIMER_MODE_LBN 14 3437227569Sphilip#define FRF_CZ_TIMER_MODE_WIDTH 2 3438227569Sphilip#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 3439227569Sphilip#define FFE_CZ_TIMER_MODE_TRIG_START 2 3440227569Sphilip#define FFE_CZ_TIMER_MODE_IMMED_START 1 3441227569Sphilip#define FFE_CZ_TIMER_MODE_DIS 0 3442227569Sphilip#define FRF_AB_TIMER_MODE_LBN 12 3443227569Sphilip#define FRF_AB_TIMER_MODE_WIDTH 2 3444227569Sphilip#define FFE_AB_TIMER_MODE_INT_HLDOFF 2 3445227569Sphilip#define FFE_AB_TIMER_MODE_TRIG_START 2 3446227569Sphilip#define FFE_AB_TIMER_MODE_IMMED_START 1 3447227569Sphilip#define FFE_AB_TIMER_MODE_DIS 0 3448227569Sphilip#define FRF_CZ_TIMER_VAL_LBN 0 3449227569Sphilip#define FRF_CZ_TIMER_VAL_WIDTH 14 3450227569Sphilip#define FRF_AB_TIMER_VAL_LBN 0 3451227569Sphilip#define FRF_AB_TIMER_VAL_WIDTH 12 3452227569Sphilip 3453227569Sphilip 3454227569Sphilip/* 3455227569Sphilip * FR_BZ_TX_PACE_TBL(128bit): 3456227569Sphilip * Transmit pacing table 3457227569Sphilip */ 3458227569Sphilip#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 3459227569Sphilip/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ 3460227569Sphilip#define FR_AZ_TX_PACE_TBL_STEP 16 3461227569Sphilip#define FR_CZ_TX_PACE_TBL_ROWS 1024 3462227569Sphilip#define FR_BB_TX_PACE_TBL_ROWS 4096 3463227569Sphilip/* 3464227569Sphilip * FR_AA_TX_PACE_TBL(128bit): 3465227569Sphilip * Transmit pacing table 3466227569Sphilip */ 3467227569Sphilip#define FR_AA_TX_PACE_TBL_OFST 0x00f80040 3468227569Sphilip/* falcona0=char_func_bar0 */ 3469227569Sphilip/* FR_AZ_TX_PACE_TBL_STEP 16 */ 3470227569Sphilip#define FR_AA_TX_PACE_TBL_ROWS 4092 3471227569Sphilip 3472227569Sphilip#define FRF_AZ_TX_PACE_LBN 0 3473227569Sphilip#define FRF_AZ_TX_PACE_WIDTH 5 3474227569Sphilip 3475227569Sphilip 3476227569Sphilip/* 3477227569Sphilip * FR_BZ_RX_INDIRECTION_TBL(7bit): 3478227569Sphilip * RX Indirection Table 3479227569Sphilip */ 3480227569Sphilip#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 3481227569Sphilip/* falconb0,sienaa0=net_func_bar2 */ 3482227569Sphilip#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 3483227569Sphilip#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 3484227569Sphilip 3485227569Sphilip#define FRF_BZ_IT_QUEUE_LBN 0 3486227569Sphilip#define FRF_BZ_IT_QUEUE_WIDTH 6 3487227569Sphilip 3488227569Sphilip 3489227569Sphilip/* 3490227569Sphilip * FR_CZ_TX_FILTER_TBL0(128bit): 3491227569Sphilip * TCP/IPv4 Transmit filter table 3492227569Sphilip */ 3493227569Sphilip#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 3494227569Sphilip/* sienaa0=net_func_bar2 */ 3495227569Sphilip#define FR_CZ_TX_FILTER_TBL0_STEP 16 3496227569Sphilip#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 3497227569Sphilip 3498227569Sphilip#define FRF_CZ_TIFT_TCP_UDP_LBN 108 3499227569Sphilip#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 3500227569Sphilip#define FRF_CZ_TIFT_TXQ_ID_LBN 96 3501227569Sphilip#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 3502227569Sphilip#define FRF_CZ_TIFT_DEST_IP_LBN 64 3503227569Sphilip#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 3504227569Sphilip#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 3505227569Sphilip#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 3506227569Sphilip#define FRF_CZ_TIFT_SRC_IP_LBN 16 3507227569Sphilip#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 3508227569Sphilip#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 3509227569Sphilip#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 3510227569Sphilip 3511227569Sphilip 3512227569Sphilip/* 3513227569Sphilip * FR_CZ_TX_MAC_FILTER_TBL0(128bit): 3514227569Sphilip * Transmit Ethernet filter table 3515227569Sphilip */ 3516227569Sphilip#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 3517227569Sphilip/* sienaa0=net_func_bar2 */ 3518227569Sphilip#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 3519227569Sphilip#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 3520227569Sphilip 3521227569Sphilip#define FRF_CZ_TMFT_TXQ_ID_LBN 61 3522227569Sphilip#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 3523227569Sphilip#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 3524227569Sphilip#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 3525227569Sphilip#define FRF_CZ_TMFT_SRC_MAC_LBN 12 3526227569Sphilip#define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 3527227569Sphilip#define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 3528227569Sphilip#define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 3529227569Sphilip#define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 3530227569Sphilip#define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 3531227569Sphilip#define FRF_CZ_TMFT_VLAN_ID_LBN 0 3532227569Sphilip#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 3533227569Sphilip 3534227569Sphilip 3535227569Sphilip/* 3536227569Sphilip * FR_CZ_MC_TREG_SMEM(32bit): 3537227569Sphilip * MC Shared Memory 3538227569Sphilip */ 3539227569Sphilip#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 3540227569Sphilip/* sienaa0=net_func_bar2 */ 3541227569Sphilip#define FR_CZ_MC_TREG_SMEM_STEP 4 3542227569Sphilip#define FR_CZ_MC_TREG_SMEM_ROWS 512 3543227569Sphilip 3544227569Sphilip#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 3545227569Sphilip#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 3546227569Sphilip 3547227569Sphilip 3548227569Sphilip/* 3549227569Sphilip * FR_BB_MSIX_VECTOR_TABLE(128bit): 3550227569Sphilip * MSIX Vector Table 3551227569Sphilip */ 3552227569Sphilip#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 3553227569Sphilip/* falconb0=net_func_bar2 */ 3554227569Sphilip#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 3555227569Sphilip#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 3556227569Sphilip/* 3557227569Sphilip * FR_CZ_MSIX_VECTOR_TABLE(128bit): 3558227569Sphilip * MSIX Vector Table 3559227569Sphilip */ 3560227569Sphilip#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 3561227569Sphilip/* sienaa0=pci_f0_bar4 */ 3562227569Sphilip/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 3563227569Sphilip#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 3564227569Sphilip 3565227569Sphilip#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 3566227569Sphilip#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 3567227569Sphilip#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 3568227569Sphilip#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 3569227569Sphilip#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 3570227569Sphilip#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 3571227569Sphilip#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 3572227569Sphilip#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 3573227569Sphilip#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 3574227569Sphilip#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 3575227569Sphilip 3576227569Sphilip 3577227569Sphilip/* 3578227569Sphilip * FR_BB_MSIX_PBA_TABLE(32bit): 3579227569Sphilip * MSIX Pending Bit Array 3580227569Sphilip */ 3581227569Sphilip#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 3582227569Sphilip/* falconb0=net_func_bar2 */ 3583227569Sphilip#define FR_BZ_MSIX_PBA_TABLE_STEP 4 3584227569Sphilip#define FR_BB_MSIX_PBA_TABLE_ROWS 2 3585227569Sphilip/* 3586227569Sphilip * FR_CZ_MSIX_PBA_TABLE(32bit): 3587227569Sphilip * MSIX Pending Bit Array 3588227569Sphilip */ 3589227569Sphilip#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 3590227569Sphilip/* sienaa0=pci_f0_bar4 */ 3591227569Sphilip/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 3592227569Sphilip#define FR_CZ_MSIX_PBA_TABLE_ROWS 32 3593227569Sphilip 3594227569Sphilip#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 3595227569Sphilip#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 3596227569Sphilip 3597227569Sphilip 3598227569Sphilip/* 3599227569Sphilip * FR_AZ_SRM_DBG_REG(64bit): 3600227569Sphilip * SRAM debug access 3601227569Sphilip */ 3602227569Sphilip#define FR_AZ_SRM_DBG_REG_OFST 0x03000000 3603227569Sphilip/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3604227569Sphilip#define FR_AZ_SRM_DBG_REG_STEP 8 3605227569Sphilip 3606227569Sphilip#define FR_CZ_SRM_DBG_REG_ROWS 262144 3607227569Sphilip#define FR_AB_SRM_DBG_REG_ROWS 2097152 3608227569Sphilip 3609227569Sphilip#define FRF_AZ_SRM_DBG_LBN 0 3610227569Sphilip#define FRF_AZ_SRM_DBG_WIDTH 64 3611227569Sphilip#define FRF_AZ_SRM_DBG_DW0_LBN 0 3612227569Sphilip#define FRF_AZ_SRM_DBG_DW0_WIDTH 32 3613227569Sphilip#define FRF_AZ_SRM_DBG_DW1_LBN 32 3614227569Sphilip#define FRF_AZ_SRM_DBG_DW1_WIDTH 32 3615227569Sphilip 3616227569Sphilip 3617227569Sphilip/* 3618227569Sphilip * FR_AA_INT_ACK_CHAR(32bit): 3619227569Sphilip * CHAR interrupt acknowledge register 3620227569Sphilip */ 3621227569Sphilip#define FR_AA_INT_ACK_CHAR_OFST 0x00000060 3622227569Sphilip/* falcona0=char_func_bar0 */ 3623227569Sphilip 3624227569Sphilip#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 3625227569Sphilip#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 3626227569Sphilip 3627227569Sphilip 3628227569Sphilip/* FS_DRIVER_EV */ 3629227569Sphilip#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 3630227569Sphilip#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 3631227569Sphilip#define FSE_AZ_TX_DSC_ERROR_EV 15 3632227569Sphilip#define FSE_AZ_RX_DSC_ERROR_EV 14 3633227569Sphilip#define FSE_AZ_RX_RECOVER_EV 11 3634227569Sphilip#define FSE_AZ_TIMER_EV 10 3635227569Sphilip#define FSE_AZ_TX_PKT_NON_TCP_UDP 9 3636227569Sphilip#define FSE_AZ_WAKE_UP_EV 6 3637227569Sphilip#define FSE_AZ_SRM_UPD_DONE_EV 5 3638227569Sphilip#define FSE_AZ_EVQ_NOT_EN_EV 3 3639227569Sphilip#define FSE_AZ_EVQ_INIT_DONE_EV 2 3640227569Sphilip#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 3641227569Sphilip#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 3642227569Sphilip#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 3643227569Sphilip#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 3644227569Sphilip 3645227569Sphilip 3646227569Sphilip/* FS_EVENT_ENTRY */ 3647227569Sphilip#define FSF_AZ_EV_CODE_LBN 60 3648227569Sphilip#define FSF_AZ_EV_CODE_WIDTH 4 3649227569Sphilip#define FSE_AZ_EV_CODE_USER_EV 8 3650227569Sphilip#define FSE_AZ_EV_CODE_DRV_GEN_EV 7 3651227569Sphilip#define FSE_AZ_EV_CODE_GLOBAL_EV 6 3652227569Sphilip#define FSE_AZ_EV_CODE_DRIVER_EV 5 3653227569Sphilip#define FSE_AZ_EV_CODE_TX_EV 2 3654227569Sphilip#define FSE_AZ_EV_CODE_RX_EV 0 3655227569Sphilip#define FSF_AZ_EV_DATA_LBN 0 3656227569Sphilip#define FSF_AZ_EV_DATA_WIDTH 60 3657227569Sphilip#define FSF_AZ_EV_DATA_DW0_LBN 0 3658227569Sphilip#define FSF_AZ_EV_DATA_DW0_WIDTH 32 3659227569Sphilip#define FSF_AZ_EV_DATA_DW1_LBN 32 3660227569Sphilip#define FSF_AZ_EV_DATA_DW1_WIDTH 28 3661227569Sphilip 3662227569Sphilip 3663227569Sphilip/* FS_GLOBAL_EV */ 3664227569Sphilip#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 3665227569Sphilip#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 3666227569Sphilip#define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 3667227569Sphilip#define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 3668227569Sphilip#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 3669227569Sphilip#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 3670227569Sphilip#define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 3671227569Sphilip#define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 3672227569Sphilip#define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 3673227569Sphilip#define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 3674227569Sphilip 3675227569Sphilip 3676227569Sphilip/* FS_RX_EV */ 3677227569Sphilip#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 3678227569Sphilip#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 3679227569Sphilip#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 3680227569Sphilip#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 3681227569Sphilip#define FSF_AZ_RX_EV_PKT_OK_LBN 56 3682227569Sphilip#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 3683227569Sphilip#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 3684227569Sphilip#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 3685227569Sphilip#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 3686227569Sphilip#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3687227569Sphilip#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 3688227569Sphilip#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 3689227569Sphilip#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 3690227569Sphilip#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 3691227569Sphilip#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 3692227569Sphilip#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 3693227569Sphilip#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 3694227569Sphilip#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 3695227569Sphilip#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 3696227569Sphilip#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 3697227569Sphilip#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 3698227569Sphilip#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 3699227569Sphilip#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 3700227569Sphilip#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 3701227569Sphilip#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 3702227569Sphilip#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 3703227569Sphilip#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 3704227569Sphilip#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 3705227569Sphilip#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 3706227569Sphilip#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 3707227569Sphilip#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 3708227569Sphilip#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 3709227569Sphilip#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 3710227569Sphilip#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 3711227569Sphilip#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 3712227569Sphilip#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 3713227569Sphilip#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 3714227569Sphilip#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 3715227569Sphilip#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 3716227569Sphilip#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 3717227569Sphilip#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 3718227569Sphilip#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 3719227569Sphilip#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 3720227569Sphilip#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 3721227569Sphilip#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 3722227569Sphilip#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 3723227569Sphilip#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 3724227569Sphilip#define FSF_AZ_RX_EV_Q_LABEL_LBN 32 3725227569Sphilip#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 3726227569Sphilip#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 3727227569Sphilip#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 3728227569Sphilip#define FSF_AZ_RX_EV_PORT_LBN 30 3729227569Sphilip#define FSF_AZ_RX_EV_PORT_WIDTH 1 3730227569Sphilip#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 3731227569Sphilip#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 3732227569Sphilip#define FSF_AZ_RX_EV_SOP_LBN 15 3733227569Sphilip#define FSF_AZ_RX_EV_SOP_WIDTH 1 3734227569Sphilip#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 3735227569Sphilip#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 3736227569Sphilip#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 3737227569Sphilip#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 3738227569Sphilip#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 3739227569Sphilip#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 3740227569Sphilip#define FSF_AZ_RX_EV_DESC_PTR_LBN 0 3741227569Sphilip#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 3742227569Sphilip 3743227569Sphilip 3744227569Sphilip/* FS_RX_KER_DESC */ 3745227569Sphilip#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 3746227569Sphilip#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 3747227569Sphilip#define FSF_AZ_RX_KER_BUF_REGION_LBN 46 3748227569Sphilip#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 3749227569Sphilip#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 3750227569Sphilip#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 3751227569Sphilip#define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 3752227569Sphilip#define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 3753227569Sphilip#define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 3754227569Sphilip#define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 3755227569Sphilip 3756227569Sphilip 3757227569Sphilip/* FS_RX_USER_DESC */ 3758227569Sphilip#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 3759227569Sphilip#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 3760227569Sphilip#define FSF_AZ_RX_USER_BUF_ID_LBN 0 3761227569Sphilip#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 3762227569Sphilip 3763227569Sphilip 3764227569Sphilip/* FS_TX_EV */ 3765227569Sphilip#define FSF_AZ_TX_EV_PKT_ERR_LBN 38 3766227569Sphilip#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 3767227569Sphilip#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 3768227569Sphilip#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 3769227569Sphilip#define FSF_AZ_TX_EV_Q_LABEL_LBN 32 3770227569Sphilip#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 3771227569Sphilip#define FSF_AZ_TX_EV_PORT_LBN 16 3772227569Sphilip#define FSF_AZ_TX_EV_PORT_WIDTH 1 3773227569Sphilip#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 3774227569Sphilip#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 3775227569Sphilip#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 3776227569Sphilip#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3777227569Sphilip#define FSF_AZ_TX_EV_COMP_LBN 12 3778227569Sphilip#define FSF_AZ_TX_EV_COMP_WIDTH 1 3779227569Sphilip#define FSF_AZ_TX_EV_DESC_PTR_LBN 0 3780227569Sphilip#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 3781227569Sphilip 3782227569Sphilip 3783227569Sphilip/* FS_TX_KER_DESC */ 3784227569Sphilip#define FSF_AZ_TX_KER_CONT_LBN 62 3785227569Sphilip#define FSF_AZ_TX_KER_CONT_WIDTH 1 3786227569Sphilip#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 3787227569Sphilip#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 3788227569Sphilip#define FSF_AZ_TX_KER_BUF_REGION_LBN 46 3789227569Sphilip#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 3790227569Sphilip#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 3791227569Sphilip#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 3792227569Sphilip#define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 3793227569Sphilip#define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 3794227569Sphilip#define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 3795227569Sphilip#define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 3796227569Sphilip 3797227569Sphilip 3798227569Sphilip/* FS_TX_USER_DESC */ 3799227569Sphilip#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 3800227569Sphilip#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 3801227569Sphilip#define FSF_AZ_TX_USER_CONT_LBN 46 3802227569Sphilip#define FSF_AZ_TX_USER_CONT_WIDTH 1 3803227569Sphilip#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 3804227569Sphilip#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 3805227569Sphilip#define FSF_AZ_TX_USER_BUF_ID_LBN 13 3806227569Sphilip#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 3807227569Sphilip#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 3808227569Sphilip#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 3809227569Sphilip 3810227569Sphilip 3811227569Sphilip/* FS_USER_EV */ 3812227569Sphilip#define FSF_CZ_USER_QID_LBN 32 3813227569Sphilip#define FSF_CZ_USER_QID_WIDTH 10 3814227569Sphilip#define FSF_CZ_USER_EV_REG_VALUE_LBN 0 3815227569Sphilip#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 3816227569Sphilip 3817227569Sphilip 3818227569Sphilip/* FS_NET_IVEC */ 3819227569Sphilip#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 3820227569Sphilip#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 3821227569Sphilip#define FSF_AZ_NET_IVEC_INT_Q_LBN 40 3822227569Sphilip#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 3823227569Sphilip#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 3824227569Sphilip#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 3825227569Sphilip#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 3826227569Sphilip#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 3827227569Sphilip#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 3828227569Sphilip#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 3829227569Sphilip 3830227569Sphilip 3831227569Sphilip/* DRIVER_EV */ 3832227569Sphilip/* Sub-fields of an RX flush completion event */ 3833227569Sphilip#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 3834227569Sphilip#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 3835227569Sphilip#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 3836227569Sphilip#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 3837227569Sphilip 3838227569Sphilip 3839227569Sphilip#ifdef __cplusplus 3840227569Sphilip} 3841227569Sphilip#endif 3842227569Sphilip 3843227569Sphilip 3844227569Sphilip 3845227569Sphilip 3846227569Sphilip#endif /* _SYS_EFX_REGS_H */ 3847