if_sfreg.h revision 50863
149076Swpaul/* 249076Swpaul * Copyright (c) 1997, 1998, 1999 349076Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 449076Swpaul * 549076Swpaul * Redistribution and use in source and binary forms, with or without 649076Swpaul * modification, are permitted provided that the following conditions 749076Swpaul * are met: 849076Swpaul * 1. Redistributions of source code must retain the above copyright 949076Swpaul * notice, this list of conditions and the following disclaimer. 1049076Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1149076Swpaul * notice, this list of conditions and the following disclaimer in the 1249076Swpaul * documentation and/or other materials provided with the distribution. 1349076Swpaul * 3. All advertising materials mentioning features or use of this software 1449076Swpaul * must display the following acknowledgement: 1549076Swpaul * This product includes software developed by Bill Paul. 1649076Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1749076Swpaul * may be used to endorse or promote products derived from this software 1849076Swpaul * without specific prior written permission. 1949076Swpaul * 2049076Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2149076Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2249076Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2349076Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2449076Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2549076Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2649076Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2749076Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2849076Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2949076Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3049076Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3149076Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/sf/if_sfreg.h 50863 1999-09-03 20:58:39Z wpaul $ 3349076Swpaul */ 3449076Swpaul 3549076Swpaul/* 3649076Swpaul * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 3749076Swpaul * register space. These registers can be accessed in the following way: 3849076Swpaul * - PCI config registers are always accessible through PCI config space 3949076Swpaul * - Full 512K space mapped into memory using PCI memory mapped access 4049076Swpaul * - 256-byte I/O space mapped through PCI I/O access 4149076Swpaul * - Full 512K space mapped through indirect I/O using PCI I/O access 4249076Swpaul * It's possible to use either memory mapped mode or I/O mode to access 4349076Swpaul * the registers, but memory mapped is usually the easiest. All registers 4449076Swpaul * are 32 bits wide and must be accessed using 32-bit operations. 4549076Swpaul */ 4649076Swpaul 4749076Swpaul/* 4849076Swpaul * Adaptec PCI vendor ID. 4949076Swpaul */ 5049076Swpaul#define AD_VENDORID 0x9004 5149076Swpaul 5249076Swpaul/* 5349076Swpaul * AIC-6915 PCI device ID. 5449076Swpaul */ 5549076Swpaul#define AD_DEVICEID_STARFIRE 0x6915 5649076Swpaul 5749076Swpaul/* 5849076Swpaul * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 5949076Swpaul * the exact kind of NIC on which the ASIC is mounted. Currently there 6049076Swpaul * are six different variations. Note: the Adaptec manual lists code 0x28 6149076Swpaul * for two different NICs: the 62044 and the 69011/TX. This is a typo: 6249076Swpaul * the code for the 62044 is really 0x18. 6349076Swpaul */ 6449076Swpaul#define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ 6549076Swpaul#define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ 6649076Swpaul#define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ 6749076Swpaul#define AD_SUBSYSID_62044 0x0018 /* quad port 10/100baseTX 64-bit */ 6849076Swpaul#define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ 6949076Swpaul#define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ 7049076Swpaul 7149076Swpaul/* 7249076Swpaul * Starfire internal register space map. The entire register space 7349076Swpaul * is available using PCI memory mapped mode. The SF_RMAP_INTREG 7449076Swpaul * space is available using PCI I/O mode. The entire space can be 7549076Swpaul * accessed using indirect I/O using the indirect I/O addr and 7649076Swpaul * indirect I/O data registers located within the SF_RMAP_INTREG space. 7749076Swpaul */ 7849076Swpaul#define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ 7949076Swpaul#define SF_RMAP_ROMADDR_MAX 0x3FFFF 8049076Swpaul 8149076Swpaul#define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ 8249076Swpaul#define SF_RMAP_EXGPIO_MAX 0x3FFFF 8349076Swpaul 8449076Swpaul#define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ 8549076Swpaul#define SF_RMAP_INTREG_MAX 0x500FF 8649076Swpaul#define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ 8749076Swpaul#define SF_RMAP_GENREG_MAX 0x5FFFF 8849076Swpaul 8949076Swpaul#define SF_RMAP_FIFO_BASE 0x60000 9049076Swpaul#define SF_RMAP_FIFO_MAX 0x6FFFF 9149076Swpaul 9249076Swpaul#define SF_RMAP_STS_BASE 0x70000 9349076Swpaul#define SF_RMAP_STS_MAX 0x70083 9449076Swpaul 9549076Swpaul#define SF_RMAP_RSVD_BASE 0x70084 9649076Swpaul#define SF_RMAP_RSVD_MAX 0x7FFFF 9749076Swpaul 9849076Swpaul/* 9949076Swpaul * PCI config header registers, 0x0000 to 0x003F 10049076Swpaul */ 10149076Swpaul#define SF_PCI_VENDOR_ID 0x0000 10249076Swpaul#define SF_PCI_DEVICE_ID 0x0002 10349076Swpaul#define SF_PCI_COMMAND 0x0004 10449076Swpaul#define SF_PCI_STATUS 0x0006 10549076Swpaul#define SF_PCI_REVID 0x0008 10649076Swpaul#define SF_PCI_CLASSCODE 0x0009 10749076Swpaul#define SF_PCI_CACHELEN 0x000C 10849076Swpaul#define SF_PCI_LATENCY_TIMER 0x000D 10949076Swpaul#define SF_PCI_HEADER_TYPE 0x000E 11049076Swpaul#define SF_PCI_LOMEM 0x0010 11149076Swpaul#define SF_PCI_LOIO 0x0014 11249076Swpaul#define SF_PCI_SUBVEN_ID 0x002C 11349076Swpaul#define SF_PCI_SYBSYS_ID 0x002E 11449076Swpaul#define SF_PCI_BIOSROM 0x0030 11549076Swpaul#define SF_PCI_INTLINE 0x003C 11649076Swpaul#define SF_PCI_INTPIN 0x003D 11749076Swpaul#define SF_PCI_MINGNT 0x003E 11849076Swpaul#define SF_PCI_MINLAT 0x003F 11949076Swpaul 12049076Swpaul/* 12149076Swpaul * PCI registers, 0x0040 to 0x006F 12249076Swpaul */ 12349076Swpaul#define SF_PCI_DEVCFG 0x0040 12449076Swpaul#define SF_BACCTL 0x0044 12549076Swpaul#define SF_PCI_MON1 0x0048 12649076Swpaul#define SF_PCI_MON2 0x004C 12749076Swpaul#define SF_PCI_CAPID 0x0050 /* 8 bits */ 12849076Swpaul#define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ 12949076Swpaul#define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ 13049076Swpaul#define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ 13149076Swpaul#define SF_PCI_PME_EVENT 0x0058 13249076Swpaul#define SF_PCI_EECTL 0x0060 13349076Swpaul#define SF_PCI_COMPLIANCE 0x0064 13449076Swpaul#define SF_INDIRECTIO_ADDR 0x0068 13549076Swpaul#define SF_INDIRECTIO_DATA 0x006C 13649076Swpaul 13749076Swpaul#define SF_PCIDEVCFG_RESET 0x00000001 13849076Swpaul#define SF_PCIDEVCFG_FORCE64 0x00000002 13949076Swpaul#define SF_PCIDEVCFG_SYSTEM64 0x00000004 14049076Swpaul#define SF_PCIDEVCFG_RSVD0 0x00000008 14149076Swpaul#define SF_PCIDEVCFG_INCR_INB 0x00000010 14249076Swpaul#define SF_PCIDEVCFG_ABTONPERR 0x00000020 14349076Swpaul#define SF_PCIDEVCFG_STPONPERR 0x00000040 14449076Swpaul#define SF_PCIDEVCFG_MR_ENB 0x00000080 14549076Swpaul#define SF_PCIDEVCFG_FIFOTHR 0x00000F00 14649076Swpaul#define SF_PCIDEVCFG_STPONCA 0x00001000 14749076Swpaul#define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ 14849076Swpaul#define SF_PCIDEVCFG_LATSTP 0x00004000 14949076Swpaul#define SF_PCIDEVCFG_BYTE_ENB 0x00008000 15049076Swpaul#define SF_PCIDEVCFG_EECSWIDTH 0x00070000 15149076Swpaul#define SF_PCIDEVCFG_STPMWCA 0x00080000 15249076Swpaul#define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 15349076Swpaul#define SF_PCIDEVCFG_INTR_ENB 0x00800000 15449076Swpaul#define SF_PCIDEVCFG_DPR_ENB 0x01000000 15549076Swpaul#define SF_PCIDEVCFG_RSVD1 0x02000000 15649076Swpaul#define SF_PCIDEVCFG_RSVD2 0x04000000 15749076Swpaul#define SF_PCIDEVCFG_STA_ENB 0x08000000 15849076Swpaul#define SF_PCIDEVCFG_RTA_ENB 0x10000000 15949076Swpaul#define SF_PCIDEVCFG_RMA_ENB 0x20000000 16049076Swpaul#define SF_PCIDEVCFG_SSE_ENB 0x40000000 16149076Swpaul#define SF_PCIDEVCFG_DPE_ENB 0x80000000 16249076Swpaul 16349076Swpaul#define SF_BACCTL_BACDMA_ENB 0x00000001 16449076Swpaul#define SF_BACCTL_PREFER_RXDMA 0x00000002 16549076Swpaul#define SF_BACCTL_PREFER_TXDMA 0x00000004 16649076Swpaul#define SF_BACCTL_SINGLE_DMA 0x00000008 16749076Swpaul#define SF_BACCTL_SWAPMODE_DATA 0x00000030 16849076Swpaul#define SF_BACCTL_SWAPMODE_DESC 0x000000C0 16949076Swpaul 17049076Swpaul#define SF_SWAPMODE_LE 0x00000000 17149076Swpaul#define SF_SWAPMODE_BE 0x00000010 17249076Swpaul 17349076Swpaul#define SF_PSTATE_MASK 0x0003 17449076Swpaul#define SF_PSTATE_D0 0x0000 17549076Swpaul#define SF_PSTATE_D1 0x0001 17649076Swpaul#define SF_PSTATE_D2 0x0002 17749076Swpaul#define SF_PSTATE_D3 0x0003 17849076Swpaul#define SF_PME_EN 0x0010 17949076Swpaul#define SF_PME_STATUS 0x8000 18049076Swpaul 18149076Swpaul 18249076Swpaul/* 18349076Swpaul * Ethernet registers 0x0070 to 0x00FF 18449076Swpaul */ 18549076Swpaul#define SF_GEN_ETH_CTL 0x0070 18649076Swpaul#define SF_TIMER_CTL 0x0074 18749076Swpaul#define SF_CURTIME 0x0078 18849076Swpaul#define SF_ISR 0x0080 18949076Swpaul#define SF_ISR_SHADOW 0x0084 19049076Swpaul#define SF_IMR 0x0088 19149076Swpaul#define SF_GPIO 0x008C 19249076Swpaul#define SF_TXDQ_CTL 0x0090 19349076Swpaul#define SF_TXDQ_ADDR_HIPRIO 0x0094 19449076Swpaul#define SF_TXDQ_ADDR_LOPRIO 0x0098 19549076Swpaul#define SF_TXDQ_ADDR_HIADDR 0x009C 19649076Swpaul#define SF_TXDQ_PRODIDX 0x00A0 19749076Swpaul#define SF_TXDQ_CONSIDX 0x00A4 19849076Swpaul#define SF_TXDMA_STS1 0x00A8 19949076Swpaul#define SF_TXDMA_STS2 0x00AC 20049076Swpaul#define SF_TX_FRAMCTL 0x00B0 20149076Swpaul#define SF_TXCQ_ADDR_HI 0x00B4 20249076Swpaul#define SF_TXCQ_CTL 0x00B8 20349076Swpaul#define SF_RXCQ_CTL_1 0x00BC 20449076Swpaul#define SF_RXCQ_CTL_2 0x00C0 20549076Swpaul#define SF_CQ_CONSIDX 0x00C4 20649076Swpaul#define SF_CQ_PRODIDX 0x00C8 20749076Swpaul#define SF_CQ_RXQ2 0x00CC 20849076Swpaul#define SF_RXDMA_CTL 0x00D0 20949076Swpaul#define SF_RXDQ_CTL_1 0x00D4 21049076Swpaul#define SF_RXDQ_CTL_2 0x00D8 21149076Swpaul#define SF_RXDQ_ADDR_HIADDR 0x00DC 21249076Swpaul#define SF_RXDQ_ADDR_Q1 0x00E0 21349076Swpaul#define SF_RXDQ_ADDR_Q2 0x00E4 21449076Swpaul#define SF_RXDQ_PTR_Q1 0x00E8 21549076Swpaul#define SF_RXDQ_PTR_Q2 0x00EC 21649076Swpaul#define SF_RXDMA_STS 0x00F0 21749076Swpaul#define SF_RXFILT 0x00F4 21849076Swpaul#define SF_RX_FRAMETEST_OUT 0x00F8 21949076Swpaul 22049076Swpaul/* Ethernet control register */ 22149076Swpaul#define SF_ETHCTL_RX_ENB 0x00000001 22249076Swpaul#define SF_ETHCTL_TX_ENB 0x00000002 22349076Swpaul#define SF_ETHCTL_RXDMA_ENB 0x00000004 22449076Swpaul#define SF_ETHCTL_TXDMA_ENB 0x00000008 22549076Swpaul#define SF_ETHCTL_RXGFP_ENB 0x00000010 22649076Swpaul#define SF_ETHCTL_TXGFP_ENB 0x00000020 22749076Swpaul#define SF_ETHCTL_SOFTINTR 0x00000800 22849076Swpaul 22949076Swpaul/* Timer control register */ 23049076Swpaul#define SF_TIMER_IMASK_INTERVAL 0x0000001F 23149076Swpaul#define SF_TIMER_IMASK_MODE 0x00000060 23249076Swpaul#define SF_TIMER_SMALLFRAME_BYP 0x00000100 23349076Swpaul#define SF_TIMER_SMALLRX_FRAME 0x00000600 23449076Swpaul#define SF_TIMER_TIMES_TEN 0x00000800 23549076Swpaul#define SF_TIMER_RXHIPRIO_BYP 0x00001000 23649076Swpaul#define SF_TIMER_TX_DMADONE_DLY 0x00002000 23749076Swpaul#define SF_TIMER_TX_QDONE_DLY 0x00004000 23849076Swpaul#define SF_TIMER_TX_FRDONE_DLY 0x00008000 23949076Swpaul#define SF_TIMER_GENTIMER 0x00FF0000 24049076Swpaul#define SF_TIMER_ONESHOT 0x01000000 24149076Swpaul#define SF_TIMER_GENTIMER_RES 0x02000000 24249076Swpaul#define SF_TIMER_TIMEST_RES 0x04000000 24349076Swpaul#define SF_TIMER_RXQ2DONE_DLY 0x10000000 24449076Swpaul#define SF_TIMER_EARLYRX2_DLY 0x20000000 24549076Swpaul#define SF_TIMER_RXQ1DONE_DLY 0x40000000 24649076Swpaul#define SF_TIMER_EARLYRX1_DLY 0x80000000 24749076Swpaul 24849076Swpaul/* Interrupt status register */ 24949076Swpaul#define SF_ISR_PCIINT_ASSERTED 0x00000001 25049076Swpaul#define SF_ISR_GFP_TX 0x00000002 25149076Swpaul#define SF_ISR_GFP_RX 0x00000004 25249076Swpaul#define SF_ISR_TX_BADID_HIPRIO 0x00000008 25349076Swpaul#define SF_ISR_TX_BADID_LOPRIO 0x00000010 25449076Swpaul#define SF_ISR_NO_TX_CSUM 0x00000020 25549076Swpaul#define SF_ISR_RXDQ2_NOBUFS 0x00000040 25649076Swpaul#define SF_ISR_RXGFP_NORESP 0x00000080 25749076Swpaul#define SF_ISR_RXDQ1_DMADONE 0x00000100 25849076Swpaul#define SF_ISR_RXDQ2_DMADONE 0x00000200 25949076Swpaul#define SF_ISR_RXDQ1_EARLY 0x00000400 26049076Swpaul#define SF_ISR_RXDQ2_EARLY 0x00000800 26149076Swpaul#define SF_ISR_TX_QUEUEDONE 0x00001000 26249076Swpaul#define SF_ISR_TX_DMADONE 0x00002000 26349076Swpaul#define SF_ISR_TX_TXDONE 0x00004000 26449076Swpaul#define SF_ISR_NORMALINTR 0x00008000 26549076Swpaul#define SF_ISR_RXDQ1_NOBUFS 0x00010000 26649076Swpaul#define SF_ISR_RXCQ2_NOBUFS 0x00020000 26749076Swpaul#define SF_ISR_TX_LOFIFO 0x00040000 26849076Swpaul#define SF_ISR_DMAERR 0x00080000 26949076Swpaul#define SF_ISR_PCIINT 0x00100000 27049076Swpaul#define SF_ISR_TXCQ_NOBUFS 0x00200000 27149076Swpaul#define SF_ISR_RXCQ1_NOBUFS 0x00400000 27249076Swpaul#define SF_ISR_SOFTINTR 0x00800000 27349076Swpaul#define SF_ISR_GENTIMER 0x01000000 27449076Swpaul#define SF_ISR_ABNORMALINTR 0x02000000 27549076Swpaul#define SF_ISR_RSVD0 0x04000000 27649076Swpaul#define SF_ISR_STATSOFLOW 0x08000000 27749076Swpaul#define SF_ISR_GPIO 0xF0000000 27849076Swpaul 27949076Swpaul/* 28049076Swpaul * Shadow interrupt status register. Unlike the normal IRQ register, 28149076Swpaul * reading bits here does not automatically cause them to reset. 28249076Swpaul */ 28349076Swpaul#define SF_SISR_PCIINT_ASSERTED 0x00000001 28449076Swpaul#define SF_SISR_GFP_TX 0x00000002 28549076Swpaul#define SF_SISR_GFP_RX 0x00000004 28649076Swpaul#define SF_SISR_TX_BADID_HIPRIO 0x00000008 28749076Swpaul#define SF_SISR_TX_BADID_LOPRIO 0x00000010 28849076Swpaul#define SF_SISR_NO_TX_CSUM 0x00000020 28949076Swpaul#define SF_SISR_RXDQ2_NOBUFS 0x00000040 29049076Swpaul#define SF_SISR_RXGFP_NORESP 0x00000080 29149076Swpaul#define SF_SISR_RXDQ1_DMADONE 0x00000100 29249076Swpaul#define SF_SISR_RXDQ2_DMADONE 0x00000200 29349076Swpaul#define SF_SISR_RXDQ1_EARLY 0x00000400 29449076Swpaul#define SF_SISR_RXDQ2_EARLY 0x00000800 29549076Swpaul#define SF_SISR_TX_QUEUEDONE 0x00001000 29649076Swpaul#define SF_SISR_TX_DMADONE 0x00002000 29749076Swpaul#define SF_SISR_TX_TXDONE 0x00004000 29849076Swpaul#define SF_SISR_NORMALINTR 0x00008000 29949076Swpaul#define SF_SISR_RXDQ1_NOBUFS 0x00010000 30049076Swpaul#define SF_SISR_RXCQ2_NOBUFS 0x00020000 30149076Swpaul#define SF_SISR_TX_LOFIFO 0x00040000 30249076Swpaul#define SF_SISR_DMAERR 0x00080000 30349076Swpaul#define SF_SISR_PCIINT 0x00100000 30449076Swpaul#define SF_SISR_TXCQ_NOBUFS 0x00200000 30549076Swpaul#define SF_SISR_RXCQ1_NOBUFS 0x00400000 30649076Swpaul#define SF_SISR_SOFTINTR 0x00800000 30749076Swpaul#define SF_SISR_GENTIMER 0x01000000 30849076Swpaul#define SF_SISR_ABNORMALINTR 0x02000000 30949076Swpaul#define SF_SISR_RSVD0 0x04000000 31049076Swpaul#define SF_SISR_STATSOFLOW 0x08000000 31149076Swpaul#define SF_SISR_GPIO 0xF0000000 31249076Swpaul 31349076Swpaul/* Interrupt mask register */ 31449076Swpaul#define SF_IMR_PCIINT_ASSERTED 0x00000001 31549076Swpaul#define SF_IMR_GFP_TX 0x00000002 31649076Swpaul#define SF_IMR_GFP_RX 0x00000004 31749076Swpaul#define SF_IMR_TX_BADID_HIPRIO 0x00000008 31849076Swpaul#define SF_IMR_TX_BADID_LOPRIO 0x00000010 31949076Swpaul#define SF_IMR_NO_TX_CSUM 0x00000020 32049076Swpaul#define SF_IMR_RXDQ2_NOBUFS 0x00000040 32149076Swpaul#define SF_IMR_RXGFP_NORESP 0x00000080 32249076Swpaul#define SF_IMR_RXDQ1_DMADONE 0x00000100 32349076Swpaul#define SF_IMR_RXDQ2_DMADONE 0x00000200 32449076Swpaul#define SF_IMR_RXDQ1_EARLY 0x00000400 32549076Swpaul#define SF_IMR_RXDQ2_EARLY 0x00000800 32649076Swpaul#define SF_IMR_TX_QUEUEDONE 0x00001000 32749076Swpaul#define SF_IMR_TX_DMADONE 0x00002000 32849076Swpaul#define SF_IMR_TX_TXDONE 0x00004000 32949076Swpaul#define SF_IMR_NORMALINTR 0x00008000 33049076Swpaul#define SF_IMR_RXDQ1_NOBUFS 0x00010000 33149076Swpaul#define SF_IMR_RXCQ2_NOBUFS 0x00020000 33249076Swpaul#define SF_IMR_TX_LOFIFO 0x00040000 33349076Swpaul#define SF_IMR_DMAERR 0x00080000 33449076Swpaul#define SF_IMR_PCIINT 0x00100000 33549076Swpaul#define SF_IMR_TXCQ_NOBUFS 0x00200000 33649076Swpaul#define SF_IMR_RXCQ1_NOBUFS 0x00400000 33749076Swpaul#define SF_IMR_SOFTINTR 0x00800000 33849076Swpaul#define SF_IMR_GENTIMER 0x01000000 33949076Swpaul#define SF_IMR_ABNORMALINTR 0x02000000 34049076Swpaul#define SF_IMR_RSVD0 0x04000000 34149076Swpaul#define SF_IMR_STATSOFLOW 0x08000000 34249076Swpaul#define SF_IMR_GPIO 0xF0000000 34349076Swpaul 34449076Swpaul#define SF_INTRS \ 34549076Swpaul (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \ 34649076Swpaul SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \ 34749076Swpaul SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ 34849076Swpaul SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW) 34949076Swpaul 35049076Swpaul/* TX descriptor queue control registers */ 35149076Swpaul#define SF_TXDQCTL_DESCTYPE 0x00000007 35249076Swpaul#define SF_TXDQCTL_NODMACMP 0x00000008 35349076Swpaul#define SF_TXDQCTL_MINSPACE 0x00000070 35449076Swpaul#define SF_TXDQCTL_64BITADDR 0x00000080 35549076Swpaul#define SF_TXDQCTL_BURSTLEN 0x00003F00 35649076Swpaul#define SF_TXDQCTL_SKIPLEN 0x001F0000 35749076Swpaul#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 35849076Swpaul 35949076Swpaul#define SF_TXBUFDESC_TYPE0 0x00000000 36049076Swpaul#define SF_TXBUFDESC_TYPE1 0x00000001 36149076Swpaul#define SF_TXBUFDESC_TYPE2 0x00000002 36249076Swpaul#define SF_TXBUFDESC_TYPE3 0x00000003 36349076Swpaul#define SF_TXBUFDESC_TYPE4 0x00000004 36449076Swpaul 36549076Swpaul#define SF_TXMINSPACE_UNLIMIT 0x00000000 36649076Swpaul#define SF_TXMINSPACE_32BYTES 0x00000010 36749076Swpaul#define SF_TXMINSPACE_64BYTES 0x00000020 36849076Swpaul#define SF_TXMINSPACE_128BYTES 0x00000030 36949076Swpaul#define SF_TXMINSPACE_256BYTES 0x00000040 37049076Swpaul 37149076Swpaul#define SF_TXSKIPLEN_0BYTES 0x00000000 37249076Swpaul#define SF_TXSKIPLEN_8BYTES 0x00010000 37349076Swpaul#define SF_TXSKIPLEN_16BYTES 0x00020000 37449076Swpaul#define SF_TXSKIPLEN_24BYTES 0x00030000 37549076Swpaul#define SF_TXSKIPLEN_32BYTES 0x00040000 37649076Swpaul 37749076Swpaul/* TX frame control register */ 37849076Swpaul#define SF_TXFRMCTL_TXTHRESH 0x000000FF 37949076Swpaul#define SF_TXFRMCTL_CPLAFTERTX 0x00000100 38049076Swpaul#define SF_TXFRMCRL_DEBUG 0x0000FE00 38149076Swpaul#define SF_TXFRMCTL_STATUS 0x01FF0000 38249076Swpaul#define SF_TXFRMCTL_MAC_TXIF 0xFE000000 38349076Swpaul 38449076Swpaul/* TX completion queue control register */ 38549076Swpaul#define SF_TXCQ_THRESH 0x0000000F 38649076Swpaul#define SF_TXCQ_COMMON 0x00000010 38749076Swpaul#define SF_TXCQ_SIZE 0x00000020 38849076Swpaul#define SF_TXCQ_WRITEENB 0x00000040 38949076Swpaul#define SF_TXCQ_USE_64BIT 0x00000080 39049076Swpaul#define SF_TXCQ_ADDR 0xFFFFFF00 39149076Swpaul 39249076Swpaul/* RX completion queue control register */ 39349076Swpaul#define SF_RXCQ_THRESH 0x0000000F 39449076Swpaul#define SF_RXCQ_TYPE 0x00000030 39549076Swpaul#define SF_RXCQ_WRITEENB 0x00000040 39649076Swpaul#define SF_RXCQ_USE_64BIT 0x00000080 39749076Swpaul#define SF_RXCQ_ADDR 0xFFFFFF00 39849076Swpaul 39949076Swpaul#define SF_RXCQTYPE_0 0x00000000 40049076Swpaul#define SF_RXCQTYPE_1 0x00000010 40149076Swpaul#define SF_RXCQTYPE_2 0x00000020 40249076Swpaul#define SF_RXCQTYPE_3 0x00000030 40349076Swpaul 40449076Swpaul/* TX descriptor queue producer index register */ 40549076Swpaul#define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 40649076Swpaul#define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 40749076Swpaul 40849076Swpaul/* TX descriptor queue consumer index register */ 40949076Swpaul#define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 41049076Swpaul#define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 41149076Swpaul 41249076Swpaul/* Completion queue consumer index register */ 41349076Swpaul#define SF_CQ_CONSIDX_RXQ1 0x000003FF 41449076Swpaul#define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 41549076Swpaul#define SF_CQ_CONSIDX_TXQ 0x03FF0000 41649076Swpaul#define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 41749076Swpaul 41849076Swpaul/* Completion queue producer index register */ 41949076Swpaul#define SF_CQ_PRODIDX_RXQ1 0x000003FF 42049076Swpaul#define SF_CQ_PRODIDX_TXQ 0x03FF0000 42149076Swpaul 42249076Swpaul/* RX completion queue 2 consumer/producer index register */ 42349076Swpaul#define SF_CQ_RXQ2_CONSIDX 0x000003FF 42449076Swpaul#define SF_CQ_RXQ2_RXTHRMODE 0x00008000 42549076Swpaul#define SF_CQ_RXQ2_PRODIDX 0x03FF0000 42649076Swpaul 42749076Swpaul#define SF_CQ_RXTHRMODE_INT_ON 0x00008000 42849076Swpaul#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 42949076Swpaul#define SF_CQ_TXTHRMODE_INT_ON 0x80000000 43049076Swpaul#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 43149076Swpaul 43249076Swpaul#define SF_IDX_LO(x) ((x) & 0x000007FF) 43349076Swpaul#define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) 43449076Swpaul 43549076Swpaul/* RX DMA control register */ 43649076Swpaul#define SF_RXDMA_BURSTSIZE 0x0000007F 43749076Swpaul#define SF_RXDMA_FPTESTMODE 0x00000080 43849076Swpaul#define SF_RXDMA_HIPRIOTHRESH 0x00000F00 43949076Swpaul#define SF_RXDMA_RXEARLYTHRESH 0x0001F000 44049076Swpaul#define SF_RXDMA_DMACRC 0x00040000 44149076Swpaul#define SF_RXDMA_USEBKUPQUEUE 0x00080000 44249076Swpaul#define SF_RXDMA_QUEUEMODE 0x00700000 44349076Swpaul#define SF_RXDMA_RXCQ2_ON 0x00800000 44449076Swpaul#define SF_RXDMA_CSUMMODE 0x03000000 44549076Swpaul#define SF_RXDMA_DMAPAUSEPKTS 0x04000000 44649076Swpaul#define SF_RXDMA_DMACTLPKTS 0x08000000 44749076Swpaul#define SF_RXDMA_DMACRXERRPKTS 0x10000000 44849076Swpaul#define SF_RXDMA_DMABADPKTS 0x20000000 44949076Swpaul#define SF_RXDMA_DMARUNTS 0x40000000 45049076Swpaul#define SF_RXDMA_REPORTBADPKTS 0x80000000 45149076Swpaul 45249076Swpaul#define SF_RXDQMODE_Q1ONLY 0x00100000 45349076Swpaul#define SF_RXDQMODE_Q2_ON_FP 0x00200000 45449076Swpaul#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 45549076Swpaul#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 45649076Swpaul#define SF_RXDQMODE_SPLITHDR 0x00500000 45749076Swpaul 45849076Swpaul#define SF_RXCSUMMODE_IGNORE 0x00000000 45949076Swpaul#define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 46049076Swpaul#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 46149076Swpaul#define SF_RXCSUMMODE_RSVD 0x03000000 46249076Swpaul 46349076Swpaul/* RX descriptor queue control registers */ 46449076Swpaul#define SF_RXDQCTL_MINDESCTHR 0x0000007F 46549076Swpaul#define SF_RXDQCTL_Q1_WE 0x00000080 46649076Swpaul#define SF_RXDQCTL_DESCSPACE 0x00000700 46749076Swpaul#define SF_RXDQCTL_64BITDADDR 0x00000800 46849076Swpaul#define SF_RXDQCTL_64BITBADDR 0x00001000 46949076Swpaul#define SF_RXDQCTL_VARIABLE 0x00002000 47049076Swpaul#define SF_RXDQCTL_ENTRIES 0x00004000 47149076Swpaul#define SF_RXDQCTL_PREFETCH 0x00008000 47249076Swpaul#define SF_RXDQCTL_BUFLEN 0xFFFF0000 47349076Swpaul 47449076Swpaul#define SF_DESCSPACE_4BYTES 0x00000000 47549076Swpaul#define SF_DESCSPACE_8BYTES 0x00000100 47649076Swpaul#define SF_DESCSPACE_16BYTES 0x00000200 47749076Swpaul#define SF_DESCSPACE_32BYTES 0x00000300 47849076Swpaul#define SF_DESCSPACE_64BYTES 0x00000400 47949076Swpaul#define SF_DESCSPACE_128_BYTES 0x00000500 48049076Swpaul 48149076Swpaul/* RX buffer consumer/producer index registers */ 48249076Swpaul#define SF_RXDQ_PRODIDX 0x000007FF 48349076Swpaul#define SF_RXDQ_CONSIDX 0x07FF0000 48449076Swpaul 48549076Swpaul/* RX filter control register */ 48649076Swpaul#define SF_RXFILT_PROMISC 0x00000001 48749076Swpaul#define SF_RXFILT_ALLMULTI 0x00000002 48849076Swpaul#define SF_RXFILT_BROAD 0x00000004 48949076Swpaul#define SF_RXFILT_HASHPRIO 0x00000008 49049076Swpaul#define SF_RXFILT_HASHMODE 0x00000030 49149076Swpaul#define SF_RXFILT_PERFMODE 0x000000C0 49249076Swpaul#define SF_RXFILT_VLANMODE 0x00000300 49349076Swpaul#define SF_RXFILT_WAKEMODE 0x00000C00 49449076Swpaul#define SF_RXFILT_MULTI_NOBROAD 0x00001000 49549076Swpaul#define SF_RXFILT_MIN_VLANPRIO 0x0000E000 49649076Swpaul#define SF_RXFILT_PEFECTPRIO 0xFFFF0000 49749076Swpaul 49849076Swpaul/* Hash filtering mode */ 49949076Swpaul#define SF_HASHMODE_OFF 0x00000000 50049076Swpaul#define SF_HASHMODE_WITHVLAN 0x00000010 50149076Swpaul#define SF_HASHMODE_ANYVLAN 0x00000020 50249076Swpaul#define SF_HASHMODE_ANY 0x00000030 50349076Swpaul 50449076Swpaul/* Perfect filtering mode */ 50549076Swpaul#define SF_PERFMODE_OFF 0x00000000 50649076Swpaul#define SF_PERFMODE_NORMAL 0x00000040 50749076Swpaul#define SF_PERFMODE_INVERSE 0x00000080 50849076Swpaul#define SF_PERFMODE_VLAN 0x000000C0 50949076Swpaul 51049076Swpaul/* VLAN mode */ 51149076Swpaul#define SF_VLANMODE_OFF 0x00000000 51249076Swpaul#define SF_VLANMODE_NOSTRIP 0x00000100 51349076Swpaul#define SF_VLANMODE_STRIP 0x00000200 51449076Swpaul#define SF_VLANMODE_RSVD 0x00000300 51549076Swpaul 51649076Swpaul/* Wakeup mode */ 51749076Swpaul#define SF_WAKEMODE_OFF 0x00000000 51849076Swpaul#define SF_WAKEMODE_FILTER 0x00000400 51949076Swpaul#define SF_WAKEMODE_FP 0x00000800 52049076Swpaul#define SF_WAKEMODE_HIPRIO 0x00000C00 52149076Swpaul 52249076Swpaul/* 52349076Swpaul * Extra PCI registers 0x0100 to 0x0FFF 52449076Swpaul */ 52549076Swpaul#define SF_PCI_TARGSTAT 0x0100 52649076Swpaul#define SF_PCI_MASTSTAT1 0x0104 52749076Swpaul#define SF_PCI_MASTSTAT2 0x0108 52849076Swpaul#define SF_PCI_DMAHOSTADDR_LO 0x010C 52949076Swpaul#define SF_BAC_DMADIAG0 0x0110 53049076Swpaul#define SF_BAC_DMADIAG1 0x0114 53149076Swpaul#define SF_BAC_DMADIAG2 0x0118 53249076Swpaul#define SF_BAC_DMADIAG3 0x011C 53349076Swpaul#define SF_PAR0 0x0120 53449076Swpaul#define SF_PAR1 0x0124 53549076Swpaul#define SF_PCICB_FUNCEVENT 0x0130 53649076Swpaul#define SF_PCICB_FUNCEVENT_MASK 0x0134 53749076Swpaul#define SF_PCICB_FUNCSTATE 0x0138 53849076Swpaul#define SF_PCICB_FUNCFORCE 0x013C 53949076Swpaul 54049076Swpaul/* 54149076Swpaul * Serial EEPROM registers 0x1000 to 0x1FFF 54249076Swpaul * Presumeably the EEPROM is mapped into this 8K window. 54349076Swpaul */ 54449076Swpaul#define SF_EEADDR_BASE 0x1000 54549076Swpaul#define SF_EEADDR_MAX 0x1FFF 54649076Swpaul 54749076Swpaul#define SF_EE_NODEADDR 14 54849076Swpaul 54949076Swpaul/* 55049076Swpaul * MII registers registers 0x2000 to 0x3FFF 55149076Swpaul * There are 32 sets of 32 registers, one set for each possible 55249076Swpaul * PHY address. Each 32 bit register is split into a 16-bit data 55349076Swpaul * port and a couple of status bits. 55449076Swpaul */ 55549076Swpaul 55649076Swpaul#define SF_MIIADDR_BASE 0x2000 55749076Swpaul#define SF_MIIADDR_MAX 0x3FFF 55849076Swpaul#define SF_MII_BLOCKS 32 55949076Swpaul 56049076Swpaul#define SF_MII_DATAVALID 0x80000000 56149076Swpaul#define SF_MII_BUSY 0x40000000 56249076Swpaul#define SF_MII_DATAPORT 0x0000FFFF 56349076Swpaul 56449076Swpaul#define SF_PHY_REG(phy, reg) \ 56549076Swpaul (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ 56649076Swpaul (reg * sizeof(u_int32_t))) 56749076Swpaul 56849076Swpaul/* 56949076Swpaul * Ethernet extra registers 0x4000 to 0x4FFF 57049076Swpaul */ 57149076Swpaul#define SF_TESTMODE 0x4000 57249076Swpaul#define SF_RX_FRAMEPROC_CTL 0x4004 57349076Swpaul#define SF_TX_FRAMEPROC_CTL 0x4008 57449076Swpaul 57549076Swpaul/* 57649076Swpaul * MAC registers 0x5000 to 0x5FFF 57749076Swpaul */ 57849076Swpaul#define SF_MACCFG_1 0x5000 57949076Swpaul#define SF_MACCFG_2 0x5004 58049076Swpaul#define SF_BKTOBKIPG 0x5008 58149076Swpaul#define SF_NONBKTOBKIPG 0x500C 58249076Swpaul#define SF_COLRETRY 0x5010 58349076Swpaul#define SF_MAXLEN 0x5014 58449076Swpaul#define SF_TXNIBBLECNT 0x5018 58549076Swpaul#define SF_TXBYTECNT 0x501C 58649076Swpaul#define SF_RETXCNT 0x5020 58749076Swpaul#define SF_RANDNUM 0x5024 58849076Swpaul#define SF_RANDNUM_MASK 0x5028 58949076Swpaul#define SF_TOTALTXCNT 0x5034 59049076Swpaul#define SF_RXBYTECNT 0x5040 59149076Swpaul#define SF_TXPAUSETIMER 0x5060 59249076Swpaul#define SF_VLANTYPE 0x5064 59349076Swpaul#define SF_MIISTATUS 0x5070 59449076Swpaul 59549076Swpaul#define SF_MACCFG1_HUGEFRAMES 0x00000001 59649076Swpaul#define SF_MACCFG1_FULLDUPLEX 0x00000002 59749076Swpaul#define SF_MACCFG1_AUTOPAD 0x00000004 59849076Swpaul#define SF_MACCFG1_HDJAM 0x00000008 59949076Swpaul#define SF_MACCFG1_DELAYCRC 0x00000010 60049076Swpaul#define SF_MACCFG1_NOBACKOFF 0x00000020 60149076Swpaul#define SF_MACCFG1_LENGTHCHECK 0x00000040 60249076Swpaul#define SF_MACCFG1_PUREPREAMBLE 0x00000080 60349076Swpaul#define SF_MACCFG1_PASSALLRX 0x00000100 60449076Swpaul#define SF_MACCFG1_PREAM_DETCNT 0x00000200 60549076Swpaul#define SF_MACCFG1_RX_FLOWENB 0x00000400 60649076Swpaul#define SF_MACCFG1_TX_FLOWENB 0x00000800 60749076Swpaul#define SF_MACCFG1_TESTMODE 0x00003000 60849076Swpaul#define SF_MACCFG1_MIILOOPBK 0x00004000 60949076Swpaul#define SF_MACCFG1_SOFTRESET 0x00008000 61049076Swpaul 61149076Swpaul/* 61249076Swpaul * RX filter registers 0x6000 to 0x6FFF 61349076Swpaul */ 61449076Swpaul#define SF_RXFILT_PERFECT_BASE 0x6000 61549076Swpaul#define SF_RXFILT_PERFECT_MAX 0x60FF 61649076Swpaul#define SF_RXFILT_PERFECT_SKIP 0x0010 61749076Swpaul#define SF_RXFILT_PERFECT_CNT 0x0010 61849076Swpaul 61949076Swpaul#define SF_RXFILT_HASH_BASE 0x6100 62049076Swpaul#define SF_RXFILT_HASH_MAX 0x62FF 62149076Swpaul#define SF_RXFILT_HASH_SKIP 0x0010 62249076Swpaul#define SF_RXFILT_HASH_CNT 0x001F 62349076Swpaul#define SF_RXFILT_HASH_ADDROFF 0x0000 62449076Swpaul#define SF_RXFILT_HASH_PRIOOFF 0x0004 62549076Swpaul#define SF_RXFILT_HASH_VLANOFF 0x0008 62649076Swpaul 62749076Swpaul/* 62849076Swpaul * Statistics registers 0x7000 to 0x7FFF 62949076Swpaul */ 63049076Swpaul#define SF_STATS_BASE 0x7000 63149076Swpaul#define SF_STATS_END 0x7FFF 63249076Swpaul 63349076Swpaul/* 63449076Swpaul * TX frame processor instruction space 0x8000 to 0x9FFF 63549076Swpaul */ 63649076Swpaul 63749076Swpaul/* 63849076Swpaul * RX frame processor instruction space 0xA000 to 0xBFFF 63949076Swpaul */ 64049076Swpaul 64149076Swpaul/* 64249076Swpaul * Ethernet FIFO access space 0xC000 to 0xDFFF 64349076Swpaul */ 64449076Swpaul 64549076Swpaul/* 64649076Swpaul * Reserved 0xE000 to 0xFFFF 64749076Swpaul */ 64849076Swpaul 64949076Swpaul/* 65049076Swpaul * Descriptor data structures. 65149076Swpaul */ 65249076Swpaul 65349076Swpaul 65449076Swpaul/* Receive descriptor formats. */ 65549076Swpaul#define SF_RX_MINSPACING 8 65649076Swpaul#define SF_RX_DLIST_CNT 256 65749076Swpaul#define SF_RX_CLIST_CNT 1024 65849076Swpaul#define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) 65949076Swpaul 66049076Swpaul/* 66149076Swpaul * RX buffer descriptor type 0, 32-bit addressing. Note that we 66249076Swpaul * program the RX buffer queue control register(s) to allow a 66349076Swpaul * descriptor spacing of 16 bytes, which leaves room after each 66449076Swpaul * descriptor to store a pointer to the mbuf for each buffer. 66549076Swpaul */ 66649076Swpaulstruct sf_rx_bufdesc_type0 { 66749076Swpaul u_int32_t sf_valid:1, 66849076Swpaul sf_end:1, 66949076Swpaul sf_addrlo:30; 67049076Swpaul u_int32_t sf_pad0; 67149076Swpaul#ifdef __i386__ 67249076Swpaul u_int32_t sf_pad1; 67349076Swpaul#endif 67449076Swpaul struct mbuf *sf_mbuf; 67549076Swpaul}; 67649076Swpaul 67749076Swpaul/* 67849076Swpaul * RX buffer descriptor type 0, 64-bit addressing. 67949076Swpaul */ 68049076Swpaulstruct sf_rx_bufdesc_type1 { 68149076Swpaul u_int32_t sf_valid:1, 68249076Swpaul sf_end:1, 68349076Swpaul sf_addrlo:30; 68449076Swpaul u_int32_t sf_addrhi; 68549076Swpaul#ifdef __i386__ 68649076Swpaul u_int32_t sf_pad; 68749076Swpaul#endif 68849076Swpaul struct mbuf *sf_mbuf; 68949076Swpaul}; 69049076Swpaul 69149076Swpaul/* 69249076Swpaul * RX completion descriptor, type 0 (short). 69349076Swpaul */ 69449076Swpaulstruct sf_rx_cmpdesc_type0 { 69549076Swpaul u_int32_t sf_len:16, 69649076Swpaul sf_endidx:11, 69749076Swpaul sf_status1:3, 69849076Swpaul sf_id:2; 69949076Swpaul}; 70049076Swpaul 70149076Swpaul/* 70249076Swpaul * RX completion descriptor, type 1 (basic). Includes vlan ID 70349076Swpaul * if this is a vlan-addressed packet, plus extended status. 70449076Swpaul */ 70549076Swpaulstruct sf_rx_cmpdesc_type1 { 70649076Swpaul u_int32_t sf_len:16, 70749076Swpaul sf_endidx:11, 70849076Swpaul sf_status1:3, 70949076Swpaul sf_id:2; 71049076Swpaul u_int16_t sf_status2; 71149076Swpaul u_int16_t sf_vlanid; 71249076Swpaul}; 71349076Swpaul 71449076Swpaul/* 71549076Swpaul * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 71649076Swpaul * checksum instead of vlan tag, plus extended status. 71749076Swpaul */ 71849076Swpaulstruct sf_rx_cmpdesc_type2 { 71949076Swpaul u_int32_t sf_len:16, 72049076Swpaul sf_endidx:11, 72149076Swpaul sf_status1:3, 72249076Swpaul sf_id:2; 72349076Swpaul u_int16_t sf_status2; 72449076Swpaul u_int16_t sf_cksum; 72549076Swpaul}; 72649076Swpaul 72749076Swpaul/* 72849076Swpaul * RX completion descriptor type 3 (full). Includes timestamp, partial 72949076Swpaul * TCP/IP checksum, vlan tag plus priority, two extended status fields. 73049076Swpaul */ 73149076Swpaulstruct sf_rx_cmpdesc_type3 { 73249076Swpaul u_int32_t sf_len:16, 73349076Swpaul sf_endidx:11, 73449076Swpaul sf_status1:3, 73549076Swpaul sf_id:2; 73649076Swpaul u_int32_t sf_startidx:10, 73749076Swpaul sf_status3:6, 73849076Swpaul sf_status2:16; 73949076Swpaul u_int16_t sf_cksum; 74049076Swpaul u_int16_t sf_vlanid_prio; 74149076Swpaul u_int32_t sf_timestamp; 74249076Swpaul}; 74349076Swpaul 74449076Swpaul#define SF_RXSTAT1_QUEUE 0x1 74549076Swpaul#define SF_RXSTAT1_FIFOFULL 0x2 74649076Swpaul#define SF_RXSTAT1_OK 0x4 74749076Swpaul 74849076Swpaul /* 0=unknown,5=unsupported */ 74949076Swpaul#define SF_RXSTAT2_FRAMETYPE 0x0007 /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */ 75049076Swpaul#define SF_RXSTAT2_UDP 0x0008 75149076Swpaul#define SF_RXSTAT2_TCP 0x0010 75249076Swpaul#define SF_RXSTAT2_FRAG 0x0020 75349076Swpaul#define SF_RXSTAT2_PCSUM_OK 0x0040 /* partial checksum ok */ 75449076Swpaul#define SF_RXSTAT2_CSUM_BAD 0x0080 /* TCP/IP checksum bad */ 75549076Swpaul#define SF_RXSTAT2_CSUM_OK 0x0100 /* TCP/IP checksum ok */ 75649076Swpaul#define SF_RXSTAT2_VLAN 0x0200 75749076Swpaul#define SF_RXSTAT2_BADRXCODE 0x0400 75849076Swpaul#define SF_RXSTAT2_DRIBBLE 0x0800 75949076Swpaul#define SF_RXSTAT2_ISL_CRCERR 0x1000 76049076Swpaul#define SF_RXSTAT2_CRCERR 0x2000 76149076Swpaul#define SF_RXSTAT2_HASH 0x4000 76249076Swpaul#define SF_RXSTAT2_PERFECT 0x8000 76349076Swpaul 76449076Swpaul#define SF_RXSTAT3_TRAILER 0x01 76549076Swpaul#define SF_RXSTAT3_HEADER 0x02 76649076Swpaul#define SF_RXSTAT3_CONTROL 0x04 76749076Swpaul#define SF_RXSTAT3_PAUSE 0x08 76849076Swpaul#define SF_RXSTAT3_ISL 0x10 76949076Swpaul 77049076Swpaul/* 77149076Swpaul * Transmit descriptor formats. 77249076Swpaul * Each transmit descriptor type allows for a skip field at the 77349076Swpaul * start of each structure. The size of the skip field can vary, 77449076Swpaul * however we always set it for 8 bytes, which is enough to hold 77549076Swpaul * a pointer (32 bits on x86, 64-bits on alpha) that we can use 77649076Swpaul * to hold the address of the head of the mbuf chain for the 77749076Swpaul * frame or fragment associated with the descriptor. This saves 77849076Swpaul * us from having to create a separate pointer array to hold 77949076Swpaul * the mbuf addresses. 78049076Swpaul */ 78149076Swpaul#define SF_TX_BUFDESC_ID 0xB 78249076Swpaul#define SF_MAXFRAGS 14 78349076Swpaul#define SF_TX_MINSPACING 128 78449076Swpaul#define SF_TX_DLIST_CNT 128 78549076Swpaul#define SF_TX_DLIST_SIZE 16384 78649076Swpaul#define SF_TX_SKIPLEN 1 78749076Swpaul#define SF_TX_CLIST_CNT 1024 78849076Swpaul 78949076Swpaulstruct sf_frag { 79049076Swpaul u_int32_t sf_addr; 79149076Swpaul u_int16_t sf_fraglen; 79249076Swpaul u_int16_t sf_pktlen; 79349076Swpaul}; 79449076Swpaul 79549076Swpaulstruct sf_frag_msdos { 79649076Swpaul u_int16_t sf_pktlen; 79749076Swpaul u_int16_t sf_fraglen; 79849076Swpaul u_int32_t sf_addr; 79949076Swpaul}; 80049076Swpaul 80149076Swpaul/* 80249076Swpaul * TX frame descriptor type 0, 32-bit addressing. One descriptor can 80349076Swpaul * be used to map multiple packet fragments. We use this format since 80449076Swpaul * BSD networking fragments packet data across mbuf chains. Note that 80549076Swpaul * the number of fragments can be variable depending on how the descriptor 80649076Swpaul * spacing is specified in the TX descriptor queue control register. 80749076Swpaul * We always use a spacing of 128 bytes, and a skipfield length of 8 80849076Swpaul * bytes: this means 16 bytes for the descriptor, including the skipfield, 80949076Swpaul * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 81049076Swpaul * which allows for 14 fragments per descriptor. The total size of the 81149076Swpaul * transmit buffer queue is limited to 16384 bytes, so with a spacing of 81249076Swpaul * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 81349076Swpaul */ 81449076Swpaulstruct sf_tx_bufdesc_type0 { 81549076Swpaul#ifdef __i386__ 81649076Swpaul u_int32_t sf_pad; 81749076Swpaul#endif 81849076Swpaul struct mbuf *sf_mbuf; 81949076Swpaul u_int32_t sf_rsvd0:24, 82049076Swpaul sf_crcen:1, 82149076Swpaul sf_caltcp:1, 82249076Swpaul sf_end:1, 82349076Swpaul sf_intr:1, 82449076Swpaul sf_id:4; 82549076Swpaul u_int8_t sf_fragcnt; 82649076Swpaul u_int8_t sf_rsvd2; 82749076Swpaul u_int16_t sf_rsvd1; 82849076Swpaul struct sf_frag sf_frags[14]; 82949076Swpaul}; 83049076Swpaul 83149076Swpaul/* 83249076Swpaul * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 83349076Swpaul * maps a single fragment. 83449076Swpaul */ 83549076Swpaulstruct sf_tx_bufdesc_type1 { 83649076Swpaul#ifdef __i386__ 83749076Swpaul u_int32_t sf_pad; 83849076Swpaul#endif 83949076Swpaul struct mbuf *sf_mbuf; 84049076Swpaul u_int32_t sf_fraglen:16, 84149076Swpaul sf_fragcnt:8, 84249076Swpaul sf_crcen:1, 84349076Swpaul sf_caltcp:1, 84449076Swpaul sf_end:1, 84549076Swpaul sf_intr:1, 84649076Swpaul sf_id:4; 84749076Swpaul u_int32_t sf_addr; 84849076Swpaul}; 84949076Swpaul 85049076Swpaul/* 85149076Swpaul * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 85249076Swpaul * maps a single fragment. 85349076Swpaul */ 85449076Swpaulstruct sf_tx_bufdesc_type2 { 85549076Swpaul#ifdef __i386__ 85649076Swpaul u_int32_t sf_pad; 85749076Swpaul#endif 85849076Swpaul struct mbuf *sf_mbuf; 85949076Swpaul u_int32_t sf_fraglen:16, 86049076Swpaul sf_fragcnt:8, 86149076Swpaul sf_crcen:1, 86249076Swpaul sf_caltcp:1, 86349076Swpaul sf_end:1, 86449076Swpaul sf_intr:1, 86549076Swpaul sf_id:4; 86649076Swpaul u_int32_t sf_addrlo; 86749076Swpaul u_int32_t sf_addrhi; 86849076Swpaul}; 86949076Swpaul 87049076Swpaul/* TX buffer descriptor type 3 is not defined. */ 87149076Swpaul 87249076Swpaul/* 87349076Swpaul * TX frame descriptor type 4, 32-bit addressing. This is a special 87449076Swpaul * case of the type 0 descriptor, identical except that the fragment 87549076Swpaul * address and length fields are ordered differently. This is done 87649076Swpaul * to optimize copies in MS-DOS and OS/2 drivers. 87749076Swpaul */ 87849076Swpaulstruct sf_tx_bufdesc_type4 { 87949076Swpaul#ifdef __i386__ 88049076Swpaul u_int32_t sf_pad; 88149076Swpaul#endif 88249076Swpaul struct mbuf *sf_mbuf; 88349076Swpaul u_int32_t sf_rsvd0:24, 88449076Swpaul sf_crcen:1, 88549076Swpaul sf_caltcp:1, 88649076Swpaul sf_end:1, 88749076Swpaul sf_intr:1, 88849076Swpaul sf_id:4; 88949076Swpaul u_int8_t sf_fragcnt; 89049076Swpaul u_int8_t sf_rsvd2; 89149076Swpaul u_int16_t sf_rsvd1; 89249076Swpaul struct sf_frag_msdos sf_frags[14]; 89349076Swpaul}; 89449076Swpaul 89549076Swpaul/* 89649076Swpaul * Transmit completion queue descriptor formats. 89749076Swpaul */ 89849076Swpaul 89949076Swpaul/* 90049076Swpaul * Transmit DMA completion descriptor, type 0. 90149076Swpaul */ 90249076Swpaul#define SF_TXCMPTYPE_DMA 0x4 90349076Swpaulstruct sf_tx_cmpdesc_type0 { 90449076Swpaul u_int32_t sf_index:15, 90549076Swpaul sf_priority:1, 90649076Swpaul sf_timestamp:13, 90749076Swpaul sf_type:3; 90849076Swpaul}; 90949076Swpaul 91049076Swpaul/* 91149076Swpaul * Transmit completion descriptor, type 1. 91249076Swpaul */ 91349076Swpaul#define SF_TXCMPTYPE_TX 0x5 91449076Swpaulstruct sf_tx_cmpdesc_type1 { 91549076Swpaul u_int32_t sf_index:15, 91649076Swpaul sf_priority:1, 91749076Swpaul sf_txstat:13, 91849076Swpaul sf_type:3; 91949076Swpaul}; 92049076Swpaul 92149076Swpaul#define SF_TXSTAT_CRCERR 0x0001 92249076Swpaul#define SF_TXSTAT_LENCHECKERR 0x0002 92349076Swpaul#define SF_TXSTAT_LENRANGEERR 0x0004 92449076Swpaul#define SF_TXSTAT_TX_OK 0x0008 92549076Swpaul#define SF_TXSTAT_TX_DEFERED 0x0010 92649076Swpaul#define SF_TXSTAT_EXCESS_DEFER 0x0020 92749076Swpaul#define SF_TXSTAT_EXCESS_COLL 0x0040 92849076Swpaul#define SF_TXSTAT_LATE_COLL 0x0080 92949076Swpaul#define SF_TXSTAT_TOOBIG 0x0100 93049076Swpaul#define SF_TXSTAT_TX_UNDERRUN 0x0200 93149076Swpaul#define SF_TXSTAT_CTLFRAME_OK 0x0400 93249076Swpaul#define SF_TXSTAT_PAUSEFRAME_OK 0x0800 93349076Swpaul#define SF_TXSTAT_PAUSED 0x1000 93449076Swpaul 93549076Swpaul/* Statistics counters. */ 93649076Swpaulstruct sf_stats { 93749076Swpaul u_int32_t sf_tx_frames; 93849076Swpaul u_int32_t sf_tx_single_colls; 93949076Swpaul u_int32_t sf_tx_multi_colls; 94049076Swpaul u_int32_t sf_tx_crcerrs; 94149076Swpaul u_int32_t sf_tx_bytes; 94249076Swpaul u_int32_t sf_tx_defered; 94349076Swpaul u_int32_t sf_tx_late_colls; 94449076Swpaul u_int32_t sf_tx_pause_frames; 94549076Swpaul u_int32_t sf_tx_control_frames; 94649076Swpaul u_int32_t sf_tx_excess_colls; 94749076Swpaul u_int32_t sf_tx_excess_defer; 94849076Swpaul u_int32_t sf_tx_mcast_frames; 94949076Swpaul u_int32_t sf_tx_bcast_frames; 95049076Swpaul u_int32_t sf_tx_frames_lost; 95149076Swpaul u_int32_t sf_rx_rx_frames; 95249076Swpaul u_int32_t sf_rx_crcerrs; 95349076Swpaul u_int32_t sf_rx_alignerrs; 95449076Swpaul u_int32_t sf_rx_bytes; 95549076Swpaul u_int32_t sf_rx_control_frames; 95649076Swpaul u_int32_t sf_rx_unsup_control_frames; 95749076Swpaul u_int32_t sf_rx_giants; 95849076Swpaul u_int32_t sf_rx_runts; 95949076Swpaul u_int32_t sf_rx_jabbererrs; 96049076Swpaul u_int32_t sf_rx_pkts_64; 96149076Swpaul u_int32_t sf_rx_pkts_65_127; 96249076Swpaul u_int32_t sf_rx_pkts_128_255; 96349076Swpaul u_int32_t sf_rx_pkts_256_511; 96449076Swpaul u_int32_t sf_rx_pkts_512_1023; 96549076Swpaul u_int32_t sf_rx_pkts_1024_1518; 96649076Swpaul u_int32_t sf_rx_frames_lost; 96749076Swpaul u_int16_t sf_tx_underruns; 96849076Swpaul u_int16_t sf_pad; 96949076Swpaul}; 97049076Swpaul 97149076Swpaul/* 97249076Swpaul * register space access macros 97349076Swpaul */ 97449076Swpaul#define CSR_WRITE_4(sc, reg, val) \ 97549076Swpaul bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) 97649076Swpaul 97749076Swpaul#define CSR_READ_4(sc, reg) \ 97849076Swpaul bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) 97949076Swpaul 98049076Swpaul#define CSR_READ_1(sc, reg) \ 98149076Swpaul bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) 98249076Swpaul 98349076Swpaul 98449076Swpaulstruct sf_type { 98549076Swpaul u_int16_t sf_vid; 98649076Swpaul u_int16_t sf_did; 98749076Swpaul char *sf_name; 98849076Swpaul}; 98949076Swpaul 99049076Swpaul#define SF_INC(x, y) (x) = (x + 1) % y 99149076Swpaul 99249076Swpaul#define ETHER_ALIGN 2 99349076Swpaul 99449076Swpaul/* 99549076Swpaul * Note: alignment is important here: each list must be aligned to 99649076Swpaul * a 256-byte boundary. It turns out that each ring is some multiple 99749076Swpaul * of 4K in length, so we can stack them all on top of each other 99849076Swpaul * and just worry about aligning the whole mess. There's one transmit 99949076Swpaul * buffer ring and two receive buffer rings: one RX ring is for small 100049076Swpaul * packets and the other is for large packets. Each buffer ring also 100149076Swpaul * has a companion completion queue. 100249076Swpaul */ 100349076Swpaulstruct sf_list_data { 100449076Swpaul struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; 100549076Swpaul struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 100649076Swpaul struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 100750863Swpaul#ifdef notdef 100850863Swpaul /* 100950863Swpaul * Unfortunately, because the Starfire doesn't allow arbitrary 101050863Swpaul * byte alignment, we have to copy packets in the RX handler in 101150863Swpaul * order to align the payload correctly. This means that we 101250863Swpaul * don't gain anything by having separate large and small descriptor 101350863Swpaul * lists, so for now we don't bother with the small one. 101450863Swpaul */ 101549076Swpaul struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 101650863Swpaul#endif 101749076Swpaul struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 101849076Swpaul}; 101949076Swpaul 102049076Swpaulstruct sf_softc { 102149076Swpaul struct arpcom arpcom; /* interface info */ 102249076Swpaul bus_space_handle_t sf_bhandle; /* bus space handle */ 102349076Swpaul bus_space_tag_t sf_btag; /* bus space tag */ 102449076Swpaul void *sf_intrhand; /* interrupt handler cookie */ 102549076Swpaul struct resource *sf_irq; /* irq resource descriptor */ 102649076Swpaul struct resource *sf_res; /* mem/ioport resource */ 102749076Swpaul struct sf_type *sf_info; /* Starfire adapter info */ 102850675Swpaul device_t sf_miibus; 102949076Swpaul u_int8_t sf_unit; /* interface number */ 103049076Swpaul struct sf_list_data *sf_ldata; 103149076Swpaul int sf_tx_cnt; 103249076Swpaul struct callout_handle sf_stat_ch; 103349076Swpaul}; 103449076Swpaul 103549076Swpaul#define SF_TIMEOUT 1000 103649076Swpaul 103749076Swpaul#ifdef __alpha__ 103849076Swpaul#undef vtophys 103949076Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 104049076Swpaul#endif 1041