ppc.c revision 56617
1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/ppc/ppc.c 56617 2000-01-25 22:21:45Z dfr $ 27 * 28 */ 29#include "ppc.h" 30 31#if NPPC > 0 32 33#include "opt_ppc.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/kernel.h> 38#include <sys/bus.h> 39#include <sys/malloc.h> 40 41#include <vm/vm.h> 42#include <vm/pmap.h> 43#include <machine/clock.h> 44#include <machine/bus.h> 45#include <machine/resource.h> 46#include <machine/vmparam.h> 47#include <sys/rman.h> 48 49#include <isa/isareg.h> 50#include <isa/isavar.h> 51 52#include <dev/ppbus/ppbconf.h> 53#include <dev/ppbus/ppb_msq.h> 54 55#include <isa/ppcreg.h> 56 57#include "ppbus_if.h" 58 59#define LOG_PPC(function, ppc, string) \ 60 if (bootverbose) printf("%s: %s\n", function, string) 61 62 63#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 64 65devclass_t ppc_devclass; 66 67static int ppc_probe(device_t dev); 68static int ppc_attach(device_t dev); 69static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val); 70 71static void ppc_reset_epp(device_t); 72static void ppc_ecp_sync(device_t); 73static void ppcintr(void *arg); 74 75static int ppc_exec_microseq(device_t, struct ppb_microseq **); 76static int ppc_setmode(device_t, int); 77 78static int ppc_read(device_t, char *, int, int); 79static int ppc_write(device_t, char *, int, int); 80 81static u_char ppc_io(device_t, int, u_char *, int, u_char); 82 83static int ppc_setup_intr(device_t, device_t, struct resource *, int, 84 void (*)(void *), void *, void **); 85static int ppc_teardown_intr(device_t, device_t, struct resource *, void *); 86 87static device_method_t ppc_methods[] = { 88 /* device interface */ 89 DEVMETHOD(device_probe, ppc_probe), 90 DEVMETHOD(device_attach, ppc_attach), 91 92 /* bus interface */ 93 DEVMETHOD(bus_read_ivar, ppc_read_ivar), 94 DEVMETHOD(bus_setup_intr, ppc_setup_intr), 95 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), 96 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 97 98 /* ppbus interface */ 99 DEVMETHOD(ppbus_io, ppc_io), 100 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), 101 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), 102 DEVMETHOD(ppbus_setmode, ppc_setmode), 103 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), 104 DEVMETHOD(ppbus_read, ppc_read), 105 DEVMETHOD(ppbus_write, ppc_write), 106 107 { 0, 0 } 108 }; 109 110static driver_t ppc_driver = { 111 "ppc", 112 ppc_methods, 113 sizeof(struct ppc_data), 114}; 115 116static char *ppc_models[] = { 117 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 118 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0 119}; 120 121/* list of available modes */ 122static char *ppc_avms[] = { 123 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 124 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 125 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 126 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 127}; 128 129/* list of current executing modes 130 * Note that few modes do not actually exist. 131 */ 132static char *ppc_modes[] = { 133 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 134 "EPP", "EPP", "EPP", "ECP", 135 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 136 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 137}; 138 139static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 140 141#ifdef __i386__ 142/* 143 * BIOS printer list - used by BIOS probe. 144 */ 145#define BIOS_PPC_PORTS 0x408 146#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 147#define BIOS_MAX_PPC 4 148#endif 149 150/* 151 * ppc_ecp_sync() XXX 152 */ 153static void 154ppc_ecp_sync(device_t dev) { 155 156 int i, r; 157 struct ppc_data *ppc = DEVTOSOFTC(dev); 158 159 if (!(ppc->ppc_avm & PPB_ECP)) 160 return; 161 162 r = r_ecr(ppc); 163 if ((r & 0xe0) != PPC_ECR_EPP) 164 return; 165 166 for (i = 0; i < 100; i++) { 167 r = r_ecr(ppc); 168 if (r & 0x1) 169 return; 170 DELAY(100); 171 } 172 173 printf("ppc%d: ECP sync failed as data still " \ 174 "present in FIFO.\n", ppc->ppc_unit); 175 176 return; 177} 178 179/* 180 * ppc_detect_fifo() 181 * 182 * Detect parallel port FIFO 183 */ 184static int 185ppc_detect_fifo(struct ppc_data *ppc) 186{ 187 char ecr_sav; 188 char ctr_sav, ctr, cc; 189 short i; 190 191 /* save registers */ 192 ecr_sav = r_ecr(ppc); 193 ctr_sav = r_ctr(ppc); 194 195 /* enter ECP configuration mode, no interrupt, no DMA */ 196 w_ecr(ppc, 0xf4); 197 198 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 199 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 200 201 /* XXX 16 and 32 bits implementations not supported */ 202 if (ppc->ppc_pword != PPC_PWORD_8) { 203 LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 204 goto error; 205 } 206 207 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 208 ctr = r_ctr(ppc); 209 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 210 211 /* enter ECP test mode, no interrupt, no DMA */ 212 w_ecr(ppc, 0xd4); 213 214 /* flush the FIFO */ 215 for (i=0; i<1024; i++) { 216 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 217 break; 218 cc = r_fifo(ppc); 219 } 220 221 if (i >= 1024) { 222 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 223 goto error; 224 } 225 226 /* enable interrupts, no DMA */ 227 w_ecr(ppc, 0xd0); 228 229 /* determine readIntrThreshold 230 * fill the FIFO until serviceIntr is set 231 */ 232 for (i=0; i<1024; i++) { 233 w_fifo(ppc, (char)i); 234 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 235 /* readThreshold reached */ 236 ppc->ppc_rthr = i+1; 237 } 238 if (r_ecr(ppc) & PPC_FIFO_FULL) { 239 ppc->ppc_fifo = i+1; 240 break; 241 } 242 } 243 244 if (i >= 1024) { 245 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 246 goto error; 247 } 248 249 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 250 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 251 w_ecr(ppc, 0xd0); /* enable interrupts */ 252 253 /* determine writeIntrThreshold 254 * empty the FIFO until serviceIntr is set 255 */ 256 for (i=ppc->ppc_fifo; i>0; i--) { 257 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 258 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 259 goto error; 260 } 261 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 262 /* writeIntrThreshold reached */ 263 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 264 } 265 /* if FIFO empty before the last byte, error */ 266 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 267 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 268 goto error; 269 } 270 } 271 272 /* FIFO must be empty after the last byte */ 273 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 274 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 275 goto error; 276 } 277 278 w_ctr(ppc, ctr_sav); 279 w_ecr(ppc, ecr_sav); 280 281 return (0); 282 283error: 284 w_ctr(ppc, ctr_sav); 285 w_ecr(ppc, ecr_sav); 286 287 return (EINVAL); 288} 289 290static int 291ppc_detect_port(struct ppc_data *ppc) 292{ 293 294 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 295 w_dtr(ppc, 0xaa); 296 if (r_dtr(ppc) != 0xaa) 297 return (0); 298 299 return (1); 300} 301 302/* 303 * EPP timeout, according to the PC87332 manual 304 * Semantics of clearing EPP timeout bit. 305 * PC87332 - reading SPP_STR does it... 306 * SMC - write 1 to EPP timeout bit XXX 307 * Others - (?) write 0 to EPP timeout bit 308 */ 309static void 310ppc_reset_epp_timeout(struct ppc_data *ppc) 311{ 312 register char r; 313 314 r = r_str(ppc); 315 w_str(ppc, r | 0x1); 316 w_str(ppc, r & 0xfe); 317 318 return; 319} 320 321static int 322ppc_check_epp_timeout(struct ppc_data *ppc) 323{ 324 ppc_reset_epp_timeout(ppc); 325 326 return (!(r_str(ppc) & TIMEOUT)); 327} 328 329/* 330 * Configure current operating mode 331 */ 332static int 333ppc_generic_setmode(struct ppc_data *ppc, int mode) 334{ 335 u_char ecr = 0; 336 337 /* check if mode is available */ 338 if (mode && !(ppc->ppc_avm & mode)) 339 return (EINVAL); 340 341 /* if ECP mode, configure ecr register */ 342 if (ppc->ppc_avm & PPB_ECP) { 343 /* return to byte mode (keeping direction bit), 344 * no interrupt, no DMA to be able to change to 345 * ECP 346 */ 347 w_ecr(ppc, PPC_ECR_RESET); 348 ecr = PPC_DISABLE_INTR; 349 350 if (mode & PPB_EPP) 351 return (EINVAL); 352 else if (mode & PPB_ECP) 353 /* select ECP mode */ 354 ecr |= PPC_ECR_ECP; 355 else if (mode & PPB_PS2) 356 /* select PS2 mode with ECP */ 357 ecr |= PPC_ECR_PS2; 358 else 359 /* select COMPATIBLE/NIBBLE mode */ 360 ecr |= PPC_ECR_STD; 361 362 w_ecr(ppc, ecr); 363 } 364 365 ppc->ppc_mode = mode; 366 367 return (0); 368} 369 370/* 371 * The ppc driver is free to choose options like FIFO or DMA 372 * if ECP mode is available. 373 * 374 * The 'RAW' option allows the upper drivers to force the ppc mode 375 * even with FIFO, DMA available. 376 */ 377static int 378ppc_smclike_setmode(struct ppc_data *ppc, int mode) 379{ 380 u_char ecr = 0; 381 382 /* check if mode is available */ 383 if (mode && !(ppc->ppc_avm & mode)) 384 return (EINVAL); 385 386 /* if ECP mode, configure ecr register */ 387 if (ppc->ppc_avm & PPB_ECP) { 388 /* return to byte mode (keeping direction bit), 389 * no interrupt, no DMA to be able to change to 390 * ECP or EPP mode 391 */ 392 w_ecr(ppc, PPC_ECR_RESET); 393 ecr = PPC_DISABLE_INTR; 394 395 if (mode & PPB_EPP) 396 /* select EPP mode */ 397 ecr |= PPC_ECR_EPP; 398 else if (mode & PPB_ECP) 399 /* select ECP mode */ 400 ecr |= PPC_ECR_ECP; 401 else if (mode & PPB_PS2) 402 /* select PS2 mode with ECP */ 403 ecr |= PPC_ECR_PS2; 404 else 405 /* select COMPATIBLE/NIBBLE mode */ 406 ecr |= PPC_ECR_STD; 407 408 w_ecr(ppc, ecr); 409 } 410 411 ppc->ppc_mode = mode; 412 413 return (0); 414} 415 416#ifdef PPC_PROBE_CHIPSET 417/* 418 * ppc_pc873xx_detect 419 * 420 * Probe for a Natsemi PC873xx-family part. 421 * 422 * References in this function are to the National Semiconductor 423 * PC87332 datasheet TL/C/11930, May 1995 revision. 424 */ 425static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 426static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 427static int pc873xx_irqtab[] = {5, 7, 5, 0}; 428 429static int pc873xx_regstab[] = { 430 PC873_FER, PC873_FAR, PC873_PTR, 431 PC873_FCR, PC873_PCR, PC873_PMC, 432 PC873_TUP, PC873_SID, PC873_PNP0, 433 PC873_PNP1, PC873_LPTBA, -1 434}; 435 436static char *pc873xx_rnametab[] = { 437 "FER", "FAR", "PTR", "FCR", "PCR", 438 "PMC", "TUP", "SID", "PNP0", "PNP1", 439 "LPTBA", NULL 440}; 441 442static int 443ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 444{ 445 static int index = 0; 446 int idport, irq; 447 int ptr, pcr, val, i; 448 449 while ((idport = pc873xx_basetab[index++])) { 450 451 /* XXX should check first to see if this location is already claimed */ 452 453 /* 454 * Pull the 873xx through the power-on ID cycle (2.2,1.). 455 * We can't use this to locate the chip as it may already have 456 * been used by the BIOS. 457 */ 458 (void)inb(idport); (void)inb(idport); 459 (void)inb(idport); (void)inb(idport); 460 461 /* 462 * Read the SID byte. Possible values are : 463 * 464 * 01010xxx PC87334 465 * 0001xxxx PC87332 466 * 01110xxx PC87306 467 */ 468 outb(idport, PC873_SID); 469 val = inb(idport + 1); 470 if ((val & 0xf0) == 0x10) { 471 ppc->ppc_model = NS_PC87332; 472 } else if ((val & 0xf8) == 0x70) { 473 ppc->ppc_model = NS_PC87306; 474 } else if ((val & 0xf8) == 0x50) { 475 ppc->ppc_model = NS_PC87334; 476 } else { 477 if (bootverbose && (val != 0xff)) 478 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 479 continue ; /* not recognised */ 480 } 481 482 /* print registers */ 483 if (bootverbose) { 484 printf("PC873xx"); 485 for (i=0; pc873xx_regstab[i] != -1; i++) { 486 outb(idport, pc873xx_regstab[i]); 487 printf(" %s=0x%x", pc873xx_rnametab[i], 488 inb(idport + 1) & 0xff); 489 } 490 printf("\n"); 491 } 492 493 /* 494 * We think we have one. Is it enabled and where we want it to be? 495 */ 496 outb(idport, PC873_FER); 497 val = inb(idport + 1); 498 if (!(val & PC873_PPENABLE)) { 499 if (bootverbose) 500 printf("PC873xx parallel port disabled\n"); 501 continue; 502 } 503 outb(idport, PC873_FAR); 504 val = inb(idport + 1) & 0x3; 505 /* XXX we should create a driver instance for every port found */ 506 if (pc873xx_porttab[val] != ppc->ppc_base) { 507 if (bootverbose) 508 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 509 pc873xx_porttab[val], ppc->ppc_base); 510 continue; 511 } 512 513 outb(idport, PC873_PTR); 514 ptr = inb(idport + 1); 515 516 /* get irq settings */ 517 if (ppc->ppc_base == 0x378) 518 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 519 else 520 irq = pc873xx_irqtab[val]; 521 522 if (bootverbose) 523 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 524 525 /* 526 * Check if irq settings are correct 527 */ 528 if (irq != ppc->ppc_irq) { 529 /* 530 * If the chipset is not locked and base address is 0x378, 531 * we have another chance 532 */ 533 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 534 if (ppc->ppc_irq == 7) { 535 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 536 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 537 } else { 538 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 539 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 540 } 541 if (bootverbose) 542 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 543 } else { 544 if (bootverbose) 545 printf("PC873xx sorry, can't change irq setting\n"); 546 } 547 } else { 548 if (bootverbose) 549 printf("PC873xx irq settings are correct\n"); 550 } 551 552 outb(idport, PC873_PCR); 553 pcr = inb(idport + 1); 554 555 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 556 if (bootverbose) 557 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 558 559 ppc->ppc_avm |= PPB_NIBBLE; 560 if (bootverbose) 561 printf(", NIBBLE"); 562 563 if (pcr & PC873_EPPEN) { 564 ppc->ppc_avm |= PPB_EPP; 565 566 if (bootverbose) 567 printf(", EPP"); 568 569 if (pcr & PC873_EPP19) 570 ppc->ppc_epp = EPP_1_9; 571 else 572 ppc->ppc_epp = EPP_1_7; 573 574 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 575 outb(idport, PC873_PTR); 576 ptr = inb(idport + 1); 577 if (ptr & PC873_EPPRDIR) 578 printf(", Regular mode"); 579 else 580 printf(", Automatic mode"); 581 } 582 } else if (pcr & PC873_ECPEN) { 583 ppc->ppc_avm |= PPB_ECP; 584 if (bootverbose) 585 printf(", ECP"); 586 587 if (pcr & PC873_ECPCLK) { /* XXX */ 588 ppc->ppc_avm |= PPB_PS2; 589 if (bootverbose) 590 printf(", PS/2"); 591 } 592 } else { 593 outb(idport, PC873_PTR); 594 ptr = inb(idport + 1); 595 if (ptr & PC873_EXTENDED) { 596 ppc->ppc_avm |= PPB_SPP; 597 if (bootverbose) 598 printf(", SPP"); 599 } 600 } 601 } else { 602 if (bootverbose) 603 printf("PC873xx unlocked"); 604 605 if (chipset_mode & PPB_ECP) { 606 if ((chipset_mode & PPB_EPP) && bootverbose) 607 printf(", ECP+EPP not supported"); 608 609 pcr &= ~PC873_EPPEN; 610 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 611 outb(idport + 1, pcr); 612 outb(idport + 1, pcr); 613 614 if (bootverbose) 615 printf(", ECP"); 616 617 } else if (chipset_mode & PPB_EPP) { 618 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 619 pcr |= (PC873_EPPEN | PC873_EPP19); 620 outb(idport + 1, pcr); 621 outb(idport + 1, pcr); 622 623 ppc->ppc_epp = EPP_1_9; /* XXX */ 624 625 if (bootverbose) 626 printf(", EPP1.9"); 627 628 /* enable automatic direction turnover */ 629 if (ppc->ppc_model == NS_PC87332) { 630 outb(idport, PC873_PTR); 631 ptr = inb(idport + 1); 632 ptr &= ~PC873_EPPRDIR; 633 outb(idport + 1, ptr); 634 outb(idport + 1, ptr); 635 636 if (bootverbose) 637 printf(", Automatic mode"); 638 } 639 } else { 640 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 641 outb(idport + 1, pcr); 642 outb(idport + 1, pcr); 643 644 /* configure extended bit in PTR */ 645 outb(idport, PC873_PTR); 646 ptr = inb(idport + 1); 647 648 if (chipset_mode & PPB_PS2) { 649 ptr |= PC873_EXTENDED; 650 651 if (bootverbose) 652 printf(", PS/2"); 653 654 } else { 655 /* default to NIBBLE mode */ 656 ptr &= ~PC873_EXTENDED; 657 658 if (bootverbose) 659 printf(", NIBBLE"); 660 } 661 outb(idport + 1, ptr); 662 outb(idport + 1, ptr); 663 } 664 665 ppc->ppc_avm = chipset_mode; 666 } 667 668 if (bootverbose) 669 printf("\n"); 670 671 ppc->ppc_type = PPC_TYPE_GENERIC; 672 ppc_generic_setmode(ppc, chipset_mode); 673 674 return(chipset_mode); 675 } 676 return(-1); 677} 678 679/* 680 * ppc_smc37c66xgt_detect 681 * 682 * SMC FDC37C66xGT configuration. 683 */ 684static int 685ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 686{ 687 int s, i; 688 u_char r; 689 int type = -1; 690 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 691 692 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 693 694 695#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 696 697 /* 698 * Detection: enter configuration mode and read CRD register. 699 */ 700 701 s = splhigh(); 702 outb(csr, SMC665_iCODE); 703 outb(csr, SMC665_iCODE); 704 splx(s); 705 706 outb(csr, 0xd); 707 if (inb(cio) == 0x65) { 708 type = SMC_37C665GT; 709 goto config; 710 } 711 712 for (i = 0; i < 2; i++) { 713 s = splhigh(); 714 outb(csr, SMC666_iCODE); 715 outb(csr, SMC666_iCODE); 716 splx(s); 717 718 outb(csr, 0xd); 719 if (inb(cio) == 0x66) { 720 type = SMC_37C666GT; 721 break; 722 } 723 724 /* Another chance, CSR may be hard-configured to be at 0x370 */ 725 csr = SMC666_CSR; 726 } 727 728config: 729 /* 730 * If chipset not found, do not continue. 731 */ 732 if (type == -1) 733 return (-1); 734 735 /* select CR1 */ 736 outb(csr, 0x1); 737 738 /* read the port's address: bits 0 and 1 of CR1 */ 739 r = inb(cio) & SMC_CR1_ADDR; 740 if (port_address[(int)r] != ppc->ppc_base) 741 return (-1); 742 743 ppc->ppc_model = type; 744 745 /* 746 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 747 * If SPP mode is detected, try to set ECP+EPP mode 748 */ 749 750 if (bootverbose) { 751 outb(csr, 0x1); 752 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 753 inb(cio) & 0xff); 754 755 outb(csr, 0x4); 756 printf(" CR4=0x%x", inb(cio) & 0xff); 757 } 758 759 /* select CR1 */ 760 outb(csr, 0x1); 761 762 if (!chipset_mode) { 763 /* autodetect mode */ 764 765 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 766 if (type == SMC_37C666GT) { 767 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 768 if (bootverbose) 769 printf(" configuration hardwired, supposing " \ 770 "ECP+EPP SPP"); 771 772 } else 773 if ((inb(cio) & SMC_CR1_MODE) == 0) { 774 /* already in extended parallel port mode, read CR4 */ 775 outb(csr, 0x4); 776 r = (inb(cio) & SMC_CR4_EMODE); 777 778 switch (r) { 779 case SMC_SPP: 780 ppc->ppc_avm |= PPB_SPP; 781 if (bootverbose) 782 printf(" SPP"); 783 break; 784 785 case SMC_EPPSPP: 786 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 787 if (bootverbose) 788 printf(" EPP SPP"); 789 break; 790 791 case SMC_ECP: 792 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 793 if (bootverbose) 794 printf(" ECP SPP"); 795 break; 796 797 case SMC_ECPEPP: 798 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 799 if (bootverbose) 800 printf(" ECP+EPP SPP"); 801 break; 802 } 803 } else { 804 /* not an extended port mode */ 805 ppc->ppc_avm |= PPB_SPP; 806 if (bootverbose) 807 printf(" SPP"); 808 } 809 810 } else { 811 /* mode forced */ 812 ppc->ppc_avm = chipset_mode; 813 814 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 815 if (type == SMC_37C666GT) 816 goto end_detect; 817 818 r = inb(cio); 819 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 820 /* do not use ECP when the mode is not forced to */ 821 outb(cio, r | SMC_CR1_MODE); 822 if (bootverbose) 823 printf(" SPP"); 824 } else { 825 /* an extended mode is selected */ 826 outb(cio, r & ~SMC_CR1_MODE); 827 828 /* read CR4 register and reset mode field */ 829 outb(csr, 0x4); 830 r = inb(cio) & ~SMC_CR4_EMODE; 831 832 if (chipset_mode & PPB_ECP) { 833 if (chipset_mode & PPB_EPP) { 834 outb(cio, r | SMC_ECPEPP); 835 if (bootverbose) 836 printf(" ECP+EPP"); 837 } else { 838 outb(cio, r | SMC_ECP); 839 if (bootverbose) 840 printf(" ECP"); 841 } 842 } else { 843 /* PPB_EPP is set */ 844 outb(cio, r | SMC_EPPSPP); 845 if (bootverbose) 846 printf(" EPP SPP"); 847 } 848 } 849 ppc->ppc_avm = chipset_mode; 850 } 851 852 /* set FIFO threshold to 16 */ 853 if (ppc->ppc_avm & PPB_ECP) { 854 /* select CRA */ 855 outb(csr, 0xa); 856 outb(cio, 16); 857 } 858 859end_detect: 860 861 if (bootverbose) 862 printf ("\n"); 863 864 if (ppc->ppc_avm & PPB_EPP) { 865 /* select CR4 */ 866 outb(csr, 0x4); 867 r = inb(cio); 868 869 /* 870 * Set the EPP protocol... 871 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 872 */ 873 if (ppc->ppc_epp == EPP_1_9) 874 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 875 else 876 outb(cio, (r | SMC_CR4_EPPTYPE)); 877 } 878 879 /* end config mode */ 880 outb(csr, 0xaa); 881 882 ppc->ppc_type = PPC_TYPE_SMCLIKE; 883 ppc_smclike_setmode(ppc, chipset_mode); 884 885 return (chipset_mode); 886} 887 888/* 889 * Winbond W83877F stuff 890 * 891 * EFER: extended function enable register 892 * EFIR: extended function index register 893 * EFDR: extended function data register 894 */ 895#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 896#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 897 898static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 899static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 900static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 901static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 902 903static int 904ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 905{ 906 int i, j, efer; 907 unsigned char r, hefere, hefras; 908 909 for (i = 0; i < 4; i ++) { 910 /* first try to enable configuration registers */ 911 efer = w83877f_efers[i]; 912 913 /* write the key to the EFER */ 914 for (j = 0; j < w83877f_keyiter[i]; j ++) 915 outb (efer, w83877f_keys[i]); 916 917 /* then check HEFERE and HEFRAS bits */ 918 outb (efir, 0x0c); 919 hefere = inb(efdr) & WINB_HEFERE; 920 921 outb (efir, 0x16); 922 hefras = inb(efdr) & WINB_HEFRAS; 923 924 /* 925 * HEFRAS HEFERE 926 * 0 1 write 89h to 250h (power-on default) 927 * 1 0 write 86h twice to 3f0h 928 * 1 1 write 87h twice to 3f0h 929 * 0 0 write 88h to 250h 930 */ 931 if ((hefere | hefras) == w83877f_hefs[i]) 932 goto found; 933 } 934 935 return (-1); /* failed */ 936 937found: 938 /* check base port address - read from CR23 */ 939 outb(efir, 0x23); 940 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 941 return (-1); 942 943 /* read CHIP ID from CR9/bits0-3 */ 944 outb(efir, 0x9); 945 946 switch (inb(efdr) & WINB_CHIPID) { 947 case WINB_W83877F_ID: 948 ppc->ppc_model = WINB_W83877F; 949 break; 950 951 case WINB_W83877AF_ID: 952 ppc->ppc_model = WINB_W83877AF; 953 break; 954 955 default: 956 ppc->ppc_model = WINB_UNKNOWN; 957 } 958 959 if (bootverbose) { 960 /* dump of registers */ 961 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 962 for (i = 0; i <= 0xd; i ++) { 963 outb(efir, i); 964 printf("0x%x ", inb(efdr)); 965 } 966 for (i = 0x10; i <= 0x17; i ++) { 967 outb(efir, i); 968 printf("0x%x ", inb(efdr)); 969 } 970 outb(efir, 0x1e); 971 printf("0x%x ", inb(efdr)); 972 for (i = 0x20; i <= 0x29; i ++) { 973 outb(efir, i); 974 printf("0x%x ", inb(efdr)); 975 } 976 printf("\n"); 977 printf("ppc%d:", ppc->ppc_unit); 978 } 979 980 ppc->ppc_type = PPC_TYPE_GENERIC; 981 982 if (!chipset_mode) { 983 /* autodetect mode */ 984 985 /* select CR0 */ 986 outb(efir, 0x0); 987 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 988 989 /* select CR9 */ 990 outb(efir, 0x9); 991 r |= (inb(efdr) & WINB_PRTMODS2); 992 993 switch (r) { 994 case WINB_W83757: 995 if (bootverbose) 996 printf("ppc%d: W83757 compatible mode\n", 997 ppc->ppc_unit); 998 return (-1); /* generic or SMC-like */ 999 1000 case WINB_EXTFDC: 1001 case WINB_EXTADP: 1002 case WINB_EXT2FDD: 1003 case WINB_JOYSTICK: 1004 if (bootverbose) 1005 printf(" not in parallel port mode\n"); 1006 return (-1); 1007 1008 case (WINB_PARALLEL | WINB_EPP_SPP): 1009 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1010 if (bootverbose) 1011 printf(" EPP SPP"); 1012 break; 1013 1014 case (WINB_PARALLEL | WINB_ECP): 1015 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1016 if (bootverbose) 1017 printf(" ECP SPP"); 1018 break; 1019 1020 case (WINB_PARALLEL | WINB_ECP_EPP): 1021 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1022 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1023 1024 if (bootverbose) 1025 printf(" ECP+EPP SPP"); 1026 break; 1027 default: 1028 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 1029 } 1030 1031 } else { 1032 /* mode forced */ 1033 1034 /* select CR9 and set PRTMODS2 bit */ 1035 outb(efir, 0x9); 1036 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1037 1038 /* select CR0 and reset PRTMODSx bits */ 1039 outb(efir, 0x0); 1040 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1041 1042 if (chipset_mode & PPB_ECP) { 1043 if (chipset_mode & PPB_EPP) { 1044 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1045 if (bootverbose) 1046 printf(" ECP+EPP"); 1047 1048 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1049 1050 } else { 1051 outb(efdr, inb(efdr) | WINB_ECP); 1052 if (bootverbose) 1053 printf(" ECP"); 1054 } 1055 } else { 1056 /* select EPP_SPP otherwise */ 1057 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1058 if (bootverbose) 1059 printf(" EPP SPP"); 1060 } 1061 ppc->ppc_avm = chipset_mode; 1062 } 1063 1064 if (bootverbose) 1065 printf("\n"); 1066 1067 /* exit configuration mode */ 1068 outb(efer, 0xaa); 1069 1070 switch (ppc->ppc_type) { 1071 case PPC_TYPE_SMCLIKE: 1072 ppc_smclike_setmode(ppc, chipset_mode); 1073 break; 1074 default: 1075 ppc_generic_setmode(ppc, chipset_mode); 1076 break; 1077 } 1078 1079 return (chipset_mode); 1080} 1081#endif 1082 1083/* 1084 * ppc_generic_detect 1085 */ 1086static int 1087ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1088{ 1089 /* default to generic */ 1090 ppc->ppc_type = PPC_TYPE_GENERIC; 1091 1092 if (bootverbose) 1093 printf("ppc%d:", ppc->ppc_unit); 1094 1095 if (!chipset_mode) { 1096 /* first, check for ECP */ 1097 w_ecr(ppc, PPC_ECR_PS2); 1098 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1099 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1100 if (bootverbose) 1101 printf(" ECP SPP"); 1102 1103 /* search for SMC style ECP+EPP mode */ 1104 w_ecr(ppc, PPC_ECR_EPP); 1105 } 1106 1107 /* try to reset EPP timeout bit */ 1108 if (ppc_check_epp_timeout(ppc)) { 1109 ppc->ppc_avm |= PPB_EPP; 1110 1111 if (ppc->ppc_avm & PPB_ECP) { 1112 /* SMC like chipset found */ 1113 ppc->ppc_model = SMC_LIKE; 1114 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1115 1116 if (bootverbose) 1117 printf(" ECP+EPP"); 1118 } else { 1119 if (bootverbose) 1120 printf(" EPP"); 1121 } 1122 } else { 1123 /* restore to standard mode */ 1124 w_ecr(ppc, PPC_ECR_STD); 1125 } 1126 1127 /* XXX try to detect NIBBLE and PS2 modes */ 1128 ppc->ppc_avm |= PPB_NIBBLE; 1129 1130 if (bootverbose) 1131 printf(" SPP"); 1132 1133 } else { 1134 ppc->ppc_avm = chipset_mode; 1135 } 1136 1137 if (bootverbose) 1138 printf("\n"); 1139 1140 switch (ppc->ppc_type) { 1141 case PPC_TYPE_SMCLIKE: 1142 ppc_smclike_setmode(ppc, chipset_mode); 1143 break; 1144 default: 1145 ppc_generic_setmode(ppc, chipset_mode); 1146 break; 1147 } 1148 1149 return (chipset_mode); 1150} 1151 1152/* 1153 * ppc_detect() 1154 * 1155 * mode is the mode suggested at boot 1156 */ 1157static int 1158ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1159 1160#ifdef PPC_PROBE_CHIPSET 1161 int i, mode; 1162 1163 /* list of supported chipsets */ 1164 int (*chipset_detect[])(struct ppc_data *, int) = { 1165 ppc_pc873xx_detect, 1166 ppc_smc37c66xgt_detect, 1167 ppc_w83877f_detect, 1168 ppc_generic_detect, 1169 NULL 1170 }; 1171#endif 1172 1173 /* if can't find the port and mode not forced return error */ 1174 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1175 return (EIO); /* failed, port not present */ 1176 1177 /* assume centronics compatible mode is supported */ 1178 ppc->ppc_avm = PPB_COMPATIBLE; 1179 1180#ifdef PPC_PROBE_CHIPSET 1181 /* we have to differenciate available chipset modes, 1182 * chipset running modes and IEEE-1284 operating modes 1183 * 1184 * after detection, the port must support running in compatible mode 1185 */ 1186 if (ppc->ppc_flags & 0x40) { 1187 if (bootverbose) 1188 printf("ppc: chipset forced to generic\n"); 1189#endif 1190 1191 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1192 1193#ifdef PPC_PROBE_CHIPSET 1194 } else { 1195 for (i=0; chipset_detect[i] != NULL; i++) { 1196 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1197 ppc->ppc_mode = mode; 1198 break; 1199 } 1200 } 1201 } 1202#endif 1203 1204 /* configure/detect ECP FIFO */ 1205 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1206 ppc_detect_fifo(ppc); 1207 1208 return (0); 1209} 1210 1211/* 1212 * ppc_exec_microseq() 1213 * 1214 * Execute a microsequence. 1215 * Microsequence mechanism is supposed to handle fast I/O operations. 1216 */ 1217static int 1218ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1219{ 1220 struct ppc_data *ppc = DEVTOSOFTC(dev); 1221 struct ppb_microseq *mi; 1222 char cc, *p; 1223 int i, iter, len; 1224 int error; 1225 1226 register int reg; 1227 register char mask; 1228 register int accum = 0; 1229 register char *ptr = 0; 1230 1231 struct ppb_microseq *stack = 0; 1232 1233/* microsequence registers are equivalent to PC-like port registers */ 1234#define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1235#define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1236 1237#define INCR_PC (mi ++) /* increment program counter */ 1238 1239 mi = *p_msq; 1240 for (;;) { 1241 switch (mi->opcode) { 1242 case MS_OP_RSET: 1243 cc = r_reg(mi->arg[0].i, ppc); 1244 cc &= (char)mi->arg[2].i; /* clear mask */ 1245 cc |= (char)mi->arg[1].i; /* assert mask */ 1246 w_reg(mi->arg[0].i, ppc, cc); 1247 INCR_PC; 1248 break; 1249 1250 case MS_OP_RASSERT_P: 1251 reg = mi->arg[1].i; 1252 ptr = ppc->ppc_ptr; 1253 1254 if ((len = mi->arg[0].i) == MS_ACCUM) { 1255 accum = ppc->ppc_accum; 1256 for (; accum; accum--) 1257 w_reg(reg, ppc, *ptr++); 1258 ppc->ppc_accum = accum; 1259 } else 1260 for (i=0; i<len; i++) 1261 w_reg(reg, ppc, *ptr++); 1262 ppc->ppc_ptr = ptr; 1263 1264 INCR_PC; 1265 break; 1266 1267 case MS_OP_RFETCH_P: 1268 reg = mi->arg[1].i; 1269 mask = (char)mi->arg[2].i; 1270 ptr = ppc->ppc_ptr; 1271 1272 if ((len = mi->arg[0].i) == MS_ACCUM) { 1273 accum = ppc->ppc_accum; 1274 for (; accum; accum--) 1275 *ptr++ = r_reg(reg, ppc) & mask; 1276 ppc->ppc_accum = accum; 1277 } else 1278 for (i=0; i<len; i++) 1279 *ptr++ = r_reg(reg, ppc) & mask; 1280 ppc->ppc_ptr = ptr; 1281 1282 INCR_PC; 1283 break; 1284 1285 case MS_OP_RFETCH: 1286 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1287 (char)mi->arg[1].i; 1288 INCR_PC; 1289 break; 1290 1291 case MS_OP_RASSERT: 1292 case MS_OP_DELAY: 1293 1294 /* let's suppose the next instr. is the same */ 1295 prefetch: 1296 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1297 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1298 1299 if (mi->opcode == MS_OP_DELAY) { 1300 DELAY(mi->arg[0].i); 1301 INCR_PC; 1302 goto prefetch; 1303 } 1304 break; 1305 1306 case MS_OP_ADELAY: 1307 if (mi->arg[0].i) 1308 tsleep(NULL, PPBPRI, "ppbdelay", 1309 mi->arg[0].i * (hz/1000)); 1310 INCR_PC; 1311 break; 1312 1313 case MS_OP_TRIG: 1314 reg = mi->arg[0].i; 1315 iter = mi->arg[1].i; 1316 p = (char *)mi->arg[2].p; 1317 1318 /* XXX delay limited to 255 us */ 1319 for (i=0; i<iter; i++) { 1320 w_reg(reg, ppc, *p++); 1321 DELAY((unsigned char)*p++); 1322 } 1323 INCR_PC; 1324 break; 1325 1326 case MS_OP_SET: 1327 ppc->ppc_accum = mi->arg[0].i; 1328 INCR_PC; 1329 break; 1330 1331 case MS_OP_DBRA: 1332 if (--ppc->ppc_accum > 0) 1333 mi += mi->arg[0].i; 1334 INCR_PC; 1335 break; 1336 1337 case MS_OP_BRSET: 1338 cc = r_str(ppc); 1339 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1340 mi += mi->arg[1].i; 1341 INCR_PC; 1342 break; 1343 1344 case MS_OP_BRCLEAR: 1345 cc = r_str(ppc); 1346 if ((cc & (char)mi->arg[0].i) == 0) 1347 mi += mi->arg[1].i; 1348 INCR_PC; 1349 break; 1350 1351 case MS_OP_BRSTAT: 1352 cc = r_str(ppc); 1353 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1354 (char)mi->arg[0].i) 1355 mi += mi->arg[2].i; 1356 INCR_PC; 1357 break; 1358 1359 case MS_OP_C_CALL: 1360 /* 1361 * If the C call returns !0 then end the microseq. 1362 * The current state of ptr is passed to the C function 1363 */ 1364 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1365 return (error); 1366 1367 INCR_PC; 1368 break; 1369 1370 case MS_OP_PTR: 1371 ppc->ppc_ptr = (char *)mi->arg[0].p; 1372 INCR_PC; 1373 break; 1374 1375 case MS_OP_CALL: 1376 if (stack) 1377 panic("%s: too much calls", __FUNCTION__); 1378 1379 if (mi->arg[0].p) { 1380 /* store the state of the actual 1381 * microsequence 1382 */ 1383 stack = mi; 1384 1385 /* jump to the new microsequence */ 1386 mi = (struct ppb_microseq *)mi->arg[0].p; 1387 } else 1388 INCR_PC; 1389 1390 break; 1391 1392 case MS_OP_SUBRET: 1393 /* retrieve microseq and pc state before the call */ 1394 mi = stack; 1395 1396 /* reset the stack */ 1397 stack = 0; 1398 1399 /* XXX return code */ 1400 1401 INCR_PC; 1402 break; 1403 1404 case MS_OP_PUT: 1405 case MS_OP_GET: 1406 case MS_OP_RET: 1407 /* can't return to ppb level during the execution 1408 * of a submicrosequence */ 1409 if (stack) 1410 panic("%s: can't return to ppb level", 1411 __FUNCTION__); 1412 1413 /* update pc for ppb level of execution */ 1414 *p_msq = mi; 1415 1416 /* return to ppb level of execution */ 1417 return (0); 1418 1419 default: 1420 panic("%s: unknown microsequence opcode 0x%x", 1421 __FUNCTION__, mi->opcode); 1422 } 1423 } 1424 1425 /* unreached */ 1426} 1427 1428static void 1429ppcintr(void *arg) 1430{ 1431 device_t dev = (device_t)arg; 1432 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1433 u_char ctr, ecr, str; 1434 1435 str = r_str(ppc); 1436 ctr = r_ctr(ppc); 1437 ecr = r_ecr(ppc); 1438 1439#if PPC_DEBUG > 1 1440 printf("![%x/%x/%x]", ctr, ecr, str); 1441#endif 1442 1443 /* don't use ecp mode with IRQENABLE set */ 1444 if (ctr & IRQENABLE) { 1445 return; 1446 } 1447 1448 /* interrupts are generated by nFault signal 1449 * only in ECP mode */ 1450 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1451 /* check if ppc driver has programmed the 1452 * nFault interrupt */ 1453 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1454 1455 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1456 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1457 } else { 1458 /* shall be handled by underlying layers XXX */ 1459 return; 1460 } 1461 } 1462 1463 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1464 /* disable interrupts (should be done by hardware though) */ 1465 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1466 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1467 ecr = r_ecr(ppc); 1468 1469 /* check if DMA completed */ 1470 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1471#ifdef PPC_DEBUG 1472 printf("a"); 1473#endif 1474 /* stop DMA */ 1475 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1476 ecr = r_ecr(ppc); 1477 1478 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1479#ifdef PPC_DEBUG 1480 printf("d"); 1481#endif 1482 isa_dmadone( 1483 ppc->ppc_dmaflags, 1484 ppc->ppc_dmaddr, 1485 ppc->ppc_dmacnt, 1486 ppc->ppc_dmachan); 1487 1488 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1489 1490 /* wakeup the waiting process */ 1491 wakeup((caddr_t)ppc); 1492 } 1493 } 1494 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1495 1496 /* classic interrupt I/O */ 1497 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1498 } 1499 1500 return; 1501} 1502 1503static int 1504ppc_read(device_t dev, char *buf, int len, int mode) 1505{ 1506 return (EINVAL); 1507} 1508 1509/* 1510 * Call this function if you want to send data in any advanced mode 1511 * of your parallel port: FIFO, DMA 1512 * 1513 * If what you want is not possible (no ECP, no DMA...), 1514 * EINVAL is returned 1515 */ 1516static int 1517ppc_write(device_t dev, char *buf, int len, int how) 1518{ 1519 struct ppc_data *ppc = DEVTOSOFTC(dev); 1520 char ecr, ecr_sav, ctr, ctr_sav; 1521 int s, error = 0; 1522 int spin; 1523 1524#ifdef PPC_DEBUG 1525 printf("w"); 1526#endif 1527 1528 ecr_sav = r_ecr(ppc); 1529 ctr_sav = r_ctr(ppc); 1530 1531 /* 1532 * Send buffer with DMA, FIFO and interrupts 1533 */ 1534 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { 1535 1536 if (ppc->ppc_dmachan >= 0) { 1537 1538 /* byte mode, no intr, no DMA, dir=0, flush fifo 1539 */ 1540 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1541 w_ecr(ppc, ecr); 1542 1543 /* disable nAck interrupts */ 1544 ctr = r_ctr(ppc); 1545 ctr &= ~IRQENABLE; 1546 w_ctr(ppc, ctr); 1547 1548 ppc->ppc_dmaflags = 0; 1549 ppc->ppc_dmaddr = (caddr_t)buf; 1550 ppc->ppc_dmacnt = (u_int)len; 1551 1552 switch (ppc->ppc_mode) { 1553 case PPB_COMPATIBLE: 1554 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1555 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1556 break; 1557 case PPB_ECP: 1558 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1559 break; 1560 default: 1561 error = EINVAL; 1562 goto error; 1563 } 1564 1565 w_ecr(ppc, ecr); 1566 ecr = r_ecr(ppc); 1567 1568 /* enter splhigh() not to be preempted 1569 * by the dma interrupt, we may miss 1570 * the wakeup otherwise 1571 */ 1572 s = splhigh(); 1573 1574 ppc->ppc_dmastat = PPC_DMA_INIT; 1575 1576 /* enable interrupts */ 1577 ecr &= ~PPC_SERVICE_INTR; 1578 ppc->ppc_irqstat = PPC_IRQ_DMA; 1579 w_ecr(ppc, ecr); 1580 1581 isa_dmastart( 1582 ppc->ppc_dmaflags, 1583 ppc->ppc_dmaddr, 1584 ppc->ppc_dmacnt, 1585 ppc->ppc_dmachan); 1586#ifdef PPC_DEBUG 1587 printf("s%d", ppc->ppc_dmacnt); 1588#endif 1589 ppc->ppc_dmastat = PPC_DMA_STARTED; 1590 1591 /* Wait for the DMA completed interrupt. We hope we won't 1592 * miss it, otherwise a signal will be necessary to unlock the 1593 * process. 1594 */ 1595 do { 1596 /* release CPU */ 1597 error = tsleep((caddr_t)ppc, 1598 PPBPRI | PCATCH, "ppcdma", 0); 1599 1600 } while (error == EWOULDBLOCK); 1601 1602 splx(s); 1603 1604 if (error) { 1605#ifdef PPC_DEBUG 1606 printf("i"); 1607#endif 1608 /* stop DMA */ 1609 isa_dmadone( 1610 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1611 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1612 1613 /* no dma, no interrupt, flush the fifo */ 1614 w_ecr(ppc, PPC_ECR_RESET); 1615 1616 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1617 goto error; 1618 } 1619 1620 /* wait for an empty fifo */ 1621 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1622 1623 for (spin=100; spin; spin--) 1624 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1625 goto fifo_empty; 1626#ifdef PPC_DEBUG 1627 printf("Z"); 1628#endif 1629 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1630 if (error != EWOULDBLOCK) { 1631#ifdef PPC_DEBUG 1632 printf("I"); 1633#endif 1634 /* no dma, no interrupt, flush the fifo */ 1635 w_ecr(ppc, PPC_ECR_RESET); 1636 1637 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1638 error = EINTR; 1639 goto error; 1640 } 1641 } 1642 1643fifo_empty: 1644 /* no dma, no interrupt, flush the fifo */ 1645 w_ecr(ppc, PPC_ECR_RESET); 1646 1647 } else 1648 error = EINVAL; /* XXX we should FIFO and 1649 * interrupts */ 1650 } else 1651 error = EINVAL; 1652 1653error: 1654 1655 /* PDRQ must be kept unasserted until nPDACK is 1656 * deasserted for a minimum of 350ns (SMC datasheet) 1657 * 1658 * Consequence may be a FIFO that never empty 1659 */ 1660 DELAY(1); 1661 1662 w_ecr(ppc, ecr_sav); 1663 w_ctr(ppc, ctr_sav); 1664 1665 return (error); 1666} 1667 1668static void 1669ppc_reset_epp(device_t dev) 1670{ 1671 struct ppc_data *ppc = DEVTOSOFTC(dev); 1672 1673 ppc_reset_epp_timeout(ppc); 1674 1675 return; 1676} 1677 1678static int 1679ppc_setmode(device_t dev, int mode) 1680{ 1681 struct ppc_data *ppc = DEVTOSOFTC(dev); 1682 1683 switch (ppc->ppc_type) { 1684 case PPC_TYPE_SMCLIKE: 1685 return (ppc_smclike_setmode(ppc, mode)); 1686 break; 1687 1688 case PPC_TYPE_GENERIC: 1689 default: 1690 return (ppc_generic_setmode(ppc, mode)); 1691 break; 1692 } 1693 1694 /* not reached */ 1695 return (ENXIO); 1696} 1697 1698static int 1699ppc_probe(device_t dev) 1700{ 1701#ifdef __i386__ 1702 static short next_bios_ppc = 0; 1703#endif 1704 struct ppc_data *ppc; 1705 device_t parent; 1706 int error; 1707 u_long port; 1708 1709 /* If we are a PNP device, abort. Otherwise we attach to *everthing* */ 1710 if (isa_get_logicalid(dev)) 1711 return ENXIO; 1712 1713 parent = device_get_parent(dev); 1714 1715 /* XXX shall be set after detection */ 1716 device_set_desc(dev, "Parallel port"); 1717 1718 /* 1719 * Allocate the ppc_data structure. 1720 */ 1721 ppc = DEVTOSOFTC(dev); 1722 bzero(ppc, sizeof(struct ppc_data)); 1723 1724 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; 1725 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; 1726 1727 /* retrieve ISA parameters */ 1728 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); 1729 1730#ifdef __i386__ 1731 /* 1732 * If port not specified, use bios list. 1733 */ 1734 if (error) { 1735 if((next_bios_ppc < BIOS_MAX_PPC) && 1736 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1737 port = *(BIOS_PORTS+next_bios_ppc++); 1738 if (bootverbose) 1739 device_printf(dev, "parallel port found at 0x%x\n", 1740 (int) port); 1741 } else { 1742 device_printf(dev, "parallel port not found.\n"); 1743 return ENXIO; 1744 } 1745 bus_set_resource(dev, SYS_RES_IOPORT, 0, port, IO_LPTSIZE); 1746 } 1747#endif 1748#ifdef __alpha__ 1749 /* 1750 * There isn't a bios list on alpha. Put it in the usual place. 1751 */ 1752 if (error) { 1753 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, IO_LPTSIZE); 1754 } 1755#endif 1756 1757 /* IO port is mandatory */ 1758 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1759 &ppc->rid_ioport, 0, ~0, 1760 IO_LPTSIZE, RF_ACTIVE); 1761 if (ppc->res_ioport == 0) { 1762 device_printf(dev, "cannot reserve I/O port range\n"); 1763 goto error; 1764 } 1765 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1766 1767 ppc->ppc_flags = device_get_flags(dev); 1768 1769 if (!(ppc->ppc_flags & 0x20)) { 1770 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq, 1771 0ul, ~0ul, 1, RF_SHAREABLE); 1772 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq, 1773 0ul, ~0ul, 1, RF_ACTIVE); 1774 } 1775 1776 if (ppc->res_irq) 1777 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1778 if (ppc->res_drq) 1779 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1780 1781 ppc->ppc_unit = device_get_unit(dev); 1782 ppc->ppc_model = GENERIC; 1783 1784 ppc->ppc_mode = PPB_COMPATIBLE; 1785 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1786 1787 ppc->ppc_type = PPC_TYPE_GENERIC; 1788 1789 /* 1790 * Try to detect the chipset and its mode. 1791 */ 1792 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1793 goto error; 1794 1795 return (0); 1796 1797error: 1798 if (ppc->res_irq != 0) { 1799 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1800 ppc->res_irq); 1801 } 1802 if (ppc->res_ioport != 0) { 1803 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1804 ppc->res_ioport); 1805 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1806 ppc->res_ioport); 1807 } 1808 if (ppc->res_drq != 0) { 1809 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1810 ppc->res_drq); 1811 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1812 ppc->res_drq); 1813 } 1814 return (ENXIO); 1815} 1816 1817static int 1818ppc_attach(device_t dev) 1819{ 1820 struct ppc_data *ppc = DEVTOSOFTC(dev); 1821 1822 device_t ppbus; 1823 device_t parent = device_get_parent(dev); 1824 1825 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1826 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1827 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1828 ppc_epp_protocol[ppc->ppc_epp] : ""); 1829 1830 if (ppc->ppc_fifo) 1831 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1832 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1833 1834 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1835 /* acquire the DMA channel forever */ /* XXX */ 1836 isa_dma_acquire(ppc->ppc_dmachan); 1837 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1838 } 1839 1840 /* add ppbus as a child of this isa to parallel bridge */ 1841 ppbus = device_add_child(dev, "ppbus", -1); 1842 1843 /* 1844 * Probe the ppbus and attach devices found. 1845 */ 1846 device_probe_and_attach(ppbus); 1847 1848 /* register the ppc interrupt handler as default */ 1849 if (ppc->res_irq) { 1850 /* default to the tty mask for registration */ /* XXX */ 1851 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, 1852 ppcintr, dev, &ppc->intr_cookie) == 0) { 1853 1854 /* remember the ppcintr is registered */ 1855 ppc->ppc_registered = 1; 1856 } 1857 } 1858 1859 return (0); 1860} 1861 1862static u_char 1863ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1864{ 1865 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1866 switch (iop) { 1867 case PPB_OUTSB_EPP: 1868 outsb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1869 break; 1870 case PPB_OUTSW_EPP: 1871 outsw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1872 break; 1873 case PPB_OUTSL_EPP: 1874 outsl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1875 break; 1876 case PPB_INSB_EPP: 1877 insb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1878 break; 1879 case PPB_INSW_EPP: 1880 insw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1881 break; 1882 case PPB_INSL_EPP: 1883 insl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1884 break; 1885 case PPB_RDTR: 1886 return (r_dtr(ppc)); 1887 break; 1888 case PPB_RSTR: 1889 return (r_str(ppc)); 1890 break; 1891 case PPB_RCTR: 1892 return (r_ctr(ppc)); 1893 break; 1894 case PPB_REPP_A: 1895 return (r_epp_A(ppc)); 1896 break; 1897 case PPB_REPP_D: 1898 return (r_epp_D(ppc)); 1899 break; 1900 case PPB_RECR: 1901 return (r_ecr(ppc)); 1902 break; 1903 case PPB_RFIFO: 1904 return (r_fifo(ppc)); 1905 break; 1906 case PPB_WDTR: 1907 w_dtr(ppc, byte); 1908 break; 1909 case PPB_WSTR: 1910 w_str(ppc, byte); 1911 break; 1912 case PPB_WCTR: 1913 w_ctr(ppc, byte); 1914 break; 1915 case PPB_WEPP_A: 1916 w_epp_A(ppc, byte); 1917 break; 1918 case PPB_WEPP_D: 1919 w_epp_D(ppc, byte); 1920 break; 1921 case PPB_WECR: 1922 w_ecr(ppc, byte); 1923 break; 1924 case PPB_WFIFO: 1925 w_fifo(ppc, byte); 1926 break; 1927 default: 1928 panic("%s: unknown I/O operation", __FUNCTION__); 1929 break; 1930 } 1931 1932 return (0); /* not significative */ 1933} 1934 1935static int 1936ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1937{ 1938 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1939 1940 switch (index) { 1941 case PPC_IVAR_EPP_PROTO: 1942 *val = (u_long)ppc->ppc_epp; 1943 break; 1944 case PPC_IVAR_IRQ: 1945 *val = (u_long)ppc->ppc_irq; 1946 break; 1947 default: 1948 return (ENOENT); 1949 } 1950 1951 return (0); 1952} 1953 1954/* 1955 * Resource is useless here since ppbus devices' interrupt handlers are 1956 * multiplexed to the same resource initially allocated by ppc 1957 */ 1958static int 1959ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 1960 void (*ihand)(void *), void *arg, void **cookiep) 1961{ 1962 int error; 1963 struct ppc_data *ppc = DEVTOSOFTC(bus); 1964 1965 if (ppc->ppc_registered) { 1966 /* XXX refuse registration if DMA is in progress */ 1967 1968 /* first, unregister the default interrupt handler */ 1969 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 1970 bus, ppc->res_irq, ppc->intr_cookie))) 1971 return (error); 1972 1973/* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 1974/* ppc->res_irq); */ 1975 1976 /* DMA/FIFO operation won't be possible anymore */ 1977 ppc->ppc_registered = 0; 1978 } 1979 1980 /* pass registration to the upper layer, ignore the incoming resource */ 1981 return (BUS_SETUP_INTR(device_get_parent(bus), child, 1982 r, flags, ihand, arg, cookiep)); 1983} 1984 1985/* 1986 * When no underlying device has a registered interrupt, register the ppc 1987 * layer one 1988 */ 1989static int 1990ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 1991{ 1992 int error; 1993 struct ppc_data *ppc = DEVTOSOFTC(bus); 1994 device_t parent = device_get_parent(bus); 1995 1996 /* pass unregistration to the upper layer */ 1997 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 1998 return (error); 1999 2000 /* default to the tty mask for registration */ /* XXX */ 2001 if (ppc->ppc_irq && 2002 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 2003 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { 2004 2005 /* remember the ppcintr is registered */ 2006 ppc->ppc_registered = 1; 2007 } 2008 2009 return (error); 2010} 2011 2012DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); 2013#endif 2014