ppc.c revision 55948
1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/ppc/ppc.c 55948 2000-01-14 05:03:23Z peter $ 27 * 28 */ 29#include "ppc.h" 30 31#if NPPC > 0 32 33#include "opt_ppc.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/kernel.h> 38#include <sys/bus.h> 39#include <sys/malloc.h> 40 41#include <vm/vm.h> 42#include <vm/pmap.h> 43#include <machine/clock.h> 44#include <machine/bus.h> 45#include <machine/resource.h> 46#include <machine/vmparam.h> 47#include <sys/rman.h> 48 49#include <isa/isareg.h> 50#include <isa/isavar.h> 51 52#include <dev/ppbus/ppbconf.h> 53#include <dev/ppbus/ppb_msq.h> 54 55#include <i386/isa/ppcreg.h> 56 57#include "ppbus_if.h" 58 59#define LOG_PPC(function, ppc, string) \ 60 if (bootverbose) printf("%s: %s\n", function, string) 61 62 63#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 64 65devclass_t ppc_devclass; 66 67static int ppc_probe(device_t dev); 68static int ppc_attach(device_t dev); 69static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val); 70 71static void ppc_reset_epp(device_t); 72static void ppc_ecp_sync(device_t); 73static void ppcintr(void *arg); 74 75static int ppc_exec_microseq(device_t, struct ppb_microseq **); 76static int ppc_setmode(device_t, int); 77 78static int ppc_read(device_t, char *, int, int); 79static int ppc_write(device_t, char *, int, int); 80 81static u_char ppc_io(device_t, int, u_char *, int, u_char); 82 83static int ppc_setup_intr(device_t, device_t, struct resource *, int, 84 void (*)(void *), void *, void **); 85static int ppc_teardown_intr(device_t, device_t, struct resource *, void *); 86 87static device_method_t ppc_methods[] = { 88 /* device interface */ 89 DEVMETHOD(device_probe, ppc_probe), 90 DEVMETHOD(device_attach, ppc_attach), 91 92 /* bus interface */ 93 DEVMETHOD(bus_read_ivar, ppc_read_ivar), 94 DEVMETHOD(bus_setup_intr, ppc_setup_intr), 95 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), 96 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 97 98 /* ppbus interface */ 99 DEVMETHOD(ppbus_io, ppc_io), 100 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), 101 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), 102 DEVMETHOD(ppbus_setmode, ppc_setmode), 103 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), 104 DEVMETHOD(ppbus_read, ppc_read), 105 DEVMETHOD(ppbus_write, ppc_write), 106 107 { 0, 0 } 108 }; 109 110static driver_t ppc_driver = { 111 "ppc", 112 ppc_methods, 113 sizeof(struct ppc_data), 114}; 115 116static char *ppc_models[] = { 117 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 118 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0 119}; 120 121/* list of available modes */ 122static char *ppc_avms[] = { 123 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 124 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 125 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 126 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 127}; 128 129/* list of current executing modes 130 * Note that few modes do not actually exist. 131 */ 132static char *ppc_modes[] = { 133 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 134 "EPP", "EPP", "EPP", "ECP", 135 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 136 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 137}; 138 139static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 140 141/* 142 * BIOS printer list - used by BIOS probe. 143 */ 144#define BIOS_PPC_PORTS 0x408 145#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 146#define BIOS_MAX_PPC 4 147 148/* 149 * ppc_ecp_sync() XXX 150 */ 151static void 152ppc_ecp_sync(device_t dev) { 153 154 int i, r; 155 struct ppc_data *ppc = DEVTOSOFTC(dev); 156 157 if (!(ppc->ppc_avm & PPB_ECP)) 158 return; 159 160 r = r_ecr(ppc); 161 if ((r & 0xe0) != PPC_ECR_EPP) 162 return; 163 164 for (i = 0; i < 100; i++) { 165 r = r_ecr(ppc); 166 if (r & 0x1) 167 return; 168 DELAY(100); 169 } 170 171 printf("ppc%d: ECP sync failed as data still " \ 172 "present in FIFO.\n", ppc->ppc_unit); 173 174 return; 175} 176 177/* 178 * ppc_detect_fifo() 179 * 180 * Detect parallel port FIFO 181 */ 182static int 183ppc_detect_fifo(struct ppc_data *ppc) 184{ 185 char ecr_sav; 186 char ctr_sav, ctr, cc; 187 short i; 188 189 /* save registers */ 190 ecr_sav = r_ecr(ppc); 191 ctr_sav = r_ctr(ppc); 192 193 /* enter ECP configuration mode, no interrupt, no DMA */ 194 w_ecr(ppc, 0xf4); 195 196 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 197 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 198 199 /* XXX 16 and 32 bits implementations not supported */ 200 if (ppc->ppc_pword != PPC_PWORD_8) { 201 LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 202 goto error; 203 } 204 205 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 206 ctr = r_ctr(ppc); 207 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 208 209 /* enter ECP test mode, no interrupt, no DMA */ 210 w_ecr(ppc, 0xd4); 211 212 /* flush the FIFO */ 213 for (i=0; i<1024; i++) { 214 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 215 break; 216 cc = r_fifo(ppc); 217 } 218 219 if (i >= 1024) { 220 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 221 goto error; 222 } 223 224 /* enable interrupts, no DMA */ 225 w_ecr(ppc, 0xd0); 226 227 /* determine readIntrThreshold 228 * fill the FIFO until serviceIntr is set 229 */ 230 for (i=0; i<1024; i++) { 231 w_fifo(ppc, (char)i); 232 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 233 /* readThreshold reached */ 234 ppc->ppc_rthr = i+1; 235 } 236 if (r_ecr(ppc) & PPC_FIFO_FULL) { 237 ppc->ppc_fifo = i+1; 238 break; 239 } 240 } 241 242 if (i >= 1024) { 243 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 244 goto error; 245 } 246 247 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 248 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 249 w_ecr(ppc, 0xd0); /* enable interrupts */ 250 251 /* determine writeIntrThreshold 252 * empty the FIFO until serviceIntr is set 253 */ 254 for (i=ppc->ppc_fifo; i>0; i--) { 255 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 256 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 257 goto error; 258 } 259 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 260 /* writeIntrThreshold reached */ 261 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 262 } 263 /* if FIFO empty before the last byte, error */ 264 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 265 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 266 goto error; 267 } 268 } 269 270 /* FIFO must be empty after the last byte */ 271 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 272 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 273 goto error; 274 } 275 276 w_ctr(ppc, ctr_sav); 277 w_ecr(ppc, ecr_sav); 278 279 return (0); 280 281error: 282 w_ctr(ppc, ctr_sav); 283 w_ecr(ppc, ecr_sav); 284 285 return (EINVAL); 286} 287 288static int 289ppc_detect_port(struct ppc_data *ppc) 290{ 291 292 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 293 w_dtr(ppc, 0xaa); 294 if (r_dtr(ppc) != 0xaa) 295 return (0); 296 297 return (1); 298} 299 300/* 301 * EPP timeout, according to the PC87332 manual 302 * Semantics of clearing EPP timeout bit. 303 * PC87332 - reading SPP_STR does it... 304 * SMC - write 1 to EPP timeout bit XXX 305 * Others - (?) write 0 to EPP timeout bit 306 */ 307static void 308ppc_reset_epp_timeout(struct ppc_data *ppc) 309{ 310 register char r; 311 312 r = r_str(ppc); 313 w_str(ppc, r | 0x1); 314 w_str(ppc, r & 0xfe); 315 316 return; 317} 318 319static int 320ppc_check_epp_timeout(struct ppc_data *ppc) 321{ 322 ppc_reset_epp_timeout(ppc); 323 324 return (!(r_str(ppc) & TIMEOUT)); 325} 326 327/* 328 * Configure current operating mode 329 */ 330static int 331ppc_generic_setmode(struct ppc_data *ppc, int mode) 332{ 333 u_char ecr = 0; 334 335 /* check if mode is available */ 336 if (mode && !(ppc->ppc_avm & mode)) 337 return (EINVAL); 338 339 /* if ECP mode, configure ecr register */ 340 if (ppc->ppc_avm & PPB_ECP) { 341 /* return to byte mode (keeping direction bit), 342 * no interrupt, no DMA to be able to change to 343 * ECP 344 */ 345 w_ecr(ppc, PPC_ECR_RESET); 346 ecr = PPC_DISABLE_INTR; 347 348 if (mode & PPB_EPP) 349 return (EINVAL); 350 else if (mode & PPB_ECP) 351 /* select ECP mode */ 352 ecr |= PPC_ECR_ECP; 353 else if (mode & PPB_PS2) 354 /* select PS2 mode with ECP */ 355 ecr |= PPC_ECR_PS2; 356 else 357 /* select COMPATIBLE/NIBBLE mode */ 358 ecr |= PPC_ECR_STD; 359 360 w_ecr(ppc, ecr); 361 } 362 363 ppc->ppc_mode = mode; 364 365 return (0); 366} 367 368/* 369 * The ppc driver is free to choose options like FIFO or DMA 370 * if ECP mode is available. 371 * 372 * The 'RAW' option allows the upper drivers to force the ppc mode 373 * even with FIFO, DMA available. 374 */ 375static int 376ppc_smclike_setmode(struct ppc_data *ppc, int mode) 377{ 378 u_char ecr = 0; 379 380 /* check if mode is available */ 381 if (mode && !(ppc->ppc_avm & mode)) 382 return (EINVAL); 383 384 /* if ECP mode, configure ecr register */ 385 if (ppc->ppc_avm & PPB_ECP) { 386 /* return to byte mode (keeping direction bit), 387 * no interrupt, no DMA to be able to change to 388 * ECP or EPP mode 389 */ 390 w_ecr(ppc, PPC_ECR_RESET); 391 ecr = PPC_DISABLE_INTR; 392 393 if (mode & PPB_EPP) 394 /* select EPP mode */ 395 ecr |= PPC_ECR_EPP; 396 else if (mode & PPB_ECP) 397 /* select ECP mode */ 398 ecr |= PPC_ECR_ECP; 399 else if (mode & PPB_PS2) 400 /* select PS2 mode with ECP */ 401 ecr |= PPC_ECR_PS2; 402 else 403 /* select COMPATIBLE/NIBBLE mode */ 404 ecr |= PPC_ECR_STD; 405 406 w_ecr(ppc, ecr); 407 } 408 409 ppc->ppc_mode = mode; 410 411 return (0); 412} 413 414#ifdef PPC_PROBE_CHIPSET 415/* 416 * ppc_pc873xx_detect 417 * 418 * Probe for a Natsemi PC873xx-family part. 419 * 420 * References in this function are to the National Semiconductor 421 * PC87332 datasheet TL/C/11930, May 1995 revision. 422 */ 423static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 424static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 425static int pc873xx_irqtab[] = {5, 7, 5, 0}; 426 427static int pc873xx_regstab[] = { 428 PC873_FER, PC873_FAR, PC873_PTR, 429 PC873_FCR, PC873_PCR, PC873_PMC, 430 PC873_TUP, PC873_SID, PC873_PNP0, 431 PC873_PNP1, PC873_LPTBA, -1 432}; 433 434static char *pc873xx_rnametab[] = { 435 "FER", "FAR", "PTR", "FCR", "PCR", 436 "PMC", "TUP", "SID", "PNP0", "PNP1", 437 "LPTBA", NULL 438}; 439 440static int 441ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 442{ 443 static int index = 0; 444 int idport, irq; 445 int ptr, pcr, val, i; 446 447 while ((idport = pc873xx_basetab[index++])) { 448 449 /* XXX should check first to see if this location is already claimed */ 450 451 /* 452 * Pull the 873xx through the power-on ID cycle (2.2,1.). 453 * We can't use this to locate the chip as it may already have 454 * been used by the BIOS. 455 */ 456 (void)inb(idport); (void)inb(idport); 457 (void)inb(idport); (void)inb(idport); 458 459 /* 460 * Read the SID byte. Possible values are : 461 * 462 * 01010xxx PC87334 463 * 0001xxxx PC87332 464 * 01110xxx PC87306 465 */ 466 outb(idport, PC873_SID); 467 val = inb(idport + 1); 468 if ((val & 0xf0) == 0x10) { 469 ppc->ppc_model = NS_PC87332; 470 } else if ((val & 0xf8) == 0x70) { 471 ppc->ppc_model = NS_PC87306; 472 } else if ((val & 0xf8) == 0x50) { 473 ppc->ppc_model = NS_PC87334; 474 } else { 475 if (bootverbose && (val != 0xff)) 476 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 477 continue ; /* not recognised */ 478 } 479 480 /* print registers */ 481 if (bootverbose) { 482 printf("PC873xx"); 483 for (i=0; pc873xx_regstab[i] != -1; i++) { 484 outb(idport, pc873xx_regstab[i]); 485 printf(" %s=0x%x", pc873xx_rnametab[i], 486 inb(idport + 1) & 0xff); 487 } 488 printf("\n"); 489 } 490 491 /* 492 * We think we have one. Is it enabled and where we want it to be? 493 */ 494 outb(idport, PC873_FER); 495 val = inb(idport + 1); 496 if (!(val & PC873_PPENABLE)) { 497 if (bootverbose) 498 printf("PC873xx parallel port disabled\n"); 499 continue; 500 } 501 outb(idport, PC873_FAR); 502 val = inb(idport + 1) & 0x3; 503 /* XXX we should create a driver instance for every port found */ 504 if (pc873xx_porttab[val] != ppc->ppc_base) { 505 if (bootverbose) 506 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 507 pc873xx_porttab[val], ppc->ppc_base); 508 continue; 509 } 510 511 outb(idport, PC873_PTR); 512 ptr = inb(idport + 1); 513 514 /* get irq settings */ 515 if (ppc->ppc_base == 0x378) 516 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 517 else 518 irq = pc873xx_irqtab[val]; 519 520 if (bootverbose) 521 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 522 523 /* 524 * Check if irq settings are correct 525 */ 526 if (irq != ppc->ppc_irq) { 527 /* 528 * If the chipset is not locked and base address is 0x378, 529 * we have another chance 530 */ 531 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 532 if (ppc->ppc_irq == 7) { 533 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 534 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 535 } else { 536 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 537 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 538 } 539 if (bootverbose) 540 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 541 } else { 542 if (bootverbose) 543 printf("PC873xx sorry, can't change irq setting\n"); 544 } 545 } else { 546 if (bootverbose) 547 printf("PC873xx irq settings are correct\n"); 548 } 549 550 outb(idport, PC873_PCR); 551 pcr = inb(idport + 1); 552 553 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 554 if (bootverbose) 555 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 556 557 ppc->ppc_avm |= PPB_NIBBLE; 558 if (bootverbose) 559 printf(", NIBBLE"); 560 561 if (pcr & PC873_EPPEN) { 562 ppc->ppc_avm |= PPB_EPP; 563 564 if (bootverbose) 565 printf(", EPP"); 566 567 if (pcr & PC873_EPP19) 568 ppc->ppc_epp = EPP_1_9; 569 else 570 ppc->ppc_epp = EPP_1_7; 571 572 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 573 outb(idport, PC873_PTR); 574 ptr = inb(idport + 1); 575 if (ptr & PC873_EPPRDIR) 576 printf(", Regular mode"); 577 else 578 printf(", Automatic mode"); 579 } 580 } else if (pcr & PC873_ECPEN) { 581 ppc->ppc_avm |= PPB_ECP; 582 if (bootverbose) 583 printf(", ECP"); 584 585 if (pcr & PC873_ECPCLK) { /* XXX */ 586 ppc->ppc_avm |= PPB_PS2; 587 if (bootverbose) 588 printf(", PS/2"); 589 } 590 } else { 591 outb(idport, PC873_PTR); 592 ptr = inb(idport + 1); 593 if (ptr & PC873_EXTENDED) { 594 ppc->ppc_avm |= PPB_SPP; 595 if (bootverbose) 596 printf(", SPP"); 597 } 598 } 599 } else { 600 if (bootverbose) 601 printf("PC873xx unlocked"); 602 603 if (chipset_mode & PPB_ECP) { 604 if ((chipset_mode & PPB_EPP) && bootverbose) 605 printf(", ECP+EPP not supported"); 606 607 pcr &= ~PC873_EPPEN; 608 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 609 outb(idport + 1, pcr); 610 outb(idport + 1, pcr); 611 612 if (bootverbose) 613 printf(", ECP"); 614 615 } else if (chipset_mode & PPB_EPP) { 616 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 617 pcr |= (PC873_EPPEN | PC873_EPP19); 618 outb(idport + 1, pcr); 619 outb(idport + 1, pcr); 620 621 ppc->ppc_epp = EPP_1_9; /* XXX */ 622 623 if (bootverbose) 624 printf(", EPP1.9"); 625 626 /* enable automatic direction turnover */ 627 if (ppc->ppc_model == NS_PC87332) { 628 outb(idport, PC873_PTR); 629 ptr = inb(idport + 1); 630 ptr &= ~PC873_EPPRDIR; 631 outb(idport + 1, ptr); 632 outb(idport + 1, ptr); 633 634 if (bootverbose) 635 printf(", Automatic mode"); 636 } 637 } else { 638 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 639 outb(idport + 1, pcr); 640 outb(idport + 1, pcr); 641 642 /* configure extended bit in PTR */ 643 outb(idport, PC873_PTR); 644 ptr = inb(idport + 1); 645 646 if (chipset_mode & PPB_PS2) { 647 ptr |= PC873_EXTENDED; 648 649 if (bootverbose) 650 printf(", PS/2"); 651 652 } else { 653 /* default to NIBBLE mode */ 654 ptr &= ~PC873_EXTENDED; 655 656 if (bootverbose) 657 printf(", NIBBLE"); 658 } 659 outb(idport + 1, ptr); 660 outb(idport + 1, ptr); 661 } 662 663 ppc->ppc_avm = chipset_mode; 664 } 665 666 if (bootverbose) 667 printf("\n"); 668 669 ppc->ppc_type = PPC_TYPE_GENERIC; 670 ppc_generic_setmode(ppc, chipset_mode); 671 672 return(chipset_mode); 673 } 674 return(-1); 675} 676 677/* 678 * ppc_smc37c66xgt_detect 679 * 680 * SMC FDC37C66xGT configuration. 681 */ 682static int 683ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 684{ 685 int s, i; 686 u_char r; 687 int type = -1; 688 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 689 690 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 691 692 693#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 694 695 /* 696 * Detection: enter configuration mode and read CRD register. 697 */ 698 699 s = splhigh(); 700 outb(csr, SMC665_iCODE); 701 outb(csr, SMC665_iCODE); 702 splx(s); 703 704 outb(csr, 0xd); 705 if (inb(cio) == 0x65) { 706 type = SMC_37C665GT; 707 goto config; 708 } 709 710 for (i = 0; i < 2; i++) { 711 s = splhigh(); 712 outb(csr, SMC666_iCODE); 713 outb(csr, SMC666_iCODE); 714 splx(s); 715 716 outb(csr, 0xd); 717 if (inb(cio) == 0x66) { 718 type = SMC_37C666GT; 719 break; 720 } 721 722 /* Another chance, CSR may be hard-configured to be at 0x370 */ 723 csr = SMC666_CSR; 724 } 725 726config: 727 /* 728 * If chipset not found, do not continue. 729 */ 730 if (type == -1) 731 return (-1); 732 733 /* select CR1 */ 734 outb(csr, 0x1); 735 736 /* read the port's address: bits 0 and 1 of CR1 */ 737 r = inb(cio) & SMC_CR1_ADDR; 738 if (port_address[(int)r] != ppc->ppc_base) 739 return (-1); 740 741 ppc->ppc_model = type; 742 743 /* 744 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 745 * If SPP mode is detected, try to set ECP+EPP mode 746 */ 747 748 if (bootverbose) { 749 outb(csr, 0x1); 750 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 751 inb(cio) & 0xff); 752 753 outb(csr, 0x4); 754 printf(" CR4=0x%x", inb(cio) & 0xff); 755 } 756 757 /* select CR1 */ 758 outb(csr, 0x1); 759 760 if (!chipset_mode) { 761 /* autodetect mode */ 762 763 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 764 if (type == SMC_37C666GT) { 765 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 766 if (bootverbose) 767 printf(" configuration hardwired, supposing " \ 768 "ECP+EPP SPP"); 769 770 } else 771 if ((inb(cio) & SMC_CR1_MODE) == 0) { 772 /* already in extended parallel port mode, read CR4 */ 773 outb(csr, 0x4); 774 r = (inb(cio) & SMC_CR4_EMODE); 775 776 switch (r) { 777 case SMC_SPP: 778 ppc->ppc_avm |= PPB_SPP; 779 if (bootverbose) 780 printf(" SPP"); 781 break; 782 783 case SMC_EPPSPP: 784 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 785 if (bootverbose) 786 printf(" EPP SPP"); 787 break; 788 789 case SMC_ECP: 790 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 791 if (bootverbose) 792 printf(" ECP SPP"); 793 break; 794 795 case SMC_ECPEPP: 796 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 797 if (bootverbose) 798 printf(" ECP+EPP SPP"); 799 break; 800 } 801 } else { 802 /* not an extended port mode */ 803 ppc->ppc_avm |= PPB_SPP; 804 if (bootverbose) 805 printf(" SPP"); 806 } 807 808 } else { 809 /* mode forced */ 810 ppc->ppc_avm = chipset_mode; 811 812 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 813 if (type == SMC_37C666GT) 814 goto end_detect; 815 816 r = inb(cio); 817 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 818 /* do not use ECP when the mode is not forced to */ 819 outb(cio, r | SMC_CR1_MODE); 820 if (bootverbose) 821 printf(" SPP"); 822 } else { 823 /* an extended mode is selected */ 824 outb(cio, r & ~SMC_CR1_MODE); 825 826 /* read CR4 register and reset mode field */ 827 outb(csr, 0x4); 828 r = inb(cio) & ~SMC_CR4_EMODE; 829 830 if (chipset_mode & PPB_ECP) { 831 if (chipset_mode & PPB_EPP) { 832 outb(cio, r | SMC_ECPEPP); 833 if (bootverbose) 834 printf(" ECP+EPP"); 835 } else { 836 outb(cio, r | SMC_ECP); 837 if (bootverbose) 838 printf(" ECP"); 839 } 840 } else { 841 /* PPB_EPP is set */ 842 outb(cio, r | SMC_EPPSPP); 843 if (bootverbose) 844 printf(" EPP SPP"); 845 } 846 } 847 ppc->ppc_avm = chipset_mode; 848 } 849 850 /* set FIFO threshold to 16 */ 851 if (ppc->ppc_avm & PPB_ECP) { 852 /* select CRA */ 853 outb(csr, 0xa); 854 outb(cio, 16); 855 } 856 857end_detect: 858 859 if (bootverbose) 860 printf ("\n"); 861 862 if (ppc->ppc_avm & PPB_EPP) { 863 /* select CR4 */ 864 outb(csr, 0x4); 865 r = inb(cio); 866 867 /* 868 * Set the EPP protocol... 869 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 870 */ 871 if (ppc->ppc_epp == EPP_1_9) 872 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 873 else 874 outb(cio, (r | SMC_CR4_EPPTYPE)); 875 } 876 877 /* end config mode */ 878 outb(csr, 0xaa); 879 880 ppc->ppc_type = PPC_TYPE_SMCLIKE; 881 ppc_smclike_setmode(ppc, chipset_mode); 882 883 return (chipset_mode); 884} 885 886/* 887 * Winbond W83877F stuff 888 * 889 * EFER: extended function enable register 890 * EFIR: extended function index register 891 * EFDR: extended function data register 892 */ 893#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 894#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 895 896static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 897static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 898static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 899static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 900 901static int 902ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 903{ 904 int i, j, efer; 905 unsigned char r, hefere, hefras; 906 907 for (i = 0; i < 4; i ++) { 908 /* first try to enable configuration registers */ 909 efer = w83877f_efers[i]; 910 911 /* write the key to the EFER */ 912 for (j = 0; j < w83877f_keyiter[i]; j ++) 913 outb (efer, w83877f_keys[i]); 914 915 /* then check HEFERE and HEFRAS bits */ 916 outb (efir, 0x0c); 917 hefere = inb(efdr) & WINB_HEFERE; 918 919 outb (efir, 0x16); 920 hefras = inb(efdr) & WINB_HEFRAS; 921 922 /* 923 * HEFRAS HEFERE 924 * 0 1 write 89h to 250h (power-on default) 925 * 1 0 write 86h twice to 3f0h 926 * 1 1 write 87h twice to 3f0h 927 * 0 0 write 88h to 250h 928 */ 929 if ((hefere | hefras) == w83877f_hefs[i]) 930 goto found; 931 } 932 933 return (-1); /* failed */ 934 935found: 936 /* check base port address - read from CR23 */ 937 outb(efir, 0x23); 938 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 939 return (-1); 940 941 /* read CHIP ID from CR9/bits0-3 */ 942 outb(efir, 0x9); 943 944 switch (inb(efdr) & WINB_CHIPID) { 945 case WINB_W83877F_ID: 946 ppc->ppc_model = WINB_W83877F; 947 break; 948 949 case WINB_W83877AF_ID: 950 ppc->ppc_model = WINB_W83877AF; 951 break; 952 953 default: 954 ppc->ppc_model = WINB_UNKNOWN; 955 } 956 957 if (bootverbose) { 958 /* dump of registers */ 959 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 960 for (i = 0; i <= 0xd; i ++) { 961 outb(efir, i); 962 printf("0x%x ", inb(efdr)); 963 } 964 for (i = 0x10; i <= 0x17; i ++) { 965 outb(efir, i); 966 printf("0x%x ", inb(efdr)); 967 } 968 outb(efir, 0x1e); 969 printf("0x%x ", inb(efdr)); 970 for (i = 0x20; i <= 0x29; i ++) { 971 outb(efir, i); 972 printf("0x%x ", inb(efdr)); 973 } 974 printf("\n"); 975 printf("ppc%d:", ppc->ppc_unit); 976 } 977 978 ppc->ppc_type = PPC_TYPE_GENERIC; 979 980 if (!chipset_mode) { 981 /* autodetect mode */ 982 983 /* select CR0 */ 984 outb(efir, 0x0); 985 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 986 987 /* select CR9 */ 988 outb(efir, 0x9); 989 r |= (inb(efdr) & WINB_PRTMODS2); 990 991 switch (r) { 992 case WINB_W83757: 993 if (bootverbose) 994 printf("ppc%d: W83757 compatible mode\n", 995 ppc->ppc_unit); 996 return (-1); /* generic or SMC-like */ 997 998 case WINB_EXTFDC: 999 case WINB_EXTADP: 1000 case WINB_EXT2FDD: 1001 case WINB_JOYSTICK: 1002 if (bootverbose) 1003 printf(" not in parallel port mode\n"); 1004 return (-1); 1005 1006 case (WINB_PARALLEL | WINB_EPP_SPP): 1007 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1008 if (bootverbose) 1009 printf(" EPP SPP"); 1010 break; 1011 1012 case (WINB_PARALLEL | WINB_ECP): 1013 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1014 if (bootverbose) 1015 printf(" ECP SPP"); 1016 break; 1017 1018 case (WINB_PARALLEL | WINB_ECP_EPP): 1019 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1020 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1021 1022 if (bootverbose) 1023 printf(" ECP+EPP SPP"); 1024 break; 1025 default: 1026 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 1027 } 1028 1029 } else { 1030 /* mode forced */ 1031 1032 /* select CR9 and set PRTMODS2 bit */ 1033 outb(efir, 0x9); 1034 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1035 1036 /* select CR0 and reset PRTMODSx bits */ 1037 outb(efir, 0x0); 1038 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1039 1040 if (chipset_mode & PPB_ECP) { 1041 if (chipset_mode & PPB_EPP) { 1042 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1043 if (bootverbose) 1044 printf(" ECP+EPP"); 1045 1046 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1047 1048 } else { 1049 outb(efdr, inb(efdr) | WINB_ECP); 1050 if (bootverbose) 1051 printf(" ECP"); 1052 } 1053 } else { 1054 /* select EPP_SPP otherwise */ 1055 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1056 if (bootverbose) 1057 printf(" EPP SPP"); 1058 } 1059 ppc->ppc_avm = chipset_mode; 1060 } 1061 1062 if (bootverbose) 1063 printf("\n"); 1064 1065 /* exit configuration mode */ 1066 outb(efer, 0xaa); 1067 1068 switch (ppc->ppc_type) { 1069 case PPC_TYPE_SMCLIKE: 1070 ppc_smclike_setmode(ppc, chipset_mode); 1071 break; 1072 default: 1073 ppc_generic_setmode(ppc, chipset_mode); 1074 break; 1075 } 1076 1077 return (chipset_mode); 1078} 1079#endif 1080 1081/* 1082 * ppc_generic_detect 1083 */ 1084static int 1085ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1086{ 1087 /* default to generic */ 1088 ppc->ppc_type = PPC_TYPE_GENERIC; 1089 1090 if (bootverbose) 1091 printf("ppc%d:", ppc->ppc_unit); 1092 1093 if (!chipset_mode) { 1094 /* first, check for ECP */ 1095 w_ecr(ppc, PPC_ECR_PS2); 1096 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1097 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1098 if (bootverbose) 1099 printf(" ECP SPP"); 1100 1101 /* search for SMC style ECP+EPP mode */ 1102 w_ecr(ppc, PPC_ECR_EPP); 1103 } 1104 1105 /* try to reset EPP timeout bit */ 1106 if (ppc_check_epp_timeout(ppc)) { 1107 ppc->ppc_avm |= PPB_EPP; 1108 1109 if (ppc->ppc_avm & PPB_ECP) { 1110 /* SMC like chipset found */ 1111 ppc->ppc_model = SMC_LIKE; 1112 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1113 1114 if (bootverbose) 1115 printf(" ECP+EPP"); 1116 } else { 1117 if (bootverbose) 1118 printf(" EPP"); 1119 } 1120 } else { 1121 /* restore to standard mode */ 1122 w_ecr(ppc, PPC_ECR_STD); 1123 } 1124 1125 /* XXX try to detect NIBBLE and PS2 modes */ 1126 ppc->ppc_avm |= PPB_NIBBLE; 1127 1128 if (bootverbose) 1129 printf(" SPP"); 1130 1131 } else { 1132 ppc->ppc_avm = chipset_mode; 1133 } 1134 1135 if (bootverbose) 1136 printf("\n"); 1137 1138 switch (ppc->ppc_type) { 1139 case PPC_TYPE_SMCLIKE: 1140 ppc_smclike_setmode(ppc, chipset_mode); 1141 break; 1142 default: 1143 ppc_generic_setmode(ppc, chipset_mode); 1144 break; 1145 } 1146 1147 return (chipset_mode); 1148} 1149 1150/* 1151 * ppc_detect() 1152 * 1153 * mode is the mode suggested at boot 1154 */ 1155static int 1156ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1157 1158#ifdef PPC_PROBE_CHIPSET 1159 int i, mode; 1160 1161 /* list of supported chipsets */ 1162 int (*chipset_detect[])(struct ppc_data *, int) = { 1163 ppc_pc873xx_detect, 1164 ppc_smc37c66xgt_detect, 1165 ppc_w83877f_detect, 1166 ppc_generic_detect, 1167 NULL 1168 }; 1169#endif 1170 1171 /* if can't find the port and mode not forced return error */ 1172 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1173 return (EIO); /* failed, port not present */ 1174 1175 /* assume centronics compatible mode is supported */ 1176 ppc->ppc_avm = PPB_COMPATIBLE; 1177 1178#ifdef PPC_PROBE_CHIPSET 1179 /* we have to differenciate available chipset modes, 1180 * chipset running modes and IEEE-1284 operating modes 1181 * 1182 * after detection, the port must support running in compatible mode 1183 */ 1184 if (ppc->ppc_flags & 0x40) { 1185 if (bootverbose) 1186 printf("ppc: chipset forced to generic\n"); 1187#endif 1188 1189 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1190 1191#ifdef PPC_PROBE_CHIPSET 1192 } else { 1193 for (i=0; chipset_detect[i] != NULL; i++) { 1194 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1195 ppc->ppc_mode = mode; 1196 break; 1197 } 1198 } 1199 } 1200#endif 1201 1202 /* configure/detect ECP FIFO */ 1203 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1204 ppc_detect_fifo(ppc); 1205 1206 return (0); 1207} 1208 1209/* 1210 * ppc_exec_microseq() 1211 * 1212 * Execute a microsequence. 1213 * Microsequence mechanism is supposed to handle fast I/O operations. 1214 */ 1215static int 1216ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1217{ 1218 struct ppc_data *ppc = DEVTOSOFTC(dev); 1219 struct ppb_microseq *mi; 1220 char cc, *p; 1221 int i, iter, len; 1222 int error; 1223 1224 register int reg; 1225 register char mask; 1226 register int accum = 0; 1227 register char *ptr = 0; 1228 1229 struct ppb_microseq *stack = 0; 1230 1231/* microsequence registers are equivalent to PC-like port registers */ 1232#define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1233#define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1234 1235#define INCR_PC (mi ++) /* increment program counter */ 1236 1237 mi = *p_msq; 1238 for (;;) { 1239 switch (mi->opcode) { 1240 case MS_OP_RSET: 1241 cc = r_reg(mi->arg[0].i, ppc); 1242 cc &= (char)mi->arg[2].i; /* clear mask */ 1243 cc |= (char)mi->arg[1].i; /* assert mask */ 1244 w_reg(mi->arg[0].i, ppc, cc); 1245 INCR_PC; 1246 break; 1247 1248 case MS_OP_RASSERT_P: 1249 reg = mi->arg[1].i; 1250 ptr = ppc->ppc_ptr; 1251 1252 if ((len = mi->arg[0].i) == MS_ACCUM) { 1253 accum = ppc->ppc_accum; 1254 for (; accum; accum--) 1255 w_reg(reg, ppc, *ptr++); 1256 ppc->ppc_accum = accum; 1257 } else 1258 for (i=0; i<len; i++) 1259 w_reg(reg, ppc, *ptr++); 1260 ppc->ppc_ptr = ptr; 1261 1262 INCR_PC; 1263 break; 1264 1265 case MS_OP_RFETCH_P: 1266 reg = mi->arg[1].i; 1267 mask = (char)mi->arg[2].i; 1268 ptr = ppc->ppc_ptr; 1269 1270 if ((len = mi->arg[0].i) == MS_ACCUM) { 1271 accum = ppc->ppc_accum; 1272 for (; accum; accum--) 1273 *ptr++ = r_reg(reg, ppc) & mask; 1274 ppc->ppc_accum = accum; 1275 } else 1276 for (i=0; i<len; i++) 1277 *ptr++ = r_reg(reg, ppc) & mask; 1278 ppc->ppc_ptr = ptr; 1279 1280 INCR_PC; 1281 break; 1282 1283 case MS_OP_RFETCH: 1284 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1285 (char)mi->arg[1].i; 1286 INCR_PC; 1287 break; 1288 1289 case MS_OP_RASSERT: 1290 case MS_OP_DELAY: 1291 1292 /* let's suppose the next instr. is the same */ 1293 prefetch: 1294 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1295 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1296 1297 if (mi->opcode == MS_OP_DELAY) { 1298 DELAY(mi->arg[0].i); 1299 INCR_PC; 1300 goto prefetch; 1301 } 1302 break; 1303 1304 case MS_OP_ADELAY: 1305 if (mi->arg[0].i) 1306 tsleep(NULL, PPBPRI, "ppbdelay", 1307 mi->arg[0].i * (hz/1000)); 1308 INCR_PC; 1309 break; 1310 1311 case MS_OP_TRIG: 1312 reg = mi->arg[0].i; 1313 iter = mi->arg[1].i; 1314 p = (char *)mi->arg[2].p; 1315 1316 /* XXX delay limited to 255 us */ 1317 for (i=0; i<iter; i++) { 1318 w_reg(reg, ppc, *p++); 1319 DELAY((unsigned char)*p++); 1320 } 1321 INCR_PC; 1322 break; 1323 1324 case MS_OP_SET: 1325 ppc->ppc_accum = mi->arg[0].i; 1326 INCR_PC; 1327 break; 1328 1329 case MS_OP_DBRA: 1330 if (--ppc->ppc_accum > 0) 1331 mi += mi->arg[0].i; 1332 INCR_PC; 1333 break; 1334 1335 case MS_OP_BRSET: 1336 cc = r_str(ppc); 1337 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1338 mi += mi->arg[1].i; 1339 INCR_PC; 1340 break; 1341 1342 case MS_OP_BRCLEAR: 1343 cc = r_str(ppc); 1344 if ((cc & (char)mi->arg[0].i) == 0) 1345 mi += mi->arg[1].i; 1346 INCR_PC; 1347 break; 1348 1349 case MS_OP_BRSTAT: 1350 cc = r_str(ppc); 1351 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1352 (char)mi->arg[0].i) 1353 mi += mi->arg[2].i; 1354 INCR_PC; 1355 break; 1356 1357 case MS_OP_C_CALL: 1358 /* 1359 * If the C call returns !0 then end the microseq. 1360 * The current state of ptr is passed to the C function 1361 */ 1362 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1363 return (error); 1364 1365 INCR_PC; 1366 break; 1367 1368 case MS_OP_PTR: 1369 ppc->ppc_ptr = (char *)mi->arg[0].p; 1370 INCR_PC; 1371 break; 1372 1373 case MS_OP_CALL: 1374 if (stack) 1375 panic("%s: too much calls", __FUNCTION__); 1376 1377 if (mi->arg[0].p) { 1378 /* store the state of the actual 1379 * microsequence 1380 */ 1381 stack = mi; 1382 1383 /* jump to the new microsequence */ 1384 mi = (struct ppb_microseq *)mi->arg[0].p; 1385 } else 1386 INCR_PC; 1387 1388 break; 1389 1390 case MS_OP_SUBRET: 1391 /* retrieve microseq and pc state before the call */ 1392 mi = stack; 1393 1394 /* reset the stack */ 1395 stack = 0; 1396 1397 /* XXX return code */ 1398 1399 INCR_PC; 1400 break; 1401 1402 case MS_OP_PUT: 1403 case MS_OP_GET: 1404 case MS_OP_RET: 1405 /* can't return to ppb level during the execution 1406 * of a submicrosequence */ 1407 if (stack) 1408 panic("%s: can't return to ppb level", 1409 __FUNCTION__); 1410 1411 /* update pc for ppb level of execution */ 1412 *p_msq = mi; 1413 1414 /* return to ppb level of execution */ 1415 return (0); 1416 1417 default: 1418 panic("%s: unknown microsequence opcode 0x%x", 1419 __FUNCTION__, mi->opcode); 1420 } 1421 } 1422 1423 /* unreached */ 1424} 1425 1426static void 1427ppcintr(void *arg) 1428{ 1429 device_t dev = (device_t)arg; 1430 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1431 u_char ctr, ecr, str; 1432 1433 str = r_str(ppc); 1434 ctr = r_ctr(ppc); 1435 ecr = r_ecr(ppc); 1436 1437#if PPC_DEBUG > 1 1438 printf("![%x/%x/%x]", ctr, ecr, str); 1439#endif 1440 1441 /* don't use ecp mode with IRQENABLE set */ 1442 if (ctr & IRQENABLE) { 1443 return; 1444 } 1445 1446 /* interrupts are generated by nFault signal 1447 * only in ECP mode */ 1448 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1449 /* check if ppc driver has programmed the 1450 * nFault interrupt */ 1451 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1452 1453 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1454 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1455 } else { 1456 /* shall be handled by underlying layers XXX */ 1457 return; 1458 } 1459 } 1460 1461 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1462 /* disable interrupts (should be done by hardware though) */ 1463 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1464 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1465 ecr = r_ecr(ppc); 1466 1467 /* check if DMA completed */ 1468 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1469#ifdef PPC_DEBUG 1470 printf("a"); 1471#endif 1472 /* stop DMA */ 1473 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1474 ecr = r_ecr(ppc); 1475 1476 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1477#ifdef PPC_DEBUG 1478 printf("d"); 1479#endif 1480 isa_dmadone( 1481 ppc->ppc_dmaflags, 1482 ppc->ppc_dmaddr, 1483 ppc->ppc_dmacnt, 1484 ppc->ppc_dmachan); 1485 1486 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1487 1488 /* wakeup the waiting process */ 1489 wakeup((caddr_t)ppc); 1490 } 1491 } 1492 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1493 1494 /* classic interrupt I/O */ 1495 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1496 } 1497 1498 return; 1499} 1500 1501static int 1502ppc_read(device_t dev, char *buf, int len, int mode) 1503{ 1504 return (EINVAL); 1505} 1506 1507/* 1508 * Call this function if you want to send data in any advanced mode 1509 * of your parallel port: FIFO, DMA 1510 * 1511 * If what you want is not possible (no ECP, no DMA...), 1512 * EINVAL is returned 1513 */ 1514static int 1515ppc_write(device_t dev, char *buf, int len, int how) 1516{ 1517 struct ppc_data *ppc = DEVTOSOFTC(dev); 1518 char ecr, ecr_sav, ctr, ctr_sav; 1519 int s, error = 0; 1520 int spin; 1521 1522#ifdef PPC_DEBUG 1523 printf("w"); 1524#endif 1525 1526 ecr_sav = r_ecr(ppc); 1527 ctr_sav = r_ctr(ppc); 1528 1529 /* 1530 * Send buffer with DMA, FIFO and interrupts 1531 */ 1532 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { 1533 1534 if (ppc->ppc_dmachan >= 0) { 1535 1536 /* byte mode, no intr, no DMA, dir=0, flush fifo 1537 */ 1538 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1539 w_ecr(ppc, ecr); 1540 1541 /* disable nAck interrupts */ 1542 ctr = r_ctr(ppc); 1543 ctr &= ~IRQENABLE; 1544 w_ctr(ppc, ctr); 1545 1546 ppc->ppc_dmaflags = 0; 1547 ppc->ppc_dmaddr = (caddr_t)buf; 1548 ppc->ppc_dmacnt = (u_int)len; 1549 1550 switch (ppc->ppc_mode) { 1551 case PPB_COMPATIBLE: 1552 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1553 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1554 break; 1555 case PPB_ECP: 1556 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1557 break; 1558 default: 1559 error = EINVAL; 1560 goto error; 1561 } 1562 1563 w_ecr(ppc, ecr); 1564 ecr = r_ecr(ppc); 1565 1566 /* enter splhigh() not to be preempted 1567 * by the dma interrupt, we may miss 1568 * the wakeup otherwise 1569 */ 1570 s = splhigh(); 1571 1572 ppc->ppc_dmastat = PPC_DMA_INIT; 1573 1574 /* enable interrupts */ 1575 ecr &= ~PPC_SERVICE_INTR; 1576 ppc->ppc_irqstat = PPC_IRQ_DMA; 1577 w_ecr(ppc, ecr); 1578 1579 isa_dmastart( 1580 ppc->ppc_dmaflags, 1581 ppc->ppc_dmaddr, 1582 ppc->ppc_dmacnt, 1583 ppc->ppc_dmachan); 1584#ifdef PPC_DEBUG 1585 printf("s%d", ppc->ppc_dmacnt); 1586#endif 1587 ppc->ppc_dmastat = PPC_DMA_STARTED; 1588 1589 /* Wait for the DMA completed interrupt. We hope we won't 1590 * miss it, otherwise a signal will be necessary to unlock the 1591 * process. 1592 */ 1593 do { 1594 /* release CPU */ 1595 error = tsleep((caddr_t)ppc, 1596 PPBPRI | PCATCH, "ppcdma", 0); 1597 1598 } while (error == EWOULDBLOCK); 1599 1600 splx(s); 1601 1602 if (error) { 1603#ifdef PPC_DEBUG 1604 printf("i"); 1605#endif 1606 /* stop DMA */ 1607 isa_dmadone( 1608 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1609 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1610 1611 /* no dma, no interrupt, flush the fifo */ 1612 w_ecr(ppc, PPC_ECR_RESET); 1613 1614 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1615 goto error; 1616 } 1617 1618 /* wait for an empty fifo */ 1619 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1620 1621 for (spin=100; spin; spin--) 1622 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1623 goto fifo_empty; 1624#ifdef PPC_DEBUG 1625 printf("Z"); 1626#endif 1627 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1628 if (error != EWOULDBLOCK) { 1629#ifdef PPC_DEBUG 1630 printf("I"); 1631#endif 1632 /* no dma, no interrupt, flush the fifo */ 1633 w_ecr(ppc, PPC_ECR_RESET); 1634 1635 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1636 error = EINTR; 1637 goto error; 1638 } 1639 } 1640 1641fifo_empty: 1642 /* no dma, no interrupt, flush the fifo */ 1643 w_ecr(ppc, PPC_ECR_RESET); 1644 1645 } else 1646 error = EINVAL; /* XXX we should FIFO and 1647 * interrupts */ 1648 } else 1649 error = EINVAL; 1650 1651error: 1652 1653 /* PDRQ must be kept unasserted until nPDACK is 1654 * deasserted for a minimum of 350ns (SMC datasheet) 1655 * 1656 * Consequence may be a FIFO that never empty 1657 */ 1658 DELAY(1); 1659 1660 w_ecr(ppc, ecr_sav); 1661 w_ctr(ppc, ctr_sav); 1662 1663 return (error); 1664} 1665 1666static void 1667ppc_reset_epp(device_t dev) 1668{ 1669 struct ppc_data *ppc = DEVTOSOFTC(dev); 1670 1671 ppc_reset_epp_timeout(ppc); 1672 1673 return; 1674} 1675 1676static int 1677ppc_setmode(device_t dev, int mode) 1678{ 1679 struct ppc_data *ppc = DEVTOSOFTC(dev); 1680 1681 switch (ppc->ppc_type) { 1682 case PPC_TYPE_SMCLIKE: 1683 return (ppc_smclike_setmode(ppc, mode)); 1684 break; 1685 1686 case PPC_TYPE_GENERIC: 1687 default: 1688 return (ppc_generic_setmode(ppc, mode)); 1689 break; 1690 } 1691 1692 /* not reached */ 1693 return (ENXIO); 1694} 1695 1696static int 1697ppc_probe(device_t dev) 1698{ 1699 static short next_bios_ppc = 0; 1700 struct ppc_data *ppc; 1701 device_t parent; 1702 int port; 1703 1704 /* If we are a PNP device, abort. Otherwise we attach to *everthing* */ 1705 if (isa_get_logicalid(dev)) 1706 return ENXIO; 1707 1708 parent = device_get_parent(dev); 1709 1710 /* XXX shall be set after detection */ 1711 device_set_desc(dev, "Parallel port"); 1712 1713 /* 1714 * Allocate the ppc_data structure. 1715 */ 1716 ppc = DEVTOSOFTC(dev); 1717 bzero(ppc, sizeof(struct ppc_data)); 1718 1719 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; 1720 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; 1721 1722 /* retrieve ISA parameters */ 1723 BUS_READ_IVAR(parent, dev, ISA_IVAR_PORT, &port); 1724 1725 /* 1726 * If port not specified, use bios list. 1727 */ 1728 if (port < 0) { 1729 if((next_bios_ppc < BIOS_MAX_PPC) && 1730 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1731 port = *(BIOS_PORTS+next_bios_ppc++); 1732 if (bootverbose) 1733 device_printf(dev, "parallel port found at 0x%x\n", 1734 port); 1735 } else { 1736 device_printf(dev, "parallel port not found.\n"); 1737 return ENXIO; 1738 } 1739 } 1740 ppc->ppc_base = port; 1741 1742 /* IO port is mandatory */ 1743 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1744 &ppc->rid_ioport, port, port, 1745 IO_LPTSIZE, RF_ACTIVE); 1746 if (ppc->res_ioport == 0) { 1747 device_printf(dev, "cannot reserve I/O port range\n"); 1748 goto error; 1749 } 1750 1751 ppc->ppc_flags = device_get_flags(dev); 1752 1753 if (!(ppc->ppc_flags & 0x20)) { 1754 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq, 1755 0ul, ~0ul, 1, RF_SHAREABLE); 1756 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq, 1757 0ul, ~0ul, 1, RF_ACTIVE); 1758 } 1759 1760 if (ppc->res_irq) 1761 BUS_READ_IVAR(parent, dev, ISA_IVAR_IRQ, &ppc->ppc_irq); 1762 if (ppc->res_drq) 1763 BUS_READ_IVAR(parent, dev, ISA_IVAR_DRQ, &ppc->ppc_dmachan); 1764 1765 ppc->ppc_unit = device_get_unit(dev); 1766 ppc->ppc_model = GENERIC; 1767 1768 ppc->ppc_mode = PPB_COMPATIBLE; 1769 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1770 1771 ppc->ppc_type = PPC_TYPE_GENERIC; 1772 1773 /* 1774 * Try to detect the chipset and its mode. 1775 */ 1776 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1777 goto error; 1778 1779 return (0); 1780 1781error: 1782 if (ppc->res_irq != 0) { 1783 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1784 ppc->res_irq); 1785 } 1786 if (ppc->res_ioport != 0) { 1787 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1788 ppc->res_ioport); 1789 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1790 ppc->res_ioport); 1791 } 1792 if (ppc->res_drq != 0) { 1793 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1794 ppc->res_drq); 1795 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1796 ppc->res_drq); 1797 } 1798 return (ENXIO); 1799} 1800 1801static int 1802ppc_attach(device_t dev) 1803{ 1804 struct ppc_data *ppc = DEVTOSOFTC(dev); 1805 1806 device_t ppbus; 1807 device_t parent = device_get_parent(dev); 1808 1809 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1810 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1811 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1812 ppc_epp_protocol[ppc->ppc_epp] : ""); 1813 1814 if (ppc->ppc_fifo) 1815 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1816 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1817 1818 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1819 /* acquire the DMA channel forever */ /* XXX */ 1820 isa_dma_acquire(ppc->ppc_dmachan); 1821 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1822 } 1823 1824 /* add ppbus as a child of this isa to parallel bridge */ 1825 ppbus = device_add_child(dev, "ppbus", -1); 1826 1827 /* 1828 * Probe the ppbus and attach devices found. 1829 */ 1830 device_probe_and_attach(ppbus); 1831 1832 /* register the ppc interrupt handler as default */ 1833 if (ppc->res_irq) { 1834 /* default to the tty mask for registration */ /* XXX */ 1835 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, 1836 ppcintr, dev, &ppc->intr_cookie) == 0) { 1837 1838 /* remember the ppcintr is registered */ 1839 ppc->ppc_registered = 1; 1840 } 1841 } 1842 1843 return (0); 1844} 1845 1846static u_char 1847ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1848{ 1849 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1850 switch (iop) { 1851 case PPB_OUTSB_EPP: 1852 outsb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1853 break; 1854 case PPB_OUTSW_EPP: 1855 outsw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1856 break; 1857 case PPB_OUTSL_EPP: 1858 outsl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1859 break; 1860 case PPB_INSB_EPP: 1861 insb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1862 break; 1863 case PPB_INSW_EPP: 1864 insw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1865 break; 1866 case PPB_INSL_EPP: 1867 insl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1868 break; 1869 case PPB_RDTR: 1870 return (r_dtr(ppc)); 1871 break; 1872 case PPB_RSTR: 1873 return (r_str(ppc)); 1874 break; 1875 case PPB_RCTR: 1876 return (r_ctr(ppc)); 1877 break; 1878 case PPB_REPP_A: 1879 return (r_epp_A(ppc)); 1880 break; 1881 case PPB_REPP_D: 1882 return (r_epp_D(ppc)); 1883 break; 1884 case PPB_RECR: 1885 return (r_ecr(ppc)); 1886 break; 1887 case PPB_RFIFO: 1888 return (r_fifo(ppc)); 1889 break; 1890 case PPB_WDTR: 1891 w_dtr(ppc, byte); 1892 break; 1893 case PPB_WSTR: 1894 w_str(ppc, byte); 1895 break; 1896 case PPB_WCTR: 1897 w_ctr(ppc, byte); 1898 break; 1899 case PPB_WEPP_A: 1900 w_epp_A(ppc, byte); 1901 break; 1902 case PPB_WEPP_D: 1903 w_epp_D(ppc, byte); 1904 break; 1905 case PPB_WECR: 1906 w_ecr(ppc, byte); 1907 break; 1908 case PPB_WFIFO: 1909 w_fifo(ppc, byte); 1910 break; 1911 default: 1912 panic("%s: unknown I/O operation", __FUNCTION__); 1913 break; 1914 } 1915 1916 return (0); /* not significative */ 1917} 1918 1919static int 1920ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1921{ 1922 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1923 1924 switch (index) { 1925 case PPC_IVAR_EPP_PROTO: 1926 *val = (u_long)ppc->ppc_epp; 1927 break; 1928 case PPC_IVAR_IRQ: 1929 BUS_READ_IVAR(device_get_parent(bus), bus, ISA_IVAR_IRQ, val); 1930 break; 1931 default: 1932 return (ENOENT); 1933 } 1934 1935 return (0); 1936} 1937 1938/* 1939 * Resource is useless here since ppbus devices' interrupt handlers are 1940 * multiplexed to the same resource initially allocated by ppc 1941 */ 1942static int 1943ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 1944 void (*ihand)(void *), void *arg, void **cookiep) 1945{ 1946 int error; 1947 struct ppc_data *ppc = DEVTOSOFTC(bus); 1948 1949 if (ppc->ppc_registered) { 1950 /* XXX refuse registration if DMA is in progress */ 1951 1952 /* first, unregister the default interrupt handler */ 1953 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 1954 bus, ppc->res_irq, ppc->intr_cookie))) 1955 return (error); 1956 1957/* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 1958/* ppc->res_irq); */ 1959 1960 /* DMA/FIFO operation won't be possible anymore */ 1961 ppc->ppc_registered = 0; 1962 } 1963 1964 /* pass registration to the upper layer, ignore the incoming resource */ 1965 return (BUS_SETUP_INTR(device_get_parent(bus), child, 1966 r, flags, ihand, arg, cookiep)); 1967} 1968 1969/* 1970 * When no underlying device has a registered interrupt, register the ppc 1971 * layer one 1972 */ 1973static int 1974ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 1975{ 1976 int error; 1977 struct ppc_data *ppc = DEVTOSOFTC(bus); 1978 device_t parent = device_get_parent(bus); 1979 1980 /* pass unregistration to the upper layer */ 1981 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 1982 return (error); 1983 1984 /* default to the tty mask for registration */ /* XXX */ 1985 if (ppc->ppc_irq && 1986 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 1987 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { 1988 1989 /* remember the ppcintr is registered */ 1990 ppc->ppc_registered = 1; 1991 } 1992 1993 return (error); 1994} 1995 1996DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); 1997#endif 1998