ppc.c revision 183053
1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * Copyright (c) 2001 Alcove - Nicolas Souchu 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ppc/ppc.c 183053 2008-09-15 22:26:32Z jhb $"); 30 31#include "opt_ppc.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/kernel.h> 37#include <sys/interrupt.h> 38#include <sys/module.h> 39#include <sys/malloc.h> 40#include <sys/proc.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <sys/rman.h> 45 46#ifdef __i386__ 47#include <vm/vm.h> 48#include <vm/pmap.h> 49#include <machine/vmparam.h> 50#endif 51 52#include <dev/ppbus/ppbconf.h> 53#include <dev/ppbus/ppb_msq.h> 54 55#include <dev/ppc/ppcvar.h> 56#include <dev/ppc/ppcreg.h> 57 58#include "ppbus_if.h" 59 60static void ppcintr(void *arg); 61 62#define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 63#define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 64 65#define LOG_PPC(function, ppc, string) \ 66 if (bootverbose) printf("%s: %s\n", function, string) 67 68#if defined(__i386__) && defined(PC98) 69#define PC98_IEEE_1284_DISABLE 0x100 70#define PC98_IEEE_1284_PORT 0x140 71#endif 72 73#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 74 75devclass_t ppc_devclass; 76const char ppc_driver_name[] = "ppc"; 77 78static char *ppc_models[] = { 79 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 80 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 81 "SMC FDC37C935", "PC87303", 0 82}; 83 84/* list of available modes */ 85static char *ppc_avms[] = { 86 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 87 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 88 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 89 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 90}; 91 92/* list of current executing modes 93 * Note that few modes do not actually exist. 94 */ 95static char *ppc_modes[] = { 96 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 97 "EPP", "EPP", "EPP", "ECP", 98 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 99 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 100}; 101 102static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 103 104#ifdef __i386__ 105/* 106 * BIOS printer list - used by BIOS probe. 107 */ 108#define BIOS_PPC_PORTS 0x408 109#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 110#define BIOS_MAX_PPC 4 111#endif 112 113/* 114 * ppc_ecp_sync() XXX 115 */ 116void 117ppc_ecp_sync(device_t dev) { 118 119 int i, r; 120 struct ppc_data *ppc = DEVTOSOFTC(dev); 121 122 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 123 return; 124 125 r = r_ecr(ppc); 126 if ((r & 0xe0) != PPC_ECR_EPP) 127 return; 128 129 for (i = 0; i < 100; i++) { 130 r = r_ecr(ppc); 131 if (r & 0x1) 132 return; 133 DELAY(100); 134 } 135 136 printf("ppc%d: ECP sync failed as data still " \ 137 "present in FIFO.\n", ppc->ppc_unit); 138 139 return; 140} 141 142/* 143 * ppc_detect_fifo() 144 * 145 * Detect parallel port FIFO 146 */ 147static int 148ppc_detect_fifo(struct ppc_data *ppc) 149{ 150 char ecr_sav; 151 char ctr_sav, ctr, cc; 152 short i; 153 154 /* save registers */ 155 ecr_sav = r_ecr(ppc); 156 ctr_sav = r_ctr(ppc); 157 158 /* enter ECP configuration mode, no interrupt, no DMA */ 159 w_ecr(ppc, 0xf4); 160 161 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 162 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 163 164 /* XXX 16 and 32 bits implementations not supported */ 165 if (ppc->ppc_pword != PPC_PWORD_8) { 166 LOG_PPC(__func__, ppc, "PWord not supported"); 167 goto error; 168 } 169 170 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 171 ctr = r_ctr(ppc); 172 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 173 174 /* enter ECP test mode, no interrupt, no DMA */ 175 w_ecr(ppc, 0xd4); 176 177 /* flush the FIFO */ 178 for (i=0; i<1024; i++) { 179 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 180 break; 181 cc = r_fifo(ppc); 182 } 183 184 if (i >= 1024) { 185 LOG_PPC(__func__, ppc, "can't flush FIFO"); 186 goto error; 187 } 188 189 /* enable interrupts, no DMA */ 190 w_ecr(ppc, 0xd0); 191 192 /* determine readIntrThreshold 193 * fill the FIFO until serviceIntr is set 194 */ 195 for (i=0; i<1024; i++) { 196 w_fifo(ppc, (char)i); 197 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 198 /* readThreshold reached */ 199 ppc->ppc_rthr = i+1; 200 } 201 if (r_ecr(ppc) & PPC_FIFO_FULL) { 202 ppc->ppc_fifo = i+1; 203 break; 204 } 205 } 206 207 if (i >= 1024) { 208 LOG_PPC(__func__, ppc, "can't fill FIFO"); 209 goto error; 210 } 211 212 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 213 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 214 w_ecr(ppc, 0xd0); /* enable interrupts */ 215 216 /* determine writeIntrThreshold 217 * empty the FIFO until serviceIntr is set 218 */ 219 for (i=ppc->ppc_fifo; i>0; i--) { 220 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 221 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 222 goto error; 223 } 224 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 225 /* writeIntrThreshold reached */ 226 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 227 } 228 /* if FIFO empty before the last byte, error */ 229 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 230 LOG_PPC(__func__, ppc, "data lost in FIFO"); 231 goto error; 232 } 233 } 234 235 /* FIFO must be empty after the last byte */ 236 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 237 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 238 goto error; 239 } 240 241 w_ctr(ppc, ctr_sav); 242 w_ecr(ppc, ecr_sav); 243 244 return (0); 245 246error: 247 w_ctr(ppc, ctr_sav); 248 w_ecr(ppc, ecr_sav); 249 250 return (EINVAL); 251} 252 253static int 254ppc_detect_port(struct ppc_data *ppc) 255{ 256 257 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 258 w_dtr(ppc, 0xaa); 259 if (r_dtr(ppc) != 0xaa) 260 return (0); 261 262 return (1); 263} 264 265/* 266 * EPP timeout, according to the PC87332 manual 267 * Semantics of clearing EPP timeout bit. 268 * PC87332 - reading SPP_STR does it... 269 * SMC - write 1 to EPP timeout bit XXX 270 * Others - (?) write 0 to EPP timeout bit 271 */ 272static void 273ppc_reset_epp_timeout(struct ppc_data *ppc) 274{ 275 register char r; 276 277 r = r_str(ppc); 278 w_str(ppc, r | 0x1); 279 w_str(ppc, r & 0xfe); 280 281 return; 282} 283 284static int 285ppc_check_epp_timeout(struct ppc_data *ppc) 286{ 287 ppc_reset_epp_timeout(ppc); 288 289 return (!(r_str(ppc) & TIMEOUT)); 290} 291 292/* 293 * Configure current operating mode 294 */ 295static int 296ppc_generic_setmode(struct ppc_data *ppc, int mode) 297{ 298 u_char ecr = 0; 299 300 /* check if mode is available */ 301 if (mode && !(ppc->ppc_avm & mode)) 302 return (EINVAL); 303 304 /* if ECP mode, configure ecr register */ 305 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 306 /* return to byte mode (keeping direction bit), 307 * no interrupt, no DMA to be able to change to 308 * ECP 309 */ 310 w_ecr(ppc, PPC_ECR_RESET); 311 ecr = PPC_DISABLE_INTR; 312 313 if (mode & PPB_EPP) 314 return (EINVAL); 315 else if (mode & PPB_ECP) 316 /* select ECP mode */ 317 ecr |= PPC_ECR_ECP; 318 else if (mode & PPB_PS2) 319 /* select PS2 mode with ECP */ 320 ecr |= PPC_ECR_PS2; 321 else 322 /* select COMPATIBLE/NIBBLE mode */ 323 ecr |= PPC_ECR_STD; 324 325 w_ecr(ppc, ecr); 326 } 327 328 ppc->ppc_mode = mode; 329 330 return (0); 331} 332 333/* 334 * The ppc driver is free to choose options like FIFO or DMA 335 * if ECP mode is available. 336 * 337 * The 'RAW' option allows the upper drivers to force the ppc mode 338 * even with FIFO, DMA available. 339 */ 340static int 341ppc_smclike_setmode(struct ppc_data *ppc, int mode) 342{ 343 u_char ecr = 0; 344 345 /* check if mode is available */ 346 if (mode && !(ppc->ppc_avm & mode)) 347 return (EINVAL); 348 349 /* if ECP mode, configure ecr register */ 350 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 351 /* return to byte mode (keeping direction bit), 352 * no interrupt, no DMA to be able to change to 353 * ECP or EPP mode 354 */ 355 w_ecr(ppc, PPC_ECR_RESET); 356 ecr = PPC_DISABLE_INTR; 357 358 if (mode & PPB_EPP) 359 /* select EPP mode */ 360 ecr |= PPC_ECR_EPP; 361 else if (mode & PPB_ECP) 362 /* select ECP mode */ 363 ecr |= PPC_ECR_ECP; 364 else if (mode & PPB_PS2) 365 /* select PS2 mode with ECP */ 366 ecr |= PPC_ECR_PS2; 367 else 368 /* select COMPATIBLE/NIBBLE mode */ 369 ecr |= PPC_ECR_STD; 370 371 w_ecr(ppc, ecr); 372 } 373 374 ppc->ppc_mode = mode; 375 376 return (0); 377} 378 379#ifdef PPC_PROBE_CHIPSET 380/* 381 * ppc_pc873xx_detect 382 * 383 * Probe for a Natsemi PC873xx-family part. 384 * 385 * References in this function are to the National Semiconductor 386 * PC87332 datasheet TL/C/11930, May 1995 revision. 387 */ 388static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 389static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 390static int pc873xx_irqtab[] = {5, 7, 5, 0}; 391 392static int pc873xx_regstab[] = { 393 PC873_FER, PC873_FAR, PC873_PTR, 394 PC873_FCR, PC873_PCR, PC873_PMC, 395 PC873_TUP, PC873_SID, PC873_PNP0, 396 PC873_PNP1, PC873_LPTBA, -1 397}; 398 399static char *pc873xx_rnametab[] = { 400 "FER", "FAR", "PTR", "FCR", "PCR", 401 "PMC", "TUP", "SID", "PNP0", "PNP1", 402 "LPTBA", NULL 403}; 404 405static int 406ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 407{ 408 static int index = 0; 409 int idport, irq; 410 int ptr, pcr, val, i; 411 412 while ((idport = pc873xx_basetab[index++])) { 413 414 /* XXX should check first to see if this location is already claimed */ 415 416 /* 417 * Pull the 873xx through the power-on ID cycle (2.2,1.). 418 * We can't use this to locate the chip as it may already have 419 * been used by the BIOS. 420 */ 421 (void)inb(idport); (void)inb(idport); 422 (void)inb(idport); (void)inb(idport); 423 424 /* 425 * Read the SID byte. Possible values are : 426 * 427 * 01010xxx PC87334 428 * 0001xxxx PC87332 429 * 01110xxx PC87306 430 * 00110xxx PC87303 431 */ 432 outb(idport, PC873_SID); 433 val = inb(idport + 1); 434 if ((val & 0xf0) == 0x10) { 435 ppc->ppc_model = NS_PC87332; 436 } else if ((val & 0xf8) == 0x70) { 437 ppc->ppc_model = NS_PC87306; 438 } else if ((val & 0xf8) == 0x50) { 439 ppc->ppc_model = NS_PC87334; 440 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 441 documentation, but probing 442 yielded 0x40... */ 443 ppc->ppc_model = NS_PC87303; 444 } else { 445 if (bootverbose && (val != 0xff)) 446 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 447 continue ; /* not recognised */ 448 } 449 450 /* print registers */ 451 if (bootverbose) { 452 printf("PC873xx"); 453 for (i=0; pc873xx_regstab[i] != -1; i++) { 454 outb(idport, pc873xx_regstab[i]); 455 printf(" %s=0x%x", pc873xx_rnametab[i], 456 inb(idport + 1) & 0xff); 457 } 458 printf("\n"); 459 } 460 461 /* 462 * We think we have one. Is it enabled and where we want it to be? 463 */ 464 outb(idport, PC873_FER); 465 val = inb(idport + 1); 466 if (!(val & PC873_PPENABLE)) { 467 if (bootverbose) 468 printf("PC873xx parallel port disabled\n"); 469 continue; 470 } 471 outb(idport, PC873_FAR); 472 val = inb(idport + 1); 473 /* XXX we should create a driver instance for every port found */ 474 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 475 476 /* First try to change the port address to that requested... */ 477 478 switch(ppc->ppc_base) { 479 case 0x378: 480 val &= 0xfc; 481 break; 482 483 case 0x3bc: 484 val &= 0xfd; 485 break; 486 487 case 0x278: 488 val &= 0xfe; 489 break; 490 491 default: 492 val &= 0xfd; 493 break; 494 } 495 496 outb(idport, PC873_FAR); 497 outb(idport + 1, val); 498 outb(idport + 1, val); 499 500 /* Check for success by reading back the value we supposedly 501 wrote and comparing...*/ 502 503 outb(idport, PC873_FAR); 504 val = inb(idport + 1) & 0x3; 505 506 /* If we fail, report the failure... */ 507 508 if (pc873xx_porttab[val] != ppc->ppc_base) { 509 if (bootverbose) 510 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 511 pc873xx_porttab[val], ppc->ppc_base); 512 } 513 continue; 514 } 515 516 outb(idport, PC873_PTR); 517 ptr = inb(idport + 1); 518 519 /* get irq settings */ 520 if (ppc->ppc_base == 0x378) 521 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 522 else 523 irq = pc873xx_irqtab[val]; 524 525 if (bootverbose) 526 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 527 528 /* 529 * Check if irq settings are correct 530 */ 531 if (irq != ppc->ppc_irq) { 532 /* 533 * If the chipset is not locked and base address is 0x378, 534 * we have another chance 535 */ 536 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 537 if (ppc->ppc_irq == 7) { 538 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 539 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 540 } else { 541 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 542 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 543 } 544 if (bootverbose) 545 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 546 } else { 547 if (bootverbose) 548 printf("PC873xx sorry, can't change irq setting\n"); 549 } 550 } else { 551 if (bootverbose) 552 printf("PC873xx irq settings are correct\n"); 553 } 554 555 outb(idport, PC873_PCR); 556 pcr = inb(idport + 1); 557 558 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 559 if (bootverbose) 560 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 561 562 ppc->ppc_avm |= PPB_NIBBLE; 563 if (bootverbose) 564 printf(", NIBBLE"); 565 566 if (pcr & PC873_EPPEN) { 567 ppc->ppc_avm |= PPB_EPP; 568 569 if (bootverbose) 570 printf(", EPP"); 571 572 if (pcr & PC873_EPP19) 573 ppc->ppc_epp = EPP_1_9; 574 else 575 ppc->ppc_epp = EPP_1_7; 576 577 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 578 outb(idport, PC873_PTR); 579 ptr = inb(idport + 1); 580 if (ptr & PC873_EPPRDIR) 581 printf(", Regular mode"); 582 else 583 printf(", Automatic mode"); 584 } 585 } else if (pcr & PC873_ECPEN) { 586 ppc->ppc_avm |= PPB_ECP; 587 if (bootverbose) 588 printf(", ECP"); 589 590 if (pcr & PC873_ECPCLK) { /* XXX */ 591 ppc->ppc_avm |= PPB_PS2; 592 if (bootverbose) 593 printf(", PS/2"); 594 } 595 } else { 596 outb(idport, PC873_PTR); 597 ptr = inb(idport + 1); 598 if (ptr & PC873_EXTENDED) { 599 ppc->ppc_avm |= PPB_SPP; 600 if (bootverbose) 601 printf(", SPP"); 602 } 603 } 604 } else { 605 if (bootverbose) 606 printf("PC873xx unlocked"); 607 608 if (chipset_mode & PPB_ECP) { 609 if ((chipset_mode & PPB_EPP) && bootverbose) 610 printf(", ECP+EPP not supported"); 611 612 pcr &= ~PC873_EPPEN; 613 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 614 outb(idport + 1, pcr); 615 outb(idport + 1, pcr); 616 617 if (bootverbose) 618 printf(", ECP"); 619 620 } else if (chipset_mode & PPB_EPP) { 621 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 622 pcr |= (PC873_EPPEN | PC873_EPP19); 623 outb(idport + 1, pcr); 624 outb(idport + 1, pcr); 625 626 ppc->ppc_epp = EPP_1_9; /* XXX */ 627 628 if (bootverbose) 629 printf(", EPP1.9"); 630 631 /* enable automatic direction turnover */ 632 if (ppc->ppc_model == NS_PC87332) { 633 outb(idport, PC873_PTR); 634 ptr = inb(idport + 1); 635 ptr &= ~PC873_EPPRDIR; 636 outb(idport + 1, ptr); 637 outb(idport + 1, ptr); 638 639 if (bootverbose) 640 printf(", Automatic mode"); 641 } 642 } else { 643 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 644 outb(idport + 1, pcr); 645 outb(idport + 1, pcr); 646 647 /* configure extended bit in PTR */ 648 outb(idport, PC873_PTR); 649 ptr = inb(idport + 1); 650 651 if (chipset_mode & PPB_PS2) { 652 ptr |= PC873_EXTENDED; 653 654 if (bootverbose) 655 printf(", PS/2"); 656 657 } else { 658 /* default to NIBBLE mode */ 659 ptr &= ~PC873_EXTENDED; 660 661 if (bootverbose) 662 printf(", NIBBLE"); 663 } 664 outb(idport + 1, ptr); 665 outb(idport + 1, ptr); 666 } 667 668 ppc->ppc_avm = chipset_mode; 669 } 670 671 if (bootverbose) 672 printf("\n"); 673 674 ppc->ppc_type = PPC_TYPE_GENERIC; 675 ppc_generic_setmode(ppc, chipset_mode); 676 677 return(chipset_mode); 678 } 679 return(-1); 680} 681 682/* 683 * ppc_smc37c66xgt_detect 684 * 685 * SMC FDC37C66xGT configuration. 686 */ 687static int 688ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 689{ 690 int s, i; 691 u_char r; 692 int type = -1; 693 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 694 695 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 696 697 698#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 699 700 /* 701 * Detection: enter configuration mode and read CRD register. 702 */ 703 704 s = splhigh(); 705 outb(csr, SMC665_iCODE); 706 outb(csr, SMC665_iCODE); 707 splx(s); 708 709 outb(csr, 0xd); 710 if (inb(cio) == 0x65) { 711 type = SMC_37C665GT; 712 goto config; 713 } 714 715 for (i = 0; i < 2; i++) { 716 s = splhigh(); 717 outb(csr, SMC666_iCODE); 718 outb(csr, SMC666_iCODE); 719 splx(s); 720 721 outb(csr, 0xd); 722 if (inb(cio) == 0x66) { 723 type = SMC_37C666GT; 724 break; 725 } 726 727 /* Another chance, CSR may be hard-configured to be at 0x370 */ 728 csr = SMC666_CSR; 729 } 730 731config: 732 /* 733 * If chipset not found, do not continue. 734 */ 735 if (type == -1) 736 return (-1); 737 738 /* select CR1 */ 739 outb(csr, 0x1); 740 741 /* read the port's address: bits 0 and 1 of CR1 */ 742 r = inb(cio) & SMC_CR1_ADDR; 743 if (port_address[(int)r] != ppc->ppc_base) 744 return (-1); 745 746 ppc->ppc_model = type; 747 748 /* 749 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 750 * If SPP mode is detected, try to set ECP+EPP mode 751 */ 752 753 if (bootverbose) { 754 outb(csr, 0x1); 755 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 756 inb(cio) & 0xff); 757 758 outb(csr, 0x4); 759 printf(" CR4=0x%x", inb(cio) & 0xff); 760 } 761 762 /* select CR1 */ 763 outb(csr, 0x1); 764 765 if (!chipset_mode) { 766 /* autodetect mode */ 767 768 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 769 if (type == SMC_37C666GT) { 770 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 771 if (bootverbose) 772 printf(" configuration hardwired, supposing " \ 773 "ECP+EPP SPP"); 774 775 } else 776 if ((inb(cio) & SMC_CR1_MODE) == 0) { 777 /* already in extended parallel port mode, read CR4 */ 778 outb(csr, 0x4); 779 r = (inb(cio) & SMC_CR4_EMODE); 780 781 switch (r) { 782 case SMC_SPP: 783 ppc->ppc_avm |= PPB_SPP; 784 if (bootverbose) 785 printf(" SPP"); 786 break; 787 788 case SMC_EPPSPP: 789 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 790 if (bootverbose) 791 printf(" EPP SPP"); 792 break; 793 794 case SMC_ECP: 795 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 796 if (bootverbose) 797 printf(" ECP SPP"); 798 break; 799 800 case SMC_ECPEPP: 801 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 802 if (bootverbose) 803 printf(" ECP+EPP SPP"); 804 break; 805 } 806 } else { 807 /* not an extended port mode */ 808 ppc->ppc_avm |= PPB_SPP; 809 if (bootverbose) 810 printf(" SPP"); 811 } 812 813 } else { 814 /* mode forced */ 815 ppc->ppc_avm = chipset_mode; 816 817 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 818 if (type == SMC_37C666GT) 819 goto end_detect; 820 821 r = inb(cio); 822 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 823 /* do not use ECP when the mode is not forced to */ 824 outb(cio, r | SMC_CR1_MODE); 825 if (bootverbose) 826 printf(" SPP"); 827 } else { 828 /* an extended mode is selected */ 829 outb(cio, r & ~SMC_CR1_MODE); 830 831 /* read CR4 register and reset mode field */ 832 outb(csr, 0x4); 833 r = inb(cio) & ~SMC_CR4_EMODE; 834 835 if (chipset_mode & PPB_ECP) { 836 if (chipset_mode & PPB_EPP) { 837 outb(cio, r | SMC_ECPEPP); 838 if (bootverbose) 839 printf(" ECP+EPP"); 840 } else { 841 outb(cio, r | SMC_ECP); 842 if (bootverbose) 843 printf(" ECP"); 844 } 845 } else { 846 /* PPB_EPP is set */ 847 outb(cio, r | SMC_EPPSPP); 848 if (bootverbose) 849 printf(" EPP SPP"); 850 } 851 } 852 ppc->ppc_avm = chipset_mode; 853 } 854 855 /* set FIFO threshold to 16 */ 856 if (ppc->ppc_avm & PPB_ECP) { 857 /* select CRA */ 858 outb(csr, 0xa); 859 outb(cio, 16); 860 } 861 862end_detect: 863 864 if (bootverbose) 865 printf ("\n"); 866 867 if (ppc->ppc_avm & PPB_EPP) { 868 /* select CR4 */ 869 outb(csr, 0x4); 870 r = inb(cio); 871 872 /* 873 * Set the EPP protocol... 874 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 875 */ 876 if (ppc->ppc_epp == EPP_1_9) 877 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 878 else 879 outb(cio, (r | SMC_CR4_EPPTYPE)); 880 } 881 882 /* end config mode */ 883 outb(csr, 0xaa); 884 885 ppc->ppc_type = PPC_TYPE_SMCLIKE; 886 ppc_smclike_setmode(ppc, chipset_mode); 887 888 return (chipset_mode); 889} 890 891/* 892 * SMC FDC37C935 configuration 893 * Found on many Alpha machines 894 */ 895static int 896ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 897{ 898 int s; 899 int type = -1; 900 901 s = splhigh(); 902 outb(SMC935_CFG, 0x55); /* enter config mode */ 903 outb(SMC935_CFG, 0x55); 904 splx(s); 905 906 outb(SMC935_IND, SMC935_ID); /* check device id */ 907 if (inb(SMC935_DAT) == 0x2) 908 type = SMC_37C935; 909 910 if (type == -1) { 911 outb(SMC935_CFG, 0xaa); /* exit config mode */ 912 return (-1); 913 } 914 915 ppc->ppc_model = type; 916 917 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 918 outb(SMC935_DAT, 3); /* which is logical device 3 */ 919 920 /* set io port base */ 921 outb(SMC935_IND, SMC935_PORTHI); 922 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 923 outb(SMC935_IND, SMC935_PORTLO); 924 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 925 926 if (!chipset_mode) 927 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 928 else { 929 ppc->ppc_avm = chipset_mode; 930 outb(SMC935_IND, SMC935_PPMODE); 931 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 932 933 /* SPP + EPP or just plain SPP */ 934 if (chipset_mode & (PPB_SPP)) { 935 if (chipset_mode & PPB_EPP) { 936 if (ppc->ppc_epp == EPP_1_9) { 937 outb(SMC935_IND, SMC935_PPMODE); 938 outb(SMC935_DAT, SMC935_EPP19SPP); 939 } 940 if (ppc->ppc_epp == EPP_1_7) { 941 outb(SMC935_IND, SMC935_PPMODE); 942 outb(SMC935_DAT, SMC935_EPP17SPP); 943 } 944 } else { 945 outb(SMC935_IND, SMC935_PPMODE); 946 outb(SMC935_DAT, SMC935_SPP); 947 } 948 } 949 950 /* ECP + EPP or just plain ECP */ 951 if (chipset_mode & PPB_ECP) { 952 if (chipset_mode & PPB_EPP) { 953 if (ppc->ppc_epp == EPP_1_9) { 954 outb(SMC935_IND, SMC935_PPMODE); 955 outb(SMC935_DAT, SMC935_ECPEPP19); 956 } 957 if (ppc->ppc_epp == EPP_1_7) { 958 outb(SMC935_IND, SMC935_PPMODE); 959 outb(SMC935_DAT, SMC935_ECPEPP17); 960 } 961 } else { 962 outb(SMC935_IND, SMC935_PPMODE); 963 outb(SMC935_DAT, SMC935_ECP); 964 } 965 } 966 } 967 968 outb(SMC935_CFG, 0xaa); /* exit config mode */ 969 970 ppc->ppc_type = PPC_TYPE_SMCLIKE; 971 ppc_smclike_setmode(ppc, chipset_mode); 972 973 return (chipset_mode); 974} 975 976/* 977 * Winbond W83877F stuff 978 * 979 * EFER: extended function enable register 980 * EFIR: extended function index register 981 * EFDR: extended function data register 982 */ 983#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 984#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 985 986static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 987static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 988static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 989static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 990 991static int 992ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 993{ 994 int i, j, efer; 995 unsigned char r, hefere, hefras; 996 997 for (i = 0; i < 4; i ++) { 998 /* first try to enable configuration registers */ 999 efer = w83877f_efers[i]; 1000 1001 /* write the key to the EFER */ 1002 for (j = 0; j < w83877f_keyiter[i]; j ++) 1003 outb (efer, w83877f_keys[i]); 1004 1005 /* then check HEFERE and HEFRAS bits */ 1006 outb (efir, 0x0c); 1007 hefere = inb(efdr) & WINB_HEFERE; 1008 1009 outb (efir, 0x16); 1010 hefras = inb(efdr) & WINB_HEFRAS; 1011 1012 /* 1013 * HEFRAS HEFERE 1014 * 0 1 write 89h to 250h (power-on default) 1015 * 1 0 write 86h twice to 3f0h 1016 * 1 1 write 87h twice to 3f0h 1017 * 0 0 write 88h to 250h 1018 */ 1019 if ((hefere | hefras) == w83877f_hefs[i]) 1020 goto found; 1021 } 1022 1023 return (-1); /* failed */ 1024 1025found: 1026 /* check base port address - read from CR23 */ 1027 outb(efir, 0x23); 1028 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1029 return (-1); 1030 1031 /* read CHIP ID from CR9/bits0-3 */ 1032 outb(efir, 0x9); 1033 1034 switch (inb(efdr) & WINB_CHIPID) { 1035 case WINB_W83877F_ID: 1036 ppc->ppc_model = WINB_W83877F; 1037 break; 1038 1039 case WINB_W83877AF_ID: 1040 ppc->ppc_model = WINB_W83877AF; 1041 break; 1042 1043 default: 1044 ppc->ppc_model = WINB_UNKNOWN; 1045 } 1046 1047 if (bootverbose) { 1048 /* dump of registers */ 1049 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 1050 for (i = 0; i <= 0xd; i ++) { 1051 outb(efir, i); 1052 printf("0x%x ", inb(efdr)); 1053 } 1054 for (i = 0x10; i <= 0x17; i ++) { 1055 outb(efir, i); 1056 printf("0x%x ", inb(efdr)); 1057 } 1058 outb(efir, 0x1e); 1059 printf("0x%x ", inb(efdr)); 1060 for (i = 0x20; i <= 0x29; i ++) { 1061 outb(efir, i); 1062 printf("0x%x ", inb(efdr)); 1063 } 1064 printf("\n"); 1065 printf("ppc%d:", ppc->ppc_unit); 1066 } 1067 1068 ppc->ppc_type = PPC_TYPE_GENERIC; 1069 1070 if (!chipset_mode) { 1071 /* autodetect mode */ 1072 1073 /* select CR0 */ 1074 outb(efir, 0x0); 1075 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1076 1077 /* select CR9 */ 1078 outb(efir, 0x9); 1079 r |= (inb(efdr) & WINB_PRTMODS2); 1080 1081 switch (r) { 1082 case WINB_W83757: 1083 if (bootverbose) 1084 printf("ppc%d: W83757 compatible mode\n", 1085 ppc->ppc_unit); 1086 return (-1); /* generic or SMC-like */ 1087 1088 case WINB_EXTFDC: 1089 case WINB_EXTADP: 1090 case WINB_EXT2FDD: 1091 case WINB_JOYSTICK: 1092 if (bootverbose) 1093 printf(" not in parallel port mode\n"); 1094 return (-1); 1095 1096 case (WINB_PARALLEL | WINB_EPP_SPP): 1097 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1098 if (bootverbose) 1099 printf(" EPP SPP"); 1100 break; 1101 1102 case (WINB_PARALLEL | WINB_ECP): 1103 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1104 if (bootverbose) 1105 printf(" ECP SPP"); 1106 break; 1107 1108 case (WINB_PARALLEL | WINB_ECP_EPP): 1109 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1110 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1111 1112 if (bootverbose) 1113 printf(" ECP+EPP SPP"); 1114 break; 1115 default: 1116 printf("%s: unknown case (0x%x)!\n", __func__, r); 1117 } 1118 1119 } else { 1120 /* mode forced */ 1121 1122 /* select CR9 and set PRTMODS2 bit */ 1123 outb(efir, 0x9); 1124 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1125 1126 /* select CR0 and reset PRTMODSx bits */ 1127 outb(efir, 0x0); 1128 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1129 1130 if (chipset_mode & PPB_ECP) { 1131 if (chipset_mode & PPB_EPP) { 1132 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1133 if (bootverbose) 1134 printf(" ECP+EPP"); 1135 1136 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1137 1138 } else { 1139 outb(efdr, inb(efdr) | WINB_ECP); 1140 if (bootverbose) 1141 printf(" ECP"); 1142 } 1143 } else { 1144 /* select EPP_SPP otherwise */ 1145 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1146 if (bootverbose) 1147 printf(" EPP SPP"); 1148 } 1149 ppc->ppc_avm = chipset_mode; 1150 } 1151 1152 if (bootverbose) 1153 printf("\n"); 1154 1155 /* exit configuration mode */ 1156 outb(efer, 0xaa); 1157 1158 switch (ppc->ppc_type) { 1159 case PPC_TYPE_SMCLIKE: 1160 ppc_smclike_setmode(ppc, chipset_mode); 1161 break; 1162 default: 1163 ppc_generic_setmode(ppc, chipset_mode); 1164 break; 1165 } 1166 1167 return (chipset_mode); 1168} 1169#endif 1170 1171/* 1172 * ppc_generic_detect 1173 */ 1174static int 1175ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1176{ 1177 /* default to generic */ 1178 ppc->ppc_type = PPC_TYPE_GENERIC; 1179 1180 if (bootverbose) 1181 printf("ppc%d:", ppc->ppc_unit); 1182 1183 /* first, check for ECP */ 1184 w_ecr(ppc, PPC_ECR_PS2); 1185 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1186 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1187 if (bootverbose) 1188 printf(" ECP SPP"); 1189 1190 /* search for SMC style ECP+EPP mode */ 1191 w_ecr(ppc, PPC_ECR_EPP); 1192 } 1193 1194 /* try to reset EPP timeout bit */ 1195 if (ppc_check_epp_timeout(ppc)) { 1196 ppc->ppc_dtm |= PPB_EPP; 1197 1198 if (ppc->ppc_dtm & PPB_ECP) { 1199 /* SMC like chipset found */ 1200 ppc->ppc_model = SMC_LIKE; 1201 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1202 1203 if (bootverbose) 1204 printf(" ECP+EPP"); 1205 } else { 1206 if (bootverbose) 1207 printf(" EPP"); 1208 } 1209 } else { 1210 /* restore to standard mode */ 1211 w_ecr(ppc, PPC_ECR_STD); 1212 } 1213 1214 /* XXX try to detect NIBBLE and PS2 modes */ 1215 ppc->ppc_dtm |= PPB_NIBBLE; 1216 1217 if (bootverbose) 1218 printf(" SPP"); 1219 1220 if (chipset_mode) 1221 ppc->ppc_avm = chipset_mode; 1222 else 1223 ppc->ppc_avm = ppc->ppc_dtm; 1224 1225 if (bootverbose) 1226 printf("\n"); 1227 1228 switch (ppc->ppc_type) { 1229 case PPC_TYPE_SMCLIKE: 1230 ppc_smclike_setmode(ppc, chipset_mode); 1231 break; 1232 default: 1233 ppc_generic_setmode(ppc, chipset_mode); 1234 break; 1235 } 1236 1237 return (chipset_mode); 1238} 1239 1240/* 1241 * ppc_detect() 1242 * 1243 * mode is the mode suggested at boot 1244 */ 1245static int 1246ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1247 1248#ifdef PPC_PROBE_CHIPSET 1249 int i, mode; 1250 1251 /* list of supported chipsets */ 1252 int (*chipset_detect[])(struct ppc_data *, int) = { 1253 ppc_pc873xx_detect, 1254 ppc_smc37c66xgt_detect, 1255 ppc_w83877f_detect, 1256 ppc_smc37c935_detect, 1257 ppc_generic_detect, 1258 NULL 1259 }; 1260#endif 1261 1262 /* if can't find the port and mode not forced return error */ 1263 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1264 return (EIO); /* failed, port not present */ 1265 1266 /* assume centronics compatible mode is supported */ 1267 ppc->ppc_avm = PPB_COMPATIBLE; 1268 1269#ifdef PPC_PROBE_CHIPSET 1270 /* we have to differenciate available chipset modes, 1271 * chipset running modes and IEEE-1284 operating modes 1272 * 1273 * after detection, the port must support running in compatible mode 1274 */ 1275 if (ppc->ppc_flags & 0x40) { 1276 if (bootverbose) 1277 printf("ppc: chipset forced to generic\n"); 1278#endif 1279 1280 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1281 1282#ifdef PPC_PROBE_CHIPSET 1283 } else { 1284 for (i=0; chipset_detect[i] != NULL; i++) { 1285 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1286 ppc->ppc_mode = mode; 1287 break; 1288 } 1289 } 1290 } 1291#endif 1292 1293 /* configure/detect ECP FIFO */ 1294 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1295 ppc_detect_fifo(ppc); 1296 1297 return (0); 1298} 1299 1300/* 1301 * ppc_exec_microseq() 1302 * 1303 * Execute a microsequence. 1304 * Microsequence mechanism is supposed to handle fast I/O operations. 1305 */ 1306int 1307ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1308{ 1309 struct ppc_data *ppc = DEVTOSOFTC(dev); 1310 struct ppb_microseq *mi; 1311 char cc, *p; 1312 int i, iter, len; 1313 int error; 1314 1315 register int reg; 1316 register char mask; 1317 register int accum = 0; 1318 register char *ptr = 0; 1319 1320 struct ppb_microseq *stack = 0; 1321 1322/* microsequence registers are equivalent to PC-like port registers */ 1323 1324#define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg)) 1325#define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte)) 1326 1327#define INCR_PC (mi ++) /* increment program counter */ 1328 1329 mi = *p_msq; 1330 for (;;) { 1331 switch (mi->opcode) { 1332 case MS_OP_RSET: 1333 cc = r_reg(mi->arg[0].i, ppc); 1334 cc &= (char)mi->arg[2].i; /* clear mask */ 1335 cc |= (char)mi->arg[1].i; /* assert mask */ 1336 w_reg(mi->arg[0].i, ppc, cc); 1337 INCR_PC; 1338 break; 1339 1340 case MS_OP_RASSERT_P: 1341 reg = mi->arg[1].i; 1342 ptr = ppc->ppc_ptr; 1343 1344 if ((len = mi->arg[0].i) == MS_ACCUM) { 1345 accum = ppc->ppc_accum; 1346 for (; accum; accum--) 1347 w_reg(reg, ppc, *ptr++); 1348 ppc->ppc_accum = accum; 1349 } else 1350 for (i=0; i<len; i++) 1351 w_reg(reg, ppc, *ptr++); 1352 ppc->ppc_ptr = ptr; 1353 1354 INCR_PC; 1355 break; 1356 1357 case MS_OP_RFETCH_P: 1358 reg = mi->arg[1].i; 1359 mask = (char)mi->arg[2].i; 1360 ptr = ppc->ppc_ptr; 1361 1362 if ((len = mi->arg[0].i) == MS_ACCUM) { 1363 accum = ppc->ppc_accum; 1364 for (; accum; accum--) 1365 *ptr++ = r_reg(reg, ppc) & mask; 1366 ppc->ppc_accum = accum; 1367 } else 1368 for (i=0; i<len; i++) 1369 *ptr++ = r_reg(reg, ppc) & mask; 1370 ppc->ppc_ptr = ptr; 1371 1372 INCR_PC; 1373 break; 1374 1375 case MS_OP_RFETCH: 1376 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1377 (char)mi->arg[1].i; 1378 INCR_PC; 1379 break; 1380 1381 case MS_OP_RASSERT: 1382 case MS_OP_DELAY: 1383 1384 /* let's suppose the next instr. is the same */ 1385 prefetch: 1386 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1387 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1388 1389 if (mi->opcode == MS_OP_DELAY) { 1390 DELAY(mi->arg[0].i); 1391 INCR_PC; 1392 goto prefetch; 1393 } 1394 break; 1395 1396 case MS_OP_ADELAY: 1397 if (mi->arg[0].i) 1398 pause("ppbdelay", mi->arg[0].i * (hz/1000)); 1399 INCR_PC; 1400 break; 1401 1402 case MS_OP_TRIG: 1403 reg = mi->arg[0].i; 1404 iter = mi->arg[1].i; 1405 p = (char *)mi->arg[2].p; 1406 1407 /* XXX delay limited to 255 us */ 1408 for (i=0; i<iter; i++) { 1409 w_reg(reg, ppc, *p++); 1410 DELAY((unsigned char)*p++); 1411 } 1412 INCR_PC; 1413 break; 1414 1415 case MS_OP_SET: 1416 ppc->ppc_accum = mi->arg[0].i; 1417 INCR_PC; 1418 break; 1419 1420 case MS_OP_DBRA: 1421 if (--ppc->ppc_accum > 0) 1422 mi += mi->arg[0].i; 1423 INCR_PC; 1424 break; 1425 1426 case MS_OP_BRSET: 1427 cc = r_str(ppc); 1428 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1429 mi += mi->arg[1].i; 1430 INCR_PC; 1431 break; 1432 1433 case MS_OP_BRCLEAR: 1434 cc = r_str(ppc); 1435 if ((cc & (char)mi->arg[0].i) == 0) 1436 mi += mi->arg[1].i; 1437 INCR_PC; 1438 break; 1439 1440 case MS_OP_BRSTAT: 1441 cc = r_str(ppc); 1442 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1443 (char)mi->arg[0].i) 1444 mi += mi->arg[2].i; 1445 INCR_PC; 1446 break; 1447 1448 case MS_OP_C_CALL: 1449 /* 1450 * If the C call returns !0 then end the microseq. 1451 * The current state of ptr is passed to the C function 1452 */ 1453 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1454 return (error); 1455 1456 INCR_PC; 1457 break; 1458 1459 case MS_OP_PTR: 1460 ppc->ppc_ptr = (char *)mi->arg[0].p; 1461 INCR_PC; 1462 break; 1463 1464 case MS_OP_CALL: 1465 if (stack) 1466 panic("%s: too much calls", __func__); 1467 1468 if (mi->arg[0].p) { 1469 /* store the state of the actual 1470 * microsequence 1471 */ 1472 stack = mi; 1473 1474 /* jump to the new microsequence */ 1475 mi = (struct ppb_microseq *)mi->arg[0].p; 1476 } else 1477 INCR_PC; 1478 1479 break; 1480 1481 case MS_OP_SUBRET: 1482 /* retrieve microseq and pc state before the call */ 1483 mi = stack; 1484 1485 /* reset the stack */ 1486 stack = 0; 1487 1488 /* XXX return code */ 1489 1490 INCR_PC; 1491 break; 1492 1493 case MS_OP_PUT: 1494 case MS_OP_GET: 1495 case MS_OP_RET: 1496 /* can't return to ppb level during the execution 1497 * of a submicrosequence */ 1498 if (stack) 1499 panic("%s: can't return to ppb level", 1500 __func__); 1501 1502 /* update pc for ppb level of execution */ 1503 *p_msq = mi; 1504 1505 /* return to ppb level of execution */ 1506 return (0); 1507 1508 default: 1509 panic("%s: unknown microsequence opcode 0x%x", 1510 __func__, mi->opcode); 1511 } 1512 } 1513 1514 /* unreached */ 1515} 1516 1517static void 1518ppcintr(void *arg) 1519{ 1520 struct ppc_data *ppc = arg; 1521 u_char ctr, ecr, str; 1522 1523 /* 1524 * If we have any child interrupt handlers registered, let 1525 * them handle this interrupt. 1526 * 1527 * XXX: If DMA is in progress should we just complete that w/o 1528 * doing this? 1529 */ 1530 if (ppc->ppc_child_handlers > 0) { 1531 intr_event_execute_handlers(curproc, ppc->ppc_intr_event); 1532 return; 1533 } 1534 1535 str = r_str(ppc); 1536 ctr = r_ctr(ppc); 1537 ecr = r_ecr(ppc); 1538 1539#if defined(PPC_DEBUG) && PPC_DEBUG > 1 1540 printf("![%x/%x/%x]", ctr, ecr, str); 1541#endif 1542 1543 /* don't use ecp mode with IRQENABLE set */ 1544 if (ctr & IRQENABLE) { 1545 return; 1546 } 1547 1548 /* interrupts are generated by nFault signal 1549 * only in ECP mode */ 1550 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1551 /* check if ppc driver has programmed the 1552 * nFault interrupt */ 1553 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1554 1555 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1556 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1557 } else { 1558 /* shall be handled by underlying layers XXX */ 1559 return; 1560 } 1561 } 1562 1563 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1564 /* disable interrupts (should be done by hardware though) */ 1565 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1566 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1567 ecr = r_ecr(ppc); 1568 1569 /* check if DMA completed */ 1570 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1571#ifdef PPC_DEBUG 1572 printf("a"); 1573#endif 1574 /* stop DMA */ 1575 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1576 ecr = r_ecr(ppc); 1577 1578 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1579#ifdef PPC_DEBUG 1580 printf("d"); 1581#endif 1582 ppc->ppc_dmadone(ppc); 1583 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1584 1585 /* wakeup the waiting process */ 1586 wakeup(ppc); 1587 } 1588 } 1589 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1590 1591 /* classic interrupt I/O */ 1592 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1593 } 1594 1595 return; 1596} 1597 1598int 1599ppc_read(device_t dev, char *buf, int len, int mode) 1600{ 1601 return (EINVAL); 1602} 1603 1604int 1605ppc_write(device_t dev, char *buf, int len, int how) 1606{ 1607 return (EINVAL); 1608} 1609 1610void 1611ppc_reset_epp(device_t dev) 1612{ 1613 struct ppc_data *ppc = DEVTOSOFTC(dev); 1614 1615 ppc_reset_epp_timeout(ppc); 1616 1617 return; 1618} 1619 1620int 1621ppc_setmode(device_t dev, int mode) 1622{ 1623 struct ppc_data *ppc = DEVTOSOFTC(dev); 1624 1625 switch (ppc->ppc_type) { 1626 case PPC_TYPE_SMCLIKE: 1627 return (ppc_smclike_setmode(ppc, mode)); 1628 break; 1629 1630 case PPC_TYPE_GENERIC: 1631 default: 1632 return (ppc_generic_setmode(ppc, mode)); 1633 break; 1634 } 1635 1636 /* not reached */ 1637 return (ENXIO); 1638} 1639 1640int 1641ppc_probe(device_t dev, int rid) 1642{ 1643#ifdef __i386__ 1644 static short next_bios_ppc = 0; 1645#ifdef PC98 1646 unsigned int pc98_ieee_mode = 0x00; 1647 unsigned int tmp; 1648#endif 1649#endif 1650 struct ppc_data *ppc; 1651 int error; 1652 u_long port; 1653 1654 /* 1655 * Allocate the ppc_data structure. 1656 */ 1657 ppc = DEVTOSOFTC(dev); 1658 bzero(ppc, sizeof(struct ppc_data)); 1659 1660 ppc->rid_ioport = rid; 1661 1662 /* retrieve ISA parameters */ 1663 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL); 1664 1665#ifdef __i386__ 1666 /* 1667 * If port not specified, use bios list. 1668 */ 1669 if (error) { 1670#ifdef PC98 1671 if (next_bios_ppc == 0) { 1672 /* Use default IEEE-1284 port of NEC PC-98x1 */ 1673 port = PC98_IEEE_1284_PORT; 1674 next_bios_ppc += 1; 1675 if (bootverbose) 1676 device_printf(dev, 1677 "parallel port found at 0x%x\n", 1678 (int) port); 1679 } 1680#else 1681 if((next_bios_ppc < BIOS_MAX_PPC) && 1682 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1683 port = *(BIOS_PORTS+next_bios_ppc++); 1684 if (bootverbose) 1685 device_printf(dev, "parallel port found at 0x%x\n", 1686 (int) port); 1687 } else { 1688 device_printf(dev, "parallel port not found.\n"); 1689 return ENXIO; 1690 } 1691#endif /* PC98 */ 1692 bus_set_resource(dev, SYS_RES_IOPORT, rid, port, 1693 IO_LPTSIZE_EXTENDED); 1694 } 1695#endif 1696 1697 /* IO port is mandatory */ 1698 1699 /* Try "extended" IO port range...*/ 1700 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1701 &ppc->rid_ioport, 0, ~0, 1702 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1703 1704 if (ppc->res_ioport != 0) { 1705 if (bootverbose) 1706 device_printf(dev, "using extended I/O port range\n"); 1707 } else { 1708 /* Failed? If so, then try the "normal" IO port range... */ 1709 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1710 &ppc->rid_ioport, 0, ~0, 1711 IO_LPTSIZE_NORMAL, 1712 RF_ACTIVE); 1713 if (ppc->res_ioport != 0) { 1714 if (bootverbose) 1715 device_printf(dev, "using normal I/O port range\n"); 1716 } else { 1717 device_printf(dev, "cannot reserve I/O port range\n"); 1718 goto error; 1719 } 1720 } 1721 1722 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1723 1724 ppc->ppc_flags = device_get_flags(dev); 1725 1726 if (!(ppc->ppc_flags & 0x20)) { 1727 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1728 &ppc->rid_irq, 1729 RF_SHAREABLE); 1730 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1731 &ppc->rid_drq, 1732 RF_ACTIVE); 1733 } 1734 1735 if (ppc->res_irq) 1736 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1737 if (ppc->res_drq) 1738 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1739 1740 ppc->ppc_unit = device_get_unit(dev); 1741 ppc->ppc_model = GENERIC; 1742 1743 ppc->ppc_mode = PPB_COMPATIBLE; 1744 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1745 1746 ppc->ppc_type = PPC_TYPE_GENERIC; 1747 1748#if defined(__i386__) && defined(PC98) 1749 /* 1750 * IEEE STD 1284 Function Check and Enable 1751 * for default IEEE-1284 port of NEC PC-98x1 1752 */ 1753 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1754 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1755 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1756 pc98_ieee_mode = tmp; 1757 if ((tmp & 0x10) == 0x10) { 1758 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10); 1759 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1760 if ((tmp & 0x10) == 0x10) 1761 goto error; 1762 } else { 1763 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10); 1764 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); 1765 if ((tmp & 0x10) != 0x10) 1766 goto error; 1767 } 1768 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10); 1769 } 1770#endif 1771 1772 /* 1773 * Try to detect the chipset and its mode. 1774 */ 1775 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1776 goto error; 1777 1778 return (0); 1779 1780error: 1781#if defined(__i386__) && defined(PC98) 1782 if (ppc->ppc_base == PC98_IEEE_1284_PORT && 1783 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { 1784 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode); 1785 } 1786#endif 1787 if (ppc->res_irq != 0) { 1788 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1789 ppc->res_irq); 1790 } 1791 if (ppc->res_ioport != 0) { 1792 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1793 ppc->res_ioport); 1794 } 1795 if (ppc->res_drq != 0) { 1796 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1797 ppc->res_drq); 1798 } 1799 return (ENXIO); 1800} 1801 1802int 1803ppc_attach(device_t dev) 1804{ 1805 struct ppc_data *ppc = DEVTOSOFTC(dev); 1806 device_t ppbus; 1807 int error; 1808 1809 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1810 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1811 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1812 ppc_epp_protocol[ppc->ppc_epp] : ""); 1813 1814 if (ppc->ppc_fifo) 1815 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1816 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1817 1818 if (ppc->res_irq) { 1819 /* 1820 * Create an interrupt event to manage the handlers of 1821 * child devices. 1822 */ 1823 error = intr_event_create(&ppc->ppc_intr_event, ppc, 0, -1, 1824 NULL, NULL, NULL, NULL, "%s:", device_get_nameunit(dev)); 1825 if (error) { 1826 device_printf(dev, 1827 "failed to create interrupt event: %d\n", error); 1828 return (error); 1829 } 1830 1831 /* default to the tty mask for registration */ /* XXX */ 1832 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY, 1833 NULL, ppcintr, ppc, &ppc->intr_cookie); 1834 if (error) { 1835 device_printf(dev, 1836 "failed to register interrupt handler: %d\n", 1837 error); 1838 return (error); 1839 } 1840 } 1841 1842 /* add ppbus as a child of this isa to parallel bridge */ 1843 ppbus = device_add_child(dev, "ppbus", -1); 1844 1845 /* 1846 * Probe the ppbus and attach devices found. 1847 */ 1848 device_probe_and_attach(ppbus); 1849 1850 return (0); 1851} 1852 1853int 1854ppc_detach(device_t dev) 1855{ 1856 struct ppc_data *ppc = DEVTOSOFTC(dev); 1857 device_t *children; 1858 int nchildren, i; 1859 1860 if (ppc->res_irq == 0) { 1861 return (ENXIO); 1862 } 1863 1864 /* detach & delete all children */ 1865 if (!device_get_children(dev, &children, &nchildren)) { 1866 for (i = 0; i < nchildren; i++) 1867 if (children[i]) 1868 device_delete_child(dev, children[i]); 1869 free(children, M_TEMP); 1870 } 1871 1872 if (ppc->res_irq != 0) { 1873 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie); 1874 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1875 ppc->res_irq); 1876 } 1877 if (ppc->res_ioport != 0) { 1878 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1879 ppc->res_ioport); 1880 } 1881 if (ppc->res_drq != 0) { 1882 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1883 ppc->res_drq); 1884 } 1885 1886 return (0); 1887} 1888 1889u_char 1890ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1891{ 1892 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1893 switch (iop) { 1894 case PPB_OUTSB_EPP: 1895 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1896 break; 1897 case PPB_OUTSW_EPP: 1898 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1899 break; 1900 case PPB_OUTSL_EPP: 1901 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1902 break; 1903 case PPB_INSB_EPP: 1904 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt); 1905 break; 1906 case PPB_INSW_EPP: 1907 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 1908 break; 1909 case PPB_INSL_EPP: 1910 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 1911 break; 1912 case PPB_RDTR: 1913 return (r_dtr(ppc)); 1914 case PPB_RSTR: 1915 return (r_str(ppc)); 1916 case PPB_RCTR: 1917 return (r_ctr(ppc)); 1918 case PPB_REPP_A: 1919 return (r_epp_A(ppc)); 1920 case PPB_REPP_D: 1921 return (r_epp_D(ppc)); 1922 case PPB_RECR: 1923 return (r_ecr(ppc)); 1924 case PPB_RFIFO: 1925 return (r_fifo(ppc)); 1926 case PPB_WDTR: 1927 w_dtr(ppc, byte); 1928 break; 1929 case PPB_WSTR: 1930 w_str(ppc, byte); 1931 break; 1932 case PPB_WCTR: 1933 w_ctr(ppc, byte); 1934 break; 1935 case PPB_WEPP_A: 1936 w_epp_A(ppc, byte); 1937 break; 1938 case PPB_WEPP_D: 1939 w_epp_D(ppc, byte); 1940 break; 1941 case PPB_WECR: 1942 w_ecr(ppc, byte); 1943 break; 1944 case PPB_WFIFO: 1945 w_fifo(ppc, byte); 1946 break; 1947 default: 1948 panic("%s: unknown I/O operation", __func__); 1949 break; 1950 } 1951 1952 return (0); /* not significative */ 1953} 1954 1955int 1956ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1957{ 1958 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1959 1960 switch (index) { 1961 case PPC_IVAR_EPP_PROTO: 1962 *val = (u_long)ppc->ppc_epp; 1963 break; 1964 default: 1965 return (ENOENT); 1966 } 1967 1968 return (0); 1969} 1970 1971/* 1972 * We allow child devices to allocate an IRQ resource at rid 0 for their 1973 * interrupt handlers. 1974 */ 1975struct resource * 1976ppc_alloc_resource(device_t bus, device_t child, int type, int *rid, 1977 u_long start, u_long end, u_long count, u_int flags) 1978{ 1979 struct ppc_data *ppc = DEVTOSOFTC(bus); 1980 1981 switch (type) { 1982 case SYS_RES_IRQ: 1983 if (*rid == 0) 1984 return (ppc->res_irq); 1985 break; 1986 } 1987 return (NULL); 1988} 1989 1990int 1991ppc_release_resource(device_t bus, device_t child, int type, int rid, 1992 struct resource *r) 1993{ 1994#ifdef INVARIANTS 1995 struct ppc_data *ppc = DEVTOSOFTC(bus); 1996#endif 1997 1998 switch (type) { 1999 case SYS_RES_IRQ: 2000 if (rid == 0) { 2001 KASSERT(r == ppc->res_irq, 2002 ("ppc child IRQ resource mismatch")); 2003 return (0); 2004 } 2005 break; 2006 } 2007 return (EINVAL); 2008} 2009 2010/* 2011 * If a child wants to add a handler for our IRQ, add it to our interrupt 2012 * event. Otherwise, fail the request. 2013 */ 2014int 2015ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 2016 driver_filter_t *filt, void (*ihand)(void *), void *arg, void **cookiep) 2017{ 2018 struct ppc_data *ppc = DEVTOSOFTC(bus); 2019 int error; 2020 2021 if (r != ppc->res_irq) 2022 return (EINVAL); 2023 2024 /* We don't allow filters. */ 2025 if (filt != NULL) 2026 return (EINVAL); 2027 2028 error = intr_event_add_handler(ppc->ppc_intr_event, 2029 device_get_nameunit(child), NULL, ihand, arg, intr_priority(flags), 2030 flags, cookiep); 2031 if (error == 0) 2032 ppc->ppc_child_handlers++; 2033 return (error); 2034} 2035 2036int 2037ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *cookie) 2038{ 2039 struct ppc_data *ppc = DEVTOSOFTC(bus); 2040 int error; 2041 2042 if (r != ppc->res_irq) 2043 return (EINVAL); 2044 2045 KASSERT(intr_handler_source(cookie) == ppc, 2046 ("ppc_teardown_intr: source mismatch")); 2047 error = intr_event_remove_handler(cookie); 2048 if (error == 0) 2049 ppc->ppc_child_handlers--; 2050 return (error); 2051} 2052 2053MODULE_DEPEND(ppc, ppbus, 1, 1, 1); 2054