1139825Simp/*- 266131Swpaul * Copyright (c) 2000 Berkeley Software Design, Inc. 366131Swpaul * Copyright (c) 1997, 1998, 1999, 2000 466131Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 566131Swpaul * 666131Swpaul * Redistribution and use in source and binary forms, with or without 766131Swpaul * modification, are permitted provided that the following conditions 866131Swpaul * are met: 966131Swpaul * 1. Redistributions of source code must retain the above copyright 1066131Swpaul * notice, this list of conditions and the following disclaimer. 1166131Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1266131Swpaul * notice, this list of conditions and the following disclaimer in the 1366131Swpaul * documentation and/or other materials provided with the distribution. 1466131Swpaul * 3. All advertising materials mentioning features or use of this software 1566131Swpaul * must display the following acknowledgement: 1666131Swpaul * This product includes software developed by Bill Paul. 1766131Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1866131Swpaul * may be used to endorse or promote products derived from this software 1966131Swpaul * without specific prior written permission. 2066131Swpaul * 2166131Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2266131Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2366131Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2466131Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2566131Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2666131Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2766131Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2866131Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2966131Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3066131Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3166131Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3266131Swpaul * 3366131Swpaul * $FreeBSD$ 3466131Swpaul */ 3566131Swpaul 3666131Swpaul/* 3766131Swpaul * I/O map in 16-bit mode. To switch to 32-bit mode, 3866131Swpaul * you need to perform a 32-bit write to the RDP register 3966131Swpaul * (writing a 0 is recommended). 4066131Swpaul */ 4166131Swpaul#define PCN_IO16_APROM00 0x00 4266131Swpaul#define PCN_IO16_APROM01 0x02 4366131Swpaul#define PCN_IO16_APROM02 0x04 4466131Swpaul#define PCN_IO16_APROM03 0x06 4566131Swpaul#define PCN_IO16_APROM04 0x08 4666131Swpaul#define PCN_IO16_APROM05 0x0A 4766131Swpaul#define PCN_IO16_APROM06 0x0C 4866131Swpaul#define PCN_IO16_APROM07 0x0E 4966131Swpaul#define PCN_IO16_RDP 0x10 5066131Swpaul#define PCN_IO16_RAP 0x12 5166131Swpaul#define PCN_IO16_RESET 0x14 5266131Swpaul#define PCN_IO16_BDP 0x16 5366131Swpaul 5466131Swpaul/* 5566131Swpaul * I/O map in 32-bit mode. 5666131Swpaul */ 5766131Swpaul#define PCN_IO32_APROM00 0x00 5866131Swpaul#define PCN_IO32_APROM01 0x04 5966131Swpaul#define PCN_IO32_APROM02 0x08 6066131Swpaul#define PCN_IO32_APROM03 0x0C 6166131Swpaul#define PCN_IO32_RDP 0x10 6266131Swpaul#define PCN_IO32_RAP 0x14 6366131Swpaul#define PCN_IO32_RESET 0x18 6466131Swpaul#define PCN_IO32_BDP 0x1C 6566131Swpaul 6666131Swpaul/* 6766131Swpaul * CSR registers 6866131Swpaul */ 6966131Swpaul#define PCN_CSR_CSR 0x00 7066131Swpaul#define PCN_CSR_IAB0 0x01 7166131Swpaul#define PCN_CSR_IAB1 0x02 7266131Swpaul#define PCN_CSR_IMR 0x03 7366131Swpaul#define PCN_CSR_TFEAT 0x04 7466131Swpaul#define PCN_CSR_EXTCTL1 0x05 7566131Swpaul#define PCN_CSR_DTBLLEN 0x06 7666131Swpaul#define PCN_CSR_EXTCTL2 0x07 7766131Swpaul#define PCN_CSR_MAR0 0x08 7866131Swpaul#define PCN_CSR_MAR1 0x09 7966131Swpaul#define PCN_CSR_MAR2 0x0A 8066131Swpaul#define PCN_CSR_MAR3 0x0B 8166131Swpaul#define PCN_CSR_PAR0 0x0C 8266131Swpaul#define PCN_CSR_PAR1 0x0D 8366131Swpaul#define PCN_CSR_PAR2 0x0E 8466131Swpaul#define PCN_CSR_MODE 0x0F 8566131Swpaul#define PCN_CSR_RXADDR0 0x18 8666131Swpaul#define PCN_CSR_RXADDR1 0x19 8766131Swpaul#define PCN_CSR_TXADDR0 0x1E 8866131Swpaul#define PCN_CSR_TXADDR1 0x1F 8966131Swpaul#define PCN_CSR_TXPOLL 0x2F 9066131Swpaul#define PCN_CSR_RXPOLL 0x31 9166131Swpaul#define PCN_CSR_RXRINGLEN 0x4C 9266131Swpaul#define PCN_CSR_TXRINGLEN 0x4E 9366131Swpaul#define PCN_CSR_DMACTL 0x50 9466131Swpaul#define PCN_CSR_BUSTIMER 0x52 9566131Swpaul#define PCN_CSR_MEMERRTIMEO 0x64 9666131Swpaul#define PCN_CSR_ONNOWMISC 0x74 9766131Swpaul#define PCN_CSR_ADVFEAT 0x7A 9866131Swpaul#define PCN_CSR_MACCFG 0x7D 9966131Swpaul#define PCN_CSR_CHIPID0 0x58 10066131Swpaul#define PCN_CSR_CHIPID1 0x59 10166131Swpaul 10266131Swpaul/* 10366131Swpaul * Control and status register (CSR0) 10466131Swpaul */ 10566131Swpaul#define PCN_CSR_INIT 0x0001 10666131Swpaul#define PCN_CSR_START 0x0002 10766131Swpaul#define PCN_CSR_STOP 0x0004 10866131Swpaul#define PCN_CSR_TX 0x0008 10966131Swpaul#define PCN_CSR_TXON 0x0010 11066131Swpaul#define PCN_CSR_RXON 0x0020 11166131Swpaul#define PCN_CSR_INTEN 0x0040 11266131Swpaul#define PCN_CSR_INTR 0x0080 11366131Swpaul#define PCN_CSR_IDONE 0x0100 11466131Swpaul#define PCN_CSR_TINT 0x0200 11566131Swpaul#define PCN_CSR_RINT 0x0400 11666131Swpaul#define PCN_CSR_MERR 0x0800 11766131Swpaul#define PCN_CSR_MISS 0x1000 11866131Swpaul#define PCN_CSR_CERR 0x2000 11966131Swpaul#define PCN_CSR_ERR 0x8000 12066131Swpaul 12166131Swpaul/* 12266131Swpaul * Interrupt masks and deferral control (CSR3) 12366131Swpaul */ 12466131Swpaul#define PCN_IMR_BSWAP 0x0004 12566131Swpaul#define PCN_IMR_ENMBA 0x0008 /* enable modified backoff alg */ 12666131Swpaul#define PCN_IMR_DXMT2PD 0x0010 12766131Swpaul#define PCN_IMR_LAPPEN 0x0020 /* lookahead packet processing enb */ 12866131Swpaul#define PCN_IMR_DXSUFLO 0x0040 /* disable TX stop on underflow */ 12966131Swpaul#define PCN_IMR_IDONE 0x0100 13066131Swpaul#define PCN_IMR_TINT 0x0200 13166131Swpaul#define PCN_IMR_RINT 0x0400 13266131Swpaul#define PCN_IMR_MERR 0x0800 13366131Swpaul#define PCN_IMR_MISS 0x1000 13466131Swpaul 13566131Swpaul/* 13666131Swpaul * Test and features control (CSR4) 13766131Swpaul */ 13866131Swpaul#define PCN_TFEAT_TXSTRTMASK 0x0004 13966131Swpaul#define PCN_TFEAT_TXSTRT 0x0008 14066131Swpaul#define PCN_TFEAT_RXCCOFLOWM 0x0010 /* Rx collision counter oflow */ 14166131Swpaul#define PCN_TFEAT_RXCCOFLOW 0x0020 14266131Swpaul#define PCN_TFEAT_UINT 0x0040 14366131Swpaul#define PCN_TFEAT_UINTREQ 0x0080 14466131Swpaul#define PCN_TFEAT_MISSOFLOWM 0x0100 14566131Swpaul#define PCN_TFEAT_MISSOFLOW 0x0200 14666131Swpaul#define PCN_TFEAT_STRIP_FCS 0x0400 14766131Swpaul#define PCN_TFEAT_PAD_TX 0x0800 14866131Swpaul#define PCN_TFEAT_TXDPOLL 0x1000 14966131Swpaul#define PCN_TFEAT_DMAPLUS 0x4000 15066131Swpaul 15166131Swpaul/* 15266131Swpaul * Extended control and interrupt 1 (CSR5) 15366131Swpaul */ 15466131Swpaul#define PCN_EXTCTL1_SPND 0x0001 /* suspend */ 15566131Swpaul#define PCN_EXTCTL1_MPMODE 0x0002 /* magic packet mode */ 15666131Swpaul#define PCN_EXTCTL1_MPENB 0x0004 /* magic packet enable */ 15766131Swpaul#define PCN_EXTCTL1_MPINTEN 0x0008 /* magic packet interrupt enable */ 15866131Swpaul#define PCN_EXTCTL1_MPINT 0x0010 /* magic packet interrupt */ 15966131Swpaul#define PCN_EXTCTL1_MPPLBA 0x0020 /* magic packet phys. logical bcast */ 16066131Swpaul#define PCN_EXTCTL1_EXDEFEN 0x0040 /* excessive deferral interrupt enb. */ 16166131Swpaul#define PCN_EXTCTL1_EXDEF 0x0080 /* excessive deferral interrupt */ 16266131Swpaul#define PCN_EXTCTL1_SINTEN 0x0400 /* system interrupt enable */ 16366131Swpaul#define PCN_EXTCTL1_SINT 0x0800 /* system interrupt */ 16466131Swpaul#define PCN_EXTCTL1_LTINTEN 0x4000 /* last TX interrupt enb */ 16566131Swpaul#define PCN_EXTCTL1_TXOKINTD 0x8000 /* TX OK interrupt disable */ 16666131Swpaul 16766131Swpaul/* 16866131Swpaul * RX/TX descriptor len (CSR6) 16966131Swpaul */ 17066131Swpaul#define PCN_DTBLLEN_RLEN 0x0F00 17166131Swpaul#define PCN_DTBLLEN_TLEN 0xF000 17266131Swpaul 17366131Swpaul/* 17466131Swpaul * Extended control and interrupt 2 (CSR7) 17566131Swpaul */ 17666131Swpaul#define PCN_EXTCTL2_MIIPDTINTE 0x0001 17766131Swpaul#define PCN_EXTCTL2_MIIPDTINT 0x0002 17866131Swpaul#define PCN_EXTCTL2_MCCIINTE 0x0004 17966131Swpaul#define PCN_EXTCTL2_MCCIINT 0x0008 18066131Swpaul#define PCN_EXTCTL2_MCCINTE 0x0010 18166131Swpaul#define PCN_EXTCTL2_MCCINT 0x0020 18266131Swpaul#define PCN_EXTCTL2_MAPINTE 0x0040 18366131Swpaul#define PCN_EXTCTL2_MAPINT 0x0080 18466131Swpaul#define PCN_EXTCTL2_MREINTE 0x0100 18566131Swpaul#define PCN_EXTCTL2_MREINT 0x0200 18666131Swpaul#define PCN_EXTCTL2_STINTE 0x0400 18766131Swpaul#define PCN_EXTCTL2_STINT 0x0800 18866131Swpaul#define PCN_EXTCTL2_RXDPOLL 0x1000 18966131Swpaul#define PCN_EXTCTL2_RDMD 0x2000 19066131Swpaul#define PCN_EXTCTL2_RXFRTG 0x4000 19166131Swpaul#define PCN_EXTCTL2_FASTSPNDE 0x8000 19266131Swpaul 19366131Swpaul 19466131Swpaul/* 19566131Swpaul * Mode (CSR15) 19666131Swpaul */ 19766131Swpaul#define PCN_MODE_RXD 0x0001 /* RX disable */ 19866131Swpaul#define PCN_MODE_TXD 0x0002 /* TX disable */ 19966131Swpaul#define PCN_MODE_LOOP 0x0004 /* loopback enable */ 20066131Swpaul#define PCN_MODE_TXCRCD 0x0008 20166131Swpaul#define PCN_MODE_FORCECOLL 0x0010 20266131Swpaul#define PCN_MODE_RETRYD 0x0020 20366131Swpaul#define PCN_MODE_INTLOOP 0x0040 20466131Swpaul#define PCN_MODE_PORTSEL 0x0180 20566131Swpaul#define PCN_MODE_RXVPAD 0x2000 20666131Swpaul#define PCN_MODE_RXNOBROAD 0x4000 20766131Swpaul#define PCN_MODE_PROMISC 0x8000 20866131Swpaul 209164712Smarius/* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1]) is 0 */ 210138351Smdodd#define PCN_PORT_AUI 0x0000 211138351Smdodd#define PCN_PORT_10BASET 0x0080 21266131Swpaul#define PCN_PORT_GPSI 0x0100 21366131Swpaul#define PCN_PORT_MII 0x0180 21466131Swpaul 21566131Swpaul/* 21666131Swpaul * Chip ID values. 21766131Swpaul */ 21866131Swpaul/* CSR88-89: Chip ID masks */ 21966131Swpaul#define AMD_MASK 0x003 22066131Swpaul#define PART_MASK 0xffff 22166131Swpaul#define Am79C971 0x2623 22266131Swpaul#define Am79C972 0x2624 22366131Swpaul#define Am79C973 0x2625 22466131Swpaul#define Am79C978 0x2626 22566690Swpaul#define Am79C975 0x2627 22666592Swpaul#define Am79C976 0x2628 22766131Swpaul 22866131Swpaul/* 22966131Swpaul * Advanced feature control (CSR122) 23066131Swpaul */ 23166131Swpaul#define PCN_AFC_RXALIGN 0x0001 23266131Swpaul 23366131Swpaul/* 23466131Swpaul * BCR (bus control) registers 23566131Swpaul */ 236138351Smdodd#define PCN_BCR_MMRA 0x00 /* Master Mode Read Active */ 237138351Smdodd#define PCN_BCR_MMW 0x01 /* Master Mode Write Active */ 23866131Swpaul#define PCN_BCR_MISCCFG 0x02 23966131Swpaul#define PCN_BCR_LED0 0x04 24066131Swpaul#define PCN_BCR_LED1 0x05 24166131Swpaul#define PCN_BCR_LED2 0x06 24266131Swpaul#define PCN_BCR_LED3 0x07 24366131Swpaul#define PCN_BCR_DUPLEX 0x09 24466131Swpaul#define PCN_BCR_BUSCTL 0x12 24566131Swpaul#define PCN_BCR_EECTL 0x13 24666131Swpaul#define PCN_BCR_SSTYLE 0x14 24766131Swpaul#define PCN_BCR_PCILAT 0x16 24866131Swpaul#define PCN_BCR_PCISUBVENID 0x17 24969067Swpaul#define PCN_BCR_PCISUBSYSID 0x18 25066131Swpaul#define PCN_BCR_SRAMSIZE 0x19 25166131Swpaul#define PCN_BCR_SRAMBOUND 0x1A 25266131Swpaul#define PCN_BCR_SRAMCTL 0x1B 25366131Swpaul#define PCN_BCR_MIICTL 0x20 25466131Swpaul#define PCN_BCR_MIIADDR 0x21 25566131Swpaul#define PCN_BCR_MIIDATA 0x22 25666131Swpaul#define PCN_BCR_PCIVENID 0x23 25766131Swpaul#define PCN_BCR_PCIPCAP 0x24 25866131Swpaul#define PCN_BCR_DATA0 0x25 25966131Swpaul#define PCN_BCR_DATA1 0x26 26066131Swpaul#define PCN_BCR_DATA2 0x27 26166131Swpaul#define PCN_BCR_DATA3 0x28 26266131Swpaul#define PCN_BCR_DATA4 0x29 26366131Swpaul#define PCN_BCR_DATA5 0x2A 26466131Swpaul#define PCN_BCR_DATA6 0x2B 26566131Swpaul#define PCN_BCR_DATA7 0x2C 26666131Swpaul#define PCN_BCR_ONNOWPAT0 0x2D 26766131Swpaul#define PCN_BCR_ONNOWPAT1 0x2E 26866131Swpaul#define PCN_BCR_ONNOWPAT2 0x2F 26966131Swpaul#define PCN_BCR_PHYSEL 0x31 27066131Swpaul 27166131Swpaul/* 272138351Smdodd * Miscellaneous Configuration (BCR2) 273138351Smdodd */ 274138351Smdodd#define PCN_MISC_TMAULOOP 1<<14 /* T-MAU Loopback packet enable. */ 275138351Smdodd#define PCN_MISC_LEDPE 1<<12 /* LED Program Enable */ 276138351Smdodd#define PCN_MISC_APROMWE 1<<8 /* Address PROM Write Enable */ 277138351Smdodd#define PCN_MISC_INTLEVEL 1<<7 /* Interrupt level */ 278138351Smdodd#define PCN_MISC_EADISEL 1<<3 /* EADI Select */ 279138351Smdodd#define PCN_MISC_AWAKE 1<<2 /* Power saving mode select */ 280138351Smdodd#define PCN_MISC_ASEL 1<<1 /* Auto Select */ 281138351Smdodd#define PCN_MISC_XMAUSEL 1<<0 /* Reserved. */ 282138351Smdodd 283138351Smdodd/* 28466131Swpaul * Full duplex control (BCR9) 28566131Swpaul */ 28666131Swpaul#define PCN_DUPLEX_FDEN 0x0001 /* Full-duplex enable */ 287138351Smdodd#define PCN_DUPLEX_AUI 0x0002 /* AUI full-duplex */ 28866131Swpaul#define PCN_DUPLEX_FDRPAD 0x0004 /* Full-duplex runt pkt accept dis. */ 28966131Swpaul 29066131Swpaul/* 29166131Swpaul * Burst and bus control register (BCR18) 29266131Swpaul */ 29366131Swpaul#define PCN_BUSCTL_BWRITE 0x0020 29466131Swpaul#define PCN_BUSCTL_BREAD 0x0040 29566131Swpaul#define PCN_BUSCTL_DWIO 0x0080 29666131Swpaul#define PCN_BUSCTL_EXTREQ 0x0100 29766131Swpaul#define PCN_BUSCTL_MEMCMD 0x0200 29866131Swpaul#define PCN_BUSCTL_NOUFLOW 0x0800 29966131Swpaul#define PCN_BUSCTL_ROMTMG 0xF000 30066131Swpaul 30166131Swpaul/* 30266131Swpaul * EEPROM control (BCR19) 30366131Swpaul */ 30466131Swpaul#define PCN_EECTL_EDATA 0x0001 30566131Swpaul#define PCN_EECTL_ECLK 0x0002 30666131Swpaul#define PCN_EECTL_EECS 0x0004 30766131Swpaul#define PCN_EECTL_EEN 0x0100 30866131Swpaul#define PCN_EECTL_EEDET 0x2000 30966131Swpaul#define PCN_EECTL_PREAD 0x4000 31066131Swpaul#define PCN_EECTL_PVALID 0x8000 31166131Swpaul 31266131Swpaul/* 31366131Swpaul * Software style (BCR20) 31466131Swpaul */ 31566131Swpaul#define PCN_SSTYLE_APERREN 0x0400 /* advanced parity error checking */ 31666131Swpaul#define PCN_SSTYLE_SSIZE32 0x0100 31766131Swpaul#define PCN_SSTYLE_SWSTYLE 0x00FF 31866131Swpaul 31966131Swpaul#define PCN_SWSTYLE_LANCE 0x0000 32066131Swpaul#define PCN_SWSTYLE_PCNETPCI 0x0102 32166131Swpaul#define PCN_SWSTYLE_PCNETPCI_BURST 0x0103 32266131Swpaul 32366131Swpaul/* 32466131Swpaul * MII control and status (BCR32) 32566131Swpaul */ 32666131Swpaul#define PCN_MIICTL_MIILP 0x0002 /* MII internal loopback */ 32766131Swpaul#define PCN_MIICTL_XPHYSP 0x0008 /* external PHY speed */ 32866131Swpaul#define PCN_MIICTL_XPHYFD 0x0010 /* external PHY full duplex */ 32966131Swpaul#define PCN_MIICTL_XPHYANE 0x0020 /* external phy auto-neg enable */ 33066131Swpaul#define PCN_MIICTL_XPHYRST 0x0040 /* external PHY reset */ 33166131Swpaul#define PCN_MIICTL_DANAS 0x0080 /* disable auto-neg auto-setup */ 33266131Swpaul#define PCN_MIICTL_APDW 0x0700 /* auto-poll dwell time */ 33366131Swpaul#define PCN_MIICTL_APEP 0x0100 /* auto-poll external PHY */ 33466131Swpaul#define PCN_MIICTL_FMDC 0x3000 /* data clock speed */ 33566131Swpaul#define PCN_MIICTL_MIIPD 0x4000 /* PHY detect */ 33666131Swpaul#define PCN_MIICTL_ANTST 0x8000 /* Manufacturing test */ 33766131Swpaul 33866131Swpaul/* 33966131Swpaul * MII address register (BCR33) 34066131Swpaul */ 34166131Swpaul#define PCN_MIIADDR_REGAD 0x001F 342164712Smarius#define PCN_MIIADDR_PHYAD 0x03E0 34366131Swpaul 344164712Smarius/* addresses of internal PHYs */ 345164712Smarius#define PCN_PHYAD_100BTX 30 346164712Smarius#define PCN_PHYAD_10BT 31 347164712Smarius 34866131Swpaul/* 34966131Swpaul * MII data register (BCR34) 35066131Swpaul */ 35166131Swpaul#define PCN_MIIDATA_MIIMD 0xFFFF 35266131Swpaul 35366131Swpaul/* 35466131Swpaul * PHY selection (BCR49) (HomePNA NIC only) 35566131Swpaul */ 35666131Swpaul#define PCN_PHYSEL_PHYSEL 0x0003 35766131Swpaul#define PCN_PHYSEL_DEFAULT 0x0300 35866131Swpaul#define PCN_PHYSEL_PCNET 0x8000 35966131Swpaul 36066131Swpaul#define PCN_PHY_10BT 0x0000 36166131Swpaul#define PCN_PHY_HOMEPNA 0x0001 36266131Swpaul#define PCN_PHY_EXTERNAL 0x0002 36366131Swpaul 36466131Swpaulstruct pcn_rx_desc { 36566131Swpaul u_int16_t pcn_rxlen; 36666131Swpaul u_int16_t pcn_rsvd0; 36766131Swpaul u_int16_t pcn_bufsz; 36866131Swpaul u_int16_t pcn_rxstat; 36966131Swpaul u_int32_t pcn_rbaddr; 37066131Swpaul u_int32_t pcn_uspace; 37166131Swpaul}; 37266131Swpaul 37366131Swpaul#define PCN_RXSTAT_BPE 0x0080 /* bus parity error */ 37466131Swpaul#define PCN_RXSTAT_ENP 0x0100 /* end of packet */ 37566131Swpaul#define PCN_RXSTAT_STP 0x0200 /* start of packet */ 37666131Swpaul#define PCN_RXSTAT_BUFF 0x0400 /* buffer error */ 37766131Swpaul#define PCN_RXSTAT_CRC 0x0800 /* CRC error */ 37866131Swpaul#define PCN_RXSTAT_OFLOW 0x1000 /* rx overrun */ 37966131Swpaul#define PCN_RXSTAT_FRAM 0x2000 /* framing error */ 38066131Swpaul#define PCN_RXSTAT_ERR 0x4000 /* error summary */ 38166131Swpaul#define PCN_RXSTAT_OWN 0x8000 38266131Swpaul 38366131Swpaul#define PCN_RXLEN_MBO 0xF000 38466131Swpaul#define PCN_RXLEN_BUFSZ 0x0FFF 38566131Swpaul 38666131Swpaul#define PCN_OWN_RXDESC(x) (((x)->pcn_rxstat & PCN_RXSTAT_OWN) == 0) 38766131Swpaul 38866131Swpaulstruct pcn_tx_desc { 38966131Swpaul u_int32_t pcn_txstat; 39066131Swpaul u_int32_t pcn_txctl; 39166131Swpaul u_int32_t pcn_tbaddr; 39266131Swpaul u_int32_t pcn_uspace; 39366131Swpaul}; 39466131Swpaul 39566131Swpaul#define PCN_TXSTAT_TRC 0x0000000F /* transmit retries */ 39666131Swpaul#define PCN_TXSTAT_RTRY 0x04000000 /* retry */ 39766131Swpaul#define PCN_TXSTAT_LCAR 0x08000000 /* lost carrier */ 39866131Swpaul#define PCN_TXSTAT_LCOL 0x10000000 /* late collision */ 39966131Swpaul#define PCN_TXSTAT_EXDEF 0x20000000 /* excessive deferrals */ 40066131Swpaul#define PCN_TXSTAT_UFLOW 0x40000000 /* transmit underrun */ 40166131Swpaul#define PCN_TXSTAT_BUFF 0x80000000 /* buffer error */ 40266131Swpaul 40366131Swpaul#define PCN_TXCTL_OWN 0x80000000 40466131Swpaul#define PCN_TXCTL_ERR 0x40000000 /* error summary */ 40566131Swpaul#define PCN_TXCTL_ADD_FCS 0x20000000 /* add FCS to pkt */ 40666131Swpaul#define PCN_TXCTL_MORE_LTINT 0x10000000 40766131Swpaul#define PCN_TXCTL_ONE 0x08000000 40866131Swpaul#define PCN_TXCTL_DEF 0x04000000 40966131Swpaul#define PCN_TXCTL_STP 0x02000000 41066131Swpaul#define PCN_TXCTL_ENP 0x01000000 41166131Swpaul#define PCN_TXCTL_BPE 0x00800000 41266131Swpaul#define PCN_TXCTL_MBO 0x0000F000 41366131Swpaul#define PCN_TXCTL_BUFSZ 0x00000FFF 41466131Swpaul 41566131Swpaul#define PCN_OWN_TXDESC(x) (((x)->pcn_txctl & PCN_TXCTL_OWN) == 0) 41666131Swpaul 41766131Swpaul#define PCN_RX_LIST_CNT 64 41866131Swpaul#define PCN_TX_LIST_CNT 256 41966131Swpaul 42066131Swpaulstruct pcn_list_data { 42166131Swpaul struct pcn_rx_desc pcn_rx_list[PCN_RX_LIST_CNT]; 42266131Swpaul struct pcn_tx_desc pcn_tx_list[PCN_TX_LIST_CNT]; 42366131Swpaul}; 42466131Swpaul 42566131Swpaulstruct pcn_ring_data { 42666131Swpaul struct mbuf *pcn_rx_chain[PCN_RX_LIST_CNT]; 42766131Swpaul struct mbuf *pcn_tx_chain[PCN_TX_LIST_CNT]; 42866131Swpaul int pcn_rx_prod; 42966131Swpaul int pcn_tx_prod; 43066131Swpaul int pcn_tx_cons; 43166131Swpaul int pcn_tx_cnt; 43266131Swpaul}; 43366131Swpaul 43466131Swpaul/* 43566131Swpaul * AMD PCI vendor ID. 43666131Swpaul */ 43766131Swpaul#define PCN_VENDORID 0x1022 43866131Swpaul 43966131Swpaul/* 44066131Swpaul * AMD PCnet/PCI device IDs 44166131Swpaul */ 44266131Swpaul#define PCN_DEVICEID_PCNET 0x2000 44366131Swpaul#define PCN_DEVICEID_HOME 0x2001 44466131Swpaul 44566131Swpaulstruct pcn_type { 44666131Swpaul u_int16_t pcn_vid; 44766131Swpaul u_int16_t pcn_did; 448164072Smarius const char *pcn_name; 44966131Swpaul}; 45066131Swpaul 45166131Swpaulstruct pcn_softc { 452147256Sbrooks struct ifnet *pcn_ifp; 45366131Swpaul bus_space_handle_t pcn_bhandle; 45466131Swpaul bus_space_tag_t pcn_btag; 45566131Swpaul struct resource *pcn_res; 45666131Swpaul struct resource *pcn_irq; 45766131Swpaul void *pcn_intrhand; 45866131Swpaul device_t pcn_miibus; 45966131Swpaul u_int8_t pcn_link; 460164712Smarius int8_t pcn_extphyaddr; 461164712Smarius int8_t pcn_inst_10bt; 46266131Swpaul int pcn_if_flags; 46366131Swpaul int pcn_type; 46466131Swpaul struct pcn_list_data *pcn_ldata; 46566131Swpaul struct pcn_ring_data pcn_cdata; 466148738Sjhb struct callout pcn_stat_callout; 46767087Swpaul struct mtx pcn_mtx; 468199560Sjhb int pcn_timer; 46966131Swpaul}; 47066131Swpaul 47172200Sbmilekic#define PCN_LOCK(_sc) mtx_lock(&(_sc)->pcn_mtx) 47272200Sbmilekic#define PCN_UNLOCK(_sc) mtx_unlock(&(_sc)->pcn_mtx) 473122689Ssam#define PCN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->pcn_mtx, MA_OWNED) 47467087Swpaul 47566131Swpaul/* 47666131Swpaul * register space access macros 47766131Swpaul */ 47866131Swpaul#define CSR_WRITE_4(sc, reg, val) \ 47966131Swpaul bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val) 48066131Swpaul 48166131Swpaul#define CSR_READ_4(sc, reg) \ 48266131Swpaul bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg) 48366131Swpaul 48466131Swpaul#define CSR_WRITE_2(sc, reg, val) \ 48566131Swpaul bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val) 48666131Swpaul 48766131Swpaul#define CSR_READ_2(sc, reg) \ 48866131Swpaul bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg) 48966131Swpaul 49066131Swpaul#define PCN_TIMEOUT 1000 49166131Swpaul#define ETHER_ALIGN 2 49266131Swpaul#define PCN_RXLEN 1536 49366131Swpaul#define PCN_MIN_FRAMELEN 60 49466131Swpaul#define PCN_INC(x, y) (x) = (x + 1) % y 49566131Swpaul/* 49666131Swpaul * PCI low memory base and low I/O base register, and 49766131Swpaul * other PCI registers. 49866131Swpaul */ 49966131Swpaul 50066131Swpaul#define PCN_PCI_VENDOR_ID 0x00 50166131Swpaul#define PCN_PCI_DEVICE_ID 0x02 50266131Swpaul#define PCN_PCI_COMMAND 0x04 50366131Swpaul#define PCN_PCI_STATUS 0x06 50466131Swpaul#define PCN_PCI_REVID 0x08 50566131Swpaul#define PCN_PCI_CLASSCODE 0x09 50666131Swpaul#define PCN_PCI_CACHELEN 0x0C 50766131Swpaul#define PCN_PCI_LATENCY_TIMER 0x0D 50866131Swpaul#define PCN_PCI_HEADER_TYPE 0x0E 50966131Swpaul#define PCN_PCI_LOIO 0x10 51066131Swpaul#define PCN_PCI_LOMEM 0x14 51166131Swpaul#define PCN_PCI_BIOSROM 0x30 51266131Swpaul#define PCN_PCI_INTLINE 0x3C 51366131Swpaul#define PCN_PCI_INTPIN 0x3D 51466131Swpaul#define PCN_PCI_MINGNT 0x3E 515138351Smdodd#define PCN_PCI_MINLAT 0x3F 51666131Swpaul#define PCN_PCI_RESETOPT 0x48 51766131Swpaul#define PCN_PCI_EEPROM_DATA 0x4C 51866131Swpaul 51966131Swpaul/* power management registers */ 52066131Swpaul#define PCN_PCI_CAPID 0x50 /* 8 bits */ 52166131Swpaul#define PCN_PCI_NEXTPTR 0x51 /* 8 bits */ 52266131Swpaul#define PCN_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 52366131Swpaul#define PCN_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 52466131Swpaul 52566131Swpaul#define PCN_PSTATE_MASK 0x0003 52666131Swpaul#define PCN_PSTATE_D0 0x0000 52766131Swpaul#define PCN_PSTATE_D1 0x0001 52866131Swpaul#define PCN_PSTATE_D2 0x0002 52966131Swpaul#define PCN_PSTATE_D3 0x0003 53066131Swpaul#define PCN_PME_EN 0x0010 53166131Swpaul#define PCN_PME_STATUS 0x8000 532