pci_subr.c revision 221324
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 221324 2011-05-02 14:13:12Z jhb $"); 33 34/* 35 * PCI:PCI bridge support. 36 */ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/kernel.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <machine/bus.h> 44#include <sys/rman.h> 45#include <sys/sysctl.h> 46 47#include <machine/resource.h> 48 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pcireg.h> 51#include <dev/pci/pci_private.h> 52#include <dev/pci/pcib_private.h> 53 54#include "pcib_if.h" 55 56static int pcib_probe(device_t dev); 57static int pcib_suspend(device_t dev); 58static int pcib_resume(device_t dev); 59static int pcib_power_for_sleep(device_t pcib, device_t dev, 60 int *pstate); 61 62static device_method_t pcib_methods[] = { 63 /* Device interface */ 64 DEVMETHOD(device_probe, pcib_probe), 65 DEVMETHOD(device_attach, pcib_attach), 66 DEVMETHOD(device_detach, bus_generic_detach), 67 DEVMETHOD(device_shutdown, bus_generic_shutdown), 68 DEVMETHOD(device_suspend, pcib_suspend), 69 DEVMETHOD(device_resume, pcib_resume), 70 71 /* Bus interface */ 72 DEVMETHOD(bus_print_child, bus_generic_print_child), 73 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 74 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 75 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 76 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 77 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 78 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 79 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 80 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 81 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 82 83 /* pcib interface */ 84 DEVMETHOD(pcib_maxslots, pcib_maxslots), 85 DEVMETHOD(pcib_read_config, pcib_read_config), 86 DEVMETHOD(pcib_write_config, pcib_write_config), 87 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 88 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 89 DEVMETHOD(pcib_release_msi, pcib_release_msi), 90 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 91 DEVMETHOD(pcib_release_msix, pcib_release_msix), 92 DEVMETHOD(pcib_map_msi, pcib_map_msi), 93 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 94 95 { 0, 0 } 96}; 97 98static devclass_t pcib_devclass; 99 100DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 101DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 102 103/* 104 * Is the prefetch window open (eg, can we allocate memory in it?) 105 */ 106static int 107pcib_is_prefetch_open(struct pcib_softc *sc) 108{ 109 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 110} 111 112/* 113 * Is the nonprefetch window open (eg, can we allocate memory in it?) 114 */ 115static int 116pcib_is_nonprefetch_open(struct pcib_softc *sc) 117{ 118 return (sc->membase > 0 && sc->membase < sc->memlimit); 119} 120 121/* 122 * Is the io window open (eg, can we allocate ports in it?) 123 */ 124static int 125pcib_is_io_open(struct pcib_softc *sc) 126{ 127 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 128} 129 130/* 131 * Get current I/O decode. 132 */ 133static void 134pcib_get_io_decode(struct pcib_softc *sc) 135{ 136 device_t dev; 137 uint32_t iolow; 138 139 dev = sc->dev; 140 141 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 142 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 143 sc->iobase = PCI_PPBIOBASE( 144 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 145 else 146 sc->iobase = PCI_PPBIOBASE(0, iolow); 147 148 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 149 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 150 sc->iolimit = PCI_PPBIOLIMIT( 151 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 152 else 153 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 154} 155 156/* 157 * Get current memory decode. 158 */ 159static void 160pcib_get_mem_decode(struct pcib_softc *sc) 161{ 162 device_t dev; 163 pci_addr_t pmemlow; 164 165 dev = sc->dev; 166 167 sc->membase = PCI_PPBMEMBASE(0, 168 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 169 sc->memlimit = PCI_PPBMEMLIMIT(0, 170 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 171 172 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 173 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 174 sc->pmembase = PCI_PPBMEMBASE( 175 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 176 else 177 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 178 179 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 180 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 181 sc->pmemlimit = PCI_PPBMEMLIMIT( 182 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 183 else 184 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 185} 186 187/* 188 * Restore previous I/O decode. 189 */ 190static void 191pcib_set_io_decode(struct pcib_softc *sc) 192{ 193 device_t dev; 194 uint32_t iohi; 195 196 dev = sc->dev; 197 198 iohi = sc->iobase >> 16; 199 if (iohi > 0) 200 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 201 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 202 203 iohi = sc->iolimit >> 16; 204 if (iohi > 0) 205 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 206 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 207} 208 209/* 210 * Restore previous memory decode. 211 */ 212static void 213pcib_set_mem_decode(struct pcib_softc *sc) 214{ 215 device_t dev; 216 pci_addr_t pmemhi; 217 218 dev = sc->dev; 219 220 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 221 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 222 223 pmemhi = sc->pmembase >> 32; 224 if (pmemhi > 0) 225 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 226 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 227 228 pmemhi = sc->pmemlimit >> 32; 229 if (pmemhi > 0) 230 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 231 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 232} 233 234/* 235 * Get current bridge configuration. 236 */ 237static void 238pcib_cfg_save(struct pcib_softc *sc) 239{ 240 device_t dev; 241 242 dev = sc->dev; 243 244 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 245 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 246 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 247 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 248 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 249 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 250 if (sc->command & PCIM_CMD_PORTEN) 251 pcib_get_io_decode(sc); 252 if (sc->command & PCIM_CMD_MEMEN) 253 pcib_get_mem_decode(sc); 254} 255 256/* 257 * Restore previous bridge configuration. 258 */ 259static void 260pcib_cfg_restore(struct pcib_softc *sc) 261{ 262 device_t dev; 263 264 dev = sc->dev; 265 266 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 267 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 268 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1); 269 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1); 270 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 271 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 272 if (sc->command & PCIM_CMD_PORTEN) 273 pcib_set_io_decode(sc); 274 if (sc->command & PCIM_CMD_MEMEN) 275 pcib_set_mem_decode(sc); 276} 277 278/* 279 * Generic device interface 280 */ 281static int 282pcib_probe(device_t dev) 283{ 284 if ((pci_get_class(dev) == PCIC_BRIDGE) && 285 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 286 device_set_desc(dev, "PCI-PCI bridge"); 287 return(-10000); 288 } 289 return(ENXIO); 290} 291 292void 293pcib_attach_common(device_t dev) 294{ 295 struct pcib_softc *sc; 296 struct sysctl_ctx_list *sctx; 297 struct sysctl_oid *soid; 298 299 sc = device_get_softc(dev); 300 sc->dev = dev; 301 302 /* 303 * Get current bridge configuration. 304 */ 305 sc->domain = pci_get_domain(dev); 306 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 307 pcib_cfg_save(sc); 308 309 /* 310 * Setup sysctl reporting nodes 311 */ 312 sctx = device_get_sysctl_ctx(dev); 313 soid = device_get_sysctl_tree(dev); 314 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 315 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 316 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 317 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 318 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 319 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 320 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 321 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 322 323 /* 324 * Quirk handling. 325 */ 326 switch (pci_get_devid(dev)) { 327 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 328 { 329 uint8_t supbus; 330 331 supbus = pci_read_config(dev, 0x41, 1); 332 if (supbus != 0xff) { 333 sc->secbus = supbus + 1; 334 sc->subbus = supbus + 1; 335 } 336 break; 337 } 338 339 /* 340 * The i82380FB mobile docking controller is a PCI-PCI bridge, 341 * and it is a subtractive bridge. However, the ProgIf is wrong 342 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 343 * happen. There's also a Toshiba bridge that behaves this 344 * way. 345 */ 346 case 0x124b8086: /* Intel 82380FB Mobile */ 347 case 0x060513d7: /* Toshiba ???? */ 348 sc->flags |= PCIB_SUBTRACTIVE; 349 break; 350 351 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 352 case 0x00dd10de: 353 { 354 char *cp; 355 356 if ((cp = getenv("smbios.planar.maker")) == NULL) 357 break; 358 if (strncmp(cp, "Compal", 6) != 0) { 359 freeenv(cp); 360 break; 361 } 362 freeenv(cp); 363 if ((cp = getenv("smbios.planar.product")) == NULL) 364 break; 365 if (strncmp(cp, "08A0", 4) != 0) { 366 freeenv(cp); 367 break; 368 } 369 freeenv(cp); 370 if (sc->subbus < 0xa) { 371 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 372 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 373 } 374 break; 375 } 376 } 377 378 if (pci_msi_device_blacklisted(dev)) 379 sc->flags |= PCIB_DISABLE_MSI; 380 381 /* 382 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 383 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 384 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 385 * This means they act as if they were subtractively decoding 386 * bridges and pass all transactions. Mark them and real ProgIf 1 387 * parts as subtractive. 388 */ 389 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 390 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 391 sc->flags |= PCIB_SUBTRACTIVE; 392 393 if (bootverbose) { 394 device_printf(dev, " domain %d\n", sc->domain); 395 device_printf(dev, " secondary bus %d\n", sc->secbus); 396 device_printf(dev, " subordinate bus %d\n", sc->subbus); 397 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 398 if (pcib_is_nonprefetch_open(sc)) 399 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 400 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 401 if (pcib_is_prefetch_open(sc)) 402 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 403 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 404 else 405 device_printf(dev, " no prefetched decode\n"); 406 if (sc->flags & PCIB_SUBTRACTIVE) 407 device_printf(dev, " Subtractively decoded bridge.\n"); 408 } 409 410 /* 411 * XXX If the secondary bus number is zero, we should assign a bus number 412 * since the BIOS hasn't, then initialise the bridge. A simple 413 * bus_alloc_resource with the a couple of busses seems like the right 414 * approach, but we don't know what busses the BIOS might have already 415 * assigned to other bridges on this bus that probe later than we do. 416 * 417 * If the subordinate bus number is less than the secondary bus number, 418 * we should pick a better value. One sensible alternative would be to 419 * pick 255; the only tradeoff here is that configuration transactions 420 * would be more widely routed than absolutely necessary. We could 421 * then do a walk of the tree later and fix it. 422 */ 423} 424 425int 426pcib_attach(device_t dev) 427{ 428 struct pcib_softc *sc; 429 device_t child; 430 431 pcib_attach_common(dev); 432 sc = device_get_softc(dev); 433 if (sc->secbus != 0) { 434 child = device_add_child(dev, "pci", sc->secbus); 435 if (child != NULL) 436 return(bus_generic_attach(dev)); 437 } 438 439 /* no secondary bus; we should have fixed this */ 440 return(0); 441} 442 443int 444pcib_suspend(device_t dev) 445{ 446 device_t pcib; 447 int dstate, error; 448 449 pcib_cfg_save(device_get_softc(dev)); 450 error = bus_generic_suspend(dev); 451 if (error == 0 && pci_do_power_suspend) { 452 dstate = PCI_POWERSTATE_D3; 453 pcib = device_get_parent(device_get_parent(dev)); 454 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 455 pci_set_powerstate(dev, dstate); 456 } 457 return (error); 458} 459 460int 461pcib_resume(device_t dev) 462{ 463 device_t pcib; 464 465 if (pci_do_power_resume) { 466 pcib = device_get_parent(device_get_parent(dev)); 467 if (PCIB_POWER_FOR_SLEEP(pcib, dev, NULL) == 0) 468 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 469 } 470 pcib_cfg_restore(device_get_softc(dev)); 471 return (bus_generic_resume(dev)); 472} 473 474int 475pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 476{ 477 struct pcib_softc *sc = device_get_softc(dev); 478 479 switch (which) { 480 case PCIB_IVAR_DOMAIN: 481 *result = sc->domain; 482 return(0); 483 case PCIB_IVAR_BUS: 484 *result = sc->secbus; 485 return(0); 486 } 487 return(ENOENT); 488} 489 490int 491pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 492{ 493 struct pcib_softc *sc = device_get_softc(dev); 494 495 switch (which) { 496 case PCIB_IVAR_DOMAIN: 497 return(EINVAL); 498 case PCIB_IVAR_BUS: 499 sc->secbus = value; 500 return(0); 501 } 502 return(ENOENT); 503} 504 505/* 506 * We have to trap resource allocation requests and ensure that the bridge 507 * is set up to, or capable of handling them. 508 */ 509struct resource * 510pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 511 u_long start, u_long end, u_long count, u_int flags) 512{ 513 struct pcib_softc *sc = device_get_softc(dev); 514 const char *name, *suffix; 515 int ok; 516 517 /* 518 * Fail the allocation for this range if it's not supported. 519 */ 520 name = device_get_nameunit(child); 521 if (name == NULL) { 522 name = ""; 523 suffix = ""; 524 } else 525 suffix = " "; 526 switch (type) { 527 case SYS_RES_IOPORT: 528 ok = 0; 529 if (!pcib_is_io_open(sc)) 530 break; 531 ok = (start >= sc->iobase && end <= sc->iolimit); 532 533 /* 534 * Make sure we allow access to VGA I/O addresses when the 535 * bridge has the "VGA Enable" bit set. 536 */ 537 if (!ok && pci_is_vga_ioport_range(start, end)) 538 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 539 540 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 541 if (!ok) { 542 if (start < sc->iobase) 543 start = sc->iobase; 544 if (end > sc->iolimit) 545 end = sc->iolimit; 546 if (start < end) 547 ok = 1; 548 } 549 } else { 550 ok = 1; 551#if 0 552 /* 553 * If we overlap with the subtractive range, then 554 * pick the upper range to use. 555 */ 556 if (start < sc->iolimit && end > sc->iobase) 557 start = sc->iolimit + 1; 558#endif 559 } 560 if (end < start) { 561 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 562 end, start); 563 start = 0; 564 end = 0; 565 ok = 0; 566 } 567 if (!ok) { 568 device_printf(dev, "%s%srequested unsupported I/O " 569 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 570 name, suffix, start, end, sc->iobase, sc->iolimit); 571 return (NULL); 572 } 573 if (bootverbose) 574 device_printf(dev, 575 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 576 name, suffix, start, end); 577 break; 578 579 case SYS_RES_MEMORY: 580 ok = 0; 581 if (pcib_is_nonprefetch_open(sc)) 582 ok = ok || (start >= sc->membase && end <= sc->memlimit); 583 if (pcib_is_prefetch_open(sc)) 584 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 585 586 /* 587 * Make sure we allow access to VGA memory addresses when the 588 * bridge has the "VGA Enable" bit set. 589 */ 590 if (!ok && pci_is_vga_memory_range(start, end)) 591 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 592 593 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 594 if (!ok) { 595 ok = 1; 596 if (flags & RF_PREFETCHABLE) { 597 if (pcib_is_prefetch_open(sc)) { 598 if (start < sc->pmembase) 599 start = sc->pmembase; 600 if (end > sc->pmemlimit) 601 end = sc->pmemlimit; 602 } else { 603 ok = 0; 604 } 605 } else { /* non-prefetchable */ 606 if (pcib_is_nonprefetch_open(sc)) { 607 if (start < sc->membase) 608 start = sc->membase; 609 if (end > sc->memlimit) 610 end = sc->memlimit; 611 } else { 612 ok = 0; 613 } 614 } 615 } 616 } else if (!ok) { 617 ok = 1; /* subtractive bridge: always ok */ 618#if 0 619 if (pcib_is_nonprefetch_open(sc)) { 620 if (start < sc->memlimit && end > sc->membase) 621 start = sc->memlimit + 1; 622 } 623 if (pcib_is_prefetch_open(sc)) { 624 if (start < sc->pmemlimit && end > sc->pmembase) 625 start = sc->pmemlimit + 1; 626 } 627#endif 628 } 629 if (end < start) { 630 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 631 end, start); 632 start = 0; 633 end = 0; 634 ok = 0; 635 } 636 if (!ok && bootverbose) 637 device_printf(dev, 638 "%s%srequested unsupported memory range %#lx-%#lx " 639 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 640 name, suffix, start, end, 641 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 642 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 643 if (!ok) 644 return (NULL); 645 if (bootverbose) 646 device_printf(dev,"%s%srequested memory range " 647 "0x%lx-0x%lx: good\n", 648 name, suffix, start, end); 649 break; 650 651 default: 652 break; 653 } 654 /* 655 * Bridge is OK decoding this resource, so pass it up. 656 */ 657 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 658 count, flags)); 659} 660 661/* 662 * PCIB interface. 663 */ 664int 665pcib_maxslots(device_t dev) 666{ 667 return(PCI_SLOTMAX); 668} 669 670/* 671 * Since we are a child of a PCI bus, its parent must support the pcib interface. 672 */ 673uint32_t 674pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 675{ 676 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 677} 678 679void 680pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 681{ 682 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 683} 684 685/* 686 * Route an interrupt across a PCI bridge. 687 */ 688int 689pcib_route_interrupt(device_t pcib, device_t dev, int pin) 690{ 691 device_t bus; 692 int parent_intpin; 693 int intnum; 694 695 /* 696 * 697 * The PCI standard defines a swizzle of the child-side device/intpin to 698 * the parent-side intpin as follows. 699 * 700 * device = device on child bus 701 * child_intpin = intpin on child bus slot (0-3) 702 * parent_intpin = intpin on parent bus slot (0-3) 703 * 704 * parent_intpin = (device + child_intpin) % 4 705 */ 706 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 707 708 /* 709 * Our parent is a PCI bus. Its parent must export the pcib interface 710 * which includes the ability to route interrupts. 711 */ 712 bus = device_get_parent(pcib); 713 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 714 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 715 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 716 pci_get_slot(dev), 'A' + pin - 1, intnum); 717 } 718 return(intnum); 719} 720 721/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 722int 723pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 724{ 725 struct pcib_softc *sc = device_get_softc(pcib); 726 device_t bus; 727 728 if (sc->flags & PCIB_DISABLE_MSI) 729 return (ENXIO); 730 bus = device_get_parent(pcib); 731 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 732 irqs)); 733} 734 735/* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 736int 737pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 738{ 739 device_t bus; 740 741 bus = device_get_parent(pcib); 742 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 743} 744 745/* Pass request to alloc an MSI-X message up to the parent bridge. */ 746int 747pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 748{ 749 struct pcib_softc *sc = device_get_softc(pcib); 750 device_t bus; 751 752 if (sc->flags & PCIB_DISABLE_MSI) 753 return (ENXIO); 754 bus = device_get_parent(pcib); 755 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 756} 757 758/* Pass request to release an MSI-X message up to the parent bridge. */ 759int 760pcib_release_msix(device_t pcib, device_t dev, int irq) 761{ 762 device_t bus; 763 764 bus = device_get_parent(pcib); 765 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 766} 767 768/* Pass request to map MSI/MSI-X message up to parent bridge. */ 769int 770pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 771 uint32_t *data) 772{ 773 device_t bus; 774 int error; 775 776 bus = device_get_parent(pcib); 777 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 778 if (error) 779 return (error); 780 781 pci_ht_map_msi(pcib, *addr); 782 return (0); 783} 784 785/* Pass request for device power state up to parent bridge. */ 786int 787pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 788{ 789 device_t bus; 790 791 bus = device_get_parent(pcib); 792 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 793} 794 795/* 796 * Try to read the bus number of a host-PCI bridge using appropriate config 797 * registers. 798 */ 799int 800host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 801 uint8_t *busnum) 802{ 803 uint32_t id; 804 805 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 806 if (id == 0xffffffff) 807 return (0); 808 809 switch (id) { 810 case 0x12258086: 811 /* Intel 824?? */ 812 /* XXX This is a guess */ 813 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 814 *busnum = bus; 815 break; 816 case 0x84c48086: 817 /* Intel 82454KX/GX (Orion) */ 818 *busnum = read_config(bus, slot, func, 0x4a, 1); 819 break; 820 case 0x84ca8086: 821 /* 822 * For the 450nx chipset, there is a whole bundle of 823 * things pretending to be host bridges. The MIOC will 824 * be seen first and isn't really a pci bridge (the 825 * actual busses are attached to the PXB's). We need to 826 * read the registers of the MIOC to figure out the 827 * bus numbers for the PXB channels. 828 * 829 * Since the MIOC doesn't have a pci bus attached, we 830 * pretend it wasn't there. 831 */ 832 return (0); 833 case 0x84cb8086: 834 switch (slot) { 835 case 0x12: 836 /* Intel 82454NX PXB#0, Bus#A */ 837 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 838 break; 839 case 0x13: 840 /* Intel 82454NX PXB#0, Bus#B */ 841 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 842 break; 843 case 0x14: 844 /* Intel 82454NX PXB#1, Bus#A */ 845 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 846 break; 847 case 0x15: 848 /* Intel 82454NX PXB#1, Bus#B */ 849 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 850 break; 851 } 852 break; 853 854 /* ServerWorks -- vendor 0x1166 */ 855 case 0x00051166: 856 case 0x00061166: 857 case 0x00081166: 858 case 0x00091166: 859 case 0x00101166: 860 case 0x00111166: 861 case 0x00171166: 862 case 0x01011166: 863 case 0x010f1014: 864 case 0x01101166: 865 case 0x02011166: 866 case 0x02251166: 867 case 0x03021014: 868 *busnum = read_config(bus, slot, func, 0x44, 1); 869 break; 870 871 /* Compaq/HP -- vendor 0x0e11 */ 872 case 0x60100e11: 873 *busnum = read_config(bus, slot, func, 0xc8, 1); 874 break; 875 default: 876 /* Don't know how to read bus number. */ 877 return 0; 878 } 879 880 return 1; 881} 882