pci_subr.c revision 124641 
1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 124641 2004-01-17 21:54:04Z imp $");
33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/kernel.h>
41#include <sys/bus.h>
42#include <machine/bus.h>
43#include <sys/rman.h>
44#include <sys/sysctl.h>
45
46#include <machine/resource.h>
47
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/pci/pcib_private.h>
51
52#include "pcib_if.h"
53
54static int		pcib_probe(device_t dev);
55
56static device_method_t pcib_methods[] = {
57    /* Device interface */
58    DEVMETHOD(device_probe,		pcib_probe),
59    DEVMETHOD(device_attach,		pcib_attach),
60    DEVMETHOD(device_shutdown,		bus_generic_shutdown),
61    DEVMETHOD(device_suspend,		bus_generic_suspend),
62    DEVMETHOD(device_resume,		bus_generic_resume),
63
64    /* Bus interface */
65    DEVMETHOD(bus_print_child,		bus_generic_print_child),
66    DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
67    DEVMETHOD(bus_write_ivar,		pcib_write_ivar),
68    DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
69    DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
70    DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
71    DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
72    DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
73    DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
74
75    /* pcib interface */
76    DEVMETHOD(pcib_maxslots,		pcib_maxslots),
77    DEVMETHOD(pcib_read_config,		pcib_read_config),
78    DEVMETHOD(pcib_write_config,	pcib_write_config),
79    DEVMETHOD(pcib_route_interrupt,	pcib_route_interrupt),
80
81    { 0, 0 }
82};
83
84static driver_t pcib_driver = {
85    "pcib",
86    pcib_methods,
87    sizeof(struct pcib_softc),
88};
89
90devclass_t pcib_devclass;
91
92DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
93
94/*
95 * Generic device interface
96 */
97static int
98pcib_probe(device_t dev)
99{
100    if ((pci_get_class(dev) == PCIC_BRIDGE) &&
101	(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
102	device_set_desc(dev, "PCI-PCI bridge");
103	return(-10000);
104    }
105    return(ENXIO);
106}
107
108void
109pcib_attach_common(device_t dev)
110{
111    struct pcib_softc	*sc;
112    uint8_t		iolow;
113
114    sc = device_get_softc(dev);
115    sc->dev = dev;
116
117    /*
118     * Get current bridge configuration.
119     */
120    sc->command   = pci_read_config(dev, PCIR_COMMAND, 1);
121    sc->secbus    = pci_read_config(dev, PCIR_SECBUS_1, 1);
122    sc->subbus    = pci_read_config(dev, PCIR_SUBBUS_1, 1);
123    sc->secstat   = pci_read_config(dev, PCIR_SECSTAT_1, 2);
124    sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
125    sc->seclat    = pci_read_config(dev, PCIR_SECLAT_1, 1);
126
127    /*
128     * Determine current I/O decode.
129     */
130    if (sc->command & PCIM_CMD_PORTEN) {
131	iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
132	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
133	    sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
134				       pci_read_config(dev, PCIR_IOBASEL_1, 1));
135	} else {
136	    sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
137	}
138
139	iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
140	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
141	    sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
142					 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
143	} else {
144	    sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
145	}
146    }
147
148    /*
149     * Determine current memory decode.
150     */
151    if (sc->command & PCIM_CMD_MEMEN) {
152	sc->membase   = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
153	sc->memlimit  = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
154	sc->pmembase  = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
155				       pci_read_config(dev, PCIR_PMBASEL_1, 2));
156	sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
157					pci_read_config(dev, PCIR_PMLIMITL_1, 2));
158    }
159
160    /*
161     * Quirk handling.
162     */
163    switch (pci_get_devid(dev)) {
164    case 0x12258086:		/* Intel 82454KX/GX (Orion) */
165	{
166	    uint8_t	supbus;
167
168	    supbus = pci_read_config(dev, 0x41, 1);
169	    if (supbus != 0xff) {
170		sc->secbus = supbus + 1;
171		sc->subbus = supbus + 1;
172	    }
173	    break;
174	}
175
176    /*
177     * The i82380FB mobile docking controller is a PCI-PCI bridge,
178     * and it is a subtractive bridge.  However, the ProgIf is wrong
179     * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
180     * happen.  There's also a Toshiba bridge that behaves this
181     * way.
182     */
183    case 0x124b8086:		/* Intel 82380FB Mobile */
184    case 0x060513d7:		/* Toshiba ???? */
185	sc->flags |= PCIB_SUBTRACTIVE;
186	break;
187    }
188
189    /*
190     * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
191     * but have a ProgIF of 0x80.  The 82801 family (AA, AB, BAM/CAM,
192     * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
193     * This means they act as if they were subtractively decoding
194     * bridges and pass all transactions.  Mark them and real ProgIf 1
195     * parts as subtractive.
196     */
197    if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
198      pci_read_config(dev, PCIR_PROGIF, 1) == 1)
199	sc->flags |= PCIB_SUBTRACTIVE;
200
201    if (bootverbose) {
202	device_printf(dev, "  secondary bus     %d\n", sc->secbus);
203	device_printf(dev, "  subordinate bus   %d\n", sc->subbus);
204	device_printf(dev, "  I/O decode        0x%x-0x%x\n", sc->iobase, sc->iolimit);
205	device_printf(dev, "  memory decode     0x%x-0x%x\n", sc->membase, sc->memlimit);
206	device_printf(dev, "  prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
207	if (sc->flags & PCIB_SUBTRACTIVE)
208	    device_printf(dev, "  Subtractively decoded bridge.\n");
209    }
210
211    /*
212     * XXX If the secondary bus number is zero, we should assign a bus number
213     *     since the BIOS hasn't, then initialise the bridge.
214     */
215
216    /*
217     * XXX If the subordinate bus number is less than the secondary bus number,
218     *     we should pick a better value.  One sensible alternative would be to
219     *     pick 255; the only tradeoff here is that configuration transactions
220     *     would be more widely routed than absolutely necessary.
221     */
222}
223
224int
225pcib_attach(device_t dev)
226{
227    struct pcib_softc	*sc;
228    device_t		child;
229
230    pcib_attach_common(dev);
231    sc = device_get_softc(dev);
232    if (sc->secbus != 0) {
233	child = device_add_child(dev, "pci", sc->secbus);
234	if (child != NULL)
235	    return(bus_generic_attach(dev));
236    }
237
238    /* no secondary bus; we should have fixed this */
239    return(0);
240}
241
242int
243pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
244{
245    struct pcib_softc	*sc = device_get_softc(dev);
246
247    switch (which) {
248    case PCIB_IVAR_BUS:
249	*result = sc->secbus;
250	return(0);
251    }
252    return(ENOENT);
253}
254
255int
256pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
257{
258    struct pcib_softc	*sc = device_get_softc(dev);
259
260    switch (which) {
261    case PCIB_IVAR_BUS:
262	sc->secbus = value;
263	break;
264    }
265    return(ENOENT);
266}
267
268/*
269 * Is the prefetch window open (eg, can we allocate memory in it?)
270 */
271static int
272pcib_is_prefetch_open(struct pcib_softc *sc)
273{
274	return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
275}
276
277/*
278 * Is the nonprefetch window open (eg, can we allocate memory in it?)
279 */
280static int
281pcib_is_nonprefetch_open(struct pcib_softc *sc)
282{
283	return (sc->membase > 0 && sc->membase < sc->memlimit);
284}
285
286/*
287 * Is the io window open (eg, can we allocate ports in it?)
288 */
289static int
290pcib_is_io_open(struct pcib_softc *sc)
291{
292	return (sc->iobase > 0 && sc->iobase < sc->iolimit);
293}
294
295/*
296 * We have to trap resource allocation requests and ensure that the bridge
297 * is set up to, or capable of handling them.
298 */
299struct resource *
300pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
301		    u_long start, u_long end, u_long count, u_int flags)
302{
303	struct pcib_softc	*sc = device_get_softc(dev);
304	int ok;
305
306	/*
307	 * Fail the allocation for this range if it's not supported.
308	 */
309	switch (type) {
310	case SYS_RES_IOPORT:
311		ok = 0;
312		if (!pcib_is_io_open(sc))
313			break;
314		ok = (start >= sc->iobase && end <= sc->iolimit);
315		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
316			if (!ok) {
317				if (start < sc->iobase)
318					start = sc->iobase;
319				if (end > sc->iolimit)
320					end = sc->iolimit;
321			}
322		} else {
323			ok = 1;
324#if 0
325			if (start < sc->iobase && end > sc->iolimit) {
326				start = sc->iobase;
327				end = sc->iolimit;
328			}
329#endif
330		}
331		if (end < start) {
332			device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start);
333			start = 0;
334			end = 0;
335			ok = 0;
336		}
337		if (!ok) {
338			device_printf(dev, "device %s requested unsupported I/O "
339			    "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
340			    device_get_nameunit(child), start, end,
341			    sc->iobase, sc->iolimit);
342			return (NULL);
343		}
344		if (bootverbose)
345			device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n",
346			    device_get_nameunit(child), start, end);
347		break;
348
349	case SYS_RES_MEMORY:
350		ok = 0;
351		if (pcib_is_nonprefetch_open(sc))
352			ok = ok || (start >= sc->membase && end <= sc->memlimit);
353		if (pcib_is_prefetch_open(sc))
354			ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
355		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
356			if (!ok) {
357				ok = 1;
358				if (flags & RF_PREFETCHABLE) {
359					if (pcib_is_prefetch_open(sc)) {
360						if (start < sc->pmembase)
361							start = sc->pmembase;
362						if (end > sc->pmemlimit)
363							end = sc->pmemlimit;
364					} else {
365						ok = 0;
366					}
367				} else {	/* non-prefetchable */
368					if (pcib_is_nonprefetch_open(sc)) {
369						if (start < sc->membase)
370							start = sc->membase;
371						if (end > sc->memlimit)
372							end = sc->memlimit;
373					} else {
374						ok = 0;
375					}
376				}
377			}
378		} else if (!ok) {
379			ok = 1;	/* subtractive bridge: always ok */
380#if 0
381			if (pcib_is_nonprefetch_open(sc)) {
382				if (start < sc->membase && end > sc->memlimit) {
383					start = sc->membase;
384					end = sc->memlimit;
385				}
386			}
387			if (pcib_is_prefetch_open(sc)) {
388				if (start < sc->pmembase && end > sc->pmemlimit) {
389					start = sc->pmembase;
390					end = sc->pmemlimit;
391				}
392			}
393#endif
394		}
395		if (end < start) {
396			device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start);
397			start = 0;
398			end = 0;
399			ok = 0;
400		}
401		if (!ok && bootverbose)
402			device_printf(dev,
403			    "device %s requested unsupported memory range "
404			    "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
405			    device_get_nameunit(child), start, end,
406			    sc->membase, sc->memlimit, sc->pmembase,
407			    sc->pmemlimit);
408		if (!ok)
409			return (NULL);
410		if (bootverbose)
411			device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n",
412			    device_get_nameunit(child), start, end);
413		break;
414
415	default:
416		break;
417	}
418	/*
419	 * Bridge is OK decoding this resource, so pass it up.
420	 */
421	return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
422}
423
424/*
425 * PCIB interface.
426 */
427int
428pcib_maxslots(device_t dev)
429{
430    return(PCI_SLOTMAX);
431}
432
433/*
434 * Since we are a child of a PCI bus, its parent must support the pcib interface.
435 */
436uint32_t
437pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
438{
439    return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
440}
441
442void
443pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
444{
445    PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
446}
447
448/*
449 * Route an interrupt across a PCI bridge.
450 */
451int
452pcib_route_interrupt(device_t pcib, device_t dev, int pin)
453{
454    device_t	bus;
455    int		parent_intpin;
456    int		intnum;
457
458    /*
459     *
460     * The PCI standard defines a swizzle of the child-side device/intpin to
461     * the parent-side intpin as follows.
462     *
463     * device = device on child bus
464     * child_intpin = intpin on child bus slot (0-3)
465     * parent_intpin = intpin on parent bus slot (0-3)
466     *
467     * parent_intpin = (device + child_intpin) % 4
468     */
469    parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
470
471    /*
472     * Our parent is a PCI bus.  Its parent must export the pcib interface
473     * which includes the ability to route interrupts.
474     */
475    bus = device_get_parent(pcib);
476    intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
477    if (PCI_INTERRUPT_VALID(intnum)) {
478	device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
479	    pci_get_slot(dev), 'A' + pin - 1, intnum);
480    }
481    return(intnum);
482}
483
484/*
485 * Try to read the bus number of a host-PCI bridge using appropriate config
486 * registers.
487 */
488int
489host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
490    uint8_t *busnum)
491{
492	uint32_t id;
493
494	id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
495	if (id == 0xffffffff)
496		return (0);
497
498	switch (id) {
499	case 0x12258086:
500		/* Intel 824?? */
501		/* XXX This is a guess */
502		/* *busnum = read_config(bus, slot, func, 0x41, 1); */
503		*busnum = bus;
504		break;
505	case 0x84c48086:
506		/* Intel 82454KX/GX (Orion) */
507		*busnum = read_config(bus, slot, func, 0x4a, 1);
508		break;
509	case 0x84ca8086:
510		/*
511		 * For the 450nx chipset, there is a whole bundle of
512		 * things pretending to be host bridges. The MIOC will
513		 * be seen first and isn't really a pci bridge (the
514		 * actual busses are attached to the PXB's). We need to
515		 * read the registers of the MIOC to figure out the
516		 * bus numbers for the PXB channels.
517		 *
518		 * Since the MIOC doesn't have a pci bus attached, we
519		 * pretend it wasn't there.
520		 */
521		return (0);
522	case 0x84cb8086:
523		switch (slot) {
524		case 0x12:
525			/* Intel 82454NX PXB#0, Bus#A */
526			*busnum = read_config(bus, 0x10, func, 0xd0, 1);
527			break;
528		case 0x13:
529			/* Intel 82454NX PXB#0, Bus#B */
530			*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
531			break;
532		case 0x14:
533			/* Intel 82454NX PXB#1, Bus#A */
534			*busnum = read_config(bus, 0x10, func, 0xd3, 1);
535			break;
536		case 0x15:
537			/* Intel 82454NX PXB#1, Bus#B */
538			*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
539			break;
540		}
541		break;
542
543		/* ServerWorks -- vendor 0x1166 */
544	case 0x00051166:
545	case 0x00061166:
546	case 0x00081166:
547	case 0x00091166:
548	case 0x00101166:
549	case 0x00111166:
550	case 0x00171166:
551	case 0x01011166:
552	case 0x010f1014:
553	case 0x02011166:
554	case 0x03021014:
555		*busnum = read_config(bus, slot, func, 0x44, 1);
556		break;
557	default:
558		/* Don't know how to read bus number. */
559		return 0;
560	}
561
562	return 1;
563}
564