1171095Ssam/*- 2171095Ssam * Copyright (c) 2002-2007 Neterion, Inc. 3171095Ssam * All rights reserved. 4171095Ssam * 5171095Ssam * Redistribution and use in source and binary forms, with or without 6171095Ssam * modification, are permitted provided that the following conditions 7171095Ssam * are met: 8171095Ssam * 1. Redistributions of source code must retain the above copyright 9171095Ssam * notice, this list of conditions and the following disclaimer. 10171095Ssam * 2. Redistributions in binary form must reproduce the above copyright 11171095Ssam * notice, this list of conditions and the following disclaimer in the 12171095Ssam * documentation and/or other materials provided with the distribution. 13171095Ssam * 14171095Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15171095Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16171095Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17171095Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18171095Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19171095Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20171095Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21171095Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22171095Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23171095Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24171095Ssam * SUCH DAMAGE. 25171095Ssam * 26171095Ssam * $FreeBSD$ 27171095Ssam */ 28171095Ssam 29171095Ssam#ifndef XGE_HAL_DEVICE_H 30171095Ssam#define XGE_HAL_DEVICE_H 31171095Ssam 32171095Ssam#include <dev/nxge/include/xge-os-pal.h> 33171095Ssam#include <dev/nxge/include/xge-queue.h> 34171095Ssam#include <dev/nxge/include/xgehal-event.h> 35171095Ssam#include <dev/nxge/include/xgehal-config.h> 36171095Ssam#include <dev/nxge/include/xgehal-regs.h> 37171095Ssam#include <dev/nxge/include/xgehal-channel.h> 38171095Ssam#include <dev/nxge/include/xgehal-stats.h> 39171095Ssam#include <dev/nxge/include/xgehal-ring.h> 40171095Ssam 41171095Ssam__EXTERN_BEGIN_DECLS 42171095Ssam 43171095Ssam#define XGE_HAL_VPD_LENGTH 80 44171095Ssam#define XGE_HAL_CARD_XENA_VPD_ADDR 0x50 45171095Ssam#define XGE_HAL_CARD_HERC_VPD_ADDR 0x80 46171095Ssam#define XGE_HAL_VPD_READ_COMPLETE 0x80 47171095Ssam#define XGE_HAL_VPD_BUFFER_SIZE 128 48173139Srwatson#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500 49173139Srwatson#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500 50173139Srwatson#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500 51173139Srwatson#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50 52173139Srwatson#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250 53173139Srwatson#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */ 54171095Ssam 55173139Srwatson#define XGE_HAL_MAGIC 0x12345678 56173139Srwatson#define XGE_HAL_DEAD 0xDEADDEAD 57171095Ssam#define XGE_HAL_DUMP_BUF_SIZE 0x4000 58171095Ssam 59173139Srwatson#define XGE_HAL_LRO_MAX_BUCKETS 32 60171095Ssam 61171095Ssam/** 62171095Ssam * enum xge_hal_card_e - Xframe adapter type. 63171095Ssam * @XGE_HAL_CARD_UNKNOWN: Unknown device. 64171095Ssam * @XGE_HAL_CARD_XENA: Xframe I device. 65171095Ssam * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device. 66171095Ssam * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device. 67171095Ssam * 68171095Ssam * Enumerates Xframe adapter types. The corresponding PCI device 69171095Ssam * IDs are listed in the file xgehal-defs.h. 70171095Ssam * (See XGE_PCI_DEVICE_ID_XENA_1, etc.) 71171095Ssam * 72171095Ssam * See also: xge_hal_device_check_id(). 73171095Ssam */ 74171095Ssamtypedef enum xge_hal_card_e { 75173139Srwatson XGE_HAL_CARD_UNKNOWN = 0, 76173139Srwatson XGE_HAL_CARD_XENA = 1, 77173139Srwatson XGE_HAL_CARD_HERC = 2, 78173139Srwatson XGE_HAL_CARD_TITAN = 3, 79171095Ssam} xge_hal_card_e; 80171095Ssam 81171095Ssam/** 82171095Ssam * struct xge_hal_device_attr_t - Device memory spaces. 83171095Ssam * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 84171095Ssam * (Linux and the rest.) 85171095Ssam * @regh1: BAR1 mapped memory handle. Same comment as above. 86171095Ssam * @bar0: BAR0 virtual address. 87171095Ssam * @bar1: BAR1 virtual address. 88171095Ssam * @irqh: IRQ handle (Solaris). 89171095Ssam * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux). 90171095Ssam * @pdev: PCI device object. 91171095Ssam * 92171095Ssam * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device 93171095Ssam * mapped memories. Also, includes a pointer to OS-specific PCI device object. 94171095Ssam */ 95171095Ssamtypedef struct xge_hal_device_attr_t { 96173139Srwatson pci_reg_h regh0; 97173139Srwatson pci_reg_h regh1; 98173139Srwatson pci_reg_h regh2; 99173139Srwatson char *bar0; 100173139Srwatson char *bar1; 101173139Srwatson char *bar2; 102173139Srwatson pci_irq_h irqh; 103173139Srwatson pci_cfg_h cfgh; 104173139Srwatson pci_dev_h pdev; 105171095Ssam} xge_hal_device_attr_t; 106171095Ssam 107171095Ssam/** 108171095Ssam * enum xge_hal_device_link_state_e - Link state enumeration. 109171095Ssam * @XGE_HAL_LINK_NONE: Invalid link state. 110171095Ssam * @XGE_HAL_LINK_DOWN: Link is down. 111171095Ssam * @XGE_HAL_LINK_UP: Link is up. 112171095Ssam * 113171095Ssam */ 114171095Ssamtypedef enum xge_hal_device_link_state_e { 115171095Ssam XGE_HAL_LINK_NONE, 116171095Ssam XGE_HAL_LINK_DOWN, 117171095Ssam XGE_HAL_LINK_UP 118171095Ssam} xge_hal_device_link_state_e; 119171095Ssam 120171095Ssam 121171095Ssam/** 122171095Ssam * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration. 123173139Srwatson * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode. 124173139Srwatson * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode. 125173139Srwatson * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode. 126173139Srwatson * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode. 127173139Srwatson * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode. 128173139Srwatson * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode. 129173139Srwatson * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode. 130173139Srwatson * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode. 131173139Srwatson * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode. 132173139Srwatson * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported. 133173139Srwatson * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported. 134173139Srwatson * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported. 135173139Srwatson * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved. 136173139Srwatson * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved. 137173139Srwatson * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value. 138173139Srwatson * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value. 139173139Srwatson * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode. 140171095Ssam * 141171095Ssam */ 142171095Ssamtypedef enum xge_hal_pci_mode_e { 143173139Srwatson XGE_HAL_PCI_33MHZ_MODE = 0x0, 144173139Srwatson XGE_HAL_PCI_66MHZ_MODE = 0x1, 145173139Srwatson XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2, 146173139Srwatson XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3, 147173139Srwatson XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4, 148173139Srwatson XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5, 149173139Srwatson XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6, 150173139Srwatson XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7, 151173139Srwatson XGE_HAL_PCIX_M1_RESERVED = 0x8, 152173139Srwatson XGE_HAL_PCIX_M1_66MHZ_NS = 0xA, 153173139Srwatson XGE_HAL_PCIX_M1_100MHZ_NS = 0xB, 154173139Srwatson XGE_HAL_PCIX_M1_133MHZ_NS = 0xC, 155173139Srwatson XGE_HAL_PCIX_M2_RESERVED = 0xD, 156173139Srwatson XGE_HAL_PCIX_533_RESERVED = 0xE, 157173139Srwatson XGE_HAL_PCI_BASIC_MODE = 0x10, 158173139Srwatson XGE_HAL_PCIX_BASIC_MODE = 0x11, 159173139Srwatson XGE_HAL_PCI_INVALID_MODE = 0x12, 160171095Ssam} xge_hal_pci_mode_e; 161171095Ssam 162171095Ssam/** 163171095Ssam * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration. 164173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ 165173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ 166173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ 167173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ 168173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ 169173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ 170173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ 171173139Srwatson * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value. 172171095Ssam * 173171095Ssam */ 174171095Ssamtypedef enum xge_hal_pci_bus_frequency_e { 175173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33, 176173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66, 177173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100, 178173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133, 179173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200, 180173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250, 181173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266, 182173139Srwatson XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0 183171095Ssam} xge_hal_pci_bus_frequency_e; 184171095Ssam 185171095Ssam/** 186171095Ssam * enum xge_hal_pci_bus_width_e - PCI bus width enumeration. 187173139Srwatson * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width. 188173139Srwatson * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width. 189171095Ssam * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width. 190171095Ssam * 191171095Ssam */ 192171095Ssamtypedef enum xge_hal_pci_bus_width_e { 193173139Srwatson XGE_HAL_PCI_BUS_WIDTH_64BIT = 0, 194173139Srwatson XGE_HAL_PCI_BUS_WIDTH_32BIT = 1, 195173139Srwatson XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2, 196171095Ssam} xge_hal_pci_bus_width_e; 197171095Ssam 198171095Ssam#if defined (XGE_HAL_CONFIG_LRO) 199171095Ssam 200173139Srwatson#define IP_TOTAL_LENGTH_OFFSET 2 201173139Srwatson#define IP_FAST_PATH_HDR_MASK 0x45 202173139Srwatson#define TCP_FAST_PATH_HDR_MASK1 0x50 203173139Srwatson#define TCP_FAST_PATH_HDR_MASK2 0x10 204173139Srwatson#define TCP_FAST_PATH_HDR_MASK3 0x18 205173139Srwatson#define IP_SOURCE_ADDRESS_OFFSET 12 206173139Srwatson#define IP_DESTINATION_ADDRESS_OFFSET 16 207173139Srwatson#define TCP_DESTINATION_PORT_OFFSET 2 208173139Srwatson#define TCP_SOURCE_PORT_OFFSET 0 209173139Srwatson#define TCP_DATA_OFFSET_OFFSET 12 210173139Srwatson#define TCP_WINDOW_OFFSET 14 211173139Srwatson#define TCP_SEQUENCE_NUMBER_OFFSET 4 212173139Srwatson#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8 213171095Ssam 214171095Ssamtypedef struct tcplro { 215171095Ssam u16 source; 216171095Ssam u16 dest; 217171095Ssam u32 seq; 218171095Ssam u32 ack_seq; 219171095Ssam u8 doff_res; 220171095Ssam u8 ctrl; 221171095Ssam u16 window; 222171095Ssam u16 check; 223171095Ssam u16 urg_ptr; 224171095Ssam} tcplro_t; 225171095Ssam 226171095Ssamtypedef struct iplro { 227171095Ssam u8 version_ihl; 228171095Ssam u8 tos; 229171095Ssam u16 tot_len; 230171095Ssam u16 id; 231171095Ssam u16 frag_off; 232171095Ssam u8 ttl; 233171095Ssam u8 protocol; 234171095Ssam u16 check; 235171095Ssam u32 saddr; 236171095Ssam u32 daddr; 237171095Ssam /*The options start here. */ 238171095Ssam} iplro_t; 239171095Ssam 240171095Ssam/* 241171095Ssam * LRO object, one per each LRO session. 242171095Ssam*/ 243171095Ssamtypedef struct lro { 244171095Ssam /* non-linear: contains scatter-gather list of 245171095Ssam xframe-mapped received buffers */ 246173139Srwatson OS_NETSTACK_BUF os_buf; 247173139Srwatson OS_NETSTACK_BUF os_buf_end; 248171095Ssam 249171095Ssam /* link layer header of the first frame; 250171095Ssam remains intack throughout the processing */ 251173139Srwatson u8 *ll_hdr; 252171095Ssam 253171095Ssam /* IP header - gets _collapsed_ */ 254173139Srwatson iplro_t *ip_hdr; 255171095Ssam 256171095Ssam /* transport header - gets _collapsed_ */ 257173139Srwatson tcplro_t *tcp_hdr; 258171095Ssam 259171095Ssam /* Next tcp sequence number */ 260173139Srwatson u32 tcp_next_seq_num; 261171095Ssam /* Current tcp seq & ack */ 262173139Srwatson u32 tcp_seq_num; 263173139Srwatson u32 tcp_ack_num; 264171095Ssam 265171095Ssam /* total number of accumulated (so far) frames */ 266173139Srwatson int sg_num; 267171095Ssam 268171095Ssam /* total data length */ 269173139Srwatson int total_length; 270171095Ssam 271171095Ssam /* receive side hash value, available from Hercules */ 272173139Srwatson u32 rth_value; 273171095Ssam 274171095Ssam /* In use */ 275173139Srwatson u8 in_use; 276171095Ssam 277171095Ssam /* Total length of the fragments clubbed with the inital frame */ 278173139Srwatson u32 frags_len; 279171095Ssam 280171095Ssam /* LRO frame contains time stamp, if (ts_off != -1) */ 281173139Srwatson int ts_off; 282173139Srwatson 283171095Ssam} lro_t; 284171095Ssam#endif 285171095Ssam 286171095Ssam/* 287171095Ssam * xge_hal_spdm_entry_t 288171095Ssam * 289171095Ssam * Represents a single spdm entry in the SPDM table. 290171095Ssam */ 291171095Ssamtypedef struct xge_hal_spdm_entry_t { 292171095Ssam xge_hal_ipaddr_t src_ip; 293171095Ssam xge_hal_ipaddr_t dst_ip; 294171095Ssam u32 jhash_value; 295171095Ssam u16 l4_sp; 296171095Ssam u16 l4_dp; 297171095Ssam u16 spdm_entry; 298171095Ssam u8 in_use; 299171095Ssam u8 is_tcp; 300171095Ssam u8 is_ipv4; 301171095Ssam u8 tgt_queue; 302171095Ssam} xge_hal_spdm_entry_t; 303171095Ssam 304171095Ssam#if defined(XGE_HAL_CONFIG_LRO) 305171095Ssamtypedef struct { 306173139Srwatson lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS]; 307173139Srwatson int lro_next_idx; 308173139Srwatson lro_t *lro_recent; 309171095Ssam} xge_hal_lro_desc_t; 310171095Ssam#endif 311171095Ssam/* 312171095Ssam * xge_hal_vpd_data_t 313171095Ssam * 314171095Ssam * Represents vpd capabilty structure 315171095Ssam */ 316171095Ssamtypedef struct xge_hal_vpd_data_t { 317173139Srwatson u8 product_name[XGE_HAL_VPD_LENGTH]; 318173139Srwatson u8 serial_num[XGE_HAL_VPD_LENGTH]; 319171095Ssam} xge_hal_vpd_data_t; 320171095Ssam 321171095Ssam/* 322171095Ssam * xge_hal_device_t 323171095Ssam * 324171095Ssam * HAL device object. Represents Xframe. 325171095Ssam */ 326171095Ssamtypedef struct { 327173139Srwatson unsigned int magic; 328173139Srwatson pci_reg_h regh0; 329173139Srwatson pci_reg_h regh1; 330173139Srwatson pci_reg_h regh2; 331173139Srwatson char *bar0; 332173139Srwatson char *isrbar0; 333173139Srwatson char *bar1; 334173139Srwatson char *bar2; 335173139Srwatson pci_irq_h irqh; 336173139Srwatson pci_cfg_h cfgh; 337173139Srwatson pci_dev_h pdev; 338173139Srwatson xge_hal_pci_config_t pci_config_space; 339173139Srwatson xge_hal_pci_config_t pci_config_space_bios; 340173139Srwatson xge_hal_device_config_t config; 341173139Srwatson xge_list_t free_channels; 342173139Srwatson xge_list_t fifo_channels; 343173139Srwatson xge_list_t ring_channels; 344173139Srwatson volatile int is_initialized; 345173139Srwatson volatile int terminating; 346173139Srwatson xge_hal_stats_t stats; 347173139Srwatson macaddr_t macaddr[1]; 348173139Srwatson xge_queue_h queueh; 349173139Srwatson volatile int mcast_refcnt; 350173139Srwatson int is_promisc; 351173139Srwatson volatile xge_hal_device_link_state_e link_state; 352173139Srwatson void *upper_layer_info; 353173139Srwatson xge_hal_device_attr_t orig_attr; 354173139Srwatson u16 device_id; 355173139Srwatson u8 revision; 356173139Srwatson int msi_enabled; 357173139Srwatson int hw_is_initialized; 358173139Srwatson u64 inject_serr; 359173139Srwatson u64 inject_ecc; 360173139Srwatson u8 inject_bad_tcode; 361173139Srwatson int inject_bad_tcode_for_chan_type; 362173139Srwatson int reset_needed_after_close; 363173139Srwatson int tti_enabled; 364173139Srwatson xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM]; 365173139Srwatson int bimodal_timer_val_us; 366173139Srwatson int bimodal_urange_a_en; 367173139Srwatson int bimodal_intr_cnt; 368173139Srwatson char *spdm_mem_base; 369173139Srwatson u16 spdm_max_entries; 370173139Srwatson xge_hal_spdm_entry_t **spdm_table; 371173139Srwatson spinlock_t spdm_lock; 372171095Ssam#if defined(XGE_HAL_CONFIG_LRO) 373173139Srwatson xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM]; 374171095Ssam#endif 375173139Srwatson spinlock_t xena_post_lock; 376171095Ssam 377171095Ssam /* bimodal workload stats */ 378173139Srwatson int irq_workload_rxd[XGE_HAL_MAX_RING_NUM]; 379173139Srwatson int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM]; 380173139Srwatson int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM]; 381173139Srwatson int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM]; 382173139Srwatson int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM]; 383173139Srwatson int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM]; 384171095Ssam 385173139Srwatson int mtu_first_time_set; 386173139Srwatson u64 rxufca_lbolt; 387173139Srwatson u64 rxufca_lbolt_time; 388173139Srwatson u64 rxufca_intr_thres; 389171095Ssam char* dump_buf; 390173139Srwatson xge_hal_pci_mode_e pci_mode; 391171095Ssam xge_hal_pci_bus_frequency_e bus_frequency; 392173139Srwatson xge_hal_pci_bus_width_e bus_width; 393171095Ssam xge_hal_vpd_data_t vpd_data; 394173139Srwatson volatile int in_poll; 395173139Srwatson u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR]; 396171095Ssam} xge_hal_device_t; 397171095Ssam 398171095Ssam 399171095Ssam/* ========================== PRIVATE API ================================= */ 400171095Ssam 401171095Ssamvoid 402171095Ssam__hal_device_event_queued(void *data, int event_type); 403171095Ssam 404171095Ssamxge_hal_status_e 405171095Ssam__hal_device_set_swapper(xge_hal_device_t *hldev); 406171095Ssam 407171095Ssamxge_hal_status_e 408171095Ssam__hal_device_rth_it_configure(xge_hal_device_t *hldev); 409171095Ssam 410171095Ssamxge_hal_status_e 411171095Ssam__hal_device_rth_spdm_configure(xge_hal_device_t *hldev); 412171095Ssam 413171095Ssamxge_hal_status_e 414171095Ssam__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status); 415171095Ssam 416171095Ssamxge_hal_status_e 417171095Ssam__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason); 418171095Ssam 419171095Ssamxge_hal_status_e 420171095Ssam__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line, 421173139Srwatson u16 spdm_entry, u64 *spdm_line_val); 422171095Ssam 423171095Ssamvoid __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, 424173139Srwatson void *addr); 425171095Ssam 426171095Ssamvoid __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, 427173139Srwatson void *addr); 428171095Ssamvoid __hal_device_get_vpd_data(xge_hal_device_t *hldev); 429171095Ssam 430171095Ssamxge_hal_status_e 431171095Ssam__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason); 432171095Ssam 433171095Ssamxge_hal_status_e 434171095Ssam__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason); 435171095Ssam 436171095Ssamxge_hal_status_e 437171095Ssam__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason); 438171095Ssam 439171095Ssamxge_hal_status_e 440171095Ssam__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason); 441171095Ssam 442171095Ssamxge_hal_status_e 443171095Ssam__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason); 444171095Ssam 445171095Ssamxge_hal_status_e 446171095Ssam__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason); 447171095Ssam 448171095Ssamxge_hal_status_e 449171095Ssam__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason); 450171095Ssam 451171095Ssamxge_hal_status_e 452171095Ssam__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason); 453171095Ssam 454171095Ssamxge_hal_status_e 455171095Ssam__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason); 456171095Ssam 457171095Ssamxge_hal_status_e 458171095Ssam__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask, 459173139Srwatson int max_millis); 460171095Ssamxge_hal_status_e 461171095Ssam__hal_device_rts_mac_configure(xge_hal_device_t *hldev); 462171095Ssam 463171095Ssamxge_hal_status_e 464171095Ssam__hal_device_rts_qos_configure(xge_hal_device_t *hldev); 465171095Ssam 466171095Ssamxge_hal_status_e 467171095Ssam__hal_device_rts_port_configure(xge_hal_device_t *hldev); 468171095Ssam 469171095Ssamxge_hal_status_e 470171095Ssam__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime); 471171095Ssam 472171095Ssamvoid 473171095Ssam__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag); 474171095Ssam 475171095Ssamvoid 476171095Ssam__hal_device_msix_intr_endis(xge_hal_device_t *hldev, 477173139Srwatson xge_hal_channel_t *channel, int flag); 478171095Ssam 479171095Ssam/* =========================== PUBLIC API ================================= */ 480171095Ssam 481171095Ssamunsigned int 482171095Ssam__hal_fix_time_ival_herc(xge_hal_device_t *hldev, 483173139Srwatson unsigned int time_ival); 484171095Ssamxge_hal_status_e 485171095Ssamxge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable, 486173139Srwatson u32 itable_size); 487171095Ssam 488171095Ssamvoid 489171095Ssamxge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type, 490173139Srwatson u16 bucket_size); 491171095Ssam 492171095Ssamvoid 493171095Ssamxge_hal_rts_rth_init(xge_hal_device_t *hldev); 494171095Ssam 495171095Ssamvoid 496171095Ssamxge_hal_rts_rth_clr(xge_hal_device_t *hldev); 497171095Ssam 498171095Ssamvoid 499171095Ssamxge_hal_rts_rth_start(xge_hal_device_t *hldev); 500171095Ssam 501171095Ssamvoid 502171095Ssamxge_hal_rts_rth_stop(xge_hal_device_t *hldev); 503171095Ssam 504171095Ssamvoid 505171095Ssamxge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key); 506171095Ssam 507171095Ssamxge_hal_status_e 508171095Ssamxge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr); 509171095Ssam 510171095Ssamxge_hal_status_e 511171095Ssamxge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index); 512171095Ssam 513171095Ssamint xge_hal_reinitialize_hw(xge_hal_device_t * hldev); 514171095Ssam 515173139Srwatsonxge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev); 516171095Ssam/** 517171095Ssam * xge_hal_device_rti_reconfigure 518171095Ssam * @hldev: Hal Device 519171095Ssam */ 520171095Ssamstatic inline xge_hal_status_e 521171095Ssamxge_hal_device_rti_reconfigure(xge_hal_device_t *hldev) 522171095Ssam{ 523171095Ssam return __hal_device_rti_configure(hldev, 1); 524171095Ssam} 525171095Ssam 526171095Ssam/** 527171095Ssam * xge_hal_device_rts_port_reconfigure 528171095Ssam * @hldev: Hal Device 529171095Ssam */ 530171095Ssamstatic inline xge_hal_status_e 531171095Ssamxge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev) 532171095Ssam{ 533171095Ssam return __hal_device_rts_port_configure(hldev); 534171095Ssam} 535171095Ssam 536171095Ssam/** 537171095Ssam * xge_hal_device_is_initialized - Returns 0 if device is not 538171095Ssam * initialized, non-zero otherwise. 539171095Ssam * @devh: HAL device handle. 540171095Ssam * 541171095Ssam * Returns 0 if device is not initialized, non-zero otherwise. 542171095Ssam */ 543171095Ssamstatic inline int 544171095Ssamxge_hal_device_is_initialized(xge_hal_device_h devh) 545171095Ssam{ 546171095Ssam return ((xge_hal_device_t*)devh)->is_initialized; 547171095Ssam} 548171095Ssam 549171095Ssam 550171095Ssam/** 551171095Ssam * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing. 552171095Ssam * @devh: HAL device handle. 553171095Ssam * 554171095Ssam * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise. 555171095Ssam */ 556171095Ssamstatic inline int 557171095Ssamxge_hal_device_in_poll(xge_hal_device_h devh) 558171095Ssam{ 559171095Ssam return ((xge_hal_device_t*)devh)->in_poll; 560171095Ssam} 561171095Ssam 562171095Ssam 563171095Ssam/** 564171095Ssam * xge_hal_device_inject_ecc - Inject ECC error. 565171095Ssam * @devh: HAL device, pointer to xge_hal_device_t structure. 566171095Ssam * @err_reg: Contains the error register. 567171095Ssam * 568171095Ssam * This function is used to inject ECC error into the driver flow. 569171095Ssam * This facility can be used to test the driver flow in the 570171095Ssam * case of ECC error is reported by the firmware. 571171095Ssam * 572171095Ssam * Returns: void 573171095Ssam * See also: xge_hal_device_inject_serr(), 574171095Ssam * xge_hal_device_inject_bad_tcode() 575171095Ssam */ 576171095Ssamstatic inline void 577171095Ssamxge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg) 578171095Ssam{ 579173139Srwatson ((xge_hal_device_t*)devh)->inject_ecc = err_reg; 580171095Ssam} 581171095Ssam 582171095Ssam 583171095Ssam/** 584171095Ssam * xge_hal_device_inject_serr - Inject SERR error. 585171095Ssam * @devh: HAL device, pointer to xge_hal_device_t structure. 586171095Ssam * @err_reg: Contains the error register. 587171095Ssam * 588171095Ssam * This function is used to inject SERR error into the driver flow. 589171095Ssam * This facility can be used to test the driver flow in the 590171095Ssam * case of SERR error is reported by firmware. 591171095Ssam * 592171095Ssam * Returns: void 593171095Ssam * See also: xge_hal_device_inject_ecc(), 594171095Ssam * xge_hal_device_inject_bad_tcode() 595171095Ssam */ 596171095Ssamstatic inline void 597171095Ssamxge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg) 598171095Ssam{ 599173139Srwatson ((xge_hal_device_t*)devh)->inject_serr = err_reg; 600171095Ssam} 601171095Ssam 602171095Ssam 603171095Ssam/** 604171095Ssam * xge_hal_device_inject_bad_tcode - Inject Bad transfer code. 605171095Ssam * @devh: HAL device, pointer to xge_hal_device_t structure. 606171095Ssam * @chan_type: Channel type (fifo/ring). 607171095Ssam * @t_code: Transfer code. 608171095Ssam * 609171095Ssam * This function is used to inject bad (Tx/Rx Data)transfer code 610171095Ssam * into the driver flow. 611171095Ssam * 612171095Ssam * This facility can be used to test the driver flow in the 613171095Ssam * case of bad transfer code reported by firmware for a Tx/Rx data 614171095Ssam * transfer. 615171095Ssam * 616171095Ssam * Returns: void 617171095Ssam * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr() 618171095Ssam */ 619171095Ssamstatic inline void 620171095Ssamxge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code) 621171095Ssam{ 622173139Srwatson ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type; 623173139Srwatson ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code; 624171095Ssam} 625171095Ssam 626173139Srwatsonvoid xge_hal_device_msi_enable(xge_hal_device_h devh); 627171095Ssam 628171095Ssam/* 629171095Ssam * xge_hal_device_msi_mode - Is MSI enabled? 630171095Ssam * @devh: HAL device handle. 631171095Ssam * 632171095Ssam * Returns 0 if MSI is enabled for the specified device, 633171095Ssam * non-zero otherwise. 634171095Ssam */ 635171095Ssamstatic inline int 636171095Ssamxge_hal_device_msi_mode(xge_hal_device_h devh) 637171095Ssam{ 638171095Ssam return ((xge_hal_device_t*)devh)->msi_enabled; 639171095Ssam} 640171095Ssam 641171095Ssam/** 642171095Ssam * xge_hal_device_queue - Get per-device event queue. 643171095Ssam * @devh: HAL device handle. 644171095Ssam * 645171095Ssam * Returns: event queue associated with the specified HAL device. 646171095Ssam */ 647171095Ssamstatic inline xge_queue_h 648171095Ssamxge_hal_device_queue (xge_hal_device_h devh) 649171095Ssam{ 650171095Ssam return ((xge_hal_device_t*)devh)->queueh; 651171095Ssam} 652171095Ssam 653171095Ssam/** 654171095Ssam * xge_hal_device_attr - Get original (user-specified) device 655171095Ssam * attributes. 656171095Ssam * @devh: HAL device handle. 657171095Ssam * 658171095Ssam * Returns: original (user-specified) device attributes. 659171095Ssam */ 660171095Ssamstatic inline xge_hal_device_attr_t* 661171095Ssamxge_hal_device_attr(xge_hal_device_h devh) 662171095Ssam{ 663171095Ssam return &((xge_hal_device_t*)devh)->orig_attr; 664171095Ssam} 665171095Ssam 666171095Ssam/** 667171095Ssam * xge_hal_device_private_set - Set ULD context. 668171095Ssam * @devh: HAL device handle. 669171095Ssam * @data: pointer to ULD context 670171095Ssam * 671171095Ssam * Use HAL device to set upper-layer driver (ULD) context. 672171095Ssam * 673171095Ssam * See also: xge_hal_device_from_private(), xge_hal_device_private() 674171095Ssam */ 675171095Ssamstatic inline void 676171095Ssamxge_hal_device_private_set(xge_hal_device_h devh, void *data) 677171095Ssam{ 678171095Ssam ((xge_hal_device_t*)devh)->upper_layer_info = data; 679171095Ssam} 680171095Ssam 681171095Ssam/** 682171095Ssam * xge_hal_device_private - Get ULD context. 683171095Ssam * @devh: HAL device handle. 684171095Ssam * 685171095Ssam * Use HAL device to get upper-layer driver (ULD) context. 686171095Ssam * 687171095Ssam * Returns: ULD context. 688171095Ssam * 689171095Ssam * See also: xge_hal_device_from_private(), xge_hal_device_private_set() 690171095Ssam */ 691171095Ssamstatic inline void* 692171095Ssamxge_hal_device_private(xge_hal_device_h devh) 693171095Ssam{ 694171095Ssam return ((xge_hal_device_t*)devh)->upper_layer_info; 695171095Ssam} 696171095Ssam 697171095Ssam/** 698171095Ssam * xge_hal_device_from_private - Get HAL device object from private. 699171095Ssam * @info_ptr: ULD context. 700171095Ssam * 701171095Ssam * Use ULD context to get HAL device. 702171095Ssam * 703171095Ssam * Returns: Device handle. 704171095Ssam * 705171095Ssam * See also: xge_hal_device_private(), xge_hal_device_private_set() 706171095Ssam */ 707171095Ssamstatic inline xge_hal_device_h 708171095Ssamxge_hal_device_from_private(void *info_ptr) 709171095Ssam{ 710171095Ssam return xge_container_of((void ** ) info_ptr, xge_hal_device_t, 711171095Ssam upper_layer_info); 712171095Ssam} 713171095Ssam 714171095Ssam/** 715171095Ssam * xge_hal_device_mtu_check - check MTU value for ranges 716171095Ssam * @hldev: the device 717171095Ssam * @new_mtu: new MTU value to check 718171095Ssam * 719171095Ssam * Will do sanity check for new MTU value. 720171095Ssam * 721171095Ssam * Returns: XGE_HAL_OK - success. 722171095Ssam * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid. 723171095Ssam * 724171095Ssam * See also: xge_hal_device_mtu_set() 725171095Ssam */ 726171095Ssamstatic inline xge_hal_status_e 727171095Ssamxge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu) 728171095Ssam{ 729171095Ssam if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) { 730173139Srwatson return XGE_HAL_ERR_INVALID_MTU_SIZE; 731171095Ssam } 732171095Ssam 733171095Ssam return XGE_HAL_OK; 734171095Ssam} 735171095Ssam 736171095Ssamvoid xge_hal_device_bcast_enable(xge_hal_device_h devh); 737171095Ssam 738171095Ssamvoid xge_hal_device_bcast_disable(xge_hal_device_h devh); 739171095Ssam 740171095Ssamvoid xge_hal_device_terminating(xge_hal_device_h devh); 741171095Ssam 742171095Ssamxge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev, 743173139Srwatson xge_hal_device_attr_t *attr, xge_hal_device_config_t *config); 744171095Ssam 745171095Ssamvoid xge_hal_device_terminate(xge_hal_device_t *hldev); 746171095Ssam 747171095Ssamxge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev); 748171095Ssam 749171095Ssamxge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev, 750173139Srwatson int index, macaddr_t *macaddr); 751171095Ssam 752171095Ssamxge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev, 753173139Srwatson int index, macaddr_t macaddr); 754171095Ssam 755171095Ssamxge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev, 756173139Srwatson int index); 757171095Ssam 758171095Ssamint xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted); 759171095Ssam 760171095Ssamxge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu); 761171095Ssam 762171095Ssamxge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status); 763171095Ssam 764171095Ssamvoid xge_hal_device_intr_enable(xge_hal_device_t *hldev); 765171095Ssam 766171095Ssamvoid xge_hal_device_intr_disable(xge_hal_device_t *hldev); 767171095Ssam 768171095Ssamxge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev); 769171095Ssam 770171095Ssamxge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev); 771171095Ssam 772171095Ssamvoid xge_hal_device_promisc_enable(xge_hal_device_t *hldev); 773171095Ssam 774171095Ssamvoid xge_hal_device_promisc_disable(xge_hal_device_t *hldev); 775171095Ssam 776171095Ssamxge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev); 777171095Ssam 778171095Ssamxge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev); 779171095Ssam 780171095Ssamxge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh, 781173139Srwatson xge_hal_dtr_h dtrh, 782173139Srwatson u8 t_code); 783171095Ssam 784171095Ssamxge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh, 785173139Srwatson xge_hal_device_link_state_e *ls); 786171095Ssam 787171095Ssamvoid xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us, 788173139Srwatson int one_shot); 789171095Ssam 790171095Ssamvoid xge_hal_device_poll(xge_hal_device_h devh); 791171095Ssam 792171095Ssamxge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh); 793171095Ssam 794171095Ssamint xge_hal_device_is_slot_freeze(xge_hal_device_h devh); 795171095Ssam 796171095Ssamxge_hal_status_e 797171095Ssamxge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, 798173139Srwatson xge_hal_pci_bus_frequency_e *bus_frequency, 799173139Srwatson xge_hal_pci_bus_width_e *bus_width); 800171095Ssam 801171095Ssamxge_hal_status_e 802171095Ssamxge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 803173139Srwatson xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 804173139Srwatson u8 is_tcp, u8 is_ipv4, u8 tgt_queue); 805171095Ssam 806171095Ssamxge_hal_status_e 807171095Ssamxge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 808173139Srwatson xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 809173139Srwatson u8 is_tcp, u8 is_ipv4); 810171095Ssam 811171095Ssamxge_hal_status_e 812171095Ssamxge_hal_device_rts_section_enable(xge_hal_device_h devh, int index); 813171095Ssam 814171095Ssamint 815171095Ssamxge_hal_device_is_closed (xge_hal_device_h devh); 816171095Ssam 817171095Ssam/* private functions, don't use them in ULD */ 818171095Ssam 819171095Ssamvoid __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg); 820171095Ssam 821171095Ssamu64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg); 822171095Ssam 823171095Ssam 824171095Ssam/* Some function protoypes for MSI implementation. */ 825171095Ssamxge_hal_status_e 826171095Ssamxge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi, 827173139Srwatson u32 msg_val); 828171095Ssamvoid 829171095Ssamxge_hal_mask_msi(xge_hal_device_t *hldev); 830171095Ssam 831171095Ssamvoid 832171095Ssamxge_hal_unmask_msi(xge_hal_channel_h channelh); 833171095Ssam 834171095Ssamxge_hal_status_e 835171095Ssamxge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx); 836171095Ssam 837171095Ssamxge_hal_status_e 838171095Ssamxge_hal_mask_msix(xge_hal_device_h devh, int msi_id); 839171095Ssam 840171095Ssamxge_hal_status_e 841171095Ssamxge_hal_unmask_msix(xge_hal_device_h devh, int msi_id); 842171095Ssam 843171095Ssam#if defined(XGE_HAL_CONFIG_LRO) 844171095Ssamxge_hal_status_e 845171095Ssamxge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev); 846173139Srwatson 847173139Srwatsonvoid 848173139Srwatsonxge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev); 849171095Ssam#endif 850171095Ssam 851171095Ssam#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE) 852171095Ssam#define __HAL_STATIC_DEVICE 853171095Ssam#define __HAL_INLINE_DEVICE 854171095Ssam 855171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int 856171095Ssamxge_hal_device_rev(xge_hal_device_t *hldev); 857171095Ssam 858171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 859171095Ssamxge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason); 860171095Ssam 861171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 862171095Ssamxge_hal_device_clear_rx(xge_hal_device_t *hldev); 863171095Ssam 864171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 865171095Ssamxge_hal_device_clear_tx(xge_hal_device_t *hldev); 866171095Ssam 867171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 868171095Ssamxge_hal_device_continue_irq(xge_hal_device_t *hldev); 869171095Ssam 870171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 871171095Ssamxge_hal_device_handle_irq(xge_hal_device_t *hldev); 872171095Ssam 873171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 874171095Ssamxge_hal_device_bar0(xge_hal_device_t *hldev); 875171095Ssam 876171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 877171095Ssamxge_hal_device_isrbar0(xge_hal_device_t *hldev); 878171095Ssam 879171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 880171095Ssamxge_hal_device_bar1(xge_hal_device_t *hldev); 881171095Ssam 882171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 883171095Ssamxge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0); 884171095Ssam 885171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 886171095Ssamxge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0); 887171095Ssam 888171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 889171095Ssamxge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh, 890173139Srwatson char *bar1); 891171095Ssam 892171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 893171095Ssamxge_hal_device_mask_tx(xge_hal_device_t *hldev); 894171095Ssam 895171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 896171095Ssamxge_hal_device_mask_rx(xge_hal_device_t *hldev); 897171095Ssam 898171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 899171095Ssamxge_hal_device_mask_all(xge_hal_device_t *hldev); 900171095Ssam 901171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 902171095Ssamxge_hal_device_unmask_tx(xge_hal_device_t *hldev); 903171095Ssam 904171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 905171095Ssamxge_hal_device_unmask_rx(xge_hal_device_t *hldev); 906171095Ssam 907171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 908171095Ssamxge_hal_device_unmask_all(xge_hal_device_t *hldev); 909171095Ssam 910171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 911171095Ssamxge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx); 912171095Ssam 913171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 914171095Ssamxge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx); 915171095Ssam 916171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 917171095Ssamxge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx); 918171095Ssam 919171095Ssam__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 920171095Ssamxge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx); 921171095Ssam 922171095Ssam#if defined (XGE_HAL_CONFIG_LRO) 923171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8 924171095Ssam__hal_header_parse_token_u8(u8 *string,u16 offset); 925171095Ssam 926171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 927171095Ssam__hal_header_parse_token_u16(u8 *string,u16 offset); 928171095Ssam 929171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32 930171095Ssam__hal_header_parse_token_u32(u8 *string,u16 offset); 931171095Ssam 932171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 933171095Ssam__hal_header_update_u8(u8 *string, u16 offset, u8 val); 934171095Ssam 935171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 936171095Ssam__hal_header_update_u16(u8 *string, u16 offset, u16 val); 937171095Ssam 938171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 939171095Ssam__hal_header_update_u32(u8 *string, u16 offset, u32 val); 940171095Ssam 941171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 942171095Ssam__hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp); 943171095Ssam 944171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 945171095Ssam__hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info); 946171095Ssam 947171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 948171095Ssam__hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off); 949171095Ssam 950171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 951171095Ssam__hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp, 952173139Srwatson xge_hal_dtr_info_t *ext_info); 953171095Ssam 954171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 955171095Ssam__hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 956173139Srwatson xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 957173139Srwatson xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3); 958171095Ssam 959171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 960171095Ssam__hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 961173139Srwatson xge_hal_device_t *hldev); 962171095Ssam 963171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 964171095Ssam__hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 965173139Srwatson xge_hal_device_t *hldev); 966171095Ssam 967171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 968171095Ssam__hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 969173139Srwatson xge_hal_device_t *hldev); 970171095Ssam 971171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 972171095Ssam__hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro, 973173139Srwatson xge_hal_device_t *hldev); 974171095Ssam 975171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 976171095Ssamxge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp, 977173139Srwatson u32 *seglen, lro_t **p_lro, 978173139Srwatson xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 979173139Srwatson lro_t **lro_end3); 980171095Ssam 981171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 982171095Ssamxge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen, 983173139Srwatson lro_t **lro, xge_hal_dtr_info_t *ext_info, 984173139Srwatson xge_hal_device_t *hldev, lro_t **lro_end3); 985171095Ssam 986173139Srwatson__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 987171095Ssamxge_hal_lro_next_session (xge_hal_device_t *hldev, int ring); 988171095Ssam 989171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 990171095Ssamxge_hal_lro_get_next_session(xge_hal_device_t *hldev); 991171095Ssam 992171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 993171095Ssam__hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 994173139Srwatson xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro, 995173139Srwatson int slot, u32 tcp_seg_len, int ts_off); 996171095Ssam 997171095Ssam__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 998173139Srwatson__hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro); 999171095Ssam#endif 1000171095Ssam 1001171095Ssam#else /* XGE_FASTPATH_EXTERN */ 1002171095Ssam#define __HAL_STATIC_DEVICE static 1003171095Ssam#define __HAL_INLINE_DEVICE inline 1004171095Ssam#include <dev/nxge/xgehal/xgehal-device-fp.c> 1005171095Ssam#endif /* XGE_FASTPATH_INLINE */ 1006171095Ssam 1007171095Ssam 1008171095Ssam__EXTERN_END_DECLS 1009171095Ssam 1010171095Ssam#endif /* XGE_HAL_DEVICE_H */ 1011