nandsim.h revision 235537
11590Srgrimes/*- 21590Srgrimes * Copyright (C) 2009-2012 Semihalf 31590Srgrimes * All rights reserved. 41590Srgrimes * 51590Srgrimes * Redistribution and use in source and binary forms, with or without 61590Srgrimes * modification, are permitted provided that the following conditions 71590Srgrimes * are met: 81590Srgrimes * 1. Redistributions of source code must retain the above copyright 91590Srgrimes * notice, this list of conditions and the following disclaimer. 101590Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 111590Srgrimes * notice, this list of conditions and the following disclaimer in the 121590Srgrimes * documentation and/or other materials provided with the distribution. 131590Srgrimes * 141590Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 151590Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 161590Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 171590Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 181590Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 191590Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 201590Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 211590Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 221590Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 231590Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 241590Srgrimes * SUCH DAMAGE. 251590Srgrimes * 261590Srgrimes * $FreeBSD: head/sys/dev/nand/nandsim.h 235537 2012-05-17 10:11:18Z gber $ 271590Srgrimes */ 281590Srgrimes 291590Srgrimes#ifndef _NANDSIM_H_ 301590Srgrimes#define _NANDSIM_H_ 311590Srgrimes 321590Srgrimes#include <sys/ioccom.h> 331590Srgrimes#include <sys/types.h> 341590Srgrimes 351590Srgrimes#define MAX_SIM_DEV 4 361590Srgrimes#define MAX_CTRL_CS 4 371590Srgrimes#define MAX_ECC_BYTES 512 381590Srgrimes#define MAX_BAD_BLOCKS 512 391590Srgrimes#define DEV_MODEL_STR_SIZE 21 401590Srgrimes#define MAN_STR_SIZE 13 411590Srgrimes#define FILENAME_SIZE 20 421590Srgrimes 431590Srgrimes#define MAX_CHIPS (MAX_SIM_DEV*MAX_CTRL_CS) 441590Srgrimes 451590Srgrimes#define NANDSIM_OUTPUT_NONE 0x0 461590Srgrimes#define NANDSIM_OUTPUT_CONSOLE 0x1 471590Srgrimes#define NANDSIM_OUTPUT_RAM 0x2 481590Srgrimes#define NANDSIM_OUTPUT_FILE 0x3 491590Srgrimes 501590Srgrimesstruct sim_ctrl_chip { 511590Srgrimes uint8_t ctrl_num; 521590Srgrimes uint8_t chip_num; 531590Srgrimes}; 541590Srgrimes 551590Srgrimes#define NANDSIM_BASE 'A' 561590Srgrimes 571590Srgrimesstruct sim_param { 581590Srgrimes uint8_t log_level; 591590Srgrimes uint8_t log_output; 601590Srgrimes}; 611590Srgrimes 621590Srgrimes#define NANDSIM_SIM_PARAM _IOW(NANDSIM_BASE, 1, struct sim_param) 631590Srgrimes 641590Srgrimesstruct sim_ctrl { 651590Srgrimes uint8_t running; 661590Srgrimes uint8_t created; 671590Srgrimes uint8_t num; 681590Srgrimes uint8_t num_cs; 691590Srgrimes uint8_t ecc; 701590Srgrimes char filename[FILENAME_SIZE]; 711590Srgrimes uint16_t ecc_layout[MAX_ECC_BYTES]; 721590Srgrimes}; 731590Srgrimes#define NANDSIM_CREATE_CTRL _IOW(NANDSIM_BASE, 2, struct sim_ctrl) 741590Srgrimes#define NANDSIM_DESTROY_CTRL _IOW(NANDSIM_BASE, 3, int) 751590Srgrimes 761590Srgrimesstruct sim_chip { 771590Srgrimes uint8_t num; 781590Srgrimes uint8_t ctrl_num; 791590Srgrimes uint8_t created; 801590Srgrimes uint8_t device_id; 811590Srgrimes uint8_t manufact_id; 821590Srgrimes char device_model[DEV_MODEL_STR_SIZE]; 831590Srgrimes char manufacturer[MAN_STR_SIZE]; 841590Srgrimes uint8_t col_addr_cycles; 851590Srgrimes uint8_t row_addr_cycles; 861590Srgrimes uint8_t features; 871590Srgrimes uint8_t width; 881590Srgrimes uint32_t page_size; 891590Srgrimes uint32_t oob_size; 901590Srgrimes uint32_t pgs_per_blk; 911590Srgrimes uint32_t blks_per_lun; 921590Srgrimes uint32_t luns; 931590Srgrimes 941590Srgrimes uint32_t prog_time; 951590Srgrimes uint32_t erase_time; 961590Srgrimes uint32_t read_time; 971590Srgrimes uint32_t ccs_time; 981590Srgrimes 991590Srgrimes uint32_t error_ratio; 1001590Srgrimes uint32_t wear_level; 1011590Srgrimes uint32_t bad_block_map[MAX_BAD_BLOCKS]; 1021590Srgrimes uint8_t is_wp; 1031590Srgrimes}; 1041590Srgrimes 1051590Srgrimes#define NANDSIM_CREATE_CHIP _IOW(NANDSIM_BASE, 3, struct sim_chip) 1061590Srgrimes 1071590Srgrimesstruct sim_chip_destroy { 1081590Srgrimes uint8_t ctrl_num; 1091590Srgrimes uint8_t chip_num; 1101590Srgrimes}; 1111590Srgrimes#define NANDSIM_DESTROY_CHIP _IOW(NANDSIM_BASE, 4, struct sim_chip_destroy) 1121590Srgrimes 1131590Srgrimes#define NANDSIM_START_CTRL _IOW(NANDSIM_BASE, 5, int) 1141590Srgrimes#define NANDSIM_STOP_CTRL _IOW(NANDSIM_BASE, 6, int) 1151590Srgrimes#define NANDSIM_RESTART_CTRL _IOW(NANDSIM_BASE, 7, int) 1161590Srgrimes 1171590Srgrimes#define NANDSIM_STATUS_CTRL _IOWR(NANDSIM_BASE, 8, struct sim_ctrl) 1181590Srgrimes#define NANDSIM_STATUS_CHIP _IOWR(NANDSIM_BASE, 9, struct sim_chip) 1191590Srgrimes 1201590Srgrimesstruct sim_mod { 1211590Srgrimes uint8_t chip_num; 1221590Srgrimes uint8_t ctrl_num; 1231590Srgrimes uint32_t field; 1241590Srgrimes uint32_t new_value; 1251590Srgrimes}; 1261590Srgrimes#define SIM_MOD_LOG_LEVEL 0 1271590Srgrimes#define SIM_MOD_ERASE_TIME 1 1281590Srgrimes#define SIM_MOD_PROG_TIME 2 1291590Srgrimes#define SIM_MOD_READ_TIME 3 1301590Srgrimes#define SIM_MOD_CCS_TIME 4 1311590Srgrimes#define SIM_MOD_ERROR_RATIO 5 1321590Srgrimes 1331590Srgrimes#define NANDSIM_MODIFY _IOW(NANDSIM_BASE, 10, struct sim_mod) 1341590Srgrimes#define NANDSIM_FREEZE _IOW(NANDSIM_BASE, 11, struct sim_ctrl_chip) 1351590Srgrimes 1361590Srgrimesstruct sim_error { 1371590Srgrimes uint8_t ctrl_num; 1381590Srgrimes uint8_t chip_num; 1391590Srgrimes uint32_t page_num; 1401590Srgrimes uint32_t column; 1411590Srgrimes uint32_t len; 1421590Srgrimes uint32_t pattern; 1431590Srgrimes}; 1441590Srgrimes#define NANDSIM_INJECT_ERROR _IOW(NANDSIM_BASE, 20, struct sim_error) 1451590Srgrimes 1461590Srgrimes#define NANDSIM_GOOD_BLOCK 0 1471590Srgrimes#define NANDSIM_BAD_BLOCK 1 1481590Srgrimesstruct sim_block_state { 1491590Srgrimes uint8_t ctrl_num; 1501590Srgrimes uint8_t chip_num; 1511590Srgrimes uint32_t block_num; 1521590Srgrimes int wearout; 1531590Srgrimes uint8_t state; 1541590Srgrimes}; 1551590Srgrimes#define NANDSIM_SET_BLOCK_STATE _IOW(NANDSIM_BASE, 21, struct sim_block_state) 1561590Srgrimes#define NANDSIM_GET_BLOCK_STATE _IOWR(NANDSIM_BASE, 22, struct sim_block_state) 1571590Srgrimes 1581590Srgrimesstruct sim_log { 1591590Srgrimes uint8_t ctrl_num; 1601590Srgrimes char* log; 1611590Srgrimes size_t len; 1621590Srgrimes}; 1631590Srgrimes#define NANDSIM_PRINT_LOG _IOWR(NANDSIM_BASE, 23, struct sim_log) 1641590Srgrimes 1651590Srgrimesstruct sim_dump { 1661590Srgrimes uint8_t ctrl_num; 1671590Srgrimes uint8_t chip_num; 1681590Srgrimes uint32_t block_num; 1691590Srgrimes uint32_t len; 1701590Srgrimes void* data; 1711590Srgrimes}; 1721590Srgrimes#define NANDSIM_DUMP _IOWR(NANDSIM_BASE, 24, struct sim_dump) 1731590Srgrimes#define NANDSIM_RESTORE _IOWR(NANDSIM_BASE, 25, struct sim_dump) 1741590Srgrimes 1751590Srgrimes#endif /* _NANDSIM_H_ */ 1761590Srgrimes