1235537Sgber/*- 2235537Sgber * Copyright (C) 2009-2012 Semihalf 3235537Sgber * All rights reserved. 4235537Sgber * 5235537Sgber * Redistribution and use in source and binary forms, with or without 6235537Sgber * modification, are permitted provided that the following conditions 7235537Sgber * are met: 8235537Sgber * 1. Redistributions of source code must retain the above copyright 9235537Sgber * notice, this list of conditions and the following disclaimer. 10235537Sgber * 2. Redistributions in binary form must reproduce the above copyright 11235537Sgber * notice, this list of conditions and the following disclaimer in the 12235537Sgber * documentation and/or other materials provided with the distribution. 13235537Sgber * 14235537Sgber * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15235537Sgber * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16235537Sgber * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17235537Sgber * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18235537Sgber * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19235537Sgber * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20235537Sgber * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21235537Sgber * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22235537Sgber * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23235537Sgber * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24235537Sgber * SUCH DAMAGE. 25235537Sgber * 26235537Sgber * $FreeBSD$ 27235537Sgber */ 28235537Sgber 29235537Sgber#ifndef _NANDSIM_H_ 30235537Sgber#define _NANDSIM_H_ 31235537Sgber 32235537Sgber#include <sys/ioccom.h> 33235537Sgber#include <sys/types.h> 34235537Sgber 35235537Sgber#define MAX_SIM_DEV 4 36235537Sgber#define MAX_CTRL_CS 4 37235537Sgber#define MAX_ECC_BYTES 512 38235537Sgber#define MAX_BAD_BLOCKS 512 39235537Sgber#define DEV_MODEL_STR_SIZE 21 40235537Sgber#define MAN_STR_SIZE 13 41235537Sgber#define FILENAME_SIZE 20 42235537Sgber 43235537Sgber#define MAX_CHIPS (MAX_SIM_DEV*MAX_CTRL_CS) 44235537Sgber 45235537Sgber#define NANDSIM_OUTPUT_NONE 0x0 46235537Sgber#define NANDSIM_OUTPUT_CONSOLE 0x1 47235537Sgber#define NANDSIM_OUTPUT_RAM 0x2 48235537Sgber#define NANDSIM_OUTPUT_FILE 0x3 49235537Sgber 50235537Sgberstruct sim_ctrl_chip { 51235537Sgber uint8_t ctrl_num; 52235537Sgber uint8_t chip_num; 53235537Sgber}; 54235537Sgber 55235537Sgber#define NANDSIM_BASE 'A' 56235537Sgber 57235537Sgberstruct sim_param { 58235537Sgber uint8_t log_level; 59235537Sgber uint8_t log_output; 60235537Sgber}; 61235537Sgber 62235537Sgber#define NANDSIM_SIM_PARAM _IOW(NANDSIM_BASE, 1, struct sim_param) 63235537Sgber 64235537Sgberstruct sim_ctrl { 65235537Sgber uint8_t running; 66235537Sgber uint8_t created; 67235537Sgber uint8_t num; 68235537Sgber uint8_t num_cs; 69235537Sgber uint8_t ecc; 70235537Sgber char filename[FILENAME_SIZE]; 71235537Sgber uint16_t ecc_layout[MAX_ECC_BYTES]; 72235537Sgber}; 73235537Sgber#define NANDSIM_CREATE_CTRL _IOW(NANDSIM_BASE, 2, struct sim_ctrl) 74235537Sgber#define NANDSIM_DESTROY_CTRL _IOW(NANDSIM_BASE, 3, int) 75235537Sgber 76235537Sgberstruct sim_chip { 77235537Sgber uint8_t num; 78235537Sgber uint8_t ctrl_num; 79235537Sgber uint8_t created; 80235537Sgber uint8_t device_id; 81235537Sgber uint8_t manufact_id; 82235537Sgber char device_model[DEV_MODEL_STR_SIZE]; 83235537Sgber char manufacturer[MAN_STR_SIZE]; 84235537Sgber uint8_t col_addr_cycles; 85235537Sgber uint8_t row_addr_cycles; 86235537Sgber uint8_t features; 87235537Sgber uint8_t width; 88235537Sgber uint32_t page_size; 89235537Sgber uint32_t oob_size; 90235537Sgber uint32_t pgs_per_blk; 91235537Sgber uint32_t blks_per_lun; 92235537Sgber uint32_t luns; 93235537Sgber 94235537Sgber uint32_t prog_time; 95235537Sgber uint32_t erase_time; 96235537Sgber uint32_t read_time; 97235537Sgber uint32_t ccs_time; 98235537Sgber 99235537Sgber uint32_t error_ratio; 100235537Sgber uint32_t wear_level; 101235537Sgber uint32_t bad_block_map[MAX_BAD_BLOCKS]; 102235537Sgber uint8_t is_wp; 103235537Sgber}; 104235537Sgber 105235537Sgber#define NANDSIM_CREATE_CHIP _IOW(NANDSIM_BASE, 3, struct sim_chip) 106235537Sgber 107235537Sgberstruct sim_chip_destroy { 108235537Sgber uint8_t ctrl_num; 109235537Sgber uint8_t chip_num; 110235537Sgber}; 111235537Sgber#define NANDSIM_DESTROY_CHIP _IOW(NANDSIM_BASE, 4, struct sim_chip_destroy) 112235537Sgber 113235537Sgber#define NANDSIM_START_CTRL _IOW(NANDSIM_BASE, 5, int) 114235537Sgber#define NANDSIM_STOP_CTRL _IOW(NANDSIM_BASE, 6, int) 115235537Sgber#define NANDSIM_RESTART_CTRL _IOW(NANDSIM_BASE, 7, int) 116235537Sgber 117235537Sgber#define NANDSIM_STATUS_CTRL _IOWR(NANDSIM_BASE, 8, struct sim_ctrl) 118235537Sgber#define NANDSIM_STATUS_CHIP _IOWR(NANDSIM_BASE, 9, struct sim_chip) 119235537Sgber 120235537Sgberstruct sim_mod { 121235537Sgber uint8_t chip_num; 122235537Sgber uint8_t ctrl_num; 123235537Sgber uint32_t field; 124235537Sgber uint32_t new_value; 125235537Sgber}; 126235537Sgber#define SIM_MOD_LOG_LEVEL 0 127235537Sgber#define SIM_MOD_ERASE_TIME 1 128235537Sgber#define SIM_MOD_PROG_TIME 2 129235537Sgber#define SIM_MOD_READ_TIME 3 130235537Sgber#define SIM_MOD_CCS_TIME 4 131235537Sgber#define SIM_MOD_ERROR_RATIO 5 132235537Sgber 133235537Sgber#define NANDSIM_MODIFY _IOW(NANDSIM_BASE, 10, struct sim_mod) 134235537Sgber#define NANDSIM_FREEZE _IOW(NANDSIM_BASE, 11, struct sim_ctrl_chip) 135235537Sgber 136235537Sgberstruct sim_error { 137235537Sgber uint8_t ctrl_num; 138235537Sgber uint8_t chip_num; 139235537Sgber uint32_t page_num; 140235537Sgber uint32_t column; 141235537Sgber uint32_t len; 142235537Sgber uint32_t pattern; 143235537Sgber}; 144235537Sgber#define NANDSIM_INJECT_ERROR _IOW(NANDSIM_BASE, 20, struct sim_error) 145235537Sgber 146235537Sgber#define NANDSIM_GOOD_BLOCK 0 147235537Sgber#define NANDSIM_BAD_BLOCK 1 148235537Sgberstruct sim_block_state { 149235537Sgber uint8_t ctrl_num; 150235537Sgber uint8_t chip_num; 151235537Sgber uint32_t block_num; 152235537Sgber int wearout; 153235537Sgber uint8_t state; 154235537Sgber}; 155235537Sgber#define NANDSIM_SET_BLOCK_STATE _IOW(NANDSIM_BASE, 21, struct sim_block_state) 156235537Sgber#define NANDSIM_GET_BLOCK_STATE _IOWR(NANDSIM_BASE, 22, struct sim_block_state) 157235537Sgber 158235537Sgberstruct sim_log { 159235537Sgber uint8_t ctrl_num; 160235537Sgber char* log; 161235537Sgber size_t len; 162235537Sgber}; 163235537Sgber#define NANDSIM_PRINT_LOG _IOWR(NANDSIM_BASE, 23, struct sim_log) 164235537Sgber 165235537Sgberstruct sim_dump { 166235537Sgber uint8_t ctrl_num; 167235537Sgber uint8_t chip_num; 168235537Sgber uint32_t block_num; 169235537Sgber uint32_t len; 170235537Sgber void* data; 171235537Sgber}; 172235537Sgber#define NANDSIM_DUMP _IOWR(NANDSIM_BASE, 24, struct sim_dump) 173235537Sgber#define NANDSIM_RESTORE _IOWR(NANDSIM_BASE, 25, struct sim_dump) 174235537Sgber 175235537Sgber#endif /* _NANDSIM_H_ */ 176