1193240Ssam/*-
2193240Ssam * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
3193240Ssam * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
4193240Ssam * All rights reserved.
5193240Ssam *
6193240Ssam * Redistribution and use in source and binary forms, with or without
7193240Ssam * modification, are permitted provided that the following conditions
8193240Ssam * are met:
9193240Ssam * 1. Redistributions of source code must retain the above copyright
10193240Ssam *    notice, this list of conditions and the following disclaimer,
11193240Ssam *    without modification.
12193240Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13193240Ssam *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14193240Ssam *    redistribution must be conditioned upon including a substantially
15193240Ssam *    similar Disclaimer requirement for further binary redistribution.
16193240Ssam *
17193240Ssam * NO WARRANTY
18193240Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19193240Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20193240Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21193240Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22193240Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23193240Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24193240Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25193240Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26193240Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27193240Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28193240Ssam * THE POSSIBILITY OF SUCH DAMAGES.
29193240Ssam *
30193240Ssam * $FreeBSD$
31193240Ssam */
32193240Ssam
33193240Ssam#ifndef _MWL_HAL_H_
34193240Ssam#define	_MWL_HAL_H_
35193240Ssam/*
36193240Ssam * Hardware Access Layer for Marvell Wireless Devices.
37193240Ssam */
38193240Ssam
39193240Ssam#define MWL_MBSS_SUPPORT		/* enable multi-bss support */
40193240Ssam
41193240Ssam/*
42193240Ssam * Define total number of TX queues in the shared memory.
43193240Ssam * This count includes the EDCA queues, Block Ack queues, and HCCA queues
44193240Ssam * In addition to this, there could be a management packet queue some
45193240Ssam * time in the future
46193240Ssam */
47193240Ssam#define MWL_NUM_EDCA_QUEUES	4
48193240Ssam#define MWL_NUM_HCCA_QUEUES	0
49193240Ssam#define MWL_NUM_BA_QUEUES	0
50193240Ssam#define MWL_NUM_MGMT_QUEUES	0
51195171Ssam#define MWL_NUM_ACK_QUEUES	0
52193240Ssam#define MWL_NUM_TX_QUEUES \
53193240Ssam	(MWL_NUM_EDCA_QUEUES + MWL_NUM_HCCA_QUEUES + MWL_NUM_BA_QUEUES + \
54195171Ssam	 MWL_NUM_MGMT_QUEUES + MWL_NUM_ACK_QUEUES)
55193240Ssam#define MWL_MAX_RXWCB_QUEUES	1
56193240Ssam
57193240Ssam#define MWL_MAX_SUPPORTED_RATES	12
58193240Ssam#define MWL_MAX_SUPPORTED_MCS	32
59193240Ssam
60193240Ssamtypedef enum {
61193240Ssam	MWL_HAL_OK
62193240Ssam} MWL_HAL_STATUS;
63193240Ssam
64193240Ssam/*
65193240Ssam * Transmit queue assignment.
66193240Ssam */
67193240Ssamenum {
68193240Ssam	MWL_WME_AC_BK	= 0,		/* background access category */
69193240Ssam	MWL_WME_AC_BE	= 1, 		/* best effort access category*/
70193240Ssam	MWL_WME_AC_VI	= 2,		/* video access category */
71193240Ssam	MWL_WME_AC_VO	= 3,		/* voice access category */
72193240Ssam};
73193240Ssam
74193240Ssamstruct device;
75193240Ssam
76193240Ssamstruct mwl_hal {
77193240Ssam	bus_space_handle_t mh_ioh;	/* BAR 1 copied from softc */
78193240Ssam	bus_space_tag_t	mh_iot;
79193240Ssam	uint32_t	mh_imask;	/* interrupt mask */
80193240Ssam	/* remainder is opaque to driver */
81193240Ssam};
82193240Ssamstruct mwl_hal *mwl_hal_attach(struct device *dev, uint16_t devid,
83193240Ssam    bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag);
84193240Ssamvoid	mwl_hal_detach(struct mwl_hal *);
85193240Ssam
86193240Ssam/*
87193240Ssam * Query whether multi-bss support is available/enabled.
88193240Ssam */
89193240Ssamint	mwl_hal_ismbsscapable(struct mwl_hal *);
90193240Ssam
91193240Ssamtypedef enum {
92193240Ssam	MWL_HAL_AP,
93193240Ssam	MWL_HAL_STA,			/* infrastructure mode */
94193240Ssam	MWL_HAL_IBSS			/* ibss/adhoc mode */
95193240Ssam} MWL_HAL_BSSTYPE;
96193240Ssamstruct mwl_hal_vap;
97193240Ssam
98193240Ssamstruct mwl_hal_vap *mwl_hal_newvap(struct mwl_hal *, MWL_HAL_BSSTYPE,
99193240Ssam    const uint8_t mac[6]);
100193240Ssamvoid	mwl_hal_delvap(struct mwl_hal_vap *);
101193240Ssam
102193240Ssamenum {
103193240Ssam	MWL_HAL_DEBUG_SENDCMD	= 0x00000001,
104193240Ssam	MWL_HAL_DEBUG_CMDDONE	= 0x00000002,
105193240Ssam	MWL_HAL_DEBUG_IGNHANG	= 0x00000004,
106193240Ssam};
107193240Ssamvoid	mwl_hal_setdebug(struct mwl_hal *, int);
108193240Ssamint	mwl_hal_getdebug(struct mwl_hal *);
109193240Ssam
110193240Ssamtypedef struct {
111193240Ssam	uint16_t freqLow, freqHigh;
112193240Ssam	int nchannels;
113193240Ssam	struct mwl_hal_channel {
114193240Ssam		uint16_t freq;		/* channel center */
115193240Ssam		uint8_t ieee;		/* channel number */
116193240Ssam		int8_t maxTxPow;	/* max tx power (dBm) */
117193240Ssam		uint8_t targetPowers[4];/* target powers (dBm) */
118193240Ssam#define	MWL_HAL_MAXCHAN	40
119193240Ssam	} channels[MWL_HAL_MAXCHAN];
120193240Ssam} MWL_HAL_CHANNELINFO;
121193240Ssamint	mwl_hal_getchannelinfo(struct mwl_hal *, int band, int chw,
122193240Ssam	    const MWL_HAL_CHANNELINFO **);
123193240Ssam
124193240Ssam/*
125193240Ssam * Return the current ISR setting and clear the cause.
126193240Ssam */
127193240Ssamstatic __inline void
128193240Ssammwl_hal_getisr(struct mwl_hal *mh, uint32_t *status)
129193240Ssam{
130193240Ssam#define MACREG_REG_A2H_INTERRUPT_CAUSE      	0x00000C30 // (From ARM to host)
131193240Ssam#define MACREG_REG_INT_CODE                 0x00000C14
132193240Ssam	uint32_t cause;
133193240Ssam
134193240Ssam	cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh,
135193240Ssam			MACREG_REG_A2H_INTERRUPT_CAUSE);
136193240Ssam	if (cause == 0xffffffff) {	/* card removed */
137193240Ssam		cause = 0;
138193240Ssam	} else if (cause != 0) {
139193240Ssam		/* clear cause bits */
140193240Ssam		bus_space_write_4(mh->mh_iot, mh->mh_ioh,
141193240Ssam			MACREG_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask);
142193240Ssam		(void) bus_space_read_4(mh->mh_iot, mh->mh_ioh,
143193240Ssam				MACREG_REG_INT_CODE);
144193240Ssam		cause &= mh->mh_imask;
145193240Ssam	}
146193240Ssam	*status = cause;
147193240Ssam#undef MACREG_REG_INT_CODE
148193240Ssam#undef MACREG_REG_A2H_INTERRUPT_CAUSE
149193240Ssam}
150193240Ssam
151193240Ssamvoid	mwl_hal_intrset(struct mwl_hal *mh, uint32_t mask);
152193240Ssam
153193240Ssam/*
154193240Ssam * Kick the firmware to tell it there are new tx descriptors
155193240Ssam * for processing.  The driver says what h/w q has work in
156193240Ssam * case the f/w ever gets smarter.
157193240Ssam */
158193240Ssamstatic __inline void
159193240Ssammwl_hal_txstart(struct mwl_hal *mh, int qnum)
160193240Ssam{
161193240Ssam#define MACREG_REG_H2A_INTERRUPT_EVENTS     	0x00000C18 // (From host to ARM)
162193240Ssam#define MACREG_H2ARIC_BIT_PPA_READY         0x00000001 // bit 0
163193240Ssam#define MACREG_REG_INT_CODE                 0x00000C14
164193240Ssam
165193240Ssam	bus_space_write_4(mh->mh_iot, mh->mh_ioh,
166193240Ssam		MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
167193240Ssam	(void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MACREG_REG_INT_CODE);
168193240Ssam#undef MACREG_REG_INT_CODE
169193240Ssam#undef MACREG_H2ARIC_BIT_PPA_READY
170193240Ssam#undef MACREG_REG_H2A_INTERRUPT_EVENTS
171193240Ssam}
172193240Ssam
173193240Ssamvoid	mwl_hal_cmddone(struct mwl_hal *mh);
174193240Ssam
175193240Ssamtypedef struct {
176193240Ssam    uint32_t	FreqBand : 6,
177193240Ssam#define MWL_FREQ_BAND_2DOT4GHZ	0x1
178193240Ssam#define MWL_FREQ_BAND_5GHZ     	0x4
179193240Ssam		ChnlWidth: 5,
180193240Ssam#define MWL_CH_10_MHz_WIDTH  	0x1
181193240Ssam#define MWL_CH_20_MHz_WIDTH  	0x2
182193240Ssam#define MWL_CH_40_MHz_WIDTH  	0x4
183193240Ssam		ExtChnlOffset: 2,
184193240Ssam#define MWL_EXT_CH_NONE		0x0
185193240Ssam#define MWL_EXT_CH_ABOVE_CTRL_CH 0x1
186193240Ssam#define MWL_EXT_CH_BELOW_CTRL_CH 0x3
187193240Ssam			 : 19;		/* reserved */
188193240Ssam} MWL_HAL_CHANNEL_FLAGS;
189193240Ssam
190193240Ssamtypedef struct {
191193240Ssam    uint32_t	channel;
192193240Ssam    MWL_HAL_CHANNEL_FLAGS channelFlags;
193193240Ssam} MWL_HAL_CHANNEL;
194193240Ssam
195193240Ssam/*
196193240Ssam * Get Hardware/Firmware capabilities.
197193240Ssam */
198193240Ssamstruct mwl_hal_hwspec {
199193240Ssam	uint8_t    hwVersion;		/* version of the HW */
200193240Ssam	uint8_t    hostInterface;	/* host interface */
201193240Ssam	uint16_t   maxNumWCB;		/* max # of WCB FW handles */
202193240Ssam	uint16_t   maxNumMCAddr;	/* max # of mcast addresses FW handles*/
203193240Ssam	uint16_t   maxNumTxWcb;		/* max # of tx descs per WCB */
204193240Ssam	uint8_t    macAddr[6];		/* MAC address programmed in HW */
205193240Ssam	uint16_t   regionCode;		/* EEPROM region code */
206193240Ssam	uint16_t   numAntennas;		/* Number of antenna used */
207193240Ssam	uint32_t   fwReleaseNumber;	/* firmware release number */
208193240Ssam	uint32_t   wcbBase0;
209193240Ssam	uint32_t   rxDescRead;
210193240Ssam	uint32_t   rxDescWrite;
211193240Ssam	uint32_t   ulFwAwakeCookie;
212195171Ssam	uint32_t   wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES];
213193240Ssam};
214193240Ssamint	mwl_hal_gethwspecs(struct mwl_hal *mh, struct mwl_hal_hwspec *);
215193240Ssam
216193240Ssam/*
217193240Ssam * Supply tx/rx dma-related settings to the firmware.
218193240Ssam */
219193240Ssamstruct mwl_hal_txrxdma {
220193240Ssam	uint32_t   maxNumWCB;		/* max # of WCB FW handles */
221193240Ssam	uint32_t   maxNumTxWcb;		/* max # of tx descs per WCB */
222193240Ssam	uint32_t   rxDescRead;
223193240Ssam	uint32_t   rxDescWrite;
224195171Ssam	uint32_t   wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES];
225193240Ssam};
226193240Ssamint	mwl_hal_sethwdma(struct mwl_hal *mh, const struct mwl_hal_txrxdma *);
227193240Ssam
228193240Ssam/*
229193240Ssam * Get Hardware Statistics.
230193240Ssam *
231193240Ssam * Items marked with ! are deprecated and not ever updated.  In
232193240Ssam * some cases this is because work has been moved to the host (e.g.
233193240Ssam * rx defragmentation).
234193240Ssam */
235193240Ssamstruct mwl_hal_hwstats {
236193240Ssam	uint32_t	TxRetrySuccesses;	/* tx success w/ 1 retry */
237193240Ssam	uint32_t	TxMultipleRetrySuccesses;/* tx success w/ >1 retry */
238193240Ssam	uint32_t	TxFailures;		/* tx fail due to no ACK */
239193240Ssam	uint32_t	RTSSuccesses;		/* CTS rx'd for RTS */
240193240Ssam	uint32_t	RTSFailures;		/* CTS not rx'd for RTS */
241193240Ssam	uint32_t	AckFailures;		/* same as TxFailures */
242193240Ssam	uint32_t	RxDuplicateFrames;	/* rx discard for dup seqno */
243193240Ssam	uint32_t	FCSErrorCount;		/* rx discard for bad FCS */
244193240Ssam	uint32_t	TxWatchDogTimeouts;	/* MAC tx hang (f/w recovery) */
245193240Ssam	uint32_t	RxOverflows;		/* no f/w buffer for rx data */
246193240Ssam	uint32_t	RxFragErrors;		/* !rx fail due to defrag */
247193240Ssam	uint32_t	RxMemErrors;		/* out of mem or desc corrupted
248193240Ssam						   in some way */
249193240Ssam	uint32_t	RxPointerErrors;	/* MAC internal ptr problem */
250193240Ssam	uint32_t	TxUnderflows;		/* !tx underflow on dma */
251193240Ssam	uint32_t	TxDone;			/* MAC tx ops completed
252193240Ssam						   (possibly w/ error) */
253193240Ssam	uint32_t	TxDoneBufTryPut;	/* ! */
254193240Ssam	uint32_t	TxDoneBufPut;		/* same as TxDone */
255193240Ssam	uint32_t	Wait4TxBuf;		/* !no f/w buf avail when
256193240Ssam						    supplied a tx descriptor */
257193240Ssam	uint32_t	TxAttempts;		/* tx descriptors processed */
258193240Ssam	uint32_t	TxSuccesses;		/* tx attempts successful */
259193240Ssam	uint32_t	TxFragments;		/* tx with fragmentation */
260193240Ssam	uint32_t	TxMulticasts;		/* tx multicast frames */
261193240Ssam	uint32_t	RxNonCtlPkts;		/* rx non-control frames */
262193240Ssam	uint32_t	RxMulticasts;		/* rx multicast frames */
263193240Ssam	uint32_t	RxUndecryptableFrames;	/* rx failed due to crypto */
264193240Ssam	uint32_t 	RxICVErrors;		/* rx failed due to ICV check */
265193240Ssam	uint32_t	RxExcludedFrames;	/* rx discarded, e.g. bssid */
266193240Ssam};
267193240Ssamint	mwl_hal_gethwstats(struct mwl_hal *mh, struct mwl_hal_hwstats *);
268193240Ssam
269193240Ssam/*
270193240Ssam * Set HT Guard Interval.
271193240Ssam *
272193240Ssam * GIType = 0:	enable long and short GI
273193240Ssam * GIType = 1:	enable short GI
274193240Ssam * GIType = 2:	enable long GI
275193240Ssam */
276193240Ssamint	mwl_hal_sethtgi(struct mwl_hal_vap *, int GIType);
277193240Ssam
278193240Ssam/*
279193240Ssam * Set Radio Configuration.
280193240Ssam *
281193240Ssam * onoff != 0 turns radio on; otherwise off.
282193240Ssam * if radio is enabled, the preamble is set too.
283193240Ssam */
284193240Ssamtypedef enum {
285193240Ssam	WL_LONG_PREAMBLE = 1,
286193240Ssam	WL_SHORT_PREAMBLE = 3,
287193240Ssam	WL_AUTO_PREAMBLE = 5,
288193240Ssam} MWL_HAL_PREAMBLE;
289193240Ssamint	mwl_hal_setradio(struct mwl_hal *mh, int onoff, MWL_HAL_PREAMBLE preamble);
290193240Ssam
291193240Ssam/*
292193240Ssam * Set Antenna Configuration (legacy operation).
293193240Ssam *
294218909Sbrucec * The RX antenna can be selected using the bitmask
295193240Ssam * ant (bit 0 = antenna 1, bit 1 = antenna 2, etc.)
296193240Ssam * (diversity?XXX)
297193240Ssam */
298193240Ssamtypedef enum {
299193240Ssam	WL_ANTENNATYPE_RX = 1,
300193240Ssam	WL_ANTENNATYPE_TX = 2,
301193240Ssam} MWL_HAL_ANTENNA;
302193240Ssamint	mwl_hal_setantenna(struct mwl_hal *mh, MWL_HAL_ANTENNA dirSet, int ant);
303193240Ssam
304193240Ssam/*
305193240Ssam * Set the threshold for using RTS on TX.
306193240Ssam */
307193240Ssamint	mwl_hal_setrtsthreshold(struct mwl_hal_vap *, int threshold);
308193240Ssam
309193240Ssam/*
310193240Ssam * Set the adapter to operate in infrastructure mode.
311193240Ssam */
312193240Ssamint	mwl_hal_setinframode(struct mwl_hal_vap *);
313193240Ssam
314193240Ssam/*
315193240Ssam * Set Radar Detection Configuration.
316193240Ssam */
317193240Ssamtypedef enum {
318193240Ssam	DR_DFS_DISABLE			= 0,
319193240Ssam	DR_CHK_CHANNEL_AVAILABLE_START	= 1,
320193240Ssam	DR_CHK_CHANNEL_AVAILABLE_STOP	= 2,
321193240Ssam	DR_IN_SERVICE_MONITOR_START	= 3
322193240Ssam} MWL_HAL_RADAR;
323193240Ssamint	mwl_hal_setradardetection(struct mwl_hal *mh, MWL_HAL_RADAR action);
324193240Ssam/*
325193240Ssam * Set the region code that selects the radar bin'ing agorithm.
326193240Ssam */
327193240Ssamint	mwl_hal_setregioncode(struct mwl_hal *mh, int regionCode);
328193240Ssam
329193240Ssam/*
330193240Ssam * Initiate an 802.11h-based channel switch.  The CSA ie
331193240Ssam * is included in the next beacon(s) using the specified
332193240Ssam * information and the firmware counts down until switch
333193240Ssam * time after which it notifies the driver by delivering
334193240Ssam * an interrupt with MACREG_A2HRIC_BIT_CHAN_SWITCH set in
335193240Ssam * the cause register.
336193240Ssam */
337193240Ssamint	mwl_hal_setchannelswitchie(struct mwl_hal *,
338193240Ssam	   const MWL_HAL_CHANNEL *nextchan, uint32_t mode, uint32_t count);
339193240Ssam
340193240Ssam/*
341193240Ssam * Set regdomain code (IEEE SKU).
342193240Ssam */
343193240Ssamenum {
344193240Ssam	DOMAIN_CODE_FCC		= 0x10,	/* USA */
345193240Ssam	DOMAIN_CODE_IC		= 0x20,	/* Canda */
346193240Ssam	DOMAIN_CODE_ETSI	= 0x30,	/* Europe */
347193240Ssam	DOMAIN_CODE_SPAIN	= 0x31,	/* Spain */
348193240Ssam	DOMAIN_CODE_FRANCE	= 0x32,	/* France */
349193240Ssam	DOMAIN_CODE_ETSI_131	= 0x130,/* ETSI w/ 1.3.1 radar type */
350193240Ssam	DOMAIN_CODE_MKK		= 0x40,	/* Japan */
351193240Ssam	DOMAIN_CODE_MKK2	= 0x41,	/* Japan w/ 10MHz chan spacing */
352193240Ssam	DOMAIN_CODE_DGT		= 0x80,	/* Taiwan */
353193240Ssam	DOMAIN_CODE_AUS		= 0x81,	/* Australia */
354193240Ssam};
355193240Ssam
356193240Ssam/*
357193240Ssam * Transmit rate control.  Rate codes with bit 0x80 set are
358193240Ssam * interpreted as MCS codes (this limits us to 0-127).  The
359193240Ssam * transmit rate can be set to a single fixed rate or can
360193240Ssam * be configured to start at an initial rate and drop based
361193240Ssam * on retry counts.
362193240Ssam */
363193240Ssamtypedef enum {
364193240Ssam	RATE_AUTO	= 0,	/* rate selected by firmware */
365193240Ssam	RATE_FIXED	= 2,	/* rate fixed */
366193240Ssam	RATE_FIXED_DROP	= 1,	/* rate starts fixed but may drop */
367193240Ssam} MWL_HAL_TXRATE_HANDLING;
368193240Ssam
369193240Ssamtypedef struct {
370193240Ssam	uint8_t	McastRate;	/* rate for multicast frames */
371193240Ssam#define	RATE_MCS	0x80	/* rate is an MCS index */
372193240Ssam	uint8_t	MgtRate;	/* rate for management frames */
373193240Ssam	struct {
374193240Ssam	    uint8_t TryCount;	/* try this many times */
375193240Ssam	    uint8_t Rate;	/* use this tx rate */
376193240Ssam	} RateSeries[4];	/* rate series */
377193240Ssam} MWL_HAL_TXRATE;
378193240Ssam
379193240Ssamint	mwl_hal_settxrate(struct mwl_hal_vap *,
380193240Ssam	    MWL_HAL_TXRATE_HANDLING handling, const MWL_HAL_TXRATE *rate);
381193240Ssam/* NB: hack for setting rates while scanning */
382193240Ssamint	mwl_hal_settxrate_auto(struct mwl_hal *, const MWL_HAL_TXRATE *rate);
383193240Ssam
384193240Ssam/*
385193240Ssam * Set the Slot Time Configuration.
386193240Ssam * NB: usecs must either be 9 or 20 for now.
387193240Ssam */
388193240Ssamint	mwl_hal_setslottime(struct mwl_hal *mh, int usecs);
389193240Ssam
390193240Ssam/*
391193240Ssam * Adjust current transmit power settings according to powerLevel.
392193240Ssam * This translates to low/medium/high use of the current tx power rate tables.
393193240Ssam */
394193240Ssamint	mwl_hal_adjusttxpower(struct mwl_hal *, uint32_t powerLevel);
395193240Ssam/*
396193240Ssam * Set the transmit power for the specified channel; the power
397193240Ssam * is taken from the calibration data and capped according to
398193240Ssam * the specified max tx power (in dBm).
399193240Ssam */
400193240Ssamint	mwl_hal_settxpower(struct mwl_hal *, const MWL_HAL_CHANNEL *,
401193240Ssam	    uint8_t maxtxpow);
402193240Ssam
403193240Ssam/*
404193240Ssam * Set the Multicast Address Filter.
405193240Ssam * A packed array addresses is specified.
406193240Ssam */
407193240Ssam#define	MWL_HAL_MCAST_MAX	32
408193240Ssamint	mwl_hal_setmcast(struct mwl_hal *mh, int nmc, const uint8_t macs[]);
409193240Ssam
410193240Ssam/*
411193240Ssam * Crypto Configuration.
412193240Ssam */
413193240Ssamtypedef struct {
414193240Ssam    uint16_t  pad;
415193240Ssam    uint16_t  keyTypeId;
416193240Ssam#define KEY_TYPE_ID_WEP		0
417193240Ssam#define KEY_TYPE_ID_TKIP	1
418193240Ssam#define KEY_TYPE_ID_AES		2	/* AES-CCMP */
419193240Ssam    uint32_t  keyFlags;
420193240Ssam#define KEY_FLAG_INUSE		0x00000001	/* indicate key is in use */
421193240Ssam#define KEY_FLAG_RXGROUPKEY	0x00000002	/* Group key for RX only */
422193240Ssam#define KEY_FLAG_TXGROUPKEY	0x00000004	/* Group key for TX */
423193240Ssam#define KEY_FLAG_PAIRWISE	0x00000008	/* pairwise */
424193240Ssam#define KEY_FLAG_RXONLY		0x00000010	/* only used for RX */
425193240Ssam#define KEY_FLAG_AUTHENTICATOR	0x00000020	/* Key is for Authenticator */
426193240Ssam#define KEY_FLAG_TSC_VALID	0x00000040	/* Sequence counters valid */
427193240Ssam#define KEY_FLAG_WEP_TXKEY	0x01000000	/* Tx key for WEP */
428193240Ssam#define KEY_FLAG_MICKEY_VALID	0x02000000	/* Tx/Rx MIC keys are valid */
429193240Ssam    uint32_t  keyIndex; 	/* for WEP only; actual key index */
430193240Ssam    uint16_t  keyLen;		/* key size in bytes */
431193240Ssam    union {			/* key material, keyLen gives size */
432193240Ssam	uint8_t	wep[16];	/* enough for 128 bits */
433193240Ssam	uint8_t	aes[16];
434193240Ssam	struct {
435193240Ssam	    /* NB: group or pairwise key is determined by keyFlags */
436193240Ssam	    uint8_t keyMaterial[16];
437193240Ssam	    uint8_t txMic[8];
438193240Ssam	    uint8_t rxMic[8];
439193240Ssam	    struct {
440193240Ssam	        uint16_t low;
441193240Ssam		uint32_t high;
442193240Ssam	    } rsc;
443193240Ssam	    struct {
444193240Ssam	        uint16_t low;
445193240Ssam		uint32_t high;
446193240Ssam	    } tsc;
447193240Ssam	} __packed tkip;
448193240Ssam    }__packed key;
449193240Ssam} __packed MWL_HAL_KEYVAL;
450193240Ssam
451193240Ssam/*
452193240Ssam * Plumb a unicast/group key.  The mac address identifies
453193240Ssam * the station, use the broadcast address for group keys.
454193240Ssam */
455193240Ssamint	mwl_hal_keyset(struct mwl_hal_vap *, const MWL_HAL_KEYVAL *kv,
456193240Ssam		const uint8_t mac[6]);
457193240Ssam
458193240Ssam/*
459193240Ssam * Plumb a unicast/group key.  The mac address identifies
460193240Ssam * the station, use the broadcast address for group keys.
461193240Ssam */
462193240Ssamint	mwl_hal_keyreset(struct mwl_hal_vap *, const MWL_HAL_KEYVAL *kv,
463193240Ssam		const uint8_t mac[6]);
464193240Ssam
465193240Ssam/*
466193240Ssam * Set the MAC address.
467193240Ssam */
468193240Ssamint	mwl_hal_setmac(struct mwl_hal_vap *, const uint8_t addr[6]);
469193240Ssam
470193240Ssam/*
471193240Ssam * Set the beacon frame contents.  The firmware will modify the
472193240Ssam * frame only to add CSA and WME ie's and to fill in dynamic fields
473193240Ssam * such as the sequence #..
474193240Ssam */
475193240Ssamint	mwl_hal_setbeacon(struct mwl_hal_vap *, const void *, size_t);
476193240Ssam
477193240Ssam/*
478193240Ssam * Handle power save operation for AP operation when offloaded to
479193240Ssam * the host (SET_HW_SPEC_HOST_POWERSAVE).  mwl_hal_setbss_powersave
480193240Ssam * informs the firmware whether 1+ associated stations are in power
481193240Ssam * save mode (it will then buffer mcast traffic). mwl_hal_setsta_powersave
482193240Ssam * specifies a change in power save state for an associated station.
483193240Ssam */
484193240Ssamint	mwl_hal_setpowersave_bss(struct mwl_hal_vap *, uint8_t nsta);
485193240Ssamint	mwl_hal_setpowersave_sta(struct mwl_hal_vap *, uint16_t aid, int ena);
486193240Ssam
487193240Ssam/*
488193240Ssam * Set Association Configuration for station operation.
489193240Ssam */
490193240Ssamint	mwl_hal_setassocid(struct mwl_hal_vap *, const uint8_t bssId[6],
491193240Ssam	    uint16_t assocId);
492193240Ssam
493193240Ssam/*
494193240Ssam * Set the current channel.
495193240Ssam */
496193240Ssamint	mwl_hal_setchannel(struct mwl_hal *mh, const MWL_HAL_CHANNEL *c);
497193240Ssam
498193240Ssam/*
499193240Ssam * A-MPDU Block Ack (BA) stream support.  There are several
500193240Ssam * streams that the driver must multiplex.  Once assigned
501193240Ssam * to a station the driver queues frames to a corresponding
502193240Ssam * transmit queue and the firmware handles all the work.
503193240Ssam *
504193240Ssam * XXX no way to find out how many streams are supported
505193240Ssam */
506193240Ssamtypedef struct {
507193240Ssam	void	*data[2];	/* opaque data */
508193240Ssam	int	txq;
509193240Ssam} MWL_HAL_BASTREAM;
510193240Ssam
511195171Ssamconst MWL_HAL_BASTREAM *mwl_hal_bastream_alloc(struct mwl_hal_vap *,
512195171Ssam	    int ba_type, const uint8_t Macaddr[6], uint8_t Tid,
513193240Ssam	    uint8_t ParamInfo, void *, void *);
514193240Ssamconst MWL_HAL_BASTREAM *mwl_hal_bastream_lookup(struct mwl_hal *mh, int s);
515195171Ssamint	mwl_hal_bastream_create(struct mwl_hal_vap *, const MWL_HAL_BASTREAM *,
516193240Ssam	    int BarThrs, int WindowSize, uint16_t seqno);
517193240Ssamint	mwl_hal_bastream_destroy(struct mwl_hal *mh, const MWL_HAL_BASTREAM *);
518195171Ssamint	mwl_hal_getwatchdogbitmap(struct mwl_hal *mh, uint8_t bitmap[1]);
519193240Ssamint	mwl_hal_bastream_get_seqno(struct mwl_hal *mh, const MWL_HAL_BASTREAM *,
520195171Ssam	    const uint8_t Macaddr[6], uint16_t *pseqno);
521193240Ssam/* for sysctl hookup for debugging */
522193240Ssamvoid	mwl_hal_setbastreams(struct mwl_hal *mh, int mask);
523193240Ssamint	mwl_hal_getbastreams(struct mwl_hal *mh);
524193240Ssam
525193240Ssam/*
526195171Ssam * Set/get A-MPDU aggregation parameters.
527195171Ssam */
528195171Ssamint	mwl_hal_setaggampduratemode(struct mwl_hal *, int mode, int thresh);
529195171Ssamint	mwl_hal_getaggampduratemode(struct mwl_hal *, int *mode, int *thresh);
530195171Ssam
531195171Ssam/*
532193240Ssam * Inform the firmware of a new association station.
533193240Ssam * The address is the MAC address of the peer station.
534193240Ssam * The AID is supplied sans the 0xc000 bits.  The station
535193240Ssam * ID is defined by the caller.  The peer information must
536193240Ssam * be supplied.
537193240Ssam *
538193240Ssam * NB: All values are in host byte order; any byte swapping
539193240Ssam *     is handled by the hal.
540193240Ssam */
541193240Ssamtypedef struct {
542193240Ssam	uint32_t LegacyRateBitMap;
543193240Ssam	uint32_t HTRateBitMap;
544193240Ssam	uint16_t CapInfo;
545193240Ssam	uint16_t HTCapabilitiesInfo;
546193240Ssam	uint8_t	MacHTParamInfo;
547193240Ssam	uint8_t	Rev;
548193240Ssam	struct {
549193240Ssam	    uint8_t ControlChan;
550193240Ssam	    uint8_t AddChan;
551193240Ssam	    uint8_t OpMode;
552193240Ssam	    uint8_t stbc;
553193240Ssam	} __packed AddHtInfo;
554193240Ssam} __packed MWL_HAL_PEERINFO;
555193240Ssamint	mwl_hal_newstation(struct mwl_hal_vap *, const uint8_t addr[6],
556193240Ssam	   uint16_t aid, uint16_t sid, const MWL_HAL_PEERINFO *,
557193240Ssam	   int isQosSta, int wmeInfo);
558193240Ssamint	mwl_hal_delstation(struct mwl_hal_vap *, const uint8_t addr[6]);
559193240Ssam
560193240Ssam/*
561193240Ssam * Prod the firmware to age packets on station power
562193240Ssam * save queues and reap frames on the tx aggregation q's.
563193240Ssam */
564193240Ssamint	mwl_hal_setkeepalive(struct mwl_hal *mh);
565193240Ssam
566193240Ssamtypedef enum {
567193240Ssam	AP_MODE_B_ONLY = 1,
568193240Ssam	AP_MODE_G_ONLY = 2,
569193240Ssam	AP_MODE_MIXED = 3,
570193240Ssam	AP_MODE_N_ONLY = 4,
571193240Ssam	AP_MODE_BandN = 5,
572193240Ssam	AP_MODE_GandN = 6,
573193240Ssam	AP_MODE_BandGandN = 7,
574193240Ssam	AP_MODE_A_ONLY = 8,
575193240Ssam	AP_MODE_AandG = 10,
576193240Ssam	AP_MODE_AandN = 12,
577193240Ssam} MWL_HAL_APMODE;
578193240Ssamint	mwl_hal_setapmode(struct mwl_hal_vap *, MWL_HAL_APMODE);
579193240Ssam
580193240Ssam/*
581193240Ssam * Enable/disable firmware operation.  mwl_hal_start is
582193240Ssam * also used to sync state updates, e.g. beacon frame
583193240Ssam * reconstruction after content changes.
584193240Ssam */
585193240Ssamint	mwl_hal_stop(struct mwl_hal_vap *);
586193240Ssamint	mwl_hal_start(struct mwl_hal_vap *);
587193240Ssam
588193240Ssam/*
589195171Ssam * Add/Remove station from Power Save TIM handling.
590195171Ssam *
591195171Ssam * If set is non-zero the AID is enabled, if zero it is removed.
592195171Ssam */
593195171Ssamint	mwl_hal_updatetim(struct mwl_hal_vap *, uint16_t aid, int set);
594195171Ssam
595195171Ssam/*
596193240Ssam * Enable/disable 11g protection use.  This call specifies
597193240Ssam * the ERP information element flags to use.
598193240Ssam */
599193240Ssamint	mwl_hal_setgprot(struct mwl_hal *, int);
600193240Ssam
601193240Ssam/*
602193240Ssam * Enable/disable WMM support.
603193240Ssam */
604193240Ssamint	mwl_hal_setwmm(struct mwl_hal *mh, int onoff);
605193240Ssam
606193240Ssam/*
607193240Ssam * Configure WMM EDCA parameters for the specified h/w ring.
608193240Ssam */
609193240Ssamint	mwl_hal_setedcaparams(struct mwl_hal *mh, uint8_t qnum,
610193240Ssam	   uint32_t CWmin, uint32_t CWmax, uint8_t AIFSN,  uint16_t TXOPLimit);
611193240Ssam
612193240Ssam/*
613193240Ssam * Configure rate adaptation for indooor/outdoor operation.
614193240Ssam * XXX wtf?
615193240Ssam */
616193240Ssamint	mwl_hal_setrateadaptmode(struct mwl_hal *mh, uint16_t mode);
617193240Ssam
618193240Ssamtypedef enum {
619193240Ssam	CSMODE_CONSERVATIVE = 0,
620193240Ssam	CSMODE_AGGRESSIVE = 1,
621193240Ssam	CSMODE_AUTO_ENA = 2,
622193240Ssam	CSMODE_AUTO_DIS = 3,
623193240Ssam} MWL_HAL_CSMODE;
624193240Ssamint	mwl_hal_setcsmode(struct mwl_hal *mh, MWL_HAL_CSMODE csmode);
625193240Ssam
626193240Ssam/*
627193240Ssam * Configure 11n protection on/off.
628193240Ssam */
629193240Ssamtypedef enum {
630193240Ssam	HTPROTECT_NONE	 = 0,		/* disable */
631193240Ssam	HTPROTECT_OPT	 = 1,		/* optional */
632193240Ssam	HTPROTECT_HT20	 = 2,		/* protect only HT20 */
633193240Ssam	HTPROTECT_HT2040 = 3,		/* protect HT20/40 */
634193240Ssam	HTPROTECT_AUTO	 = 4,		/* automatic */
635193240Ssam}  MWL_HAL_HTPROTECT;
636193240Ssamint	mwl_hal_setnprot(struct mwl_hal_vap *, MWL_HAL_HTPROTECT mode);
637193240Ssam/*
638193240Ssam * Configure 11n protection mechanism for when protection is enabled.
639193240Ssam */
640193240Ssamint	mwl_hal_setnprotmode(struct mwl_hal_vap *, uint8_t mode);
641193240Ssam
642193240Ssam/*
643193240Ssam * Enable/disable Marvell "turbo mode"".
644193240Ssam */
645193240Ssamint	mwl_hal_setoptimizationlevel(struct mwl_hal *mh, int onoff);
646193240Ssam
647193240Ssam/*
648193240Ssam * Set MIMO Power Save handling for a station; the enable and mode
649193240Ssam * values come directly from the Action frame.
650193240Ssam */
651193240Ssamint	mwl_hal_setmimops(struct mwl_hal *mh, const uint8_t addr[6],
652193240Ssam	    uint8_t enable, uint8_t mode);
653193240Ssam
654193240Ssam/*
655193240Ssam * Retrieve the region/country code from the EEPROM.
656193240Ssam */
657193240Ssamint	mwl_hal_getregioncode(struct mwl_hal *mh, uint8_t *countryCode);
658193240Ssamint	mwl_hal_GetBeacon(struct mwl_hal *mh, uint8_t *pBcn, uint16_t *pLen);
659193240Ssamint	mwl_hal_SetRifs(struct mwl_hal *mh, uint8_t QNum);
660193240Ssam
661193240Ssam/*
662193240Ssam * Set/get promiscuous mode.
663193240Ssam */
664193240Ssamint	mwl_hal_setpromisc(struct mwl_hal *, int ena);
665193240Ssamint	mwl_hal_getpromisc(struct mwl_hal *);
666193240Ssam
667193240Ssam/*
668195171Ssam * Enable/disable CF-End use.
669195171Ssam */
670195171Ssamint	mwl_hal_setcfend(struct mwl_hal *, int ena);
671195171Ssam
672195171Ssam/*
673195171Ssam * Enable/disable sta-mode DWDS use/operation.
674195171Ssam */
675195171Ssamint	mwl_hal_setdwds(struct mwl_hal *, int ena);
676195171Ssam
677195171Ssam/*
678193240Ssam * Diagnostic interface.  This is an open-ended interface that
679193240Ssam * is opaque to applications.  Diagnostic programs use this to
680193240Ssam * retrieve internal data structures, etc.  There is no guarantee
681193240Ssam * that calling conventions for calls other than MWL_DIAG_REVS
682193240Ssam * are stable between HAL releases; a diagnostic application must
683193240Ssam * use the HAL revision information to deal with ABI/API differences.
684193240Ssam */
685193240Ssamint	mwl_hal_getdiagstate(struct mwl_hal *mh, int request,
686193240Ssam		const void *args, uint32_t argsize,
687193240Ssam		void **result, uint32_t *resultsize);
688193240Ssam
689193240Ssamint	mwl_hal_fwload(struct mwl_hal *mh, void *fwargs);
690193240Ssam#endif /* _MWL_HAL_H_ */
691