mvs_pci.c revision 207536
1/*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/mvs/mvs_pci.c 207536 2010-05-02 19:28:30Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <vm/uma.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "mvs.h" 47 48/* local prototypes */ 49static int mvs_setup_interrupt(device_t dev); 50static void mvs_intr(void *data); 51static int mvs_suspend(device_t dev); 52static int mvs_resume(device_t dev); 53static int mvs_ctlr_setup(device_t dev); 54 55static struct { 56 uint32_t id; 57 uint8_t rev; 58 const char *name; 59 int ports; 60 int quirks; 61} mvs_ids[] = { 62 {0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI}, 63 {0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI}, 64 {0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI}, 65 {0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI}, 66 {0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII}, 67 {0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII}, 68 {0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE}, 69 {0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII}, 70 {0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII}, 71 {0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT}, 72 {0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII}, 73 {0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT}, 74 {0x00000000, 0x00, NULL, 0, 0} 75}; 76 77static int 78mvs_probe(device_t dev) 79{ 80 char buf[64]; 81 int i; 82 uint32_t devid = pci_get_devid(dev); 83 uint8_t revid = pci_get_revid(dev); 84 85 for (i = 0; mvs_ids[i].id != 0; i++) { 86 if (mvs_ids[i].id == devid && 87 mvs_ids[i].rev <= revid) { 88 snprintf(buf, sizeof(buf), "%s SATA controller", 89 mvs_ids[i].name); 90 device_set_desc_copy(dev, buf); 91 return (BUS_PROBE_VENDOR); 92 } 93 } 94 return (ENXIO); 95} 96 97static int 98mvs_attach(device_t dev) 99{ 100 struct mvs_controller *ctlr = device_get_softc(dev); 101 device_t child; 102 int error, unit, i; 103 uint32_t devid = pci_get_devid(dev); 104 uint8_t revid = pci_get_revid(dev); 105 106 ctlr->dev = dev; 107 i = 0; 108 while (mvs_ids[i].id != 0 && 109 (mvs_ids[i].id != devid || 110 mvs_ids[i].rev > revid)) 111 i++; 112 ctlr->channels = mvs_ids[i].ports; 113 ctlr->quirks = mvs_ids[i].quirks; 114 resource_int_value(device_get_name(dev), 115 device_get_unit(dev), "ccc", &ctlr->ccc); 116 ctlr->cccc = 8; 117 resource_int_value(device_get_name(dev), 118 device_get_unit(dev), "cccc", &ctlr->cccc); 119 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 120 ctlr->ccc = 0; 121 ctlr->cccc = 0; 122 } 123 if (ctlr->ccc > 100000) 124 ctlr->ccc = 100000; 125 device_printf(dev, 126 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 127 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 128 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 129 ctlr->channels, 130 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 131 ((ctlr->quirks & MVS_Q_GENI) ? 132 "not supported" : "supported"), 133 ((ctlr->quirks & MVS_Q_GENIIE) ? 134 " with FBS" : "")); 135 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 136 /* We should have a memory BAR(0). */ 137 ctlr->r_rid = PCIR_BAR(0); 138 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 139 &ctlr->r_rid, RF_ACTIVE))) 140 return ENXIO; 141 /* Setup our own memory management for channels. */ 142 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 143 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 144 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 145 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 146 return (error); 147 } 148 if ((error = rman_manage_region(&ctlr->sc_iomem, 149 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 150 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 151 rman_fini(&ctlr->sc_iomem); 152 return (error); 153 } 154 pci_enable_busmaster(dev); 155 mvs_ctlr_setup(dev); 156 /* Setup interrupts. */ 157 if (mvs_setup_interrupt(dev)) { 158 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 159 rman_fini(&ctlr->sc_iomem); 160 return ENXIO; 161 } 162 /* Attach all channels on this controller */ 163 for (unit = 0; unit < ctlr->channels; unit++) { 164 child = device_add_child(dev, "mvsch", -1); 165 if (child == NULL) 166 device_printf(dev, "failed to add channel device\n"); 167 else 168 device_set_ivars(child, (void *)(intptr_t)unit); 169 } 170 bus_generic_attach(dev); 171 return 0; 172} 173 174static int 175mvs_detach(device_t dev) 176{ 177 struct mvs_controller *ctlr = device_get_softc(dev); 178 device_t *children; 179 int nchildren, i; 180 181 /* Detach & delete all children */ 182 if (!device_get_children(dev, &children, &nchildren)) { 183 for (i = 0; i < nchildren; i++) 184 device_delete_child(dev, children[i]); 185 free(children, M_TEMP); 186 } 187 /* Free interrupt. */ 188 if (ctlr->irq.r_irq) { 189 bus_teardown_intr(dev, ctlr->irq.r_irq, 190 ctlr->irq.handle); 191 bus_release_resource(dev, SYS_RES_IRQ, 192 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 193 } 194 pci_release_msi(dev); 195 /* Free memory. */ 196 rman_fini(&ctlr->sc_iomem); 197 if (ctlr->r_mem) 198 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 199 mtx_destroy(&ctlr->mtx); 200 return (0); 201} 202 203static int 204mvs_ctlr_setup(device_t dev) 205{ 206 struct mvs_controller *ctlr = device_get_softc(dev); 207 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 208 209 /* Mask chip interrupts */ 210 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 211 /* Mask PCI interrupts */ 212 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 213 /* Clear PCI interrupts */ 214 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000); 215 if (ccc && bootverbose) { 216 device_printf(dev, 217 "CCC with %dus/%dcmd enabled\n", 218 ctlr->ccc, ctlr->cccc); 219 } 220 ccc *= 150; 221 /* Configure chip-global CCC */ 222 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) { 223 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc); 224 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc); 225 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 226 if (ccc) 227 ccim |= IC_ALL_PORTS_COAL_DONE; 228 ccc = 0; 229 cccc = 0; 230 } 231 for (i = 0; i < ctlr->channels / 4; i++) { 232 /* Configure per-HC CCC */ 233 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc); 234 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc); 235 if (ccc) 236 ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT)); 237 /* Clear HC interrupts */ 238 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000); 239 } 240 /* Enable chip interrupts */ 241 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) | 242 IC_ERR_HC0 | IC_ERR_HC1; 243 ctlr->mim = ctlr->gmim | ctlr->pmim; 244 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 245 /* Enable PCI interrupts */ 246 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff); 247 return (0); 248} 249 250static void 251mvs_edma(device_t dev, device_t child, int mode) 252{ 253 struct mvs_controller *ctlr = device_get_softc(dev); 254 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 255 int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ; 256 257 if (ctlr->ccc == 0) 258 return; 259 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 260 mtx_lock(&ctlr->mtx); 261 if (mode == MVS_EDMA_OFF) 262 ctlr->pmim |= bit; 263 else 264 ctlr->pmim &= ~bit; 265 ctlr->mim = ctlr->gmim | ctlr->pmim; 266 if (!ctlr->msia) 267 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 268 mtx_unlock(&ctlr->mtx); 269} 270 271static int 272mvs_suspend(device_t dev) 273{ 274 struct mvs_controller *ctlr = device_get_softc(dev); 275 276 bus_generic_suspend(dev); 277 /* Mask chip interrupts */ 278 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 279 /* Mask PCI interrupts */ 280 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 281 return 0; 282} 283 284static int 285mvs_resume(device_t dev) 286{ 287 288 mvs_ctlr_setup(dev); 289 return (bus_generic_resume(dev)); 290} 291 292static int 293mvs_setup_interrupt(device_t dev) 294{ 295 struct mvs_controller *ctlr = device_get_softc(dev); 296 int msi = 0; 297 298 /* Process hints. */ 299 resource_int_value(device_get_name(dev), 300 device_get_unit(dev), "msi", &msi); 301 if (msi < 0) 302 msi = 0; 303 else if (msi > 0) 304 msi = min(1, pci_msi_count(dev)); 305 /* Allocate MSI if needed/present. */ 306 if (msi && pci_alloc_msi(dev, &msi) != 0) 307 msi = 0; 308 ctlr->msi = msi; 309 /* Allocate all IRQs. */ 310 ctlr->irq.r_irq_rid = msi ? 1 : 0; 311 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 312 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 313 device_printf(dev, "unable to map interrupt\n"); 314 return (ENXIO); 315 } 316 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 317 mvs_intr, ctlr, &ctlr->irq.handle))) { 318 device_printf(dev, "unable to setup interrupt\n"); 319 bus_release_resource(dev, SYS_RES_IRQ, 320 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 321 ctlr->irq.r_irq = 0; 322 return (ENXIO); 323 } 324 return (0); 325} 326 327/* 328 * Common case interrupt handler. 329 */ 330static void 331mvs_intr(void *data) 332{ 333 struct mvs_controller *ctlr = data; 334 struct mvs_intr_arg arg; 335 void (*function)(void *); 336 int p; 337 u_int32_t ic, aic; 338 339 ic = ATA_INL(ctlr->r_mem, CHIP_MIC); 340//device_printf(ctlr->dev, "irq MIC:%08x\n", ic); 341 if (ctlr->msi) { 342 /* We have to to mask MSI during processing. */ 343 mtx_lock(&ctlr->mtx); 344 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0); 345 ctlr->msia = 1; /* Deny MIM update during processing. */ 346 mtx_unlock(&ctlr->mtx); 347 } else if (ic == 0) 348 return; 349 /* Acknowledge all-ports CCC interrupt. */ 350 if (ic & IC_ALL_PORTS_COAL_DONE) 351 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 352 for (p = 0; p < ctlr->channels; p++) { 353 if ((p & 3) == 0) { 354 if (p != 0) 355 ic >>= 1; 356 if ((ic & IC_HC0) == 0) { 357 p += 3; 358 ic >>= 8; 359 continue; 360 } 361 /* Acknowledge interrupts of this HC. */ 362 aic = 0; 363 if (ic & (IC_DONE_IRQ << 0)) 364 aic |= HC_IC_DONE(0) | HC_IC_DEV(0); 365 if (ic & (IC_DONE_IRQ << 2)) 366 aic |= HC_IC_DONE(1) | HC_IC_DEV(1); 367 if (ic & (IC_DONE_IRQ << 4)) 368 aic |= HC_IC_DONE(2) | HC_IC_DEV(2); 369 if (ic & (IC_DONE_IRQ << 6)) 370 aic |= HC_IC_DONE(3) | HC_IC_DEV(3); 371 if (ic & IC_HC0_COAL_DONE) 372 aic |= HC_IC_COAL; 373 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic); 374 } 375 /* Call per-port interrupt handler. */ 376 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 377 if ((arg.cause != 0) && 378 (function = ctlr->interrupt[p].function)) { 379 arg.arg = ctlr->interrupt[p].argument; 380 function(&arg); 381 } 382 ic >>= 2; 383 } 384 if (ctlr->msi) { 385 /* Unmasking MSI triggers next interrupt, if needed. */ 386 mtx_lock(&ctlr->mtx); 387 ctlr->msia = 0; /* Allow MIM update. */ 388 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 389 mtx_unlock(&ctlr->mtx); 390 } 391} 392 393static struct resource * 394mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 395 u_long start, u_long end, u_long count, u_int flags) 396{ 397 struct mvs_controller *ctlr = device_get_softc(dev); 398 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 399 struct resource *res = NULL; 400 int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03); 401 long st; 402 403 switch (type) { 404 case SYS_RES_MEMORY: 405 st = rman_get_start(ctlr->r_mem); 406 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 407 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 408 if (res) { 409 bus_space_handle_t bsh; 410 bus_space_tag_t bst; 411 bsh = rman_get_bushandle(ctlr->r_mem); 412 bst = rman_get_bustag(ctlr->r_mem); 413 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 414 rman_set_bushandle(res, bsh); 415 rman_set_bustag(res, bst); 416 } 417 break; 418 case SYS_RES_IRQ: 419 if (*rid == ATA_IRQ_RID) 420 res = ctlr->irq.r_irq; 421 break; 422 } 423 return (res); 424} 425 426static int 427mvs_release_resource(device_t dev, device_t child, int type, int rid, 428 struct resource *r) 429{ 430 431 switch (type) { 432 case SYS_RES_MEMORY: 433 rman_release_resource(r); 434 return (0); 435 case SYS_RES_IRQ: 436 if (rid != ATA_IRQ_RID) 437 return ENOENT; 438 return (0); 439 } 440 return (EINVAL); 441} 442 443static int 444mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 445 int flags, driver_filter_t *filter, driver_intr_t *function, 446 void *argument, void **cookiep) 447{ 448 struct mvs_controller *ctlr = device_get_softc(dev); 449 int unit = (intptr_t)device_get_ivars(child); 450 451 if (filter != NULL) { 452 printf("mvs.c: we cannot use a filter here\n"); 453 return (EINVAL); 454 } 455 ctlr->interrupt[unit].function = function; 456 ctlr->interrupt[unit].argument = argument; 457 return (0); 458} 459 460static int 461mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 462 void *cookie) 463{ 464 struct mvs_controller *ctlr = device_get_softc(dev); 465 int unit = (intptr_t)device_get_ivars(child); 466 467 ctlr->interrupt[unit].function = NULL; 468 ctlr->interrupt[unit].argument = NULL; 469 return (0); 470} 471 472static int 473mvs_print_child(device_t dev, device_t child) 474{ 475 int retval; 476 477 retval = bus_print_child_header(dev, child); 478 retval += printf(" at channel %d", 479 (int)(intptr_t)device_get_ivars(child)); 480 retval += bus_print_child_footer(dev, child); 481 482 return (retval); 483} 484 485static device_method_t mvs_methods[] = { 486 DEVMETHOD(device_probe, mvs_probe), 487 DEVMETHOD(device_attach, mvs_attach), 488 DEVMETHOD(device_detach, mvs_detach), 489 DEVMETHOD(device_suspend, mvs_suspend), 490 DEVMETHOD(device_resume, mvs_resume), 491 DEVMETHOD(bus_print_child, mvs_print_child), 492 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 493 DEVMETHOD(bus_release_resource, mvs_release_resource), 494 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 495 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 496 DEVMETHOD(mvs_edma, mvs_edma), 497 { 0, 0 } 498}; 499static driver_t mvs_driver = { 500 "mvs", 501 mvs_methods, 502 sizeof(struct mvs_controller) 503}; 504DRIVER_MODULE(mvs, pci, mvs_driver, mvs_devclass, 0, 0); 505MODULE_VERSION(mvs, 1); 506MODULE_DEPEND(mvs, cam, 1, 1, 1); 507 508