if_mskreg.h revision 204545
150397Sobrien/****************************************************************************** 2169689Skan * 3169689Skan * Name: skgehw.h 450397Sobrien * Project: Gigabit Ethernet Adapters, Common Modules 550397Sobrien * Version: $Revision: 2.49 $ 650397Sobrien * Date: $Date: 2005/01/20 13:01:35 $ 790075Sobrien * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family 850397Sobrien * 990075Sobrien ******************************************************************************/ 1090075Sobrien 1190075Sobrien/****************************************************************************** 1290075Sobrien * 1350397Sobrien * LICENSE: 1490075Sobrien * Copyright (C) Marvell International Ltd. and/or its affiliates 1590075Sobrien * 1690075Sobrien * The computer program files contained in this folder ("Files") 1790075Sobrien * are provided to you under the BSD-type license terms provided 1850397Sobrien * below, and any use of such Files and any derivative works 1990075Sobrien * thereof created by you shall be governed by the following terms 2090075Sobrien * and conditions: 21169689Skan * 22169689Skan * - Redistributions of source code must retain the above copyright 2350397Sobrien * notice, this list of conditions and the following disclaimer. 2490075Sobrien * - Redistributions in binary form must reproduce the above 2590075Sobrien * copyright notice, this list of conditions and the following 2690075Sobrien * disclaimer in the documentation and/or other materials provided 2750397Sobrien * with the distribution. 2850397Sobrien * - Neither the name of Marvell nor the names of its contributors 2950397Sobrien * may be used to endorse or promote products derived from this 3050397Sobrien * software without specific prior written permission. 3150397Sobrien * 3250397Sobrien * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3350397Sobrien * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3450397Sobrien * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 3550397Sobrien * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 3650397Sobrien * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 3750397Sobrien * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 3850397Sobrien * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 3950397Sobrien * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 4050397Sobrien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 4150397Sobrien * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 4250397Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 4350397Sobrien * OF THE POSSIBILITY OF SUCH DAMAGE. 4450397Sobrien * /LICENSE 4550397Sobrien * 4650397Sobrien ******************************************************************************/ 4750397Sobrien 4850397Sobrien/*- 4950397Sobrien * Copyright (c) 1997, 1998, 1999, 2000 5050397Sobrien * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5150397Sobrien * 5250397Sobrien * Redistribution and use in source and binary forms, with or without 5350397Sobrien * modification, are permitted provided that the following conditions 5450397Sobrien * are met: 5550397Sobrien * 1. Redistributions of source code must retain the above copyright 5650397Sobrien * notice, this list of conditions and the following disclaimer. 5750397Sobrien * 2. Redistributions in binary form must reproduce the above copyright 5850397Sobrien * notice, this list of conditions and the following disclaimer in the 5950397Sobrien * documentation and/or other materials provided with the distribution. 6050397Sobrien * 3. All advertising materials mentioning features or use of this software 6150397Sobrien * must display the following acknowledgement: 6250397Sobrien * This product includes software developed by Bill Paul. 6350397Sobrien * 4. Neither the name of the author nor the names of any co-contributors 6450397Sobrien * may be used to endorse or promote products derived from this software 6550397Sobrien * without specific prior written permission. 6650397Sobrien * 6750397Sobrien * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 6850397Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 6950397Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 7050397Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 7150397Sobrien * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 7250397Sobrien * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 7350397Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 7450397Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 7550397Sobrien * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 7650397Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 7750397Sobrien * THE POSSIBILITY OF SUCH DAMAGE. 7850397Sobrien */ 7950397Sobrien 8050397Sobrien/*- 8150397Sobrien * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 8250397Sobrien * 8350397Sobrien * Permission to use, copy, modify, and distribute this software for any 8450397Sobrien * purpose with or without fee is hereby granted, provided that the above 8550397Sobrien * copyright notice and this permission notice appear in all copies. 8650397Sobrien * 8750397Sobrien * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8850397Sobrien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 8950397Sobrien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 9050397Sobrien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 9150397Sobrien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 9250397Sobrien * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 9350397Sobrien * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 9450397Sobrien */ 9550397Sobrien 9650397Sobrien/*$FreeBSD: head/sys/dev/msk/if_mskreg.h 204545 2010-03-02 01:45:02Z yongari $*/ 9750397Sobrien 9850397Sobrien/* 9950397Sobrien * SysKonnect PCI vendor ID 10050397Sobrien */ 10150397Sobrien#define VENDORID_SK 0x1148 10250397Sobrien 10350397Sobrien/* 10450397Sobrien * Marvell PCI vendor ID 10550397Sobrien */ 10650397Sobrien#define VENDORID_MARVELL 0x11AB 10750397Sobrien 10850397Sobrien/* 10950397Sobrien * D-Link PCI vendor ID 11050397Sobrien */ 11150397Sobrien#define VENDORID_DLINK 0x1186 11250397Sobrien 11350397Sobrien/* 11450397Sobrien * SysKonnect ethernet device IDs 11550397Sobrien */ 11650397Sobrien#define DEVICEID_SK_YUKON2 0x9000 11750397Sobrien#define DEVICEID_SK_YUKON2_EXPR 0x9e00 11850397Sobrien 119132718Skan/* 12050397Sobrien * Marvell gigabit ethernet device IDs 12150397Sobrien */ 12250397Sobrien#define DEVICEID_MRVL_8021CU 0x4340 12350397Sobrien#define DEVICEID_MRVL_8022CU 0x4341 12450397Sobrien#define DEVICEID_MRVL_8061CU 0x4342 12590075Sobrien#define DEVICEID_MRVL_8062CU 0x4343 12650397Sobrien#define DEVICEID_MRVL_8021X 0x4344 12750397Sobrien#define DEVICEID_MRVL_8022X 0x4345 12850397Sobrien#define DEVICEID_MRVL_8061X 0x4346 129132718Skan#define DEVICEID_MRVL_8062X 0x4347 130132718Skan#define DEVICEID_MRVL_8035 0x4350 13152284Sobrien#define DEVICEID_MRVL_8036 0x4351 13250397Sobrien#define DEVICEID_MRVL_8038 0x4352 13390075Sobrien#define DEVICEID_MRVL_8039 0x4353 13490075Sobrien#define DEVICEID_MRVL_8040 0x4354 13550397Sobrien#define DEVICEID_MRVL_8040T 0x4355 13690075Sobrien#define DEVICEID_MRVL_8042 0x4357 13750397Sobrien#define DEVICEID_MRVL_8048 0x435A 13850397Sobrien#define DEVICEID_MRVL_4360 0x4360 13950397Sobrien#define DEVICEID_MRVL_4361 0x4361 14050397Sobrien#define DEVICEID_MRVL_4362 0x4362 14150397Sobrien#define DEVICEID_MRVL_4363 0x4363 14252284Sobrien#define DEVICEID_MRVL_4364 0x4364 14390075Sobrien#define DEVICEID_MRVL_4365 0x4365 14490075Sobrien#define DEVICEID_MRVL_436A 0x436A 145169689Skan#define DEVICEID_MRVL_436B 0x436B 146169689Skan#define DEVICEID_MRVL_436C 0x436C 14750397Sobrien#define DEVICEID_MRVL_4380 0x4380 14850397Sobrien 14950397Sobrien/* 15050397Sobrien * D-Link gigabit ethernet device ID 15150397Sobrien */ 15250397Sobrien#define DEVICEID_DLINK_DGE550SX 0x4001 15350397Sobrien#define DEVICEID_DLINK_DGE560SX 0x4002 15450397Sobrien#define DEVICEID_DLINK_DGE560T 0x4b00 15550397Sobrien 15650397Sobrien#define BIT_31 (1 << 31) 15790075Sobrien#define BIT_30 (1 << 30) 15850397Sobrien#define BIT_29 (1 << 29) 15950397Sobrien#define BIT_28 (1 << 28) 16050397Sobrien#define BIT_27 (1 << 27) 16150397Sobrien#define BIT_26 (1 << 26) 16250397Sobrien#define BIT_25 (1 << 25) 16350397Sobrien#define BIT_24 (1 << 24) 16450397Sobrien#define BIT_23 (1 << 23) 16550397Sobrien#define BIT_22 (1 << 22) 16690075Sobrien#define BIT_21 (1 << 21) 16750397Sobrien#define BIT_20 (1 << 20) 16890075Sobrien#define BIT_19 (1 << 19) 16990075Sobrien#define BIT_18 (1 << 18) 17090075Sobrien#define BIT_17 (1 << 17) 17150397Sobrien#define BIT_16 (1 << 16) 17290075Sobrien#define BIT_15 (1 << 15) 17390075Sobrien#define BIT_14 (1 << 14) 17450397Sobrien#define BIT_13 (1 << 13) 17550397Sobrien#define BIT_12 (1 << 12) 17690075Sobrien#define BIT_11 (1 << 11) 17750397Sobrien#define BIT_10 (1 << 10) 17850397Sobrien#define BIT_9 (1 << 9) 179132718Skan#define BIT_8 (1 << 8) 18050397Sobrien#define BIT_7 (1 << 7) 18150397Sobrien#define BIT_6 (1 << 6) 18250397Sobrien#define BIT_5 (1 << 5) 18350397Sobrien#define BIT_4 (1 << 4) 184169689Skan#define BIT_3 (1 << 3) 18550397Sobrien#define BIT_2 (1 << 2) 18650397Sobrien#define BIT_1 (1 << 1) 18790075Sobrien#define BIT_0 (1 << 0) 18850397Sobrien 18990075Sobrien#define SHIFT31(x) ((x) << 31) 19090075Sobrien#define SHIFT30(x) ((x) << 30) 191169689Skan#define SHIFT29(x) ((x) << 29) 19250397Sobrien#define SHIFT28(x) ((x) << 28) 193169689Skan#define SHIFT27(x) ((x) << 27) 194169689Skan#define SHIFT26(x) ((x) << 26) 195169689Skan#define SHIFT25(x) ((x) << 25) 196169689Skan#define SHIFT24(x) ((x) << 24) 197169689Skan#define SHIFT23(x) ((x) << 23) 198169689Skan#define SHIFT22(x) ((x) << 22) 199169689Skan#define SHIFT21(x) ((x) << 21) 200169689Skan#define SHIFT20(x) ((x) << 20) 201169689Skan#define SHIFT19(x) ((x) << 19) 202169689Skan#define SHIFT18(x) ((x) << 18) 20350397Sobrien#define SHIFT17(x) ((x) << 17) 20450397Sobrien#define SHIFT16(x) ((x) << 16) 20550397Sobrien#define SHIFT15(x) ((x) << 15) 20650397Sobrien#define SHIFT14(x) ((x) << 14) 20750397Sobrien#define SHIFT13(x) ((x) << 13) 20850397Sobrien#define SHIFT12(x) ((x) << 12) 20950397Sobrien#define SHIFT11(x) ((x) << 11) 21050397Sobrien#define SHIFT10(x) ((x) << 10) 211169689Skan#define SHIFT9(x) ((x) << 9) 212169689Skan#define SHIFT8(x) ((x) << 8) 213169689Skan#define SHIFT7(x) ((x) << 7) 214169689Skan#define SHIFT6(x) ((x) << 6) 215169689Skan#define SHIFT5(x) ((x) << 5) 216169689Skan#define SHIFT4(x) ((x) << 4) 217169689Skan#define SHIFT3(x) ((x) << 3) 218169689Skan#define SHIFT2(x) ((x) << 2) 219169689Skan#define SHIFT1(x) ((x) << 1) 220169689Skan#define SHIFT0(x) ((x) << 0) 221169689Skan 222169689Skan/* 223169689Skan * PCI Configuration Space header 224169689Skan */ 225169689Skan#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 226169689Skan#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 227169689Skan#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ 228169689Skan#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ 229169689Skan#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ 230169689Skan#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ 231169689Skan#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ 232169689Skan#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ 233169689Skan#define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ 234169689Skan#define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ 23550397Sobrien 23650397Sobrien/* PCI Express Capability */ 23750397Sobrien#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ 23850397Sobrien#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ 23950397Sobrien#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ 24050397Sobrien#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ 24150397Sobrien#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ 24250397Sobrien#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ 24350397Sobrien#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ 24450397Sobrien#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ 24550397Sobrien#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ 24650397Sobrien 24750397Sobrien/* PCI Express Extended Capabilities */ 24850397Sobrien#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ 24950397Sobrien#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ 25050397Sobrien#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ 25150397Sobrien#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ 25250397Sobrien#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ 25350397Sobrien#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ 25450397Sobrien#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ 25550397Sobrien#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ 25650397Sobrien 257169689Skan/* PCI_OUR_REG_1 32 bit Our Register 1 */ 25850397Sobrien#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ 25950397Sobrien#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ 26050397Sobrien#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ 26150397Sobrien#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ 26250397Sobrien#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ 26350397Sobrien#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ 26450397Sobrien#define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ 26550397Sobrien#define PCI_EN_IO BIT_23 /* Mapping to I/O space */ 26650397Sobrien#define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ 26750397Sobrien /* 1 = Map Flash to memory */ 26850397Sobrien /* 0 = Disable addr. dec */ 26950397Sobrien#define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ 27050397Sobrien#define PCI_PAGE_16 (0L<<20)/* 16 k pages */ 27150397Sobrien#define PCI_PAGE_32K (1L<<20)/* 32 k pages */ 27250397Sobrien#define PCI_PAGE_64K (2L<<20)/* 64 k pages */ 27350397Sobrien#define PCI_PAGE_128K (3L<<20)/* 128 k pages */ 274169689Skan#define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ 275169689Skan#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ 276169689Skan#define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ 277169689Skan#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ 278169689Skan#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ 279117395Skan#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ 280117395Skan#define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ 28150397Sobrien#define PCI_BURST_DIS BIT_9 /* Burst Disable */ 28250397Sobrien#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ 283169689Skan#define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ 284169689Skan#define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ 28550397Sobrien#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ 286169689Skan 287169689Skan/* PCI_OUR_REG_2 32 bit Our Register 2 */ 288169689Skan#define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ 289169689Skan#define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ 290169689Skan#define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ 291169689Skan /* Bit 13..12: reserved */ 292169689Skan#define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ 293169689Skan#define PCI_PATCH_DIR_3 BIT_11 294169689Skan#define PCI_PATCH_DIR_2 BIT_10 295169689Skan#define PCI_PATCH_DIR_1 BIT_9 296117395Skan#define PCI_PATCH_DIR_0 BIT_8 297117395Skan#define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ 298117395Skan#define PCI_EXT_PATCH_3 BIT_7 299117395Skan#define PCI_EXT_PATCH_2 BIT_6 300117395Skan#define PCI_EXT_PATCH_1 BIT_5 301117395Skan#define PCI_EXT_PATCH_0 BIT_4 302169689Skan#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ 303117395Skan#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ 304117395Skan#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ 305117395Skan 306117395Skan/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ 307117395Skan#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ 308117395Skan#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ 30990075Sobrien#define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ 31090075Sobrien#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ 31190075Sobrien#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ 31290075Sobrien#define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ 31390075Sobrien#define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ 31490075Sobrien#define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ 31590075Sobrien 31650397Sobrien#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ 31790075Sobrien/* possible values for the speed field of the register */ 31890075Sobrien#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ 31990075Sobrien#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ 32090075Sobrien#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ 32190075Sobrien#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ 32290075Sobrien 32390075Sobrien/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 32450397Sobrien#define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ 325169689Skan#define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ 326169689Skan#define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ 327169689Skan#define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ 328169689Skan#define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ 329169689Skan#define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ 330169689Skan#define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ 331169689Skan#define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ 332169689Skan#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ 333169689Skan#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ 334132718Skan 335132718Skan/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 336132718Skan /* Bit 31..27: for A3 & later */ 337132718Skan#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ 338169689Skan#define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ 339132718Skan#define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ 340132718Skan#define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ 341132718Skan#define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ 342132718Skan#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27) 343132718Skan /* Bit 26..16: Release Clock on Event */ 344132718Skan#define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ 345132718Skan#define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ 346132718Skan#define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ 347132718Skan#define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ 348132718Skan#define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ 349132718Skan#define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ 350132718Skan#define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ 351132718Skan#define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ 352132718Skan#define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ 353132718Skan#define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ 354132718Skan#define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ 355132718Skan /* Bit 10.. 0: Mask for Gate Clock */ 356132718Skan#define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ 357132718Skan#define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ 358132718Skan#define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ 359132718Skan#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ 360132718Skan#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ 361132718Skan#define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ 362132718Skan#define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ 363132718Skan#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ 364132718Skan#define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ 365132718Skan#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ 366132718Skan#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ 367132718Skan 368132718Skan/* PCI_CFG_REG_1 32 bit Config Register 1 */ 369132718Skan#define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ 370132718Skan /* Bit 23..21: Release Clock on Event */ 371132718Skan#define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ 372132718Skan#define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ 373132718Skan#define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ 374132718Skan /* Bit 20..18: Gate Clock on Event */ 375132718Skan#define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ 376132718Skan#define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ 377132718Skan#define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ 378132718Skan#define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 379132718Skan#define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ 380132718Skan 381132718Skan#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ 382132718Skan#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ 383132718Skan#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ 384132718Skan 385132718Skan/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ 386132718Skan#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ 387132718Skan#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ 388132718Skan#define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ 389132718Skan#define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ 390132718Skan#define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ 391132718Skan#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ 392132718Skan#define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ 393132718Skan#define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ 394132718Skan#define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ 395132718Skan#define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ 396132718Skan#define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ 397132718Skan 398132718Skan#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) 399132718Skan 400132718Skan/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ 401132718Skan#define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ 402132718Skan#define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ 403132718Skan#define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ 404132718Skan#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ 405132718Skan#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ 406132718Skan 407132718Skan/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 408132718Skan#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ 409132718Skan#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ 410132718Skan#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ 411132718Skan#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ 412132718Skan#define PEX_COMP_TO BIT_14 /* Completion Timeout */ 413132718Skan#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ 414132718Skan#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ 415132718Skan#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ 416132718Skan 417132718Skan#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) 418132718Skan 419132718Skan/* Control Register File (Address Map) */ 420132718Skan 421132718Skan/* 422132718Skan * Bank 0 423132718Skan */ 424132718Skan#define B0_RAP 0x0000 /* 8 bit Register Address Port */ 425132718Skan#define B0_CTST 0x0004 /* 16 bit Control/Status register */ 426132718Skan#define B0_LED 0x0006 /* 8 Bit LED register */ 427132718Skan#define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ 428132718Skan#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ 429132718Skan#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ 430132718Skan#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ 431132718Skan#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ 432132718Skan#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ 433132718Skan 434132718Skan/* Special ISR registers (Yukon-2 only) */ 435132718Skan#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ 436132718Skan#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ 437132718Skan#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ 438132718Skan#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ 439132718Skan#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ 440132718Skan 441132718Skan/* 442132718Skan * Bank 1 443132718Skan * - completely empty (this is the RAP Block window) 444132718Skan * Note: if RAP = 1 this page is reserved 445132718Skan */ 446132718Skan 447132718Skan/* 448132718Skan * Bank 2 449132718Skan */ 450132718Skan/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ 451132718Skan#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ 452132718Skan#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ 453132718Skan#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ 454132718Skan#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ 455132718Skan#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ 456132718Skan#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ 457132718Skan#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ 458132718Skan#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ 459132718Skan#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ 460132718Skan#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ 461132718Skan#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ 462132718Skan#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ 463132718Skan#define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ 464132718Skan#define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ 465132718Skan#define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ 466132718Skan#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ 467132718Skan#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ 468132718Skan#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ 469132718Skan#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ 470132718Skan#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ 471132718Skan#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ 472132718Skan#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ 473132718Skan#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ 474132718Skan#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ 475132718Skan#define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ 476132718Skan#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ 477132718Skan#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ 478132718Skan#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ 479132718Skan#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ 480132718Skan 481132718Skan#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ 482132718Skan#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ 483132718Skan 484132718Skan/* 485132718Skan * Bank 3 486132718Skan */ 487132718Skan/* RAM Random Registers */ 488132718Skan#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ 489132718Skan#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ 490132718Skan#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ 491132718Skan 492132718Skan#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ 493132718Skan 494132718Skan/* RAM Interface Registers */ 49550397Sobrien/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ 496117395Skan/* 497169689Skan * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 498132718Skan * not usable in SW. Please notice these are NOT real timeouts, these are 499132718Skan * the number of qWords transferred continuously. 500132718Skan */ 501132718Skan#define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ 502169689Skan#define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ 503132718Skan#define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ 504169689Skan#define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ 505169689Skan#define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ 506132718Skan#define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ 507132718Skan#define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ 50850397Sobrien#define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ 50950397Sobrien#define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ 51050397Sobrien#define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ 51150397Sobrien#define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ 51250397Sobrien#define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ 51350397Sobrien#define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ 51450397Sobrien#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ 51550397Sobrien#define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ 51650397Sobrien 51750397Sobrien/* 51850397Sobrien * Bank 4 - 5 51950397Sobrien */ 52050397Sobrien/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 52150397Sobrien#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ 52250397Sobrien#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ 52350397Sobrien#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ 52450397Sobrien#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ 52550397Sobrien#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ 52650397Sobrien#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ 52750397Sobrien#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ 52850397Sobrien 52950397Sobrien#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) 53050397Sobrien 53150397Sobrien/* RSS key registers for Yukon-2 Family */ 532132718Skan#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ 533132718Skan/* RSS key register offsets */ 534169689Skan#define KEY_IDX_0 0 /* offset for location of KEY 0 */ 53550397Sobrien#define KEY_IDX_1 4 /* offset for location of KEY 1 */ 536132718Skan#define KEY_IDX_2 8 /* offset for location of KEY 2 */ 537169689Skan#define KEY_IDX_3 12 /* offset for location of KEY 3 */ 538132718Skan /* 0x0280 - 0x0292: MAC 2 */ 539132718Skan#define RSS_KEY_ADDR(Port, KeyIndex) \ 54050397Sobrien ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) 541132718Skan 542132718Skan/* 54350397Sobrien * Bank 8 - 15 544132718Skan */ 54550397Sobrien/* Receive and Transmit Queue Registers, use Q_ADDR() to access */ 546169689Skan#define B8_Q_REGS 0x0400 54750397Sobrien 548117395Skan/* Queue Register Offsets, use Q_ADDR() to access */ 549169689Skan#define Q_D 0x00 /* 8*32 bit Current Descriptor */ 550132718Skan#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ 551132718Skan#define Q_DONE 0x24 /* 16 bit Done Index */ 552169689Skan#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ 553169689Skan#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ 554117395Skan#define Q_BC 0x30 /* 32 bit Current Byte Counter */ 555132718Skan#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ 556117395Skan#define Q_F 0x38 /* 32 bit Flag Register */ 557169689Skan#define Q_T1 0x3c /* 32 bit Test Register 1 */ 558169689Skan#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ 559169689Skan#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ 560169689Skan#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ 561169689Skan#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ 562169689Skan#define Q_WM 0x40 /* 16 bit FIFO Watermark */ 563169689Skan#define Q_AL 0x42 /* 8 bit FIFO Alignment */ 564169689Skan#define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ 565169689Skan#define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ 566169689Skan#define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ 567169689Skan#define Q_RL 0x4a /* 8 bit FIFO Read Level */ 568169689Skan#define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ 569169689Skan#define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ 570169689Skan#define Q_WL 0x4e /* 8 bit FIFO Write Level */ 571169689Skan#define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ 572169689Skan 573169689Skan#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) 574169689Skan 575169689Skan/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */ 576169689Skan#define Y2_B8_PREF_REGS 0x0450 577169689Skan 578169689Skan#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ 579169689Skan#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ 580169689Skan#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ 581169689Skan#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ 582169689Skan#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ 583169689Skan#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ 584169689Skan#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ 585169689Skan#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ 586169689Skan#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ 587169689Skan#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ 588169689Skan 589169689Skan#define PREF_UNIT_MASK_IDX 0x0fff 590169689Skan 591169689Skan#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) 592169689Skan 593169689Skan/* 594169689Skan * Bank 16 - 23 595169689Skan */ 596169689Skan/* RAM Buffer Registers */ 597169689Skan#define B16_RAM_REGS 0x0800 598169689Skan 599169689Skan/* RAM Buffer Register Offsets, use RB_ADDR() to access */ 600169689Skan#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ 601169689Skan#define RB_END 0x04 /* 32 bit RAM Buffer End Address */ 602169689Skan#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ 60350397Sobrien#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ 60450397Sobrien#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ 60590075Sobrien#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ 60690075Sobrien#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ 60750397Sobrien#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ 60850397Sobrien#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ 60950397Sobrien#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ 610169689Skan#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ 61150397Sobrien#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ 61250397Sobrien#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ 61350397Sobrien 61450397Sobrien/* 615169689Skan * Bank 24 616169689Skan */ 617169689Skan/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 61850397Sobrien#define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ 61950397Sobrien#define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 62050397Sobrien#define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ 62150397Sobrien#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ 62250397Sobrien#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ 62350397Sobrien#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ 624169689Skan#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ 625169689Skan#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ 626169689Skan#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ 62750397Sobrien#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ 62890075Sobrien#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ 629169689Skan#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ 63050397Sobrien#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ 631169689Skan 632169689Skan/* 63350397Sobrien * Bank 25 63450397Sobrien */ 635169689Skan /* 0x0c80 - 0x0cbf: MAC 2 */ 636169689Skan /* 0x0cc0 - 0x0cff: reserved */ 637169689Skan 638169689Skan/* 639169689Skan * Bank 26 64050397Sobrien */ 64150397Sobrien/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 64250397Sobrien#define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ 643169689Skan#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 644169689Skan#define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ 64550397Sobrien#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ 64690075Sobrien#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ 64750397Sobrien#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ 648117395Skan#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ 64950397Sobrien#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ 650117395Skan#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ 651117395Skan#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ 652117395Skan 653117395Skan/* 654117395Skan * Bank 27 65550397Sobrien */ 656117395Skan /* 0x0d80 - 0x0dbf: MAC 2 */ 657117395Skan /* 0x0daa - 0x0dff: reserved */ 65850397Sobrien 65950397Sobrien/* 66050397Sobrien * Bank 28 661169689Skan */ 662117395Skan/* Descriptor Poll Timer Registers */ 663117395Skan#define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ 664132718Skan#define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ 66550397Sobrien#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ 66650397Sobrien#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ 66750397Sobrien/* Time Stamp Timer Registers (YUKON only) */ 66850397Sobrien#define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ 66990075Sobrien#define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ 670169689Skan#define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ 67150397Sobrien/* Polling Unit Registers (Yukon-2 only) */ 67250397Sobrien#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ 673117395Skan#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ 674117395Skan#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ 675117395Skan#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ 676117395Skan/* ASF Subsystem Registers (Yukon-2 only) */ 67790075Sobrien#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ 678117395Skan#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ 67950397Sobrien#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ 680169689Skan#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ 681169689Skan#define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ 682169689Skan#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ 68390075Sobrien#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ 684169689Skan#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ 685169689Skan#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ 686169689Skan#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ 687117395Skan 688169689Skan/* 689169689Skan * Bank 29 690169689Skan */ 691169689Skan 692117395Skan/* Status BMU Registers (Yukon-2 only)*/ 693169689Skan#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ 694169689Skan#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ 69590075Sobrien#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ 696117395Skan#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ 697169689Skan#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ 698169689Skan#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ 699169689Skan#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ 700169689Skan#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ 701169689Skan#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ 702169689Skan#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ 703169689Skan/* FIFO Control/Status Registers (Yukon-2 only)*/ 704169689Skan#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ 705117395Skan#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ 706117395Skan#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ 707117395Skan#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ 70850397Sobrien#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ 709132718Skan#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ 71050397Sobrien#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ 71150397Sobrien/* Level and ISR Timer Registers (Yukon-2 only)*/ 71250397Sobrien#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ 71350397Sobrien#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ 71450397Sobrien#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ 71550397Sobrien#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ 716132718Skan#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ 71750397Sobrien#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ 71850397Sobrien#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ 71950397Sobrien#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ 72090075Sobrien#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ 72150397Sobrien#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ 72250397Sobrien#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ 72390075Sobrien#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ 72450397Sobrien 72590075Sobrien#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ 72690075Sobrien#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ 72750397Sobrien#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ 72850397Sobrien#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ 72950397Sobrien 73050397Sobrien/* 731169689Skan * Bank 30 732169689Skan */ 73350397Sobrien/* GMAC and GPHY Control Registers (YUKON only) */ 734169689Skan#define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ 735169689Skan#define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ 736169689Skan#define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ 737169689Skan#define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ 73850397Sobrien#define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ 739169689Skan 740169689Skan/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 741169689Skan 742169689Skan#define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ 743169689Skan 744169689Skan#define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ 745169689Skan#define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ 746169689Skan#define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ 747169689Skan#define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ 748169689Skan#define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ 749169689Skan#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ 75050397Sobrien#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ 751169689Skan#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ 752169689Skan 753169689Skan/* WOL Pattern Length Registers (YUKON only) */ 754169689Skan 755169689Skan#define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ 756169689Skan#define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ 757169689Skan 758169689Skan/* WOL Pattern Counter Registers (YUKON only) */ 759169689Skan 760169689Skan#define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ 761169689Skan#define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ 762169689Skan 763169689Skan/* 764169689Skan * Bank 32 - 33 765169689Skan */ 766169689Skan#define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ 767169689Skan#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ 768169689Skan 769169689Skan/* offset to configuration space on Yukon-2 */ 770169689Skan#define Y2_CFG_SPC 0x1c00 771169689Skan#define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ 772169689Skan#define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ 773169689Skan 774169689Skan/* 775169689Skan * Control Register Bit Definitions: 776169689Skan */ 777169689Skan/* B0_CTST 24 bit Control/Status register */ 778169689Skan#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ 779169689Skan#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ 780169689Skan#define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ 781169689Skan#define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ 782169689Skan#define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ 783169689Skan#define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ 78450397Sobrien#define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ 785169689Skan#define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ 786169689Skan#define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ 787169689Skan#define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ 788169689Skan#define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ 789169689Skan#define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ 790169689Skan#define CS_STOP_DONE BIT_5 /* Stop Master is finished */ 79150397Sobrien#define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ 792169689Skan#define CS_MRST_CLR BIT_3 /* Clear Master Reset */ 79350397Sobrien#define CS_MRST_SET BIT_2 /* Set Master Reset */ 79490075Sobrien#define CS_RST_CLR BIT_1 /* Clear Software Reset */ 79590075Sobrien#define CS_RST_SET BIT_0 /* Set Software Reset */ 79650397Sobrien 79750397Sobrien#define LED_STAT_ON BIT_1 /* Status LED On */ 79890075Sobrien#define LED_STAT_OFF BIT_0 /* Status LED Off */ 79950397Sobrien 80050397Sobrien/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 80150397Sobrien#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ 802132718Skan#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ 80350397Sobrien#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ 80450397Sobrien#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ 80550397Sobrien#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ 80650397Sobrien#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ 80750397Sobrien#define PC_VCC_ON BIT_1 /* Switch VCC On */ 80850397Sobrien#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ 80950397Sobrien 81050397Sobrien/* B0_ISRC 32 bit Interrupt Source Register */ 81150397Sobrien/* B0_IMSK 32 bit Interrupt Mask Register */ 81250397Sobrien/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ 81350397Sobrien/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 81450397Sobrien/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 81550397Sobrien/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 816132718Skan/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 81750397Sobrien/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 81890075Sobrien#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) 81990075Sobrien#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ 82050397Sobrien#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ 82150397Sobrien#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ 82290075Sobrien#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ 82350397Sobrien#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ 824132718Skan#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ 825132718Skan#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ 826132718Skan#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ 827132718Skan#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ 82890075Sobrien#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ 82950397Sobrien#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ 830132718Skan#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ 83150397Sobrien#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ 83250397Sobrien#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ 83350397Sobrien#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ 834169689Skan#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ 835169689Skan#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ 836169689Skan 837169689Skan#define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ 838169689Skan 839169689Skan#define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ 840169689Skan 841169689Skan#define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ 842169689Skan 843169689Skan#define Y2_IS_PORT_A \ 844169689Skan (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) 845169689Skan#define Y2_IS_PORT_B \ 846169689Skan (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) 847169689Skan 848169689Skan/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ 849169689Skan/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ 850169689Skan/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 851169689Skan#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ 852169689Skan#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ 853169689Skan#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ 854169689Skan#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ 855169689Skan#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ 856169689Skan#define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ 857169689Skan#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ 85890075Sobrien#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ 85950397Sobrien#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ 86050397Sobrien#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ 861132718Skan#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ 86250397Sobrien#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ 86390075Sobrien#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ 86490075Sobrien#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ 86590075Sobrien#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ 86650397Sobrien#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ 86790075Sobrien#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ 868169689Skan#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ 86950397Sobrien 87050397Sobrien#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ 87150397Sobrien Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) 87250397Sobrien#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ 87350397Sobrien Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) 87450397Sobrien 87550397Sobrien#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ 87650397Sobrien Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ 87750397Sobrien Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) 87850397Sobrien 87950397Sobrien/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 88050397Sobrien#define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ 88150397Sobrien#define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ 88250397Sobrien#define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ 88350397Sobrien 88450397Sobrien/* B2_CHIP_ID 8 bit Chip Identification Number */ 88550397Sobrien#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ 88650397Sobrien#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ 88750397Sobrien#define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 88850397Sobrien#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ 88950397Sobrien#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ 89050397Sobrien#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ 89150397Sobrien#define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ 89250397Sobrien#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ 89350397Sobrien#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ 89450397Sobrien#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ 89590075Sobrien#define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ 89650397Sobrien#define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ 89750397Sobrien 89850397Sobrien#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ 89950397Sobrien#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ 90050397Sobrien#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ 90150397Sobrien#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ 90250397Sobrien 90350397Sobrien#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ 90450397Sobrien#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ 90550397Sobrien#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ 90650397Sobrien 90750397Sobrien#define CHIP_REV_YU_EC_U_A0 1 90850397Sobrien#define CHIP_REV_YU_EC_U_A1 2 90990075Sobrien 91050397Sobrien#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ 91150397Sobrien 91250397Sobrien#define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ 91350397Sobrien#define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ 91450397Sobrien 91550397Sobrien/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 91650397Sobrien#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ 91750397Sobrien#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ 91850397Sobrien#define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ 919132718Skan#define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ 92050397Sobrien#define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ 92150397Sobrien#define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ 92250397Sobrien#define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ 92350397Sobrien#define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ 92450397Sobrien 92550397Sobrien/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 92650397Sobrien#define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ 92750397Sobrien#define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ 92850397Sobrien#define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ 92950397Sobrien 93050397Sobrien#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 93150397Sobrien#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 93250397Sobrien 93350397Sobrien/* B2_E_3 8 bit lower 4 bits used for HW self test result */ 93450397Sobrien#define B2_E3_RES_MASK 0x0f 93550397Sobrien 93650397Sobrien/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ 937132718Skan/* Yukon-EC/FE */ 93850397Sobrien#define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ 93950397Sobrien#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) 94050397Sobrien/* Yukon-2 */ 941169689Skan#define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ 942169689Skan#define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ 943169689Skan#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) 94450397Sobrien#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) 94550397Sobrien#define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ 94650397Sobrien#define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ 94750397Sobrien 94850397Sobrien/* B2_TI_CTRL 8 bit Timer control */ 94990075Sobrien/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 95090075Sobrien#define TIM_START BIT_2 /* Start Timer */ 95150397Sobrien#define TIM_STOP BIT_1 /* Stop Timer */ 95290075Sobrien#define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ 95350397Sobrien 954169689Skan/* B2_TI_TEST 8 Bit Timer Test */ 955169689Skan/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 95650397Sobrien/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 95750397Sobrien#define TIM_T_ON BIT_2 /* Test mode on */ 958169689Skan#define TIM_T_OFF BIT_1 /* Test mode off */ 959169689Skan#define TIM_T_STEP BIT_0 /* Test step */ 960169689Skan 961169689Skan/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ 962169689Skan/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ 963169689Skan#define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ 964169689Skan 965169689Skan/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 966169689Skan#define DPT_START BIT_1 /* Start Descriptor Poll Timer */ 967169689Skan#define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ 96890075Sobrien 96990075Sobrien/* B2_TST_CTRL1 8 bit Test Control Register 1 */ 97050397Sobrien#define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ 97190075Sobrien#define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ 972132718Skan#define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ 97350397Sobrien#define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ 974169689Skan#define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ 97590075Sobrien#define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ 97690075Sobrien#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ 97750397Sobrien#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ 978169689Skan 979169689Skan/* B2_GP_IO */ 98050397Sobrien#define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ 981169689Skan#define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ 982169689Skan 98390075Sobrien#define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ 984169689Skan#define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ 98550397Sobrien#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ 986169689Skan#define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ 987169689Skan#define GLB_GPIO_TEST_SEL_BASE BIT_11 988169689Skan#define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ 989169689Skan#define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ 990169689Skan 991169689Skan/* B2_I2C_CTRL 32 bit I2C HW Control Register */ 992169689Skan#define I2C_FLAG BIT_31 /* Start read/write if WR */ 993169689Skan#define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ 99450397Sobrien#define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ 995169689Skan#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ 996169689Skan#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ 997169689Skan#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ 998169689Skan#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ 999169689Skan#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ 1000169689Skan#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ 1001169689Skan#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ 1002169689Skan#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ 1003169689Skan#define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ 1004169689Skan#define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ 1005169689Skan#define I2C_STOP BIT_0 /* Interrupt I2C transfer */ 1006169689Skan 1007169689Skan/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ 1008169689Skan#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ 100990075Sobrien 1010169689Skan/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ 1011169689Skan#define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ 1012169689Skan#define I2C_DATA BIT_1 /* I2C Data Port */ 101350397Sobrien#define I2C_CLK BIT_0 /* I2C Clock Port */ 101450397Sobrien 101590075Sobrien/* I2C Address */ 101690075Sobrien#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ 101790075Sobrien 101890075Sobrien 1019132718Skan/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ 102090075Sobrien#define BSC_START BIT_1 /* Start Blink Source Counter */ 102190075Sobrien#define BSC_STOP BIT_0 /* Stop Blink Source Counter */ 1022169689Skan 1023169689Skan/* B2_BSC_STAT 8 bit Blink Source Counter Status */ 102490075Sobrien#define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ 102590075Sobrien 102690075Sobrien/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ 102790075Sobrien#define BSC_T_ON BIT_2 /* Test mode on */ 102890075Sobrien#define BSC_T_OFF BIT_1 /* Test mode off */ 1029169689Skan#define BSC_T_STEP BIT_0 /* Test step */ 1030169689Skan 1031169689Skan/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 1032169689Skan#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ 103390075Sobrien#define PEX_DB_ACCESS BIT_30 /* Access to debug register */ 103490075Sobrien 103590075Sobrien/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 1036117395Skan#define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ 1037117395Skan 1038117395Skan/* RAM Interface Registers */ 1039117395Skan/* B3_RI_CTRL 16 bit RAM Interface Control Register */ 1040117395Skan#define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ 1041117395Skan#define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ 1042117395Skan#define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ 1043117395Skan#define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ 1044117395Skan 1045132718Skan#define MSK_RI_TO_53 36 /* RAM interface timeout */ 1046117395Skan 1047169689Skan/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 1048169689Skan/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 1049117395Skan/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 1050117395Skan/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 1051117395Skan/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 1052117395Skan#define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ 1053117395Skan 1054117395Skan/* TXA_CTRL 8 bit Tx Arbiter Control Register */ 1055117395Skan#define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ 1056117395Skan#define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ 1057132718Skan#define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ 1058117395Skan#define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ 1059117395Skan#define TXA_START_RC BIT_3 /* Start sync Rate Control */ 1060117395Skan#define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ 1061117395Skan#define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ 1062117395Skan#define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ 1063117395Skan 1064169689Skan/* TXA_TEST 8 bit Tx Arbiter Test Register */ 1065117395Skan#define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ 1066117395Skan#define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ 1067117395Skan#define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ 1068117395Skan#define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ 1069169689Skan#define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ 1070117395Skan#define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ 1071117395Skan 1072117395Skan/* TXA_STAT 8 bit Tx Arbiter Status Register */ 1073169689Skan#define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ 1074169689Skan 1075169689Skan/* Q_BC 32 bit Current Byte Counter */ 1076169689Skan#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ 1077169689Skan 1078117395Skan/* Rx BMU Control / Status Registers (Yukon-2) */ 1079169689Skan#define BMU_IDLE BIT_31 /* BMU Idle State */ 1080169689Skan#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ 1081169689Skan#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ 1082169689Skan#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ 1083169689Skan#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ 1084169689Skan#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ 1085169689Skan#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ 1086169689Skan#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ 1087169689Skan#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ 108890075Sobrien#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ 108990075Sobrien#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ 109090075Sobrien#define BMU_START BIT_8 /* Start Rx/Tx Queue */ 109190075Sobrien#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ 1092132718Skan#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ 109390075Sobrien#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ 109490075Sobrien#define BMU_FIFO_RST BIT_4 /* Reset FIFO */ 109590075Sobrien#define BMU_OP_ON BIT_3 /* BMU Operational On */ 109690075Sobrien#define BMU_OP_OFF BIT_2 /* BMU Operational Off */ 109790075Sobrien#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ 109850397Sobrien#define BMU_RST_SET BIT_0 /* Set BMU Reset */ 109990075Sobrien 110090075Sobrien#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) 110150397Sobrien#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \ 110250397Sobrien BMU_START | BMU_FIFO_ENA | BMU_OP_ON) 1103132718Skan 110450397Sobrien/* Tx BMU Control / Status Registers (Yukon-2) */ 110590075Sobrien /* Bit 31: same as for Rx */ 110690075Sobrien#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ 110790075Sobrien#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ 110890075Sobrien#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ 110950397Sobrien /* Bit 10..0: same as for Rx */ 111090075Sobrien 111150397Sobrien/* Q_F 32 bit Flag Register */ 111290075Sobrien#define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ 111390075Sobrien#define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ 1114169689Skan#define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ 111550397Sobrien#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ 111650397Sobrien#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ 1117117395Skan#define F_WM_REACHED BIT_25 /* Watermark reached */ 1118117395Skan#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ 1119132718Skan#define F_FIFO_LEVEL (0x1f<<16) 1120117395Skan /* Bit 23..16: # of Qwords in FIFO */ 1121169689Skan#define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ 1122169689Skan 1123169689Skan/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ 1124117395Skan/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ 1125169689Skan#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ 1126169689Skan#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ 1127169689Skan#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ 1128169689Skan#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ 1129169689Skan 1130117395Skan/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 1131117395Skan/* RB_START 32 bit RAM Buffer Start Address */ 113252284Sobrien/* RB_END 32 bit RAM Buffer End Address */ 113352284Sobrien/* RB_WP 32 bit RAM Buffer Write Pointer */ 113452284Sobrien/* RB_RP 32 bit RAM Buffer Read Pointer */ 113550397Sobrien/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 113690075Sobrien/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 1137132718Skan/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 1138132718Skan/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 1139132718Skan/* RB_PC 32 bit RAM Buffer Packet Counter */ 114050397Sobrien/* RB_LEV 32 bit RAM Buffer Level Register */ 1141132718Skan#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 1142169689Skan 114350397Sobrien/* RB_TST2 8 bit RAM Buffer Test Register 2 */ 114450397Sobrien#define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ 1145132718Skan#define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ 114650397Sobrien#define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ 1147169689Skan#define RB_PC_INC BIT_0 /* Packet Counter Increment */ 114850397Sobrien 1149117395Skan/* RB_TST1 8 bit RAM Buffer Test Register 1 */ 1150117395Skan#define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ 1151117395Skan#define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ 1152132718Skan#define RB_WP_INC BIT_4 /* Write Pointer Increment */ 1153169689Skan#define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ 1154117395Skan#define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ 1155117395Skan#define RB_RP_INC BIT_0 /* Read Pointer Increment */ 1156117395Skan 1157117395Skan/* RB_CTRL 8 bit RAM Buffer Control Register */ 1158117395Skan#define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ 1159117395Skan#define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ 1160117395Skan#define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ 116150397Sobrien#define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ 1162169689Skan#define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ 1163169689Skan#define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ 1164169689Skan 1165169689Skan/* RAM Buffer High Pause Threshold values */ 1166169689Skan#define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ 116750397Sobrien#define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ 1168169689Skan#define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ 1169169689Skan 1170169689Skan/* Threshold values for Yukon-EC Ultra */ 1171169689Skan#define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ 1172169689Skan#define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ 1173169689Skan#define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ 1174169689Skan#define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ 1175169689Skan#define MSK_ECU_JUMBO_WM 0x01 1176169689Skan 1177169689Skan#define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ 1178169689Skan#define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ 1179169689Skan/* performance sensitive drivers should set this define to 0x80 */ 1180169689Skan#define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ 118150397Sobrien 1182169689Skan/* Receive and Transmit Queues */ 1183169689Skan#define Q_R1 0x0000 /* Receive Queue 1 */ 1184169689Skan#define Q_R2 0x0080 /* Receive Queue 2 */ 1185132718Skan#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ 1186169689Skan#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ 1187169689Skan#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ 1188132718Skan#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ 118950397Sobrien 119050397Sobrien#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ 1191169689Skan#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ 119250397Sobrien#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ 1193169689Skan#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ 119450397Sobrien 1195169689Skan#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) 1196169689Skan 1197169689Skan/* Minimum RAM Buffer Rx Queue Size */ 1198169689Skan#define MSK_MIN_RXQ_SIZE 10 1199169689Skan/* Minimum RAM Buffer Tx Queue Size */ 1200169689Skan#define MSK_MIN_TXQ_SIZE 10 1201169689Skan/* Percentage of queue size from whole memory. 80 % for receive */ 1202169689Skan#define MSK_RAM_QUOTA_RX 80 120350397Sobrien 1204169689Skan/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1205169689Skan#define WOL_CTL_LINK_CHG_OCC BIT_15 1206169689Skan#define WOL_CTL_MAGIC_PKT_OCC BIT_14 1207169689Skan#define WOL_CTL_PATTERN_OCC BIT_13 1208169689Skan#define WOL_CTL_CLEAR_RESULT BIT_12 1209169689Skan#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 1210169689Skan#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 121150397Sobrien#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 121250397Sobrien#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 121390075Sobrien#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 121452284Sobrien#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 121552284Sobrien#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 121652284Sobrien#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 121752284Sobrien#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 1218132718Skan#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 1219117395Skan#define WOL_CTL_ENA_PATTERN_UNIT BIT_1 1220117395Skan#define WOL_CTL_DIS_PATTERN_UNIT BIT_0 122152284Sobrien 1222132718Skan#define WOL_CTL_DEFAULT \ 1223169689Skan (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1224169689Skan WOL_CTL_DIS_PME_ON_PATTERN | \ 122552284Sobrien WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1226169689Skan WOL_CTL_DIS_LINK_CHG_UNIT | \ 1227132718Skan WOL_CTL_DIS_PATTERN_UNIT | \ 122850397Sobrien WOL_CTL_DIS_MAGIC_PKT_UNIT) 122950397Sobrien 123090075Sobrien/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 123150397Sobrien#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) 123250397Sobrien 123350397Sobrien/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ 123450397Sobrien#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ 123550397Sobrien#define WOL_PATT_MATCH_PME_ALL 0x7f 123650397Sobrien 1237132718Skan 123850397Sobrien/* 123950397Sobrien * Marvel-PHY Registers, indirect addressed over GMAC 124050397Sobrien */ 1241169689Skan#define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 124250397Sobrien#define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 124350397Sobrien#define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 1244169689Skan#define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 1245169689Skan#define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 124650397Sobrien#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 124750397Sobrien#define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 124850397Sobrien#define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 124950397Sobrien#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 125050397Sobrien /* Marvel-specific registers */ 125150397Sobrien#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 1252169689Skan#define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 1253169689Skan /* 0x0b - 0x0e: reserved */ 1254169689Skan#define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 1255169689Skan#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ 1256169689Skan#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ 1257169689Skan#define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 1258169689Skan#define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 1259169689Skan#define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 1260169689Skan#define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 1261169689Skan#define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 1262169689Skan#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ 126390075Sobrien#define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 1264169689Skan#define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 126550397Sobrien#define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 126650397Sobrien#define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 126750397Sobrien#define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 126850397Sobrien#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ 126950397Sobrien#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ 127050397Sobrien 127150397Sobrien/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 127250397Sobrien#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ 127350397Sobrien#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ 127450397Sobrien#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ 127550397Sobrien#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ 127650397Sobrien#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ 127750397Sobrien 127850397Sobrien#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 127950397Sobrien#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 128050397Sobrien#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ 128150397Sobrien#define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 128250397Sobrien#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ 1283132718Skan#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ 128450397Sobrien#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 128550397Sobrien#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 128650397Sobrien#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ 1287169689Skan#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ 128850397Sobrien 128950397Sobrien#define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 129050397Sobrien#define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 129150397Sobrien#define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 129250397Sobrien 1293169689Skan#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 1294169689Skan#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ 129550397Sobrien#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 129650397Sobrien#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ 129750397Sobrien#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 129850397Sobrien#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 129950397Sobrien#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ 130050397Sobrien#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 1301169689Skan 1302169689Skan#define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 1303169689Skan#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 1304169689Skan#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ 1305169689Skan 1306169689Skan/* different Marvell PHY Ids */ 1307169689Skan#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ 1308169689Skan 1309169689Skan#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ 1310169689Skan#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ 1311169689Skan#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ 131250397Sobrien#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ 131350397Sobrien#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ 131450397Sobrien#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ 131550397Sobrien 131650397Sobrien/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 131750397Sobrien#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 131850397Sobrien#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 131950397Sobrien#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 132050397Sobrien#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 132150397Sobrien#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 132250397Sobrien#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1323169689Skan#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 1324169689Skan 132550397Sobrien/***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 132690075Sobrien/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 1327169689Skan#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 132850397Sobrien#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 1329169689Skan#define PHY_M_AN_RF BIT_13 /* Remote Fault */ 1330169689Skan#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 1331169689Skan#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 1332169689Skan#define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ 133350397Sobrien#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 1334169689Skan#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 1335169689Skan#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 133650397Sobrien#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 1337169689Skan#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ 1338169689Skan 1339169689Skan/* special defines for FIBER (88E1011S only) */ 1340169689Skan#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 1341169689Skan#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 1342169689Skan#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 1343169689Skan#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 1344169689Skan 1345169689Skan/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1346169689Skan#define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 1347169689Skan#define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 1348169689Skan#define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 1349169689Skan#define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 1350169689Skan 1351169689Skan/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1352169689Skan#define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1353169689Skan#define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ 1354169689Skan#define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ 1355169689Skan#define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ 1356169689Skan#define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ 1357169689Skan#define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ 1358169689Skan 1359169689Skan/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 136050397Sobrien#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 136150397Sobrien#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 136290075Sobrien#define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ 136350397Sobrien#define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ 136490075Sobrien#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 1365132718Skan#define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ 136650397Sobrien#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 136790075Sobrien#define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ 136890075Sobrien#define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ 1369169689Skan#define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ 137090075Sobrien#define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ 137190075Sobrien#define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ 137290075Sobrien 137390075Sobrien#define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 137490075Sobrien#define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 137590075Sobrien 137690075Sobrien#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) 137790075Sobrien 137890075Sobrien#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 137990075Sobrien#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 138090075Sobrien#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 1381132718Skan 138290075Sobrien/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 138350397Sobrien#define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ 138450397Sobrien#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ 138550397Sobrien#define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ 138650397Sobrien /* !!! Errata in spec. (1 = disable) */ 138750397Sobrien 138850397Sobrien#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) 138950397Sobrien /* 000=1x; 001=2x; 010=3x; 011=4x */ 139050397Sobrien /* 100=5x; 101=6x; 110=7x; 111=8x */ 139150397Sobrien 139250397Sobrien/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 139350397Sobrien#define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ 1394169689Skan#define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ 139550397Sobrien#define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ 139650397Sobrien#define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ 139750397Sobrien#define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ 139850397Sobrien#define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ 1399169689Skan#define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ 140050397Sobrien#define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ 140150397Sobrien#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ 140250397Sobrien 140350397Sobrien/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 140490075Sobrien#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 140590075Sobrien#define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ 140650397Sobrien#define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ 140790075Sobrien#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 1408132718Skan#define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ 140950397Sobrien#define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ 141050397Sobrien#define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ 141150397Sobrien#define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ 141250397Sobrien#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ 141350397Sobrien#define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ 141450397Sobrien#define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ 141550397Sobrien#define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ 141650397Sobrien#define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ 141790075Sobrien#define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ 141850397Sobrien#define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ 141950397Sobrien#define PHY_M_PS_JABBER BIT_0 /* Jabber */ 142050397Sobrien 142150397Sobrien#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 142290075Sobrien 1423169689Skan/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 142450397Sobrien#define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ 142550397Sobrien#define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 142650397Sobrien 142750397Sobrien/***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 142850397Sobrien/***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 142990075Sobrien#define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ 143090075Sobrien#define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ 143190075Sobrien#define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ 143250397Sobrien#define PHY_M_IS_AN_PR BIT_12 /* Page Received */ 143390075Sobrien#define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ 1434132718Skan#define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ 143550397Sobrien#define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ 143650397Sobrien#define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ 143750397Sobrien#define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ 143890075Sobrien#define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ 143950397Sobrien#define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ 144090075Sobrien#define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ 144190075Sobrien#define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ 144250397Sobrien#define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ 144350397Sobrien#define PHY_M_IS_JABBER BIT_0 /* Jabber */ 144450397Sobrien 144550397Sobrien#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 144650397Sobrien PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 144750397Sobrien 144850397Sobrien/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 144950397Sobrien#define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ 1450169689Skan#define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ 145150397Sobrien#define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ 145250397Sobrien#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ 145350397Sobrien /* (88E1011 only) */ 145450397Sobrien#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ 145550397Sobrien /* (88E1011 only) */ 1456169689Skan#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ 145750397Sobrien /* (88E1111 only) */ 145850397Sobrien#define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ 145950397Sobrien /* !!! Errata in spec. (1 = disable) */ 146050397Sobrien#define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ 146150397Sobrien#define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 1462169689Skan#define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ 146390075Sobrien#define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ 146450397Sobrien#define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ 146550397Sobrien#define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ 146650397Sobrien 1467169689Skan#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) 1468169689Skan /* 00=1x; 01=2x; 10=3x; 11=4x */ 1469169689Skan#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) 147050397Sobrien /* 00=dis; 01=1x; 10=2x; 11=3x */ 1471169689Skan#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) 1472169689Skan /* 01X=0; 110=2.5; 111=25 (MHz) */ 1473169689Skan 147450397Sobrien#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) 147550397Sobrien /* 000=1x; 001=2x; 010=3x; 011=4x */ 147650397Sobrien /* 100=5x; 101=6x; 110=7x; 111=8x */ 147750397Sobrien#define MAC_TX_CLK_0_MHZ 2 147850397Sobrien#define MAC_TX_CLK_2_5_MHZ 6 147950397Sobrien#define MAC_TX_CLK_25_MHZ 7 148050397Sobrien 148150397Sobrien/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 148250397Sobrien#define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ 148350397Sobrien#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 148450397Sobrien#define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ 1485169689Skan#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 148650397Sobrien#define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ 148750397Sobrien#define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ 148850397Sobrien#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ 148950397Sobrien /* (88E1111 only) */ 149050397Sobrien#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 1491169689Skan /* (88E1011 only) */ 149250397Sobrien#define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ 1493169689Skan#define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ 149450397Sobrien#define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ 149550397Sobrien#define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ 149650397Sobrien#define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ 149790075Sobrien 149850397Sobrien#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) 149950397Sobrien 150050397Sobrien#define PULS_NO_STR 0 /* no pulse stretching */ 150150397Sobrien#define PULS_21MS 1 /* 21 ms to 42 ms */ 150250397Sobrien#define PULS_42MS 2 /* 42 ms to 84 ms */ 150390075Sobrien#define PULS_84MS 3 /* 84 ms to 170 ms */ 1504132718Skan#define PULS_170MS 4 /* 170 ms to 340 ms */ 150550397Sobrien#define PULS_340MS 5 /* 340 ms to 670 ms */ 150650397Sobrien#define PULS_670MS 6 /* 670 ms to 1.3 s */ 150750397Sobrien#define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 150850397Sobrien 150950397Sobrien#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) 151050397Sobrien 151150397Sobrien#define BLINK_42MS 0 /* 42 ms */ 151250397Sobrien#define BLINK_84MS 1 /* 84 ms */ 151350397Sobrien#define BLINK_170MS 2 /* 170 ms */ 151450397Sobrien#define BLINK_340MS 3 /* 340 ms */ 1515169689Skan#define BLINK_670MS 4 /* 670 ms */ 151650397Sobrien 151750397Sobrien/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 151850397Sobrien#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ 151950397Sobrien#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 152050397Sobrien#define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 1521169689Skan#define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 152250397Sobrien#define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 152350397Sobrien#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 152450397Sobrien#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 1525169689Skan 1526169689Skan#define MO_LED_NORM 0 1527169689Skan#define MO_LED_BLINK 1 152850397Sobrien#define MO_LED_OFF 2 1529169689Skan#define MO_LED_ON 3 1530169689Skan 1531169689Skan/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 153250397Sobrien#define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ 153350397Sobrien#define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ 1534169689Skan#define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ 153550397Sobrien#define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ 153650397Sobrien#define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 153750397Sobrien 153850397Sobrien/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 153950397Sobrien#define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ 154050397Sobrien#define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ 1541169689Skan#define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ 154250397Sobrien#define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ 1543169689Skan#define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ 154450397Sobrien#define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ 154550397Sobrien#define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ 154650397Sobrien /* (88E1111 only) */ 154750397Sobrien#define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ 154850397Sobrien#define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ 154990075Sobrien#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 155050397Sobrien 155150397Sobrien/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 155290075Sobrien#define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ 155350397Sobrien#define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ 155450397Sobrien /* (88E1111 only) */ 155590075Sobrien#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ 1556132718Skan#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ 155750397Sobrien /* (88E1111 only) */ 155850397Sobrien#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ 155950397Sobrien 156050397Sobrien/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 156190075Sobrien#define CABD_STAT_NORMAL 0 156290075Sobrien#define CABD_STAT_SHORT 1 156350397Sobrien#define CABD_STAT_OPEN 2 156450397Sobrien#define CABD_STAT_FAIL 3 156550397Sobrien 156650397Sobrien/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 156750397Sobrien/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 156850397Sobrien#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ 156950397Sobrien#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ 157050397Sobrien#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ 157150397Sobrien 157250397Sobrien#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) 1573169689Skan#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) 157450397Sobrien#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) 157550397Sobrien 157650397Sobrien#define LED_PAR_CTRL_COLX 0x00 157750397Sobrien#define LED_PAR_CTRL_ERROR 0x01 157850397Sobrien#define LED_PAR_CTRL_DUPLEX 0x02 1579169689Skan#define LED_PAR_CTRL_DP_COL 0x03 158050397Sobrien#define LED_PAR_CTRL_SPEED 0x04 158150397Sobrien#define LED_PAR_CTRL_LINK 0x05 158250397Sobrien#define LED_PAR_CTRL_TX 0x06 158350397Sobrien#define LED_PAR_CTRL_RX 0x07 158490075Sobrien#define LED_PAR_CTRL_ACT 0x08 158550397Sobrien#define LED_PAR_CTRL_LNK_RX 0x09 1586132718Skan#define LED_PAR_CTRL_LNK_AC 0x0a 1587132718Skan#define LED_PAR_CTRL_ACT_BL 0x0b 1588132718Skan#define LED_PAR_CTRL_TX_BL 0x0c 1589132718Skan#define LED_PAR_CTRL_RX_BL 0x0d 1590132718Skan#define LED_PAR_CTRL_COL_BL 0x0e 1591132718Skan#define LED_PAR_CTRL_INACT 0x0f 1592132718Skan 1593132718Skan/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1594132718Skan#define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ 1595132718Skan#define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ 1596132718Skan#define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ 1597132718Skan 1598132718Skan/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1599169689Skan/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1600132718Skan#define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ 1601132718Skan#define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ 1602132718Skan#define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ 1603132718Skan 1604132718Skan/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1605132718Skan#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ 1606132718Skan#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ 1607132718Skan#define PHY_M_MAC_MD_COPPER 5 /* Copper only */ 1608132718Skan#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ 1609132718Skan#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) 1610132718Skan 161190075Sobrien/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 161250397Sobrien#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ 161350397Sobrien#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1614169689Skan#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 161550397Sobrien#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 161650397Sobrien 161750397Sobrien#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) 1618169689Skan#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) 161950397Sobrien#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) 162050397Sobrien#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) 162150397Sobrien 1622169689Skan/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ 1623169689Skan#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1624169689Skan#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1625169689Skan#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1626169689Skan#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1627169689Skan#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1628169689Skan#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1629169689Skan 1630169689Skan#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) 1631169689Skan#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) 1632169689Skan#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) 1633169689Skan#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) 1634169689Skan#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) 1635169689Skan#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) 1636169689Skan 1637169689Skan/* 1638169689Skan * GMAC registers 1639169689Skan * 1640169689Skan * The GMAC registers are 16 or 32 bits wide. 1641169689Skan * The GMACs host processor interface is 16 bits wide, 164250397Sobrien * therefore ALL registers will be addressed with 16 bit accesses. 1643169689Skan * 1644169689Skan * Note: NA reg = Network Address e.g DA, SA etc. 164550397Sobrien */ 1646169689Skan 1647169689Skan/* Port Registers */ 164850397Sobrien#define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 164950397Sobrien#define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 1650169689Skan#define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 1651169689Skan#define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 1652169689Skan#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 1653169689Skan#define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 1654169689Skan#define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 1655169689Skan 1656169689Skan/* Source Address Registers */ 1657169689Skan#define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 1658169689Skan#define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 165950397Sobrien#define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 166050397Sobrien#define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 166150397Sobrien#define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 166250397Sobrien#define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 166390075Sobrien 1664132718Skan/* Multicast Address Hash Registers */ 166550397Sobrien#define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 166650397Sobrien#define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 166750397Sobrien#define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 166850397Sobrien#define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 166950397Sobrien 167050397Sobrien/* Interrupt Source Registers */ 167150397Sobrien#define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 167250397Sobrien#define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 167350397Sobrien#define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 167450397Sobrien 167550397Sobrien/* Interrupt Mask Registers */ 167650397Sobrien#define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 167750397Sobrien#define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 167850397Sobrien#define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 167990075Sobrien 168090075Sobrien/* Serial Management Interface (SMI) Registers */ 168150397Sobrien#define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 1682169689Skan#define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 1683169689Skan#define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 1684169689Skan 1685169689Skan/* MIB Counters */ 1686169689Skan#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1687169689Skan#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1688169689Skan 1689169689Skan/* 1690169689Skan * MIB Counters base address definitions (low word) - 1691169689Skan * use offset 4 for access to high word (32 bit r/o) 1692169689Skan */ 1693169689Skan#define GM_RXF_UC_OK \ 1694169689Skan (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 1695169689Skan#define GM_RXF_BC_OK \ 1696169689Skan (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 1697169689Skan#define GM_RXF_MPAUSE \ 169850397Sobrien (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 1699169689Skan#define GM_RXF_MC_OK \ 170050397Sobrien (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 170150397Sobrien#define GM_RXF_FCS_ERR \ 170250397Sobrien (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 170390075Sobrien#define GM_RXF_SPARE1 \ 170450397Sobrien (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ 170590075Sobrien#define GM_RXO_OK_LO \ 170650397Sobrien (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 1707169689Skan#define GM_RXO_OK_HI \ 170850397Sobrien (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 170950397Sobrien#define GM_RXO_ERR_LO \ 171050397Sobrien (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 171150397Sobrien#define GM_RXO_ERR_HI \ 171250397Sobrien (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 171350397Sobrien#define GM_RXF_SHT \ 171450397Sobrien (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 171550397Sobrien#define GM_RXE_FRAG \ 171650397Sobrien (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 171790075Sobrien#define GM_RXF_64B \ 171890075Sobrien (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 171950397Sobrien#define GM_RXF_127B \ 1720169689Skan (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 172150397Sobrien#define GM_RXF_255B \ 172290075Sobrien (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 172350397Sobrien#define GM_RXF_511B \ 1724169689Skan (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 172550397Sobrien#define GM_RXF_1023B \ 1726117395Skan (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 1727117395Skan#define GM_RXF_1518B \ 1728117395Skan (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 172950397Sobrien#define GM_RXF_MAX_SZ \ 1730117395Skan (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 1731117395Skan#define GM_RXF_LNG_ERR \ 173250397Sobrien (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 173350397Sobrien#define GM_RXF_JAB_PKT \ 173450397Sobrien (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 173550397Sobrien#define GM_RXF_SPARE2 \ 173650397Sobrien (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ 173750397Sobrien#define GM_RXE_FIFO_OV \ 173850397Sobrien (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 1739132718Skan#define GM_RXF_SPARE3 \ 1740132718Skan (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ 1741132718Skan#define GM_TXF_UC_OK \ 1742132718Skan (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 1743132718Skan#define GM_TXF_BC_OK \ 1744132718Skan (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 1745132718Skan#define GM_TXF_MPAUSE \ 1746132718Skan (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 1747132718Skan#define GM_TXF_MC_OK \ 1748132718Skan (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 1749132718Skan#define GM_TXO_OK_LO \ 1750132718Skan (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 1751132718Skan#define GM_TXO_OK_HI \ 1752132718Skan (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 1753132718Skan#define GM_TXF_64B \ 1754132718Skan (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 1755132718Skan#define GM_TXF_127B \ 1756132718Skan (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 1757132718Skan#define GM_TXF_255B \ 1758132718Skan (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 1759132718Skan#define GM_TXF_511B \ 1760132718Skan (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 1761132718Skan#define GM_TXF_1023B \ 1762132718Skan (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 1763132718Skan#define GM_TXF_1518B \ 1764132718Skan (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 1765169689Skan#define GM_TXF_MAX_SZ \ 1766132718Skan (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 1767132718Skan#define GM_TXF_SPARE1 \ 1768132718Skan (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ 1769132718Skan#define GM_TXF_COL \ 1770132718Skan (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 1771132718Skan#define GM_TXF_LAT_COL \ 1772132718Skan (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 1773132718Skan#define GM_TXF_ABO_COL \ 1774132718Skan (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 1775132718Skan#define GM_TXF_MUL_COL \ 1776132718Skan (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 1777132718Skan#define GM_TXF_SNG_COL \ 1778132718Skan (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 1779132718Skan#define GM_TXE_FIFO_UR \ 1780132718Skan (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 1781132718Skan 1782132718Skan/*----------------------------------------------------------------------------*/ 1783132718Skan/* 1784132718Skan * GMAC Bit Definitions 1785132718Skan * 1786132718Skan * If the bit access behaviour differs from the register access behaviour 1787132718Skan * (r/w, r/o) this is documented after the bit number. 1788132718Skan * The following bit access behaviours are used: 1789132718Skan * (sc) self clearing 1790132718Skan * (r/o) read only 1791132718Skan */ 1792132718Skan 1793132718Skan/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1794132718Skan#define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ 1795132718Skan#define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ 1796132718Skan#define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ 1797132718Skan#define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ 1798132718Skan#define GM_GPSR_PAUSE BIT_11 /* Pause State */ 1799132718Skan#define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ 1800132718Skan#define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occured */ 1801132718Skan#define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occured */ 1802132718Skan#define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ 1803132718Skan#define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ 1804132718Skan#define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ 1805132718Skan#define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ 1806132718Skan 1807132718Skan/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1808132718Skan#define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ 1809132718Skan#define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ 1810132718Skan#define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ 1811132718Skan#define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ 1812132718Skan#define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ 1813132718Skan#define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ 1814132718Skan#define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ 1815132718Skan#define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ 1816132718Skan#define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ 1817132718Skan#define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ 1818132718Skan#define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ 1819132718Skan#define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ 1820132718Skan#define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ 1821132718Skan#define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ 1822132718Skan#define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ 1823132718Skan 1824132718Skan#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1825169689Skan#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 1826132718Skan GM_GPCR_AU_SPD_DIS) 1827132718Skan 1828132718Skan/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1829132718Skan#define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ 1830132718Skan#define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ 1831132718Skan#define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ 1832132718Skan#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ 1833132718Skan#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ 1834132718Skan /* (Yukon-2 only) */ 1835132718Skan 1836132718Skan#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1837132718Skan#define TX_COL_DEF 0x04 1838132718Skan 1839132718Skan/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1840132718Skan#define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ 1841132718Skan#define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ 1842132718Skan#define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ 1843132718Skan#define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ 1844132718Skan 1845132718Skan/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1846132718Skan#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ 1847132718Skan#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ 1848132718Skan#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ 1849132718Skan#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ 1850132718Skan /* (Yukon-2 only) */ 1851132718Skan 1852132718Skan#define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 1853132718Skan#define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 1854132718Skan#define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 1855132718Skan#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1856132718Skan 1857132718Skan#define TX_JAM_LEN_DEF 0x03 1858132718Skan#define TX_JAM_IPG_DEF 0x0b 1859169689Skan#define TX_IPG_JAM_DEF 0x1c 1860132718Skan#define TX_BOF_LIM_DEF 0x04 1861132718Skan 1862132718Skan/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1863132718Skan#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ 1864132718Skan /* r/o on Yukon, r/w on Yukon-EC */ 1865132718Skan#define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ 1866132718Skan#define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ 1867132718Skan#define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ 1868132718Skan#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ 1869132718Skan 1870132718Skan#define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 1871132718Skan#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) 1872132718Skan 1873132718Skan#define DATA_BLIND_DEF 0x04 1874169689Skan#define IPG_DATA_DEF 0x1e 1875169689Skan 1876132718Skan/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1877132718Skan#define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 1878132718Skan#define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 1879132718Skan#define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ 1880132718Skan#define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ 1881132718Skan#define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ 1882132718Skan 1883132718Skan#define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 1884132718Skan#define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 1885132718Skan 1886132718Skan/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1887132718Skan#define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ 1888132718Skan#define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ 1889132718Skan 1890132718Skan/* Receive Frame Status Encoding */ 1891132718Skan#define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ 1892132718Skan#define GMR_FS_VLAN BIT_13 /* VLAN Packet */ 189390075Sobrien#define GMR_FS_JABBER BIT_12 /* Jabber Packet */ 189450397Sobrien#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ 189550397Sobrien#define GMR_FS_MC BIT_10 /* Multicast Packet */ 1896132718Skan#define GMR_FS_BC BIT_9 /* Broadcast Packet */ 189750397Sobrien#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ 189890075Sobrien#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ 189950397Sobrien#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ 190050397Sobrien#define GMR_FS_MII_ERR BIT_5 /* MII Error */ 190190075Sobrien#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ 1902117395Skan#define GMR_FS_FRAGMENT BIT_3 /* Fragment */ 1903117395Skan#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ 1904117395Skan#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ 1905117395Skan 190650397Sobrien#define GMR_FS_LEN_SHIFT 16 190790075Sobrien 190890075Sobrien#define GMR_FS_ANY_ERR ( \ 190990075Sobrien GMR_FS_RX_FF_OV | \ 191090075Sobrien GMR_FS_CRC_ERR | \ 191150397Sobrien GMR_FS_FRAGMENT | \ 191250397Sobrien GMR_FS_LONG_ERR | \ 191390075Sobrien GMR_FS_MII_ERR | \ 1914169689Skan GMR_FS_BAD_FC | \ 191590075Sobrien GMR_FS_GOOD_FC | \ 191690075Sobrien GMR_FS_UN_SIZE | \ 1917169689Skan GMR_FS_JABBER) 191850397Sobrien 1919169689Skan/* Rx GMAC FIFO Flush Mask (default) */ 1920169689Skan#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR 192150397Sobrien 1922169689Skan/* Receive and Transmit GMAC FIFO Registers (YUKON only) */ 192350397Sobrien 192450397Sobrien/* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ 192550397Sobrien/* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ 192690075Sobrien/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ 192750397Sobrien/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ 192890075Sobrien/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ 192990075Sobrien/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ 1930117395Skan/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 193150397Sobrien/* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 193250397Sobrien/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ 193350397Sobrien/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ 193450397Sobrien/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ 193550397Sobrien/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ 1936169689Skan/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ 1937169689Skan/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ 1938169689Skan 1939169689Skan/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1940169689Skan#define RX_TRUNC_ON BIT_27 /* enable packet truncation */ 194150397Sobrien#define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ 1942169689Skan#define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ 1943169689Skan#define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ 1944169689Skan#define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ 1945169689Skan#define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ 1946169689Skan#define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ 194750397Sobrien#define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ 1948169689Skan#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ 1949169689Skan#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ 1950169689Skan#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ 1951169689Skan#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ 195250397Sobrien#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ 1953169689Skan#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ 1954169689Skan#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ 1955169689Skan#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ 1956169689Skan#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ 1957169689Skan#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ 1958169689Skan#define GMF_OPER_ON BIT_3 /* Operational Mode On */ 195950397Sobrien#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ 1960169689Skan#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ 1961169689Skan#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ 1962169689Skan 1963169689Skan/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ 1964169689Skan#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ 1965169689Skan#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ 196650397Sobrien#define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ 1967169689Skan#define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ 1968169689Skan#define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ 1969132718Skan#define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ 1970169689Skan#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ 1971169689Skan#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ 1972169689Skan#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ 1973169689Skan /* Bits 15..8: same as for RX_GMF_CTRL_T */ 1974169689Skan#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ 1975169689Skan#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ 1976169689Skan#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ 1977169689Skan /* Bits 3..0: same as for RX_GMF_CTRL_T */ 1978169689Skan 1979169689Skan#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) 1980169689Skan#define GMF_TX_CTRL_DEF GMF_OPER_ON 1981169689Skan 1982169689Skan#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ 1983169689Skan#define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ 1984169689Skan 1985169689Skan/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 1986169689Skan#define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ 1987169689Skan#define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ 1988169689Skan#define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ 1989169689Skan 1990169689Skan/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ 1991169689Skan#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ 1992169689Skan#define PC_POLL_RQ BIT_4 /* Poll Request Start */ 1993169689Skan#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ 1994169689Skan#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ 1995169689Skan#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ 1996169689Skan#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ 1997169689Skan 1998169689Skan/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 1999169689Skan/* This register is used by the host driver software */ 2000169689Skan#define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ 2001169689Skan#define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ 2002169689Skan#define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ 2003169689Skan#define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ 2004169689Skan#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ 2005169689Skan 2006169689Skan#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ 2007169689Skan#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ 2008169689Skan 2009169689Skan/* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */ 2010169689Skan#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ 2011169689Skan#define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ 2012169689Skan#define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ 2013169689Skan#define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ 2014169689Skan#define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ 2015169689Skan#define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ 2016169689Skan#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ 2017169689Skan#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ 2018169689Skan#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 2019169689Skan#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 2020169689Skan#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 2021169689Skan#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */ 2022169689Skan#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 202350397Sobrien#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ 202450397Sobrien /* Microcontroller State */ 2025117395Skan#define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 2026117395Skan#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 2027117395Skan#define Y2_ASF_HCU_CCSR_ASF_RESET 0 2028117395Skan#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 2029117395Skan#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 2030117395Skan 2031117395Skan/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 2032117395Skan/* This register is used by the ASF firmware */ 2033117395Skan#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ 2034117395Skan#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ 2035117395Skan 2036117395Skan/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 2037117395Skan#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ 2038117395Skan#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ 2039117395Skan#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ 2040117395Skan#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ 2041117395Skan#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ 2042117395Skan 2043117395Skan/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 2044117395Skan#define GMC_SEC_RST BIT_15 /* MAC SEC RST */ 2045117395Skan#define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ 2046117395Skan#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ 2047117395Skan#define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ 2048117395Skan#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ 2049117395Skan#define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ 2050117395Skan#define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ 2051117395Skan#define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ 2052117395Skan#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ 2053117395Skan#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ 2054117395Skan#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ 2055117395Skan#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ 2056117395Skan#define GMC_PAUSE_ON BIT_3 /* Pause On */ 2057117395Skan#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ 2058117395Skan#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ 2059117395Skan#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ 2060117395Skan 2061117395Skan/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 2062117395Skan#define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ 2063117395Skan#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ 2064117395Skan#define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ 2065117395Skan#define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ 2066117395Skan#define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ 2067117395Skan#define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ 2068117395Skan#define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ 2069117395Skan#define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ 2070117395Skan#define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ 2071117395Skan#define GPC_ANEG_0 BIT_19 /* ANEG[0] */ 2072169689Skan#define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ 2073169689Skan#define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ 2074169689Skan#define GPC_ANEG_3 BIT_16 /* ANEG[3] */ 2075169689Skan#define GPC_ANEG_2 BIT_15 /* ANEG[2] */ 2076169689Skan#define GPC_ANEG_1 BIT_14 /* ANEG[1] */ 2077117395Skan#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ 2078169689Skan#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ 2079117395Skan#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ 2080169689Skan#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ 2081117395Skan#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ 2082117395Skan#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ 2083117395Skan#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ 2084117395Skan#define GPC_RST_SET BIT_0 /* Set GPHY Reset */ 2085117395Skan 2086117395Skan/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 2087117395Skan/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 2088117395Skan#define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ 2089117395Skan#define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ 2090117395Skan#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ 2091117395Skan#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ 2092117395Skan#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ 2093117395Skan#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ 2094117395Skan 2095117395Skan#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) 2096117395Skan 2097117395Skan/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 2098117395Skan#define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ 2099117395Skan#define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ 2100117395Skan 2101117395Skan#define MSK_PORT_A 0 2102117395Skan#define MSK_PORT_B 1 2103117395Skan 2104117395Skan/* Register access macros */ 2105169689Skan#define CSR_WRITE_4(sc, reg, val) \ 2106169689Skan bus_write_4((sc)->msk_res[0], (reg), (val)) 2107117395Skan#define CSR_WRITE_2(sc, reg, val) \ 2108117395Skan bus_write_2((sc)->msk_res[0], (reg), (val)) 2109117395Skan#define CSR_WRITE_1(sc, reg, val) \ 2110117395Skan bus_write_1((sc)->msk_res[0], (reg), (val)) 2111117395Skan 2112117395Skan#define CSR_READ_4(sc, reg) \ 2113117395Skan bus_read_4((sc)->msk_res[0], (reg)) 2114117395Skan#define CSR_READ_2(sc, reg) \ 2115117395Skan bus_read_2((sc)->msk_res[0], (reg)) 2116117395Skan#define CSR_READ_1(sc, reg) \ 2117117395Skan bus_read_1((sc)->msk_res[0], (reg)) 2118117395Skan 2119117395Skan#define CSR_PCI_WRITE_4(sc, reg, val) \ 2120117395Skan bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2121117395Skan#define CSR_PCI_WRITE_2(sc, reg, val) \ 2122117395Skan bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2123117395Skan#define CSR_PCI_WRITE_1(sc, reg, val) \ 2124117395Skan bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2125117395Skan 2126117395Skan#define CSR_PCI_READ_4(sc, reg) \ 2127117395Skan bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2128117395Skan#define CSR_PCI_READ_2(sc, reg) \ 2129169689Skan bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2130117395Skan#define CSR_PCI_READ_1(sc, reg) \ 2131117395Skan bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2132117395Skan 2133117395Skan#define MSK_IF_READ_4(sc_if, reg) \ 2134117395Skan CSR_READ_4((sc_if)->msk_softc, (reg)) 2135117395Skan#define MSK_IF_READ_2(sc_if, reg) \ 2136117395Skan CSR_READ_2((sc_if)->msk_softc, (reg)) 2137117395Skan#define MSK_IF_READ_1(sc_if, reg) \ 2138117395Skan CSR_READ_1((sc_if)->msk_softc, (reg)) 2139117395Skan 2140117395Skan#define MSK_IF_WRITE_4(sc_if, reg, val) \ 2141117395Skan CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) 2142117395Skan#define MSK_IF_WRITE_2(sc_if, reg, val) \ 2143117395Skan CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) 2144117395Skan#define MSK_IF_WRITE_1(sc_if, reg, val) \ 2145117395Skan CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) 2146169689Skan 2147169689Skan#define GMAC_REG(port, reg) \ 2148169689Skan ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) 2149169689Skan#define GMAC_WRITE_2(sc, port, reg, val) \ 2150169689Skan CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) 2151169689Skan#define GMAC_READ_2(sc, port, reg) \ 2152169689Skan CSR_READ_2((sc), GMAC_REG((port), (reg))) 2153169689Skan 2154117395Skan/* GPHY address (bits 15..11 of SMI control reg) */ 2155117395Skan#define PHY_ADDR_MARV 0 2156117395Skan 2157117395Skan#define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 2158117395Skan#define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 2159117395Skan 2160117395Skan/* 2161117395Skan * At first I guessed 8 bytes, the size of a single descriptor, would be 2162132718Skan * required alignment constraints. But, it seems that Yukon II have 4096 2163117395Skan * bytes boundary alignment constraints. 2164117395Skan */ 2165117395Skan#define MSK_RING_ALIGN 4096 2166117395Skan#define MSK_STAT_ALIGN 4096 2167169689Skan 2168117395Skan/* Rx descriptor data structure */ 2169117395Skanstruct msk_rx_desc { 2170117395Skan uint32_t msk_addr; 2171117395Skan uint32_t msk_control; 2172117395Skan}; 2173169689Skan 2174117395Skan/* Tx descriptor data structure */ 2175169689Skanstruct msk_tx_desc { 2176169689Skan uint32_t msk_addr; 2177117395Skan uint32_t msk_control; 2178117395Skan}; 2179117395Skan 2180117395Skan/* Status descriptor data structure */ 2181117395Skanstruct msk_stat_desc { 2182117395Skan uint32_t msk_status; 2183117395Skan uint32_t msk_control; 2184117395Skan}; 2185117395Skan 2186117395Skan/* mask and shift value to get Tx async queue status for port 1 */ 2187169689Skan#define STLE_TXA1_MSKL 0x00000fff 2188169689Skan#define STLE_TXA1_SHIFTL 0 2189169689Skan 2190169689Skan/* mask and shift value to get Tx sync queue status for port 1 */ 2191169689Skan#define STLE_TXS1_MSKL 0x00fff000 2192169689Skan#define STLE_TXS1_SHIFTL 12 2193169689Skan 2194169689Skan/* mask and shift value to get Tx async queue status for port 2 */ 2195169689Skan#define STLE_TXA2_MSKL 0xff000000 2196169689Skan#define STLE_TXA2_SHIFTL 24 2197169689Skan#define STLE_TXA2_MSKH 0x000f 2198169689Skan/* this one shifts up */ 2199169689Skan#define STLE_TXA2_SHIFTH 8 2200169689Skan 2201169689Skan/* mask and shift value to get Tx sync queue status for port 2 */ 2202169689Skan#define STLE_TXS2_MSKL 0x00000000 2203169689Skan#define STLE_TXS2_SHIFTL 0 2204169689Skan#define STLE_TXS2_MSKH 0xfff0 2205169689Skan#define STLE_TXS2_SHIFTH 4 2206169689Skan 2207169689Skan/* YUKON-2 bit values */ 2208169689Skan#define HW_OWNER 0x80000000 2209169689Skan#define SW_OWNER 0x00000000 2210169689Skan 2211169689Skan#define PU_PUTIDX_VALID 0x10000000 2212169689Skan 2213169689Skan/* YUKON-2 Control flags */ 2214169689Skan#define UDPTCP 0x00010000 2215169689Skan#define CALSUM 0x00020000 2216169689Skan#define WR_SUM 0x00040000 2217169689Skan#define INIT_SUM 0x00080000 2218169689Skan#define LOCK_SUM 0x00100000 2219169689Skan#define INS_VLAN 0x00200000 2220169689Skan#define FRC_STAT 0x00400000 2221169689Skan#define EOP 0x00800000 2222169689Skan 2223169689Skan#define TX_LOCK 0x01000000 2224169689Skan#define BUF_SEND 0x02000000 2225169689Skan#define PACKET_SEND 0x04000000 2226169689Skan 2227169689Skan#define NO_WARNING 0x40000000 2228169689Skan#define NO_UPDATE 0x80000000 2229169689Skan 2230169689Skan/* YUKON-2 Rx/Tx opcodes defines */ 2231169689Skan#define OP_TCPWRITE 0x11000000 2232169689Skan#define OP_TCPSTART 0x12000000 2233169689Skan#define OP_TCPINIT 0x14000000 2234117395Skan#define OP_TCPLCK 0x18000000 2235117395Skan#define OP_TCPCHKSUM OP_TCPSTART 2236117395Skan#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) 2237132718Skan#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) 2238132718Skan#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) 2239169689Skan#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) 2240169689Skan#define OP_ADDR64 0x21000000 2241132718Skan#define OP_VLAN 0x22000000 2242169689Skan#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) 2243169689Skan#define OP_LRGLEN 0x24000000 2244169689Skan#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) 2245169689Skan#define OP_MSS 0x28000000 2246169689Skan#define OP_MSSVLAN (OP_MSS | OP_VLAN) 2247117395Skan#define OP_BUFFER 0x40000000 2248169689Skan#define OP_PACKET 0x41000000 2249169689Skan#define OP_LARGESEND 0x43000000 2250117395Skan 2251117395Skan/* YUKON-2 STATUS opcodes defines */ 2252117395Skan#define OP_RXSTAT 0x60000000 2253117395Skan#define OP_RXTIMESTAMP 0x61000000 2254117395Skan#define OP_RXVLAN 0x62000000 2255117395Skan#define OP_RXCHKS 0x64000000 2256169689Skan#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) 2257169689Skan#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) 2258169689Skan#define OP_RSS_HASH 0x65000000 225996263Sobrien#define OP_TXINDEXLE 0x68000000 226090075Sobrien 2261169689Skan/* YUKON-2 SPECIAL opcodes defines */ 226250397Sobrien#define OP_PUTIDX 0x70000000 226390075Sobrien 2264132718Skan#define STLE_OP_MASK 0xff000000 226550397Sobrien#define STLE_CSS_MASK 0x00ff0000 2266117395Skan#define STLE_LEN_MASK 0x0000ffff 2267132718Skan 226850397Sobrien/* CSS defined in status LE(valid for descriptor V2 format). */ 226990075Sobrien#define CSS_TCPUDP_CSUM_OK 0x00800000 227090075Sobrien#define CSS_UDP 0x00400000 227190075Sobrien#define CSS_TCP 0x00200000 227290075Sobrien#define CSS_IPFRAG 0x00100000 227390075Sobrien#define CSS_IPV6 0x00080000 227450397Sobrien#define CSS_IPV4_CSUM_OK 0x00040000 227550397Sobrien#define CSS_IPV4 0x00020000 227650397Sobrien#define CSS_PORT 0x00010000 227750397Sobrien 227850397Sobrien/* Descriptor Bit Definition */ 227950397Sobrien/* TxCtrl Transmit Buffer Control Field */ 228050397Sobrien/* RxCtrl Receive Buffer Control Field */ 228150397Sobrien#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ 2282169689Skan#define BMU_STF BIT_30 /* Start of Frame */ 228350397Sobrien#define BMU_EOF BIT_29 /* End of Frame */ 2284169689Skan#define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ 2285169689Skan#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ 228690075Sobrien/* TxCtrl specific bits */ 228750397Sobrien#define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ 2288169689Skan#define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ 228950397Sobrien#define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ 2290169689Skan/* RxCtrl specific bits */ 229150397Sobrien#define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ 2292169689Skan#define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ 2293169689Skan#define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ 2294169689Skan /* Bit 23..16: BMU Check Opcodes */ 2295169689Skan#define BMU_CHECK (0x55<<16) /* Default BMU check */ 2296169689Skan#define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ 229750397Sobrien#define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ 2298169689Skan#define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ 2299169689Skan 2300169689Skan#define MSK_TX_RING_CNT 256 230190075Sobrien#define MSK_RX_RING_CNT 256 230290075Sobrien#define MSK_RX_BUF_ALIGN 8 230350397Sobrien#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT 2304169689Skan#define MSK_STAT_RING_CNT ((1 + 3) * (MSK_TX_RING_CNT + MSK_RX_RING_CNT)) 2305169689Skan#define MSK_MAXTXSEGS 32 2306117395Skan#define MSK_TSO_MAXSGSIZE 4096 230790075Sobrien#define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 2308169689Skan 230950397Sobrien/* 231096263Sobrien * It seems that the hardware requires extra decriptors(LEs) to offload 231196263Sobrien * TCP/UDP checksum, VLAN hardware tag inserstion and TSO. 231250397Sobrien * 2313169689Skan * 1 descriptor for TCP/UDP checksum offload. 2314169689Skan * 1 descriptor VLAN hardware tag insertion. 2315169689Skan * 1 descriptor for TSO(TCP Segmentation Offload) 231690075Sobrien * 1 descriptor for 64bits DMA : Not applicatable due to the use of 231790075Sobrien * BUS_SPACE_MAXADDR_32BIT in parent DMA tag creation. 231850397Sobrien */ 231950397Sobrien#define MSK_RESERVED_TX_DESC_CNT 3 232050397Sobrien 2321169689Skan/* 2322169689Skan * Jumbo buffer stuff. Note that we must allocate more jumbo 2323117395Skan * buffers than there are descriptors in the receive ring. This 2324169689Skan * is because we don't know how long it will take for a packet 2325169689Skan * to be released after we hand it off to the upper protocol 2326169689Skan * layers. To be safe, we allocate 1.5 times the number of 2327169689Skan * receive descriptors. 2328169689Skan */ 2329169689Skan#define MSK_JUMBO_FRAMELEN 9022 2330169689Skan#define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2331169689Skan#define MSK_MAX_FRAMELEN \ 2332169689Skan (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 2333169689Skan#define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 2334169689Skan 2335169689Skanstruct msk_txdesc { 2336169689Skan struct mbuf *tx_m; 2337169689Skan bus_dmamap_t tx_dmamap; 2338169689Skan struct msk_tx_desc *tx_le; 2339169689Skan}; 2340169689Skan 2341169689Skanstruct msk_rxdesc { 2342169689Skan struct mbuf *rx_m; 2343169689Skan bus_dmamap_t rx_dmamap; 2344169689Skan struct msk_rx_desc *rx_le; 2345169689Skan}; 2346169689Skan 2347169689Skanstruct msk_chain_data { 2348169689Skan bus_dma_tag_t msk_parent_tag; 2349169689Skan bus_dma_tag_t msk_tx_tag; 2350169689Skan struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT]; 2351169689Skan bus_dma_tag_t msk_rx_tag; 2352169689Skan struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT]; 2353169689Skan bus_dma_tag_t msk_tx_ring_tag; 2354169689Skan bus_dma_tag_t msk_rx_ring_tag; 2355169689Skan bus_dmamap_t msk_tx_ring_map; 2356169689Skan bus_dmamap_t msk_rx_ring_map; 2357169689Skan bus_dmamap_t msk_rx_sparemap; 2358169689Skan bus_dma_tag_t msk_jumbo_rx_tag; 2359117395Skan struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]; 2360117395Skan bus_dma_tag_t msk_jumbo_rx_ring_tag; 2361132718Skan bus_dmamap_t msk_jumbo_rx_ring_map; 236290075Sobrien bus_dmamap_t msk_jumbo_rx_sparemap; 2363132718Skan uint16_t msk_tso_mtu; 236490075Sobrien uint32_t msk_last_csum; 236590075Sobrien int msk_tx_prod; 236650397Sobrien int msk_tx_cons; 2367132718Skan int msk_tx_cnt; 2368132718Skan int msk_tx_put; 2369132718Skan int msk_rx_cons; 237050397Sobrien int msk_rx_prod; 2371132718Skan int msk_rx_putwm; 2372117395Skan}; 2373132718Skan 237450397Sobrienstruct msk_ring_data { 2375132718Skan struct msk_tx_desc *msk_tx_ring; 2376132718Skan bus_addr_t msk_tx_ring_paddr; 2377132718Skan struct msk_rx_desc *msk_rx_ring; 2378132718Skan bus_addr_t msk_rx_ring_paddr; 2379132718Skan struct msk_rx_desc *msk_jumbo_rx_ring; 238050397Sobrien bus_addr_t msk_jumbo_rx_ring_paddr; 2381169689Skan}; 2382132718Skan 2383132718Skan#define MSK_TX_RING_ADDR(sc, i) \ 2384132718Skan ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) 2385132718Skan#define MSK_RX_RING_ADDR(sc, i) \ 2386132718Skan ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2387132718Skan#define MSK_JUMBO_RX_RING_ADDR(sc, i) \ 2388132718Skan ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2389132718Skan 2390132718Skan#define MSK_TX_RING_SZ \ 2391132718Skan (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) 2392132718Skan#define MSK_RX_RING_SZ \ 239350397Sobrien (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) 2394132718Skan#define MSK_JUMBO_RX_RING_SZ \ 2395132718Skan (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) 2396132718Skan#define MSK_STAT_RING_SZ \ 2397132718Skan (sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT) 2398132718Skan 2399132718Skan#define MSK_INC(x, y) (x) = (x + 1) % y 2400132718Skan 2401132718Skan#define MSK_PCI_BUS 0 240250397Sobrien#define MSK_PCIX_BUS 1 240350397Sobrien#define MSK_PEX_BUS 2 240490075Sobrien 240590075Sobrien#define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) 2406132718Skan#define MSK_PROC_MIN 30 2407132718Skan#define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) 2408132718Skan 240990075Sobrien#define MSK_INT_HOLDOFF_DEFAULT 100 2410169689Skan 2411169689Skan#define MSK_TX_TIMEOUT 5 2412169689Skan#define MSK_PUT_WM 10 241390075Sobrien 241490075Sobrienstruct msk_mii_data { 241590075Sobrien int port; 2416117395Skan uint32_t pmd; 2417117395Skan int mii_flags; 2418117395Skan}; 241950397Sobrien 2420117395Skan/* Forward decl. */ 2421117395Skanstruct msk_if_softc; 2422132718Skan 242350397Sobrienstruct msk_hw_stats { 2424117395Skan /* Rx stats. */ 2425117395Skan uint32_t rx_ucast_frames; 2426169689Skan uint32_t rx_bcast_frames; 2427117395Skan uint32_t rx_pause_frames; 2428117395Skan uint32_t rx_mcast_frames; 2429117395Skan uint32_t rx_crc_errs; 243050397Sobrien uint32_t rx_spare1; 2431169689Skan uint64_t rx_good_octets; 2432169689Skan uint64_t rx_bad_octets; 2433169689Skan uint32_t rx_runts; 2434117395Skan uint32_t rx_runt_errs; 2435169689Skan uint32_t rx_pkts_64; 2436169689Skan uint32_t rx_pkts_65_127; 2437169689Skan uint32_t rx_pkts_128_255; 2438169689Skan uint32_t rx_pkts_256_511; 2439169689Skan uint32_t rx_pkts_512_1023; 2440169689Skan uint32_t rx_pkts_1024_1518; 2441169689Skan uint32_t rx_pkts_1519_max; 2442169689Skan uint32_t rx_pkts_too_long; 2443117395Skan uint32_t rx_pkts_jabbers; 2444132718Skan uint32_t rx_spare2; 2445169689Skan uint32_t rx_fifo_oflows; 2446169689Skan uint32_t rx_spare3; 2447169689Skan /* Tx stats. */ 2448169689Skan uint32_t tx_ucast_frames; 2449132718Skan uint32_t tx_bcast_frames; 2450169689Skan uint32_t tx_pause_frames; 2451169689Skan uint32_t tx_mcast_frames; 2452169689Skan uint64_t tx_octets; 2453169689Skan uint32_t tx_pkts_64; 2454169689Skan uint32_t tx_pkts_65_127; 2455169689Skan uint32_t tx_pkts_128_255; 2456169689Skan uint32_t tx_pkts_256_511; 2457169689Skan uint32_t tx_pkts_512_1023; 2458169689Skan uint32_t tx_pkts_1024_1518; 2459132718Skan uint32_t tx_pkts_1519_max; 2460169689Skan uint32_t tx_spare1; 2461169689Skan uint32_t tx_colls; 2462169689Skan uint32_t tx_late_colls; 2463169689Skan uint32_t tx_excess_colls; 2464169689Skan uint32_t tx_multi_colls; 2465169689Skan uint32_t tx_single_colls; 2466169689Skan uint32_t tx_underflows; 2467169689Skan}; 2468169689Skan 2469169689Skan/* Softc for the Marvell Yukon II controller. */ 2470169689Skanstruct msk_softc { 2471169689Skan struct resource *msk_res[1]; /* I/O resource */ 2472169689Skan struct resource_spec *msk_res_spec; 2473169689Skan struct resource *msk_irq[1]; /* IRQ resources */ 2474169689Skan struct resource_spec *msk_irq_spec; 2475169689Skan void *msk_intrhand; /* irq handler handle */ 2476169689Skan device_t msk_dev; 2477169689Skan uint8_t msk_hw_id; 2478169689Skan uint8_t msk_hw_rev; 2479132718Skan uint8_t msk_bustype; 2480169689Skan uint8_t msk_num_port; 2481169689Skan int msk_expcap; 2482169689Skan int msk_pcixcap; 2483169689Skan int msk_ramsize; /* amount of SRAM on NIC */ 2484169689Skan uint32_t msk_pmd; /* physical media type */ 2485169689Skan uint32_t msk_intrmask; 2486169689Skan uint32_t msk_intrhwemask; 2487169689Skan uint32_t msk_pflags; 2488169689Skan int msk_clock; 2489169689Skan struct msk_if_softc *msk_if[2]; 2490117395Skan device_t msk_devs[2]; 2491169689Skan int msk_txqsize; 2492169689Skan int msk_rxqsize; 2493169689Skan int msk_txqstart[2]; 2494169689Skan int msk_txqend[2]; 2495169689Skan int msk_rxqstart[2]; 2496117395Skan int msk_rxqend[2]; 2497169689Skan bus_dma_tag_t msk_stat_tag; 2498169689Skan bus_dmamap_t msk_stat_map; 2499169689Skan struct msk_stat_desc *msk_stat_ring; 2500169689Skan bus_addr_t msk_stat_ring_paddr; 2501169689Skan int msk_int_holdoff; 2502169689Skan int msk_process_limit; 2503169689Skan int msk_stat_cons; 2504169689Skan struct mtx msk_mtx; 2505117395Skan}; 250690075Sobrien 250750397Sobrien#define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) 250850397Sobrien#define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) 2509169689Skan#define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) 2510169689Skan#define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) 2511169689Skan#define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) 2512169689Skan#define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) 2513169689Skan 2514169689Skan#define MSK_USECS(sc, us) ((sc)->msk_clock * (us)) 251590075Sobrien 251650397Sobrien/* Softc for each logical interface. */ 251750397Sobrienstruct msk_if_softc { 2518169689Skan struct ifnet *msk_ifp; /* interface info */ 2519169689Skan device_t msk_miibus; 2520169689Skan device_t msk_if_dev; 2521169689Skan int32_t msk_port; /* port # on controller */ 2522169689Skan int msk_framesize; 2523169689Skan int msk_phytype; 2524169689Skan int msk_phyaddr; 2525169689Skan uint32_t msk_flags; 252650397Sobrien#define MSK_FLAG_MSI 0x0001 2527169689Skan#define MSK_FLAG_FASTETHER 0x0004 2528169689Skan#define MSK_FLAG_JUMBO 0x0008 2529169689Skan#define MSK_FLAG_JUMBO_NOCSUM 0x0010 2530169689Skan#define MSK_FLAG_RAMBUF 0x0020 253150397Sobrien#define MSK_FLAG_DESCV2 0x0040 2532169689Skan#define MSK_FLAG_AUTOTX_CSUM 0x0080 2533169689Skan#define MSK_FLAG_NOHWVLAN 0x0100 2534169689Skan#define MSK_FLAG_NORXCHK 0x0200 2535169689Skan#define MSK_FLAG_NORX_CSUM 0x0400 2536169689Skan#define MSK_FLAG_SUSPEND 0x2000 2537169689Skan#define MSK_FLAG_DETACH 0x4000 2538169689Skan#define MSK_FLAG_LINK 0x8000 2539117395Skan struct callout msk_tick_ch; 2540169689Skan int msk_watchdog_timer; 2541169689Skan uint32_t msk_txq; /* Tx. Async Queue offset */ 2542169689Skan uint32_t msk_txsq; /* Tx. Syn Queue offset */ 2543169689Skan uint32_t msk_rxq; /* Rx. Qeueue offset */ 2544169689Skan struct msk_chain_data msk_cdata; 2545169689Skan struct msk_ring_data msk_rdata; 2546169689Skan struct msk_softc *msk_softc; /* parent controller */ 2547169689Skan struct msk_hw_stats msk_stats; 2548169689Skan int msk_if_flags; 2549169689Skan uint16_t msk_vtag; /* VLAN tag id. */ 2550169689Skan}; 2551169689Skan 2552169689Skan#define MSK_TIMEOUT 1000 2553117395Skan#define MSK_PHY_POWERUP 1 2554169689Skan#define MSK_PHY_POWERDOWN 0 2555169689Skan