e1000phyreg.h revision 173133
1238104Sdes/* $FreeBSD: head/sys/dev/mii/e1000phyreg.h 173133 2007-10-29 05:50:22Z yongari $ */ 2238104Sdes/*- 3238104Sdes * Principal Author: Parag Patel 4238104Sdes * Copyright (c) 2001 5238104Sdes * All rights reserved. 6238104Sdes * 7238104Sdes * Redistribution and use in source and binary forms, with or without 8238104Sdes * modification, are permitted provided that the following conditions 9238104Sdes * are met: 10238104Sdes * 1. Redistributions of source code must retain the above copyright 11238104Sdes * notice unmodified, this list of conditions, and the following 12238104Sdes * disclaimer. 13238104Sdes * 2. Redistributions in binary form must reproduce the above copyright 14238104Sdes * notice, this list of conditions and the following disclaimer in the 15238104Sdes * documentation and/or other materials provided with the distribution. 16238104Sdes * 17238104Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18238104Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19238104Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20238104Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21238104Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22238104Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23238104Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24238104Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25238104Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26238104Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27238104Sdes * SUCH DAMAGE. 28238104Sdes * 29238104Sdes * Additonal Copyright (c) 2001 by Traakan Software under same licence. 30238104Sdes * Secondary Author: Matthew Jacob 31238104Sdes */ 32238104Sdes 33238104Sdes/*- 34238104Sdes * Derived by information released by Intel under the following license: 35238104Sdes * 36238104Sdes * Copyright (c) 1999 - 2001, Intel Corporation 37238104Sdes * 38238104Sdes * All rights reserved. 39238104Sdes * 40238104Sdes * Redistribution and use in source and binary forms, with or without 41238104Sdes * modification, are permitted provided that the following conditions are met: 42238104Sdes * 43238104Sdes * 1. Redistributions of source code must retain the above copyright notice, 44238104Sdes * this list of conditions and the following disclaimer. 45238104Sdes * 46238104Sdes * 2. Redistributions in binary form must reproduce the above copyright notice, 47238104Sdes * this list of conditions and the following disclaimer in the 48238104Sdes * documentation and/or other materials provided with the distribution. 49238104Sdes * 50238104Sdes * 3. Neither the name of Intel Corporation nor the names of its contributors 51238104Sdes * may be used to endorse or promote products derived from this software 52238104Sdes * without specific prior written permission. 53238104Sdes * 54238104Sdes * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 55238104Sdes * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56238104Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57238104Sdes * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 58238104Sdes * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59238104Sdes * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60238104Sdes * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 61238104Sdes * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62238104Sdes * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 63238104Sdes * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64238104Sdes * 65238104Sdes */ 66238104Sdes 67238104Sdes/* 68238104Sdes * Marvell E1000 PHY registers 69238104Sdes */ 70238104Sdes 71238104Sdes#define E1000_MAX_REG_ADDRESS 0x1F 72238104Sdes 73238104Sdes#define E1000_CR 0x00 /* control register */ 74238104Sdes#define E1000_CR_SPEED_SELECT_MSB 0x0040 75238104Sdes#define E1000_CR_COLL_TEST_ENABLE 0x0080 76238104Sdes#define E1000_CR_FULL_DUPLEX 0x0100 77238104Sdes#define E1000_CR_RESTART_AUTO_NEG 0x0200 78238104Sdes#define E1000_CR_ISOLATE 0x0400 79238104Sdes#define E1000_CR_POWER_DOWN 0x0800 80238104Sdes#define E1000_CR_AUTO_NEG_ENABLE 0x1000 81238104Sdes#define E1000_CR_SPEED_SELECT_LSB 0x2000 82238104Sdes#define E1000_CR_LOOPBACK 0x4000 83238104Sdes#define E1000_CR_RESET 0x8000 84238104Sdes 85238104Sdes#define E1000_CR_SPEED_1000 0x0040 86238104Sdes#define E1000_CR_SPEED_100 0x2000 87238104Sdes#define E1000_CR_SPEED_10 0x0000 88238104Sdes 89238104Sdes#define E1000_SR 0x01 /* status register */ 90238104Sdes#define E1000_SR_EXTENDED 0x0001 91238104Sdes#define E1000_SR_JABBER_DETECT 0x0002 92238104Sdes#define E1000_SR_LINK_STATUS 0x0004 93238104Sdes#define E1000_SR_AUTO_NEG 0x0008 94238104Sdes#define E1000_SR_REMOTE_FAULT 0x0010 95238104Sdes#define E1000_SR_AUTO_NEG_COMPLETE 0x0020 96238104Sdes#define E1000_SR_PREAMBLE_SUPPRESS 0x0040 97238104Sdes#define E1000_SR_EXTENDED_STATUS 0x0100 98238104Sdes#define E1000_SR_100T2 0x0200 99238104Sdes#define E1000_SR_100T2_FD 0x0400 100238104Sdes#define E1000_SR_10T 0x0800 101238104Sdes#define E1000_SR_10T_FD 0x1000 102238104Sdes#define E1000_SR_100TX 0x2000 103238104Sdes#define E1000_SR_100TX_FD 0x4000 104238104Sdes#define E1000_SR_100T4 0x8000 105238104Sdes 106238104Sdes#define E1000_ID1 0x02 /* ID register 1 */ 107238104Sdes#define E1000_ID2 0x03 /* ID register 2 */ 108238104Sdes#define E1000_ID_88E1000 0x01410C50 109238104Sdes#define E1000_ID_88E1000S 0x01410C40 110238104Sdes#define E1000_ID_88E1011 0x01410C20 111238104Sdes#define E1000_ID_MASK 0xFFFFFFF0 112238104Sdes 113238104Sdes#define E1000_AR 0x04 /* autonegotiation advertise reg */ 114238104Sdes#define E1000_AR_SELECTOR_FIELD 0x0001 115238104Sdes#define E1000_AR_10T 0x0020 116238104Sdes#define E1000_AR_10T_FD 0x0040 117238104Sdes#define E1000_AR_100TX 0x0080 118238104Sdes#define E1000_AR_100TX_FD 0x0100 119238104Sdes#define E1000_AR_100T4 0x0200 120238104Sdes#define E1000_AR_PAUSE 0x0400 121238104Sdes#define E1000_AR_ASM_DIR 0x0800 122238104Sdes#define E1000_AR_REMOTE_FAULT 0x2000 123238104Sdes#define E1000_AR_NEXT_PAGE 0x8000 124238104Sdes#define E1000_AR_SPEED_MASK 0x01E0 125238104Sdes 126238104Sdes/* Autonegotiation register bits for fiber cards (Alaska Only!) */ 127238104Sdes#define E1000_FA_1000X_FD 0x0020 128238104Sdes#define E1000_FA_1000X 0x0040 129238104Sdes#define E1000_FA_SYM_PAUSE 0x0080 130238104Sdes#define E1000_FA_ASYM_PAUSE 0x0100 131238104Sdes#define E1000_FA_FAULT1 0x1000 132238104Sdes#define E1000_FA_FAULT2 0x2000 133238104Sdes#define E1000_FA_NEXT_PAGE 0x8000 134238104Sdes 135238104Sdes#define E1000_LPAR 0x05 /* autoneg link partner abilities reg */ 136238104Sdes#define E1000_LPAR_SELECTOR_FIELD 0x0001 137238104Sdes#define E1000_LPAR_10T 0x0020 138238104Sdes#define E1000_LPAR_10T_FD 0x0040 139238104Sdes#define E1000_LPAR_100TX 0x0080 140238104Sdes#define E1000_LPAR_100TX_FD 0x0100 141238104Sdes#define E1000_LPAR_100T4 0x0200 142238104Sdes#define E1000_LPAR_PAUSE 0x0400 143238104Sdes#define E1000_LPAR_ASM_DIR 0x0800 144238104Sdes#define E1000_LPAR_REMOTE_FAULT 0x2000 145238104Sdes#define E1000_LPAR_ACKNOWLEDGE 0x4000 146238104Sdes#define E1000_LPAR_NEXT_PAGE 0x8000 147238104Sdes 148238104Sdes/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */ 149238104Sdes#define E1000_FPAR_1000X_FD 0x0020 150238104Sdes#define E1000_FPAR_1000X 0x0040 151238104Sdes#define E1000_FPAR_SYM_PAUSE 0x0080 152238104Sdes#define E1000_FPAR_ASYM_PAUSE 0x0100 153238104Sdes#define E1000_FPAR_FAULT1 0x1000 154238104Sdes#define E1000_FPAR_FAULT2 0x2000 155238104Sdes#define E1000_FPAR_ACK 0x4000 156238104Sdes#define E1000_FPAR_NEXT_PAGE 0x8000 157238104Sdes 158238104Sdes#define E1000_ER 0x06 /* autoneg expansion reg */ 159238104Sdes#define E1000_ER_LP_NWAY 0x0001 160238104Sdes#define E1000_ER_PAGE_RXD 0x0002 161238104Sdes#define E1000_ER_NEXT_PAGE 0x0004 162238104Sdes#define E1000_ER_LP_NEXT_PAGE 0x0008 163238104Sdes#define E1000_ER_PAR_DETECT_FAULT 0x0100 164238104Sdes 165238104Sdes#define E1000_NPTX 0x07 /* autoneg next page TX */ 166238104Sdes#define E1000_NPTX_MSG_CODE_FIELD 0x0001 167238104Sdes#define E1000_NPTX_TOGGLE 0x0800 168238104Sdes#define E1000_NPTX_ACKNOWLDGE2 0x1000 169238104Sdes#define E1000_NPTX_MSG_PAGE 0x2000 170238104Sdes#define E1000_NPTX_NEXT_PAGE 0x8000 171238104Sdes 172238104Sdes#define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */ 173238104Sdes#define E1000_RNPR_MSG_CODE_FIELD 0x0001 174238104Sdes#define E1000_RNPR_TOGGLE 0x0800 175238104Sdes#define E1000_RNPR_ACKNOWLDGE2 0x1000 176238104Sdes#define E1000_RNPR_MSG_PAGE 0x2000 177238104Sdes#define E1000_RNPR_ACKNOWLDGE 0x4000 178238104Sdes#define E1000_RNPR_NEXT_PAGE 0x8000 179238104Sdes 180238104Sdes#define E1000_1GCR 0x09 /* 1000T (1G) control reg */ 181238104Sdes#define E1000_1GCR_ASYM_PAUSE 0x0080 182238104Sdes#define E1000_1GCR_1000T 0x0100 183238104Sdes#define E1000_1GCR_1000T_FD 0x0200 184238104Sdes#define E1000_1GCR_REPEATER_DTE 0x0400 185238104Sdes#define E1000_1GCR_MS_VALUE 0x0800 186238104Sdes#define E1000_1GCR_MS_ENABLE 0x1000 187238104Sdes#define E1000_1GCR_TEST_MODE_NORMAL 0x0000 188238104Sdes#define E1000_1GCR_TEST_MODE_1 0x2000 189238104Sdes#define E1000_1GCR_TEST_MODE_2 0x4000 190238104Sdes#define E1000_1GCR_TEST_MODE_3 0x6000 191238104Sdes#define E1000_1GCR_TEST_MODE_4 0x8000 192238104Sdes#define E1000_1GCR_SPEED_MASK 0x0300 193238104Sdes 194238104Sdes#define E1000_1GSR 0x0A /* 1000T (1G) status reg */ 195238104Sdes#define E1000_1GSR_IDLE_ERROR_CNT 0x0000 196238104Sdes#define E1000_1GSR_ASYM_PAUSE_DIR 0x0100 197238104Sdes#define E1000_1GSR_LP 0x0400 198238104Sdes#define E1000_1GSR_LP_FD 0x0800 199238104Sdes#define E1000_1GSR_REMOTE_RX_STATUS 0x1000 200238104Sdes#define E1000_1GSR_LOCAL_RX_STATUS 0x2000 201238104Sdes#define E1000_1GSR_MS_CONFIG_RES 0x4000 202238104Sdes#define E1000_1GSR_MS_CONFIG_FAULT 0x8000 203238104Sdes 204238104Sdes#define E1000_ESR 0x0F /* IEEE extended status reg */ 205238104Sdes#define E1000_ESR_1000T 0x1000 206238104Sdes#define E1000_ESR_1000T_FD 0x2000 207238104Sdes#define E1000_ESR_1000X 0x4000 208238104Sdes#define E1000_ESR_1000X_FD 0x8000 209238104Sdes 210238104Sdes#define E1000_TX_POLARITY_MASK 0x0100 211238104Sdes#define E1000_TX_NORMAL_POLARITY 0 212238104Sdes 213238104Sdes#define E1000_AUTO_POLARITY_DISABLE 0x0010 214238104Sdes 215238104Sdes#define E1000_SCR 0x10 /* special control register */ 216238104Sdes#define E1000_SCR_JABBER_DISABLE 0x0001 217238104Sdes#define E1000_SCR_POLARITY_REVERSAL 0x0002 218238104Sdes#define E1000_SCR_SQE_TEST 0x0004 219238104Sdes#define E1000_SCR_INT_FIFO_DISABLE 0x0008 220238104Sdes#define E1000_SCR_CLK125_DISABLE 0x0010 221238104Sdes#define E1000_SCR_MDI_MANUAL_MODE 0x0000 222238104Sdes#define E1000_SCR_MDIX_MANUAL_MODE 0x0020 223238104Sdes#define E1000_SCR_AUTO_X_1000T 0x0040 224238104Sdes#define E1000_SCR_AUTO_X_MODE 0x0060 225238104Sdes#define E1000_SCR_10BT_EXT_ENABLE 0x0080 226238104Sdes#define E1000_SCR_MII_5BIT_ENABLE 0x0100 227238104Sdes#define E1000_SCR_SCRAMBLER_DISABLE 0x0200 228238104Sdes#define E1000_SCR_FORCE_LINK_GOOD 0x0400 229238104Sdes#define E1000_SCR_ASSERT_CRS_ON_TX 0x0800 230238104Sdes#define E1000_SCR_RX_FIFO_DEPTH_6 0x0000 231238104Sdes#define E1000_SCR_RX_FIFO_DEPTH_8 0x1000 232238104Sdes#define E1000_SCR_RX_FIFO_DEPTH_10 0x2000 233238104Sdes#define E1000_SCR_RX_FIFO_DEPTH_12 0x3000 234238104Sdes#define E1000_SCR_TX_FIFO_DEPTH_6 0x0000 235238104Sdes#define E1000_SCR_TX_FIFO_DEPTH_8 0x4000 236238104Sdes#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000 237238104Sdes#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000 238238104Sdes 239238104Sdes#define E1000_SCR_EN_DETECT_MASK 0x0300 240238104Sdes 241238104Sdes/* 88E1112 page 2 */ 242238104Sdes#define E1000_SCR_MODE_MASK 0x0380 243238104Sdes#define E1000_SCR_MODE_AUTO 0x0180 244238104Sdes#define E1000_SCR_MODE_COPPER 0x0280 245238104Sdes#define E1000_SCR_MODE_1000BX 0x0380 246238104Sdes 247238104Sdes/* 88E1116 page 0 */ 248238104Sdes#define E1000_SCR_POWER_DOWN 0x0004 249238104Sdes/* 88E1116 page 2 */ 250238104Sdes#define E1000_SCR_RGMII_POWER_UP 0x0008 251238104Sdes 252238104Sdes#define E1000_SSR 0x11 /* special status register */ 253238104Sdes#define E1000_SSR_JABBER 0x0001 254238104Sdes#define E1000_SSR_REV_POLARITY 0x0002 255238104Sdes#define E1000_SSR_MDIX 0x0020 256238104Sdes#define E1000_SSR_LINK 0x0400 257238104Sdes#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800 258238104Sdes#define E1000_SSR_PAGE_RCVD 0x1000 259238104Sdes#define E1000_SSR_DUPLEX 0x2000 260238104Sdes#define E1000_SSR_SPEED 0xC000 261238104Sdes#define E1000_SSR_10MBS 0x0000 262238104Sdes#define E1000_SSR_100MBS 0x4000 263238104Sdes#define E1000_SSR_1000MBS 0x8000 264238104Sdes 265238104Sdes#define E1000_IER 0x12 /* interrupt enable reg */ 266238104Sdes#define E1000_IER_JABBER 0x0001 267238104Sdes#define E1000_IER_POLARITY_CHANGE 0x0002 268238104Sdes#define E1000_IER_MDIX_CHANGE 0x0040 269238104Sdes#define E1000_IER_FIFO_OVER_UNDERUN 0x0080 270238104Sdes#define E1000_IER_FALSE_CARRIER 0x0100 271238104Sdes#define E1000_IER_SYMBOL_ERROR 0x0200 272238104Sdes#define E1000_IER_LINK_STAT_CHANGE 0x0400 273238104Sdes#define E1000_IER_AUTO_NEG_COMPLETE 0x0800 274238104Sdes#define E1000_IER_PAGE_RECEIVED 0x1000 275238104Sdes#define E1000_IER_DUPLEX_CHANGED 0x2000 276238104Sdes#define E1000_IER_SPEED_CHANGED 0x4000 277238104Sdes#define E1000_IER_AUTO_NEG_ERR 0x8000 278238104Sdes 279238104Sdes#define E1000_ISR 0x13 /* interrupt status reg */ 280238104Sdes#define E1000_ISR_JABBER 0x0001 281238104Sdes#define E1000_ISR_POLARITY_CHANGE 0x0002 282238104Sdes#define E1000_ISR_MDIX_CHANGE 0x0040 283238104Sdes#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080 284238104Sdes#define E1000_ISR_FALSE_CARRIER 0x0100 285238104Sdes#define E1000_ISR_SYMBOL_ERROR 0x0200 286238104Sdes#define E1000_ISR_LINK_STAT_CHANGE 0x0400 287238104Sdes#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800 288238104Sdes#define E1000_ISR_PAGE_RECEIVED 0x1000 289238104Sdes#define E1000_ISR_DUPLEX_CHANGED 0x2000 290238104Sdes#define E1000_ISR_SPEED_CHANGED 0x4000 291238104Sdes#define E1000_ISR_AUTO_NEG_ERR 0x8000 292238104Sdes 293238104Sdes#define E1000_ESCR 0x14 /* extended special control reg */ 294238104Sdes#define E1000_ESCR_FIBER_LOOPBACK 0x4000 295238104Sdes#define E1000_ESCR_DOWN_NO_IDLE 0x8000 296238104Sdes#define E1000_ESCR_TX_CLK_2_5 0x0060 297238104Sdes#define E1000_ESCR_TX_CLK_25 0x0070 298238104Sdes#define E1000_ESCR_TX_CLK_0 0x0000 299238104Sdes 300238104Sdes#define E1000_RECR 0x15 /* RX error counter reg */ 301238104Sdes 302238104Sdes#define E1000_EADR 0x16 /* extended address reg */ 303238104Sdes 304238104Sdes#define E1000_LCR 0x18 /* LED control reg */ 305238104Sdes#define E1000_LCR_LED_TX 0x0001 306238104Sdes#define E1000_LCR_LED_RX 0x0002 307238104Sdes#define E1000_LCR_LED_DUPLEX 0x0004 308238104Sdes#define E1000_LCR_LINK 0x0008 309238104Sdes#define E1000_LCR_BLINK_42MS 0x0000 310238104Sdes#define E1000_LCR_BLINK_84MS 0x0100 311238104Sdes#define E1000_LCR_BLINK_170MS 0x0200 312238104Sdes#define E1000_LCR_BLINK_340MS 0x0300 313238104Sdes#define E1000_LCR_BLINK_670MS 0x0400 314238104Sdes#define E1000_LCR_PULSE_OFF 0x0000 315238104Sdes#define E1000_LCR_PULSE_21_42MS 0x1000 316238104Sdes#define E1000_LCR_PULSE_42_84MS 0x2000 317238104Sdes#define E1000_LCR_PULSE_84_170MS 0x3000 318238104Sdes#define E1000_LCR_PULSE_170_340MS 0x4000 319238104Sdes#define E1000_LCR_PULSE_340_670MS 0x5000 320238104Sdes#define E1000_LCR_PULSE_670_13S 0x6000 321238104Sdes#define E1000_LCR_PULSE_13_26S 0x7000 322238104Sdes 323238104Sdes/* The following register is found only on the 88E1011 Alaska PHY */ 324238104Sdes#define E1000_ESSR 0x1B /* Extended PHY specific sts */ 325238104Sdes#define E1000_ESSR_FIBER_LINK 0x2000 326238104Sdes#define E1000_ESSR_GMII_COPPER 0x000f 327238104Sdes#define E1000_ESSR_GMII_FIBER 0x0007 328238104Sdes#define E1000_ESSR_TBI_COPPER 0x000d 329238104Sdes#define E1000_ESSR_TBI_FIBER 0x0005 330238104Sdes