ciphy.c revision 213364 
1/*-
2 * Copyright (c) 2004
3 *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 *    may be used to endorse or promote products derived from this software
18 *    without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/ciphy.c 213364 2010-10-02 18:53:12Z marius $");
35
36/*
37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/if_arp.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/ciphyreg.h>
56
57#include "miibus_if.h"
58
59#include <machine/bus.h>
60/*
61#include <dev/vge/if_vgereg.h>
62*/
63static int ciphy_probe(device_t);
64static int ciphy_attach(device_t);
65
66static device_method_t ciphy_methods[] = {
67	/* device interface */
68	DEVMETHOD(device_probe,		ciphy_probe),
69	DEVMETHOD(device_attach,	ciphy_attach),
70	DEVMETHOD(device_detach,	mii_phy_detach),
71	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
72	{ 0, 0 }
73};
74
75static devclass_t ciphy_devclass;
76
77static driver_t ciphy_driver = {
78	"ciphy",
79	ciphy_methods,
80	sizeof(struct mii_softc)
81};
82
83DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
84
85static int	ciphy_service(struct mii_softc *, struct mii_data *, int);
86static void	ciphy_status(struct mii_softc *);
87static void	ciphy_reset(struct mii_softc *);
88static void	ciphy_fixup(struct mii_softc *);
89
90static const struct mii_phydesc ciphys[] = {
91	MII_PHY_DESC(CICADA, CS8201),
92	MII_PHY_DESC(CICADA, CS8201A),
93	MII_PHY_DESC(CICADA, CS8201B),
94	MII_PHY_DESC(CICADA, CS8204),
95	MII_PHY_DESC(CICADA, VSC8211),
96	MII_PHY_DESC(CICADA, CS8244),
97	MII_PHY_DESC(VITESSE, VSC8601),
98	MII_PHY_END
99};
100
101static int
102ciphy_probe(device_t dev)
103{
104
105	return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
106}
107
108static int
109ciphy_attach(device_t dev)
110{
111	struct mii_softc *sc;
112	struct mii_attach_args *ma;
113	struct mii_data *mii;
114
115	sc = device_get_softc(dev);
116	ma = device_get_ivars(dev);
117	sc->mii_dev = device_get_parent(dev);
118	mii = ma->mii_data;
119	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
120
121	sc->mii_inst = mii->mii_instance++;
122	sc->mii_phy = ma->mii_phyno;
123	sc->mii_service = ciphy_service;
124	sc->mii_pdata = mii;
125
126	sc->mii_flags |= MIIF_NOISOLATE;
127
128	ciphy_reset(sc);
129
130	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
131	if (sc->mii_capabilities & BMSR_EXTSTAT)
132		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
133	device_printf(dev, " ");
134	mii_phy_add_media(sc);
135	printf("\n");
136
137	MIIBUS_MEDIAINIT(sc->mii_dev);
138	return (0);
139}
140
141static int
142ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
143{
144	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
145	int reg, speed, gig;
146
147	switch (cmd) {
148	case MII_POLLSTAT:
149		break;
150
151	case MII_MEDIACHG:
152		/*
153		 * If the interface is not up, don't do anything.
154		 */
155		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
156			break;
157
158		ciphy_fixup(sc);	/* XXX hardware bug work-around */
159
160		switch (IFM_SUBTYPE(ife->ifm_media)) {
161		case IFM_AUTO:
162#ifdef foo
163			/*
164			 * If we're already in auto mode, just return.
165			 */
166			if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
167				return (0);
168#endif
169			(void) mii_phy_auto(sc);
170			break;
171		case IFM_1000_T:
172			speed = CIPHY_S1000;
173			goto setit;
174		case IFM_100_TX:
175			speed = CIPHY_S100;
176			goto setit;
177		case IFM_10_T:
178			speed = CIPHY_S10;
179setit:
180			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
181				speed |= CIPHY_BMCR_FDX;
182				gig = CIPHY_1000CTL_AFD;
183			} else {
184				gig = CIPHY_1000CTL_AHD;
185			}
186
187			PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
188			PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
189			PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
190
191			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
192				break;
193
194			PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
195			PHY_WRITE(sc, CIPHY_MII_BMCR,
196			    speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
197
198			/*
199			 * When setting the link manually, one side must
200			 * be the master and the other the slave. However
201			 * ifmedia doesn't give us a good way to specify
202			 * this, so we fake it by using one of the LINK
203			 * flags. If LINK0 is set, we program the PHY to
204			 * be a master, otherwise it's a slave.
205			 */
206			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
207				PHY_WRITE(sc, CIPHY_MII_1000CTL,
208				    gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
209			} else {
210				PHY_WRITE(sc, CIPHY_MII_1000CTL,
211				    gig|CIPHY_1000CTL_MSE);
212			}
213			break;
214		case IFM_NONE:
215			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
216			break;
217		case IFM_100_T4:
218		default:
219			return (EINVAL);
220		}
221		break;
222
223	case MII_TICK:
224		/*
225		 * Is the interface even up?
226		 */
227		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
228			return (0);
229
230		/*
231		 * Only used for autonegotiation.
232		 */
233		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
234			break;
235
236		/*
237		 * Check to see if we have link.  If we do, we don't
238		 * need to restart the autonegotiation process.  Read
239		 * the BMSR twice in case it's latched.
240		 */
241		reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
242		if (reg & BMSR_LINK)
243			break;
244
245		/* Announce link loss right after it happens. */
246		if (++sc->mii_ticks == 0)
247			break;
248		/*
249		 * Only retry autonegotiation every mii_anegticks seconds.
250		 */
251		if (sc->mii_ticks <= sc->mii_anegticks)
252			break;
253
254		sc->mii_ticks = 0;
255		mii_phy_auto(sc);
256		break;
257	}
258
259	/* Update the media status. */
260	ciphy_status(sc);
261
262	/*
263	 * Callback if something changed. Note that we need to poke
264	 * apply fixups for certain PHY revs.
265	 */
266	if (sc->mii_media_active != mii->mii_media_active ||
267	    sc->mii_media_status != mii->mii_media_status ||
268	    cmd == MII_MEDIACHG) {
269		ciphy_fixup(sc);
270	}
271	mii_phy_update(sc, cmd);
272	return (0);
273}
274
275static void
276ciphy_status(struct mii_softc *sc)
277{
278	struct mii_data *mii = sc->mii_pdata;
279	int bmsr, bmcr;
280
281	mii->mii_media_status = IFM_AVALID;
282	mii->mii_media_active = IFM_ETHER;
283
284	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
285
286	if (bmsr & BMSR_LINK)
287		mii->mii_media_status |= IFM_ACTIVE;
288
289	bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
290
291	if (bmcr & CIPHY_BMCR_LOOP)
292		mii->mii_media_active |= IFM_LOOP;
293
294	if (bmcr & CIPHY_BMCR_AUTOEN) {
295		if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
296			/* Erg, still trying, I guess... */
297			mii->mii_media_active |= IFM_NONE;
298			return;
299		}
300	}
301
302	bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
303	switch (bmsr & CIPHY_AUXCSR_SPEED) {
304	case CIPHY_SPEED10:
305		mii->mii_media_active |= IFM_10_T;
306		break;
307	case CIPHY_SPEED100:
308		mii->mii_media_active |= IFM_100_TX;
309		break;
310	case CIPHY_SPEED1000:
311		mii->mii_media_active |= IFM_1000_T;
312		break;
313	default:
314		device_printf(sc->mii_dev, "unknown PHY speed %x\n",
315		    bmsr & CIPHY_AUXCSR_SPEED);
316		break;
317	}
318
319	if (bmsr & CIPHY_AUXCSR_FDX)
320		mii->mii_media_active |= IFM_FDX;
321	else
322		mii->mii_media_active |= IFM_HDX;
323}
324
325static void
326ciphy_reset(struct mii_softc *sc)
327{
328
329	mii_phy_reset(sc);
330	DELAY(1000);
331}
332
333#define PHY_SETBIT(x, y, z) \
334	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
335#define PHY_CLRBIT(x, y, z) \
336	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
337
338static void
339ciphy_fixup(struct mii_softc *sc)
340{
341	uint16_t		model;
342	uint16_t		status, speed;
343	uint16_t		val;
344
345	model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
346	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
347	speed = status & CIPHY_AUXCSR_SPEED;
348
349	if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
350	    "nfe") == 0) {
351		/* need to set for 2.5V RGMII for NVIDIA adapters */
352		val = PHY_READ(sc, CIPHY_MII_ECTL1);
353		val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
354		val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
355		PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
356		/* From Linux. */
357		val = PHY_READ(sc, CIPHY_MII_AUXCSR);
358		val |= CIPHY_AUXCSR_MDPPS;
359		PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
360		val = PHY_READ(sc, CIPHY_MII_10BTCSR);
361		val |= CIPHY_10BTCSR_ECHO;
362		PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
363	}
364
365	switch (model) {
366	case MII_MODEL_CICADA_CS8204:
367	case MII_MODEL_CICADA_CS8201:
368
369		/* Turn off "aux mode" (whatever that means) */
370		PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
371
372		/*
373		 * Work around speed polling bug in VT3119/VT3216
374		 * when using MII in full duplex mode.
375		 */
376		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
377		    (status & CIPHY_AUXCSR_FDX)) {
378			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
379		} else {
380			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
381		}
382
383		/* Enable link/activity LED blink. */
384		PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
385
386		break;
387
388	case MII_MODEL_CICADA_CS8201A:
389	case MII_MODEL_CICADA_CS8201B:
390
391		/*
392		 * Work around speed polling bug in VT3119/VT3216
393		 * when using MII in full duplex mode.
394		 */
395		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
396		    (status & CIPHY_AUXCSR_FDX)) {
397			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
398		} else {
399			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
400		}
401
402		break;
403	case MII_MODEL_CICADA_VSC8211:
404	case MII_MODEL_CICADA_CS8244:
405	case MII_MODEL_VITESSE_VSC8601:
406		break;
407	default:
408		device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
409		    model);
410		break;
411	}
412}
413