ciphy.c revision 213229
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/mii/ciphy.c 213229 2010-09-27 20:31:03Z marius $"); 35 36/* 37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/bus.h> 46 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_media.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include "miidevs.h" 54 55#include <dev/mii/ciphyreg.h> 56 57#include "miibus_if.h" 58 59#include <machine/bus.h> 60/* 61#include <dev/vge/if_vgereg.h> 62*/ 63static int ciphy_probe(device_t); 64static int ciphy_attach(device_t); 65 66static device_method_t ciphy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, ciphy_probe), 69 DEVMETHOD(device_attach, ciphy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73}; 74 75static devclass_t ciphy_devclass; 76 77static driver_t ciphy_driver = { 78 "ciphy", 79 ciphy_methods, 80 sizeof(struct mii_softc) 81}; 82 83DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 84 85static int ciphy_service(struct mii_softc *, struct mii_data *, int); 86static void ciphy_status(struct mii_softc *); 87static void ciphy_reset(struct mii_softc *); 88static void ciphy_fixup(struct mii_softc *); 89 90static const struct mii_phydesc ciphys[] = { 91 MII_PHY_DESC(CICADA, CS8201), 92 MII_PHY_DESC(CICADA, CS8201A), 93 MII_PHY_DESC(CICADA, CS8201B), 94 MII_PHY_DESC(CICADA, CS8204), 95 MII_PHY_DESC(CICADA, VSC8211), 96 MII_PHY_DESC(CICADA, CS8244), 97 MII_PHY_DESC(VITESSE, VSC8601), 98 MII_PHY_END 99}; 100 101static int 102ciphy_probe(device_t dev) 103{ 104 105 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT)); 106} 107 108static int 109ciphy_attach(device_t dev) 110{ 111 struct mii_softc *sc; 112 struct mii_attach_args *ma; 113 struct mii_data *mii; 114 115 sc = device_get_softc(dev); 116 ma = device_get_ivars(dev); 117 sc->mii_dev = device_get_parent(dev); 118 mii = ma->mii_data; 119 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 120 121 sc->mii_inst = mii->mii_instance; 122 sc->mii_phy = ma->mii_phyno; 123 sc->mii_service = ciphy_service; 124 sc->mii_pdata = mii; 125 126 sc->mii_flags |= MIIF_NOISOLATE; 127 mii->mii_instance++; 128 129 ciphy_reset(sc); 130 131 sc->mii_capabilities = 132 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 133 if (sc->mii_capabilities & BMSR_EXTSTAT) 134 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 135 device_printf(dev, " "); 136 mii_phy_add_media(sc); 137 printf("\n"); 138 139 MIIBUS_MEDIAINIT(sc->mii_dev); 140 return (0); 141} 142 143static int 144ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 145{ 146 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 147 int reg, speed, gig; 148 149 switch (cmd) { 150 case MII_POLLSTAT: 151 /* 152 * If we're not polling our PHY instance, just return. 153 */ 154 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 155 return (0); 156 break; 157 158 case MII_MEDIACHG: 159 /* 160 * If the media indicates a different PHY instance, 161 * isolate ourselves. 162 */ 163 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 164 reg = PHY_READ(sc, MII_BMCR); 165 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 166 return (0); 167 } 168 169 /* 170 * If the interface is not up, don't do anything. 171 */ 172 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 173 break; 174 175 ciphy_fixup(sc); /* XXX hardware bug work-around */ 176 177 switch (IFM_SUBTYPE(ife->ifm_media)) { 178 case IFM_AUTO: 179#ifdef foo 180 /* 181 * If we're already in auto mode, just return. 182 */ 183 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 184 return (0); 185#endif 186 (void) mii_phy_auto(sc); 187 break; 188 case IFM_1000_T: 189 speed = CIPHY_S1000; 190 goto setit; 191 case IFM_100_TX: 192 speed = CIPHY_S100; 193 goto setit; 194 case IFM_10_T: 195 speed = CIPHY_S10; 196setit: 197 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 198 speed |= CIPHY_BMCR_FDX; 199 gig = CIPHY_1000CTL_AFD; 200 } else { 201 gig = CIPHY_1000CTL_AHD; 202 } 203 204 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); 205 PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 206 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 207 208 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 209 break; 210 211 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 212 PHY_WRITE(sc, CIPHY_MII_BMCR, 213 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); 214 215 /* 216 * When setting the link manually, one side must 217 * be the master and the other the slave. However 218 * ifmedia doesn't give us a good way to specify 219 * this, so we fake it by using one of the LINK 220 * flags. If LINK0 is set, we program the PHY to 221 * be a master, otherwise it's a slave. 222 */ 223 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 224 PHY_WRITE(sc, CIPHY_MII_1000CTL, 225 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); 226 } else { 227 PHY_WRITE(sc, CIPHY_MII_1000CTL, 228 gig|CIPHY_1000CTL_MSE); 229 } 230 break; 231 case IFM_NONE: 232 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 233 break; 234 case IFM_100_T4: 235 default: 236 return (EINVAL); 237 } 238 break; 239 240 case MII_TICK: 241 /* 242 * If we're not currently selected, just return. 243 */ 244 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 245 return (0); 246 247 /* 248 * Is the interface even up? 249 */ 250 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 251 return (0); 252 253 /* 254 * Only used for autonegotiation. 255 */ 256 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 257 break; 258 259 /* 260 * Check to see if we have link. If we do, we don't 261 * need to restart the autonegotiation process. Read 262 * the BMSR twice in case it's latched. 263 */ 264 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 265 if (reg & BMSR_LINK) 266 break; 267 268 /* Announce link loss right after it happens. */ 269 if (++sc->mii_ticks == 0) 270 break; 271 /* 272 * Only retry autonegotiation every mii_anegticks seconds. 273 */ 274 if (sc->mii_ticks <= sc->mii_anegticks) 275 break; 276 277 sc->mii_ticks = 0; 278 mii_phy_auto(sc); 279 break; 280 } 281 282 /* Update the media status. */ 283 ciphy_status(sc); 284 285 /* 286 * Callback if something changed. Note that we need to poke 287 * apply fixups for certain PHY revs. 288 */ 289 if (sc->mii_media_active != mii->mii_media_active || 290 sc->mii_media_status != mii->mii_media_status || 291 cmd == MII_MEDIACHG) { 292 ciphy_fixup(sc); 293 } 294 mii_phy_update(sc, cmd); 295 return (0); 296} 297 298static void 299ciphy_status(struct mii_softc *sc) 300{ 301 struct mii_data *mii = sc->mii_pdata; 302 int bmsr, bmcr; 303 304 mii->mii_media_status = IFM_AVALID; 305 mii->mii_media_active = IFM_ETHER; 306 307 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 308 309 if (bmsr & BMSR_LINK) 310 mii->mii_media_status |= IFM_ACTIVE; 311 312 bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 313 314 if (bmcr & CIPHY_BMCR_LOOP) 315 mii->mii_media_active |= IFM_LOOP; 316 317 if (bmcr & CIPHY_BMCR_AUTOEN) { 318 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 319 /* Erg, still trying, I guess... */ 320 mii->mii_media_active |= IFM_NONE; 321 return; 322 } 323 } 324 325 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 326 switch (bmsr & CIPHY_AUXCSR_SPEED) { 327 case CIPHY_SPEED10: 328 mii->mii_media_active |= IFM_10_T; 329 break; 330 case CIPHY_SPEED100: 331 mii->mii_media_active |= IFM_100_TX; 332 break; 333 case CIPHY_SPEED1000: 334 mii->mii_media_active |= IFM_1000_T; 335 break; 336 default: 337 device_printf(sc->mii_dev, "unknown PHY speed %x\n", 338 bmsr & CIPHY_AUXCSR_SPEED); 339 break; 340 } 341 342 if (bmsr & CIPHY_AUXCSR_FDX) 343 mii->mii_media_active |= IFM_FDX; 344 else 345 mii->mii_media_active |= IFM_HDX; 346} 347 348static void 349ciphy_reset(struct mii_softc *sc) 350{ 351 352 mii_phy_reset(sc); 353 DELAY(1000); 354} 355 356#define PHY_SETBIT(x, y, z) \ 357 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 358#define PHY_CLRBIT(x, y, z) \ 359 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 360 361static void 362ciphy_fixup(struct mii_softc *sc) 363{ 364 uint16_t model; 365 uint16_t status, speed; 366 uint16_t val; 367 368 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 369 status = PHY_READ(sc, CIPHY_MII_AUXCSR); 370 speed = status & CIPHY_AUXCSR_SPEED; 371 372 if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), 373 "nfe") == 0) { 374 /* need to set for 2.5V RGMII for NVIDIA adapters */ 375 val = PHY_READ(sc, CIPHY_MII_ECTL1); 376 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); 377 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); 378 PHY_WRITE(sc, CIPHY_MII_ECTL1, val); 379 /* From Linux. */ 380 val = PHY_READ(sc, CIPHY_MII_AUXCSR); 381 val |= CIPHY_AUXCSR_MDPPS; 382 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); 383 val = PHY_READ(sc, CIPHY_MII_10BTCSR); 384 val |= CIPHY_10BTCSR_ECHO; 385 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); 386 } 387 388 switch (model) { 389 case MII_MODEL_CICADA_CS8204: 390 case MII_MODEL_CICADA_CS8201: 391 392 /* Turn off "aux mode" (whatever that means) */ 393 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 394 395 /* 396 * Work around speed polling bug in VT3119/VT3216 397 * when using MII in full duplex mode. 398 */ 399 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 400 (status & CIPHY_AUXCSR_FDX)) { 401 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 402 } else { 403 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 404 } 405 406 /* Enable link/activity LED blink. */ 407 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 408 409 break; 410 411 case MII_MODEL_CICADA_CS8201A: 412 case MII_MODEL_CICADA_CS8201B: 413 414 /* 415 * Work around speed polling bug in VT3119/VT3216 416 * when using MII in full duplex mode. 417 */ 418 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 419 (status & CIPHY_AUXCSR_FDX)) { 420 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 421 } else { 422 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 423 } 424 425 break; 426 case MII_MODEL_CICADA_VSC8211: 427 case MII_MODEL_CICADA_CS8244: 428 case MII_MODEL_VITESSE_VSC8601: 429 break; 430 default: 431 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", 432 model); 433 break; 434 } 435} 436