brgphyreg.h revision 256281
1292068Ssjg/*- 2236769Sobrien * Copyright (c) 2000 3236769Sobrien * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4236769Sobrien * 5236769Sobrien * Redistribution and use in source and binary forms, with or without 6236769Sobrien * modification, are permitted provided that the following conditions 7236769Sobrien * are met: 8236769Sobrien * 1. Redistributions of source code must retain the above copyright 9236769Sobrien * notice, this list of conditions and the following disclaimer. 10236769Sobrien * 2. Redistributions in binary form must reproduce the above copyright 11236769Sobrien * notice, this list of conditions and the following disclaimer in the 12236769Sobrien * documentation and/or other materials provided with the distribution. 13236769Sobrien * 3. All advertising materials mentioning features or use of this software 14236769Sobrien * must display the following acknowledgement: 15236769Sobrien * This product includes software developed by Bill Paul. 16236769Sobrien * 4. Neither the name of the author nor the names of any co-contributors 17236769Sobrien * may be used to endorse or promote products derived from this software 18236769Sobrien * without specific prior written permission. 19236769Sobrien * 20236769Sobrien * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21236769Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22236769Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23236769Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24236769Sobrien * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25236769Sobrien * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26236769Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27236769Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28236769Sobrien * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29236769Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30236769Sobrien * THE POSSIBILITY OF SUCH DAMAGE. 31236769Sobrien * 32236769Sobrien * $FreeBSD: stable/10/sys/dev/mii/brgphyreg.h 220938 2011-04-22 09:22:27Z marius $ 33236769Sobrien */ 34236769Sobrien 35236769Sobrien#ifndef _DEV_MII_BRGPHYREG_H_ 36236769Sobrien#define _DEV_MII_BRGPHYREG_H_ 37236769Sobrien 38236769Sobrien/* 39236769Sobrien * Broadcom BCM5400 registers 40236769Sobrien */ 41292068Ssjg 42236769Sobrien#define BRGPHY_MII_BMCR 0x00 43292068Ssjg#define BRGPHY_BMCR_RESET 0x8000 44292068Ssjg#define BRGPHY_BMCR_LOOP 0x4000 45292068Ssjg#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ 46236769Sobrien#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 47236769Sobrien#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ 48236769Sobrien#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ 49236769Sobrien#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ 50236769Sobrien#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ 51236769Sobrien#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 52236769Sobrien#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ 53236769Sobrien 54236769Sobrien#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ 55236769Sobrien#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ 56236769Sobrien#define BRGPHY_S10 0 /* 10mbps */ 57236769Sobrien 58236769Sobrien#define BRGPHY_MII_BMSR 0x01 59236769Sobrien#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 60236769Sobrien#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 61236769Sobrien#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 62253883Ssjg#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occurred */ 63253883Ssjg#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 64236769Sobrien#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ 65253883Ssjg#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 66253883Ssjg#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */ 67253883Ssjg 68253883Ssjg#define BRGPHY_MII_ANAR 0x04 69236769Sobrien#define BRGPHY_ANAR_NP 0x8000 /* Next page */ 70236769Sobrien#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */ 71236769Sobrien#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ 72236769Sobrien#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */ 73236769Sobrien#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 74236769Sobrien 75236769Sobrien#define BRGPHY_MII_ANLPAR 0x05 76236769Sobrien#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */ 77236769Sobrien#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */ 78236769Sobrien#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ 79236769Sobrien#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */ 80238152Sobrien#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 81236769Sobrien 82236769Sobrien#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */ 83236769Sobrien 84236769Sobrien#define BRGPHY_MII_ANER 0x06 85236769Sobrien#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */ 86236769Sobrien#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */ 87236769Sobrien#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */ 88236769Sobrien#define BRGPHY_ANER_RX 0x0002 /* Next page received */ 89236769Sobrien#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ 90236769Sobrien 91236769Sobrien#define BRGPHY_MII_NEXTP 0x07 /* Next page */ 92236769Sobrien 93236769Sobrien#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ 94236769Sobrien 95236769Sobrien#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ 96236769Sobrien#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */ 97236769Sobrien#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ 98236769Sobrien#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ 99236769Sobrien#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ 100236769Sobrien#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ 101236769Sobrien#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ 102236769Sobrien 103236769Sobrien#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */ 104236769Sobrien#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */ 105236769Sobrien#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */ 106236769Sobrien#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */ 107236769Sobrien#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */ 108236769Sobrien#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ 109236769Sobrien#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ 110236769Sobrien#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */ 111236769Sobrien 112236769Sobrien#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */ 113236769Sobrien#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ 114236769Sobrien#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ 115236769Sobrien#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ 116236769Sobrien#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ 117236769Sobrien 118236769Sobrien#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ 119236769Sobrien#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ 120236769Sobrien#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ 121236769Sobrien#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */ 122236769Sobrien#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ 123236769Sobrien#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ 124236769Sobrien#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ 125236769Sobrien#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ 126236769Sobrien#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ 127236769Sobrien#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ 128236769Sobrien#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ 129236769Sobrien#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ 130236769Sobrien#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ 131236769Sobrien#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ 132236769Sobrien#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ 133236769Sobrien#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ 134236769Sobrien#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ 135236769Sobrien 136236769Sobrien#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ 137236769Sobrien#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ 138236769Sobrien#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ 139236769Sobrien#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ 140236769Sobrien#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ 141236769Sobrien#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ 142236769Sobrien#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ 143236769Sobrien#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ 144236769Sobrien#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ 145236769Sobrien#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ 146236769Sobrien#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ 147236769Sobrien#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ 148236769Sobrien#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ 149236769Sobrien#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ 150236769Sobrien#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ 151236769Sobrien 152236769Sobrien#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ 153236769Sobrien 154236769Sobrien#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ 155236769Sobrien#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ 156236769Sobrien 157236769Sobrien#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ 158236769Sobrien#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ 159236769Sobrien#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ 160236769Sobrien 161236769Sobrien#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ 162236769Sobrien 163292068Ssjg#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ 164236769Sobrien#define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */ 165236769Sobrien 166236769Sobrien#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 167236769Sobrien#define BRGPHY_DSP_AGC_A 0x00 168236769Sobrien#define BRGPHY_DSP_AGC_B 0x01 169236769Sobrien#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 170236769Sobrien#define BRGPHY_DSP_SOFT_DECISION 0x03 171236769Sobrien#define BRGPHY_DSP_PHASE_REG 0x04 172236769Sobrien#define BRGPHY_DSP_SKEW 0x05 173236769Sobrien#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 174292068Ssjg#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 175236769Sobrien#define BRGPHY_DSP_LAST_ECHO 0x08 176292068Ssjg#define BRGPHY_DSP_FREQUENCY 0x09 177292068Ssjg#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A 178236769Sobrien#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B 179236769Sobrien 180292068Ssjg#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 181236769Sobrien#define BRGPHY_DSP_FILTER_FEXT3 0x0B00 182236769Sobrien#define BRGPHY_DSP_FILTER_FEXT2 0x0A00 183236769Sobrien#define BRGPHY_DSP_FILTER_FEXT1 0x0900 184236769Sobrien#define BRGPHY_DSP_FILTER_FEXT0 0x0800 185236769Sobrien#define BRGPHY_DSP_FILTER_NEXT3 0x0700 186236769Sobrien#define BRGPHY_DSP_FILTER_NEXT2 0x0600 187236769Sobrien#define BRGPHY_DSP_FILTER_NEXT1 0x0500 188236769Sobrien#define BRGPHY_DSP_FILTER_NEXT0 0x0400 189236769Sobrien#define BRGPHY_DSP_FILTER_ECHO 0x0300 190236769Sobrien#define BRGPHY_DSP_FILTER_DFE 0x0200 191236769Sobrien#define BRGPHY_DSP_FILTER_FFE 0x0100 192236769Sobrien 193236769Sobrien#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 194236769Sobrien 195236769Sobrien#define BRGPHY_DSP_SEL_CH_0 0x0000 196236769Sobrien#define BRGPHY_DSP_SEL_CH_1 0x2000 197236769Sobrien#define BRGPHY_DSP_SEL_CH_2 0x4000 198236769Sobrien#define BRGPHY_DSP_SEL_CH_3 0x6000 199236769Sobrien 200236769Sobrien#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 201236769Sobrien#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ 202236769Sobrien#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ 203236769Sobrien#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ 204236769Sobrien#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ 205236769Sobrien#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ 206236769Sobrien#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ 207236769Sobrien 208236769Sobrien#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ 209236769Sobrien#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ 210236769Sobrien#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ 211236769Sobrien#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ 212236769Sobrien#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ 213236769Sobrien#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ 214236769Sobrien#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ 215236769Sobrien#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ 216236769Sobrien#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ 217236769Sobrien#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */ 218236769Sobrien#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */ 219236769Sobrien#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ 220236769Sobrien#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ 221236769Sobrien#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ 222236769Sobrien 223236769Sobrien#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ 224236769Sobrien#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ 225236769Sobrien#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ 226236769Sobrien#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ 227236769Sobrien#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ 228236769Sobrien#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ 229236769Sobrien#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ 230236769Sobrien 231236769Sobrien#define BRGPHY_MII_ISR 0x1A /* Interrupt status */ 232236769Sobrien#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ 233236769Sobrien#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ 234236769Sobrien#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ 235236769Sobrien#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ 236236769Sobrien#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ 237236769Sobrien#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ 238236769Sobrien#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ 239236769Sobrien#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 240236769Sobrien#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 241236769Sobrien#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ 242236769Sobrien#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ 243236769Sobrien#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ 244236769Sobrien#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ 245236769Sobrien#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ 246236769Sobrien#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ 247236769Sobrien 248236769Sobrien#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ 249236769Sobrien#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ 250236769Sobrien#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ 251236769Sobrien#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ 252236769Sobrien#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ 253236769Sobrien#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ 254236769Sobrien#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ 255236769Sobrien#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ 256236769Sobrien#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 257236769Sobrien#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 258236769Sobrien#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ 259236769Sobrien#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ 260236769Sobrien#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ 261236769Sobrien#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ 262236769Sobrien#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 263236769Sobrien#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ 264236769Sobrien 265236769Sobrien/*******************************************************/ 266236769Sobrien/* Begin: Shared SerDes PHY register definitions */ 267236769Sobrien/*******************************************************/ 268236769Sobrien 269236769Sobrien/* SerDes autoneg is different from copper */ 270236769Sobrien#define BRGPHY_SERDES_ANAR 0x04 271236769Sobrien#define BRGPHY_SERDES_ANAR_FDX 0x0020 272236769Sobrien#define BRGPHY_SERDES_ANAR_HDX 0x0040 273236769Sobrien#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) 274236769Sobrien#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) 275236769Sobrien#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) 276236769Sobrien#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) 277236769Sobrien 278236769Sobrien#define BRGPHY_SERDES_ANLPAR 0x05 279236769Sobrien#define BRGPHY_SERDES_ANLPAR_FDX 0x0020 280236769Sobrien#define BRGPHY_SERDES_ANLPAR_HDX 0x0040 281236769Sobrien#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) 282236769Sobrien#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) 283236769Sobrien#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) 284236769Sobrien#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) 285236769Sobrien 286236769Sobrien/*******************************************************/ 287236769Sobrien/* End: Shared SerDes PHY register definitions */ 288236769Sobrien/*******************************************************/ 289236769Sobrien 290236769Sobrien/*******************************************************/ 291236769Sobrien/* Begin: PHY register values for the 5706 PHY */ 292236769Sobrien/*******************************************************/ 293236769Sobrien 294236769Sobrien/* 295236769Sobrien * Shadow register 0x1C, bit 15 is write enable, 296236769Sobrien * bits 14-10 select function (0x00 to 0x1F). 297236769Sobrien */ 298236769Sobrien#define BRGPHY_MII_SHADOW_1C 0x1C 299236769Sobrien#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 300236769Sobrien#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 301236769Sobrien 302236769Sobrien/* Shadow 0x1C Mode Control Register (select value 0x1F) */ 303236769Sobrien#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) 304236769Sobrien/* When set, Regs 0-0x0F are 1000X, else 1000T */ 305236769Sobrien#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 306236769Sobrien 307236769Sobrien#define BRGPHY_MII_TEST1 0x1E 308236769Sobrien#define BRGPHY_TEST1_TRIM_EN 0x0010 309236769Sobrien#define BRGPHY_TEST1_CRC_EN 0x8000 310236769Sobrien 311236769Sobrien#define BRGPHY_MII_TEST2 0x1F 312236769Sobrien 313236769Sobrien/*******************************************************/ 314236769Sobrien/* End: PHY register values for the 5706 PHY */ 315236769Sobrien/*******************************************************/ 316236769Sobrien 317236769Sobrien/*******************************************************/ 318236769Sobrien/* Begin: PHY register values for the 5708S SerDes PHY */ 319236769Sobrien/*******************************************************/ 320236769Sobrien 321236769Sobrien/* Autoneg Next Page Transmit 1 Regiser */ 322236769Sobrien#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B 323236769Sobrien#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 324236769Sobrien 325236769Sobrien/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ 326236769Sobrien#define BRGPHY_5708S_BLOCK_ADDR 0x1f 327236769Sobrien#define BRGPHY_5708S_DIG_PG0 0x0000 328236769Sobrien#define BRGPHY_5708S_DIG3_PG2 0x0002 329236769Sobrien#define BRGPHY_5708S_TX_MISC_PG5 0x0005 330236769Sobrien 331292068Ssjg/* 5708S SerDes "Digital" Registers (page 0) */ 332236769Sobrien#define BRGPHY_5708S_PG0_1000X_CTL1 0x10 333236769Sobrien#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 334236769Sobrien#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 335236769Sobrien 336236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1 0x14 337236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 338236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 339236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 340236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) 341236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) 342236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) 343236769Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) 344236769Sobrien 345236769Sobrien 346236769Sobrien#define BRGPHY_5708S_PG0_1000X_CTL2 0x11 347236769Sobrien#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 348236769Sobrien 349236769Sobrien/* 5708S SerDes "Digital 3" Registers (page 2) */ 350236769Sobrien#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 351236769Sobrien#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 352236769Sobrien 353236769Sobrien/* 5708S SerDes "TX Misc" Registers (page 5) */ 354236769Sobrien#define BRGPHY_5708S_PG5_2500STATUS1 0x10 355236769Sobrien#define BRGPHY_5708S_PG5_TXACTL1 0x15 356236769Sobrien#define BRGPHY_5708S_PG5_TXACTL3 0x17 357236769Sobrien 358236769Sobrien/*******************************************************/ 359236769Sobrien/* End: PHY register values for the 5708S SerDes PHY */ 360236769Sobrien/*******************************************************/ 361236769Sobrien 362236769Sobrien/*******************************************************/ 363236769Sobrien/* Begin: PHY register values for the 5709S SerDes PHY */ 364236769Sobrien/*******************************************************/ 365236769Sobrien 366236769Sobrien/* 5709S SerDes "General Purpose Status" Registers */ 367236769Sobrien#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 368236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B 369236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 370236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 371236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 372236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 373236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 374292068Ssjg#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 375236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 376236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 377236769Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 378236769Sobrien 379236769Sobrien/* 5709S SerDes "SerDes Digital" Registers */ 380236769Sobrien#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 381236769Sobrien#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 382236769Sobrien#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 383236769Sobrien#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 384236769Sobrien 385236769Sobrien/* 5709S SerDes "Over 1G" Registers */ 386236769Sobrien#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 387236769Sobrien#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 388236769Sobrien 389236769Sobrien/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ 390236769Sobrien#define BRGPHY_BLOCK_ADDR_MRBE 0x8350 391236769Sobrien#define BRGPHY_MRBE_MSG_PG5_NP 0x10 392236769Sobrien#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 393236769Sobrien#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002 394236769Sobrien 395236769Sobrien/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 396236769Sobrien#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 397236769Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 398236769Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 399236769Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 400236769Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 401236769Sobrien 402236769Sobrien/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 403236769Sobrien#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 404236769Sobrien 405236769Sobrien/* 5709S SerDes "Combo IEEE 0" Registers */ 406236769Sobrien#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 407236769Sobrien 408236769Sobrien#define BRGPHY_ADDR_EXT 0x1E 409236769Sobrien#define BRGPHY_BLOCK_ADDR 0x1F 410236769Sobrien 411236769Sobrien#define BRGPHY_ADDR_EXT_AN_MMD 0x3800 412236769Sobrien 413236769Sobrien/*******************************************************/ 414236769Sobrien/* End: PHY register values for the 5709S SerDes PHY */ 415236769Sobrien/*******************************************************/ 416236769Sobrien 417236769Sobrien#define BRGPHY_INTRS \ 418236769Sobrien ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 419236769Sobrien 420236769Sobrien#endif /* _DEV_BRGPHY_MIIREG_H_ */ 421236769Sobrien