brgphyreg.h revision 220938
168349Sobrien/*- 268349Sobrien * Copyright (c) 2000 368349Sobrien * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 468349Sobrien * 568349Sobrien * Redistribution and use in source and binary forms, with or without 668349Sobrien * modification, are permitted provided that the following conditions 768349Sobrien * are met: 868349Sobrien * 1. Redistributions of source code must retain the above copyright 968349Sobrien * notice, this list of conditions and the following disclaimer. 1068349Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1168349Sobrien * notice, this list of conditions and the following disclaimer in the 1268349Sobrien * documentation and/or other materials provided with the distribution. 1368349Sobrien * 3. All advertising materials mentioning features or use of this software 1468349Sobrien * must display the following acknowledgement: 1568349Sobrien * This product includes software developed by Bill Paul. 1668349Sobrien * 4. Neither the name of the author nor the names of any co-contributors 1768349Sobrien * may be used to endorse or promote products derived from this software 1868349Sobrien * without specific prior written permission. 1968349Sobrien * 2068349Sobrien * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2168349Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2268349Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2368349Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2468349Sobrien * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2568349Sobrien * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2668349Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2768349Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2868349Sobrien * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2968349Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3068349Sobrien * THE POSSIBILITY OF SUCH DAMAGE. 3168349Sobrien * 3268349Sobrien * $FreeBSD: head/sys/dev/mii/brgphyreg.h 220938 2011-04-22 09:22:27Z marius $ 3368349Sobrien */ 3468349Sobrien 3568349Sobrien#ifndef _DEV_MII_BRGPHYREG_H_ 3668349Sobrien#define _DEV_MII_BRGPHYREG_H_ 3768349Sobrien 3868349Sobrien/* 3968349Sobrien * Broadcom BCM5400 registers 4068349Sobrien */ 4168349Sobrien 4268349Sobrien#define BRGPHY_MII_BMCR 0x00 4368349Sobrien#define BRGPHY_BMCR_RESET 0x8000 4468349Sobrien#define BRGPHY_BMCR_LOOP 0x4000 4568349Sobrien#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ 4668349Sobrien#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 4768349Sobrien#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ 4868349Sobrien#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ 4968349Sobrien#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ 5068349Sobrien#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ 5168349Sobrien#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 5268349Sobrien#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ 5368349Sobrien 5468349Sobrien#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ 5568349Sobrien#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ 5668349Sobrien#define BRGPHY_S10 0 /* 10mbps */ 5768349Sobrien 5868349Sobrien#define BRGPHY_MII_BMSR 0x01 5968349Sobrien#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 6068349Sobrien#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 6168349Sobrien#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 6268349Sobrien#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occurred */ 6368349Sobrien#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 6468349Sobrien#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ 6568349Sobrien#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 6668349Sobrien#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */ 6768349Sobrien 6868349Sobrien#define BRGPHY_MII_ANAR 0x04 6968349Sobrien#define BRGPHY_ANAR_NP 0x8000 /* Next page */ 7068349Sobrien#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */ 7168349Sobrien#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ 7268349Sobrien#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */ 7368349Sobrien#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 7468349Sobrien 7568349Sobrien#define BRGPHY_MII_ANLPAR 0x05 7668349Sobrien#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */ 7768349Sobrien#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */ 7868349Sobrien#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ 7968349Sobrien#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */ 8068349Sobrien#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */ 8168349Sobrien 8268349Sobrien#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */ 8368349Sobrien 8468349Sobrien#define BRGPHY_MII_ANER 0x06 8568349Sobrien#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */ 8668349Sobrien#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */ 8768349Sobrien#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */ 8868349Sobrien#define BRGPHY_ANER_RX 0x0002 /* Next page received */ 8968349Sobrien#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ 9068349Sobrien 9168349Sobrien#define BRGPHY_MII_NEXTP 0x07 /* Next page */ 9268349Sobrien 9368349Sobrien#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ 9468349Sobrien 9568349Sobrien#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ 9668349Sobrien#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */ 9768349Sobrien#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ 9868349Sobrien#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ 9968349Sobrien#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ 10068349Sobrien#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ 10168349Sobrien#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ 10268349Sobrien 10368349Sobrien#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */ 10468349Sobrien#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */ 10568349Sobrien#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */ 10668349Sobrien#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */ 10768349Sobrien#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */ 10868349Sobrien#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ 10968349Sobrien#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ 11068349Sobrien#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */ 11168349Sobrien 11268349Sobrien#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */ 11368349Sobrien#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ 11468349Sobrien#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ 11568349Sobrien#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ 11668349Sobrien#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ 11768349Sobrien 11868349Sobrien#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ 11968349Sobrien#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ 12068349Sobrien#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ 12168349Sobrien#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */ 12268349Sobrien#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ 12368349Sobrien#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ 12468349Sobrien#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ 12568349Sobrien#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ 12668349Sobrien#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ 12768349Sobrien#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ 12868349Sobrien#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ 12968349Sobrien#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ 13068349Sobrien#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ 13168349Sobrien#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ 13268349Sobrien#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ 13368349Sobrien#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ 13468349Sobrien#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ 13568349Sobrien 13668349Sobrien#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ 13768349Sobrien#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ 13868349Sobrien#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ 13968349Sobrien#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ 14068349Sobrien#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ 14168349Sobrien#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ 14268349Sobrien#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ 14368349Sobrien#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ 14468349Sobrien#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ 14568349Sobrien#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ 14668349Sobrien#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ 14768349Sobrien#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ 14868349Sobrien#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ 14968349Sobrien#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ 15068349Sobrien#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ 15168349Sobrien 15268349Sobrien#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ 15368349Sobrien 15468349Sobrien#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ 15568349Sobrien#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ 15668349Sobrien 15768349Sobrien#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ 15868349Sobrien#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ 15968349Sobrien#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ 16068349Sobrien 16168349Sobrien#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ 16268349Sobrien 16368349Sobrien#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ 16468349Sobrien#define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */ 16568349Sobrien 16668349Sobrien#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 16768349Sobrien#define BRGPHY_DSP_AGC_A 0x00 16868349Sobrien#define BRGPHY_DSP_AGC_B 0x01 16968349Sobrien#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 17068349Sobrien#define BRGPHY_DSP_SOFT_DECISION 0x03 17168349Sobrien#define BRGPHY_DSP_PHASE_REG 0x04 17268349Sobrien#define BRGPHY_DSP_SKEW 0x05 17368349Sobrien#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 17468349Sobrien#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 17568349Sobrien#define BRGPHY_DSP_LAST_ECHO 0x08 17668349Sobrien#define BRGPHY_DSP_FREQUENCY 0x09 17768349Sobrien#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A 17868349Sobrien#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B 17968349Sobrien 18068349Sobrien#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 18168349Sobrien#define BRGPHY_DSP_FILTER_FEXT3 0x0B00 18268349Sobrien#define BRGPHY_DSP_FILTER_FEXT2 0x0A00 18368349Sobrien#define BRGPHY_DSP_FILTER_FEXT1 0x0900 18468349Sobrien#define BRGPHY_DSP_FILTER_FEXT0 0x0800 18568349Sobrien#define BRGPHY_DSP_FILTER_NEXT3 0x0700 18668349Sobrien#define BRGPHY_DSP_FILTER_NEXT2 0x0600 18768349Sobrien#define BRGPHY_DSP_FILTER_NEXT1 0x0500 18868349Sobrien#define BRGPHY_DSP_FILTER_NEXT0 0x0400 18968349Sobrien#define BRGPHY_DSP_FILTER_ECHO 0x0300 19068349Sobrien#define BRGPHY_DSP_FILTER_DFE 0x0200 19168349Sobrien#define BRGPHY_DSP_FILTER_FFE 0x0100 19268349Sobrien 19368349Sobrien#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 19468349Sobrien 19568349Sobrien#define BRGPHY_DSP_SEL_CH_0 0x0000 19668349Sobrien#define BRGPHY_DSP_SEL_CH_1 0x2000 19768349Sobrien#define BRGPHY_DSP_SEL_CH_2 0x4000 19868349Sobrien#define BRGPHY_DSP_SEL_CH_3 0x6000 19968349Sobrien 20068349Sobrien#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 20168349Sobrien#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ 20268349Sobrien#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ 20368349Sobrien#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ 20468349Sobrien#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ 20568349Sobrien#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ 20668349Sobrien#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ 20768349Sobrien 20868349Sobrien#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ 20968349Sobrien#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ 21068349Sobrien#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ 21168349Sobrien#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ 21268349Sobrien#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ 21368349Sobrien#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ 21468349Sobrien#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ 21568349Sobrien#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ 21668349Sobrien#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ 21768349Sobrien#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */ 21868349Sobrien#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */ 21968349Sobrien#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ 22068349Sobrien#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ 22168349Sobrien#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ 22268349Sobrien 22368349Sobrien#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ 22468349Sobrien#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ 22568349Sobrien#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ 22668349Sobrien#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ 22768349Sobrien#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ 22868349Sobrien#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ 22968349Sobrien#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ 23068349Sobrien 23168349Sobrien#define BRGPHY_MII_ISR 0x1A /* Interrupt status */ 23268349Sobrien#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ 23368349Sobrien#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ 23468349Sobrien#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ 23568349Sobrien#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ 23668349Sobrien#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ 23768349Sobrien#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ 23868349Sobrien#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ 23968349Sobrien#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 24068349Sobrien#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 24168349Sobrien#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ 24268349Sobrien#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ 24368349Sobrien#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ 24468349Sobrien#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ 24568349Sobrien#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ 24668349Sobrien#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ 24768349Sobrien 24868349Sobrien#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ 24968349Sobrien#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ 25068349Sobrien#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ 25168349Sobrien#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ 25268349Sobrien#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ 25368349Sobrien#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ 25468349Sobrien#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ 25568349Sobrien#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ 25668349Sobrien#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 25768349Sobrien#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 25868349Sobrien#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ 25968349Sobrien#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ 26068349Sobrien#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ 26168349Sobrien#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ 26268349Sobrien#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 26368349Sobrien#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ 26468349Sobrien 26568349Sobrien/*******************************************************/ 26668349Sobrien/* Begin: Shared SerDes PHY register definitions */ 26768349Sobrien/*******************************************************/ 26868349Sobrien 26968349Sobrien/* SerDes autoneg is different from copper */ 27068349Sobrien#define BRGPHY_SERDES_ANAR 0x04 27168349Sobrien#define BRGPHY_SERDES_ANAR_FDX 0x0020 27268349Sobrien#define BRGPHY_SERDES_ANAR_HDX 0x0040 27368349Sobrien#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) 27468349Sobrien#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) 27568349Sobrien#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) 27668349Sobrien#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) 27768349Sobrien 27868349Sobrien#define BRGPHY_SERDES_ANLPAR 0x05 27968349Sobrien#define BRGPHY_SERDES_ANLPAR_FDX 0x0020 28068349Sobrien#define BRGPHY_SERDES_ANLPAR_HDX 0x0040 28168349Sobrien#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) 28268349Sobrien#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) 28368349Sobrien#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) 28468349Sobrien#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) 28568349Sobrien 28668349Sobrien/*******************************************************/ 28768349Sobrien/* End: Shared SerDes PHY register definitions */ 28868349Sobrien/*******************************************************/ 28968349Sobrien 29068349Sobrien/*******************************************************/ 29168349Sobrien/* Begin: PHY register values for the 5706 PHY */ 29268349Sobrien/*******************************************************/ 29368349Sobrien 29468349Sobrien/* 29568349Sobrien * Shadow register 0x1C, bit 15 is write enable, 29668349Sobrien * bits 14-10 select function (0x00 to 0x1F). 29768349Sobrien */ 29868349Sobrien#define BRGPHY_MII_SHADOW_1C 0x1C 29968349Sobrien#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 30068349Sobrien#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 30168349Sobrien 30268349Sobrien/* Shadow 0x1C Mode Control Register (select value 0x1F) */ 30368349Sobrien#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) 30468349Sobrien/* When set, Regs 0-0x0F are 1000X, else 1000T */ 30568349Sobrien#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 30668349Sobrien 30768349Sobrien#define BRGPHY_MII_TEST1 0x1E 30868349Sobrien#define BRGPHY_TEST1_TRIM_EN 0x0010 30968349Sobrien#define BRGPHY_TEST1_CRC_EN 0x8000 31068349Sobrien 31168349Sobrien#define BRGPHY_MII_TEST2 0x1F 31268349Sobrien 31368349Sobrien/*******************************************************/ 31468349Sobrien/* End: PHY register values for the 5706 PHY */ 31568349Sobrien/*******************************************************/ 31668349Sobrien 31768349Sobrien/*******************************************************/ 31868349Sobrien/* Begin: PHY register values for the 5708S SerDes PHY */ 31968349Sobrien/*******************************************************/ 32068349Sobrien 32168349Sobrien/* Autoneg Next Page Transmit 1 Regiser */ 32268349Sobrien#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B 32368349Sobrien#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 32468349Sobrien 32568349Sobrien/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ 32668349Sobrien#define BRGPHY_5708S_BLOCK_ADDR 0x1f 32768349Sobrien#define BRGPHY_5708S_DIG_PG0 0x0000 32868349Sobrien#define BRGPHY_5708S_DIG3_PG2 0x0002 32968349Sobrien#define BRGPHY_5708S_TX_MISC_PG5 0x0005 33068349Sobrien 33168349Sobrien/* 5708S SerDes "Digital" Registers (page 0) */ 33268349Sobrien#define BRGPHY_5708S_PG0_1000X_CTL1 0x10 33368349Sobrien#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 33468349Sobrien#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 33568349Sobrien 33668349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1 0x14 33768349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 33868349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 33968349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 34068349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) 34168349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) 34268349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) 34368349Sobrien#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) 34468349Sobrien 34568349Sobrien 34668349Sobrien#define BRGPHY_5708S_PG0_1000X_CTL2 0x11 34768349Sobrien#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 34868349Sobrien 34968349Sobrien/* 5708S SerDes "Digital 3" Registers (page 2) */ 35068349Sobrien#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 35168349Sobrien#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 35268349Sobrien 35368349Sobrien/* 5708S SerDes "TX Misc" Registers (page 5) */ 35468349Sobrien#define BRGPHY_5708S_PG5_2500STATUS1 0x10 35568349Sobrien#define BRGPHY_5708S_PG5_TXACTL1 0x15 35668349Sobrien#define BRGPHY_5708S_PG5_TXACTL3 0x17 35768349Sobrien 35868349Sobrien/*******************************************************/ 35968349Sobrien/* End: PHY register values for the 5708S SerDes PHY */ 36068349Sobrien/*******************************************************/ 36168349Sobrien 36268349Sobrien/*******************************************************/ 36368349Sobrien/* Begin: PHY register values for the 5709S SerDes PHY */ 36468349Sobrien/*******************************************************/ 36568349Sobrien 36668349Sobrien/* 5709S SerDes "General Purpose Status" Registers */ 36768349Sobrien#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 36868349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B 36968349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 37068349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 37168349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 37268349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 37368349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 37468349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 37568349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 37668349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 37768349Sobrien#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 37868349Sobrien 37968349Sobrien/* 5709S SerDes "SerDes Digital" Registers */ 38068349Sobrien#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 38168349Sobrien#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 38268349Sobrien#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 38368349Sobrien#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 38468349Sobrien 38568349Sobrien/* 5709S SerDes "Over 1G" Registers */ 38668349Sobrien#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 38768349Sobrien#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 38868349Sobrien 38968349Sobrien/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ 39068349Sobrien#define BRGPHY_BLOCK_ADDR_MRBE 0x8350 39168349Sobrien#define BRGPHY_MRBE_MSG_PG5_NP 0x10 39268349Sobrien#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 39368349Sobrien#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002 39468349Sobrien 39568349Sobrien/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 39668349Sobrien#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 39768349Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 39868349Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 39968349Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 40068349Sobrien#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 40168349Sobrien 40268349Sobrien/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 40368349Sobrien#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 40468349Sobrien 40568349Sobrien/* 5709S SerDes "Combo IEEE 0" Registers */ 40668349Sobrien#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 40768349Sobrien 40868349Sobrien#define BRGPHY_ADDR_EXT 0x1E 40968349Sobrien#define BRGPHY_BLOCK_ADDR 0x1F 41068349Sobrien 41168349Sobrien#define BRGPHY_ADDR_EXT_AN_MMD 0x3800 41268349Sobrien 41368349Sobrien/*******************************************************/ 41468349Sobrien/* End: PHY register values for the 5709S SerDes PHY */ 41568349Sobrien/*******************************************************/ 41668349Sobrien 41768349Sobrien#define BRGPHY_INTRS \ 41868349Sobrien ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 41968349Sobrien 42068349Sobrien#endif /* _DEV_BRGPHY_MIIREG_H_ */ 42168349Sobrien