brgphy.c revision 231913
1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 231913 2012-02-19 12:09:17Z marius $"); 35 36/* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/bus.h> 46 47#include <net/if.h> 48#include <net/ethernet.h> 49#include <net/if_media.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include "miidevs.h" 54 55#include <dev/mii/brgphyreg.h> 56#include <net/if_arp.h> 57#include <machine/bus.h> 58#include <dev/bge/if_bgereg.h> 59#include <dev/bce/if_bcereg.h> 60 61#include <dev/pci/pcireg.h> 62#include <dev/pci/pcivar.h> 63 64#include "miibus_if.h" 65 66static int brgphy_probe(device_t); 67static int brgphy_attach(device_t); 68 69struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int serdes_flags; /* Keeps track of the serdes type used */ 72#define BRGPHY_5706S 0x0001 73#define BRGPHY_5708S 0x0002 74#define BRGPHY_NOANWAIT 0x0004 75#define BRGPHY_5709S 0x0008 76 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 77}; 78 79static device_method_t brgphy_methods[] = { 80 /* device interface */ 81 DEVMETHOD(device_probe, brgphy_probe), 82 DEVMETHOD(device_attach, brgphy_attach), 83 DEVMETHOD(device_detach, mii_phy_detach), 84 DEVMETHOD(device_shutdown, bus_generic_shutdown), 85 DEVMETHOD_END 86}; 87 88static devclass_t brgphy_devclass; 89 90static driver_t brgphy_driver = { 91 "brgphy", 92 brgphy_methods, 93 sizeof(struct brgphy_softc) 94}; 95 96DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 97 98static int brgphy_service(struct mii_softc *, struct mii_data *, int); 99static void brgphy_setmedia(struct mii_softc *, int); 100static void brgphy_status(struct mii_softc *); 101static void brgphy_mii_phy_auto(struct mii_softc *, int); 102static void brgphy_reset(struct mii_softc *); 103static void brgphy_enable_loopback(struct mii_softc *); 104static void bcm5401_load_dspcode(struct mii_softc *); 105static void bcm5411_load_dspcode(struct mii_softc *); 106static void bcm54k2_load_dspcode(struct mii_softc *); 107static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 108static void brgphy_fixup_adc_bug(struct mii_softc *); 109static void brgphy_fixup_adjust_trim(struct mii_softc *); 110static void brgphy_fixup_ber_bug(struct mii_softc *); 111static void brgphy_fixup_crc_bug(struct mii_softc *); 112static void brgphy_fixup_jitter_bug(struct mii_softc *); 113static void brgphy_ethernet_wirespeed(struct mii_softc *); 114static void brgphy_jumbo_settings(struct mii_softc *, u_long); 115 116static const struct mii_phydesc brgphys[] = { 117 MII_PHY_DESC(BROADCOM, BCM5400), 118 MII_PHY_DESC(BROADCOM, BCM5401), 119 MII_PHY_DESC(BROADCOM, BCM5411), 120 MII_PHY_DESC(BROADCOM, BCM54K2), 121 MII_PHY_DESC(BROADCOM, BCM5701), 122 MII_PHY_DESC(BROADCOM, BCM5703), 123 MII_PHY_DESC(BROADCOM, BCM5704), 124 MII_PHY_DESC(BROADCOM, BCM5705), 125 MII_PHY_DESC(BROADCOM, BCM5706), 126 MII_PHY_DESC(BROADCOM, BCM5714), 127 MII_PHY_DESC(BROADCOM, BCM5421), 128 MII_PHY_DESC(BROADCOM, BCM5750), 129 MII_PHY_DESC(BROADCOM, BCM5752), 130 MII_PHY_DESC(BROADCOM, BCM5780), 131 MII_PHY_DESC(BROADCOM, BCM5708C), 132 MII_PHY_DESC(BROADCOM2, BCM5482), 133 MII_PHY_DESC(BROADCOM2, BCM5708S), 134 MII_PHY_DESC(BROADCOM2, BCM5709C), 135 MII_PHY_DESC(BROADCOM2, BCM5709S), 136 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 137 MII_PHY_DESC(BROADCOM2, BCM5722), 138 MII_PHY_DESC(BROADCOM2, BCM5755), 139 MII_PHY_DESC(BROADCOM2, BCM5754), 140 MII_PHY_DESC(BROADCOM2, BCM5761), 141 MII_PHY_DESC(BROADCOM2, BCM5784), 142#ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 143 MII_PHY_DESC(BROADCOM2, BCM5785), 144#endif 145 MII_PHY_DESC(BROADCOM3, BCM5717C), 146 MII_PHY_DESC(BROADCOM3, BCM5719C), 147 MII_PHY_DESC(BROADCOM3, BCM5720C), 148 MII_PHY_DESC(BROADCOM3, BCM57765), 149 MII_PHY_DESC(BROADCOM3, BCM57780), 150 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 151 MII_PHY_END 152}; 153 154static const struct mii_phy_funcs brgphy_funcs = { 155 brgphy_service, 156 brgphy_status, 157 brgphy_reset 158}; 159 160#define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 161#define HS21_BCM_CHIPID 0x57081021 162 163static int 164detect_hs21(struct bce_softc *bce_sc) 165{ 166 char *sysenv; 167 int found; 168 169 found = 0; 170 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { 171 sysenv = getenv("smbios.system.product"); 172 if (sysenv != NULL) { 173 if (strncmp(sysenv, HS21_PRODUCT_ID, 174 strlen(HS21_PRODUCT_ID)) == 0) 175 found = 1; 176 freeenv(sysenv); 177 } 178 } 179 return (found); 180} 181 182/* Search for our PHY in the list of known PHYs */ 183static int 184brgphy_probe(device_t dev) 185{ 186 187 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 188} 189 190/* Attach the PHY to the MII bus */ 191static int 192brgphy_attach(device_t dev) 193{ 194 struct brgphy_softc *bsc; 195 struct bge_softc *bge_sc = NULL; 196 struct bce_softc *bce_sc = NULL; 197 struct mii_softc *sc; 198 struct ifnet *ifp; 199 200 bsc = device_get_softc(dev); 201 sc = &bsc->mii_sc; 202 203 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 204 &brgphy_funcs, 0); 205 206 bsc->serdes_flags = 0; 207 208 /* Handle any special cases based on the PHY ID */ 209 switch (sc->mii_mpd_oui) { 210 case MII_OUI_BROADCOM: 211 switch (sc->mii_mpd_model) { 212 case MII_MODEL_BROADCOM_BCM5706: 213 case MII_MODEL_BROADCOM_BCM5714: 214 /* 215 * The 5464 PHY used in the 5706 supports both copper 216 * and fiber interfaces over GMII. Need to check the 217 * shadow registers to see which mode is actually 218 * in effect, and therefore whether we have 5706C or 219 * 5706S. 220 */ 221 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 222 BRGPHY_SHADOW_1C_MODE_CTRL); 223 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 224 BRGPHY_SHADOW_1C_ENA_1000X) { 225 bsc->serdes_flags |= BRGPHY_5706S; 226 sc->mii_flags |= MIIF_HAVEFIBER; 227 } 228 break; 229 } 230 break; 231 case MII_OUI_BROADCOM2: 232 switch (sc->mii_mpd_model) { 233 case MII_MODEL_BROADCOM2_BCM5708S: 234 bsc->serdes_flags |= BRGPHY_5708S; 235 sc->mii_flags |= MIIF_HAVEFIBER; 236 break; 237 case MII_MODEL_BROADCOM2_BCM5709S: 238 bsc->serdes_flags |= BRGPHY_5709S; 239 sc->mii_flags |= MIIF_HAVEFIBER; 240 break; 241 } 242 break; 243 } 244 245 ifp = sc->mii_pdata->mii_ifp; 246 247 /* Find the MAC driver associated with this PHY. */ 248 if (strcmp(ifp->if_dname, "bge") == 0) { 249 bge_sc = ifp->if_softc; 250 } else if (strcmp(ifp->if_dname, "bce") == 0) { 251 bce_sc = ifp->if_softc; 252 } 253 254 PHY_RESET(sc); 255 256 /* Read the PHY's capabilities. */ 257 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 258 if (sc->mii_capabilities & BMSR_EXTSTAT) 259 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 260 device_printf(dev, " "); 261 262#define ADD(m, c) ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL) 263 264 /* Add the supported media types */ 265 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 266 mii_phy_add_media(sc); 267 printf("\n"); 268 } else { 269 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 270 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 271 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 272 printf("1000baseSX-FDX, "); 273 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 274 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 275 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 276 printf("2500baseSX-FDX, "); 277 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 278 (detect_hs21(bce_sc) != 0)) { 279 /* 280 * There appears to be certain silicon revision 281 * in IBM HS21 blades that is having issues with 282 * this driver wating for the auto-negotiation to 283 * complete. This happens with a specific chip id 284 * only and when the 1000baseSX-FDX is the only 285 * mode. Workaround this issue since it's unlikely 286 * to be ever addressed. 287 */ 288 printf("auto-neg workaround, "); 289 bsc->serdes_flags |= BRGPHY_NOANWAIT; 290 } 291 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 292 printf("auto\n"); 293 } 294 295#undef ADD 296 MIIBUS_MEDIAINIT(sc->mii_dev); 297 return (0); 298} 299 300static int 301brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 302{ 303 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 304 int val; 305 306 switch (cmd) { 307 case MII_POLLSTAT: 308 break; 309 case MII_MEDIACHG: 310 /* If the interface is not up, don't do anything. */ 311 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 312 break; 313 314 /* Todo: Why is this here? Is it really needed? */ 315 PHY_RESET(sc); /* XXX hardware bug work-around */ 316 317 switch (IFM_SUBTYPE(ife->ifm_media)) { 318 case IFM_AUTO: 319 brgphy_mii_phy_auto(sc, ife->ifm_media); 320 break; 321 case IFM_2500_SX: 322 case IFM_1000_SX: 323 case IFM_1000_T: 324 case IFM_100_TX: 325 case IFM_10_T: 326 brgphy_setmedia(sc, ife->ifm_media); 327 break; 328 default: 329 return (EINVAL); 330 } 331 break; 332 case MII_TICK: 333 /* Bail if the interface isn't up. */ 334 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 335 return (0); 336 337 338 /* Bail if autoneg isn't in process. */ 339 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 340 sc->mii_ticks = 0; 341 break; 342 } 343 344 /* 345 * Check to see if we have link. If we do, we don't 346 * need to restart the autonegotiation process. 347 */ 348 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 349 if (val & BMSR_LINK) { 350 sc->mii_ticks = 0; /* Reset autoneg timer. */ 351 break; 352 } 353 354 /* Announce link loss right after it happens. */ 355 if (sc->mii_ticks++ == 0) 356 break; 357 358 /* Only retry autonegotiation every mii_anegticks seconds. */ 359 if (sc->mii_ticks <= sc->mii_anegticks) 360 break; 361 362 363 /* Retry autonegotiation */ 364 sc->mii_ticks = 0; 365 brgphy_mii_phy_auto(sc, ife->ifm_media); 366 break; 367 } 368 369 /* Update the media status. */ 370 PHY_STATUS(sc); 371 372 /* 373 * Callback if something changed. Note that we need to poke 374 * the DSP on the Broadcom PHYs if the media changes. 375 */ 376 if (sc->mii_media_active != mii->mii_media_active || 377 sc->mii_media_status != mii->mii_media_status || 378 cmd == MII_MEDIACHG) { 379 switch (sc->mii_mpd_oui) { 380 case MII_OUI_BROADCOM: 381 switch (sc->mii_mpd_model) { 382 case MII_MODEL_BROADCOM_BCM5400: 383 bcm5401_load_dspcode(sc); 384 break; 385 case MII_MODEL_BROADCOM_BCM5401: 386 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 387 bcm5401_load_dspcode(sc); 388 break; 389 case MII_MODEL_BROADCOM_BCM5411: 390 bcm5411_load_dspcode(sc); 391 break; 392 case MII_MODEL_BROADCOM_BCM54K2: 393 bcm54k2_load_dspcode(sc); 394 break; 395 } 396 break; 397 } 398 } 399 mii_phy_update(sc, cmd); 400 return (0); 401} 402 403/****************************************************************************/ 404/* Sets the PHY link speed. */ 405/* */ 406/* Returns: */ 407/* None */ 408/****************************************************************************/ 409static void 410brgphy_setmedia(struct mii_softc *sc, int media) 411{ 412 int bmcr = 0, gig; 413 414 switch (IFM_SUBTYPE(media)) { 415 case IFM_2500_SX: 416 break; 417 case IFM_1000_SX: 418 case IFM_1000_T: 419 bmcr = BRGPHY_S1000; 420 break; 421 case IFM_100_TX: 422 bmcr = BRGPHY_S100; 423 break; 424 case IFM_10_T: 425 default: 426 bmcr = BRGPHY_S10; 427 break; 428 } 429 430 if ((media & IFM_FDX) != 0) { 431 bmcr |= BRGPHY_BMCR_FDX; 432 gig = BRGPHY_1000CTL_AFD; 433 } else { 434 gig = BRGPHY_1000CTL_AHD; 435 } 436 437 /* Force loopback to disconnect PHY from Ethernet medium. */ 438 brgphy_enable_loopback(sc); 439 440 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 441 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 442 443 if (IFM_SUBTYPE(media) != IFM_1000_T && 444 IFM_SUBTYPE(media) != IFM_1000_SX) { 445 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 446 return; 447 } 448 449 if (IFM_SUBTYPE(media) == IFM_1000_T) { 450 gig |= BRGPHY_1000CTL_MSE; 451 if ((media & IFM_ETH_MASTER) != 0) 452 gig |= BRGPHY_1000CTL_MSC; 453 } 454 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 455 PHY_WRITE(sc, BRGPHY_MII_BMCR, 456 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 457} 458 459/****************************************************************************/ 460/* Set the media status based on the PHY settings. */ 461/* */ 462/* Returns: */ 463/* None */ 464/****************************************************************************/ 465static void 466brgphy_status(struct mii_softc *sc) 467{ 468 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 469 struct mii_data *mii = sc->mii_pdata; 470 int aux, bmcr, bmsr, val, xstat; 471 u_int flowstat; 472 473 mii->mii_media_status = IFM_AVALID; 474 mii->mii_media_active = IFM_ETHER; 475 476 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 477 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 478 479 if (bmcr & BRGPHY_BMCR_LOOP) { 480 mii->mii_media_active |= IFM_LOOP; 481 } 482 483 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 484 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 485 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 486 /* Erg, still trying, I guess... */ 487 mii->mii_media_active |= IFM_NONE; 488 return; 489 } 490 491 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 492 /* 493 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 494 * wedges at least the PHY of BCM5704 (but not others). 495 */ 496 flowstat = mii_phy_flowstatus(sc); 497 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 498 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 499 500 /* If copper link is up, get the negotiated speed/duplex. */ 501 if (aux & BRGPHY_AUXSTS_LINK) { 502 mii->mii_media_status |= IFM_ACTIVE; 503 switch (aux & BRGPHY_AUXSTS_AN_RES) { 504 case BRGPHY_RES_1000FD: 505 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 506 case BRGPHY_RES_1000HD: 507 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 508 case BRGPHY_RES_100FD: 509 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 510 case BRGPHY_RES_100T4: 511 mii->mii_media_active |= IFM_100_T4; break; 512 case BRGPHY_RES_100HD: 513 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 514 case BRGPHY_RES_10FD: 515 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 516 case BRGPHY_RES_10HD: 517 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 518 default: 519 mii->mii_media_active |= IFM_NONE; break; 520 } 521 522 if ((mii->mii_media_active & IFM_FDX) != 0) 523 mii->mii_media_active |= flowstat; 524 525 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 526 (xstat & BRGPHY_1000STS_MSR) != 0) 527 mii->mii_media_active |= IFM_ETH_MASTER; 528 } 529 } else { 530 /* Todo: Add support for flow control. */ 531 /* If serdes link is up, get the negotiated speed/duplex. */ 532 if (bmsr & BRGPHY_BMSR_LINK) { 533 mii->mii_media_status |= IFM_ACTIVE; 534 } 535 536 /* Check the link speed/duplex based on the PHY type. */ 537 if (bsc->serdes_flags & BRGPHY_5706S) { 538 mii->mii_media_active |= IFM_1000_SX; 539 540 /* If autoneg enabled, read negotiated duplex settings */ 541 if (bmcr & BRGPHY_BMCR_AUTOEN) { 542 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 543 if (val & BRGPHY_SERDES_ANAR_FDX) 544 mii->mii_media_active |= IFM_FDX; 545 else 546 mii->mii_media_active |= IFM_HDX; 547 } 548 } else if (bsc->serdes_flags & BRGPHY_5708S) { 549 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 550 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 551 552 /* Check for MRBE auto-negotiated speed results. */ 553 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 554 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 555 mii->mii_media_active |= IFM_10_FL; break; 556 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 557 mii->mii_media_active |= IFM_100_FX; break; 558 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 559 mii->mii_media_active |= IFM_1000_SX; break; 560 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 561 mii->mii_media_active |= IFM_2500_SX; break; 562 } 563 564 /* Check for MRBE auto-negotiated duplex results. */ 565 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 566 mii->mii_media_active |= IFM_FDX; 567 else 568 mii->mii_media_active |= IFM_HDX; 569 } else if (bsc->serdes_flags & BRGPHY_5709S) { 570 /* Select GP Status Block of the AN MMD, get autoneg results. */ 571 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 572 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 573 574 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 575 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 576 577 /* Check for MRBE auto-negotiated speed results. */ 578 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 579 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 580 mii->mii_media_active |= IFM_10_FL; break; 581 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 582 mii->mii_media_active |= IFM_100_FX; break; 583 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 584 mii->mii_media_active |= IFM_1000_SX; break; 585 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 586 mii->mii_media_active |= IFM_2500_SX; break; 587 } 588 589 /* Check for MRBE auto-negotiated duplex results. */ 590 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 591 mii->mii_media_active |= IFM_FDX; 592 else 593 mii->mii_media_active |= IFM_HDX; 594 } 595 } 596} 597 598static void 599brgphy_mii_phy_auto(struct mii_softc *sc, int media) 600{ 601 int anar, ktcr = 0; 602 603 PHY_RESET(sc); 604 605 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 606 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 607 if ((media & IFM_FLOW) != 0 || 608 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 609 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 610 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 611 } else { 612 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 613 if ((media & IFM_FLOW) != 0 || 614 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 615 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 616 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 617 } 618 619 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 620 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 621 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 622 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 623 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 624 625 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 626 BRGPHY_BMCR_STARTNEG); 627 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 628} 629 630/* Enable loopback to force the link down. */ 631static void 632brgphy_enable_loopback(struct mii_softc *sc) 633{ 634 int i; 635 636 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 637 for (i = 0; i < 15000; i++) { 638 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 639 break; 640 DELAY(10); 641 } 642} 643 644/* Turn off tap power management on 5401. */ 645static void 646bcm5401_load_dspcode(struct mii_softc *sc) 647{ 648 static const struct { 649 int reg; 650 uint16_t val; 651 } dspcode[] = { 652 { BRGPHY_MII_AUXCTL, 0x0c20 }, 653 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 654 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 655 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 656 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 657 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 658 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 659 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 660 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 661 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 662 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 663 { 0, 0 }, 664 }; 665 int i; 666 667 for (i = 0; dspcode[i].reg != 0; i++) 668 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 669 DELAY(40); 670} 671 672static void 673bcm5411_load_dspcode(struct mii_softc *sc) 674{ 675 static const struct { 676 int reg; 677 uint16_t val; 678 } dspcode[] = { 679 { 0x1c, 0x8c23 }, 680 { 0x1c, 0x8ca3 }, 681 { 0x1c, 0x8c23 }, 682 { 0, 0 }, 683 }; 684 int i; 685 686 for (i = 0; dspcode[i].reg != 0; i++) 687 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 688} 689 690void 691bcm54k2_load_dspcode(struct mii_softc *sc) 692{ 693 static const struct { 694 int reg; 695 uint16_t val; 696 } dspcode[] = { 697 { 4, 0x01e1 }, 698 { 9, 0x0300 }, 699 { 0, 0 }, 700 }; 701 int i; 702 703 for (i = 0; dspcode[i].reg != 0; i++) 704 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 705 706} 707 708static void 709brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 710{ 711 static const struct { 712 int reg; 713 uint16_t val; 714 } dspcode[] = { 715 { 0x1c, 0x8d68 }, 716 { 0x1c, 0x8d68 }, 717 { 0, 0 }, 718 }; 719 int i; 720 721 for (i = 0; dspcode[i].reg != 0; i++) 722 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 723} 724 725static void 726brgphy_fixup_adc_bug(struct mii_softc *sc) 727{ 728 static const struct { 729 int reg; 730 uint16_t val; 731 } dspcode[] = { 732 { BRGPHY_MII_AUXCTL, 0x0c00 }, 733 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 734 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 735 { 0, 0 }, 736 }; 737 int i; 738 739 for (i = 0; dspcode[i].reg != 0; i++) 740 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 741} 742 743static void 744brgphy_fixup_adjust_trim(struct mii_softc *sc) 745{ 746 static const struct { 747 int reg; 748 uint16_t val; 749 } dspcode[] = { 750 { BRGPHY_MII_AUXCTL, 0x0c00 }, 751 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 752 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 753 { BRGPHY_MII_TEST1, 0x0014 }, 754 { BRGPHY_MII_AUXCTL, 0x0400 }, 755 { 0, 0 }, 756 }; 757 int i; 758 759 for (i = 0; dspcode[i].reg != 0; i++) 760 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 761} 762 763static void 764brgphy_fixup_ber_bug(struct mii_softc *sc) 765{ 766 static const struct { 767 int reg; 768 uint16_t val; 769 } dspcode[] = { 770 { BRGPHY_MII_AUXCTL, 0x0c00 }, 771 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 772 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 773 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 774 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 775 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 776 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 777 { BRGPHY_MII_AUXCTL, 0x0400 }, 778 { 0, 0 }, 779 }; 780 int i; 781 782 for (i = 0; dspcode[i].reg != 0; i++) 783 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 784} 785 786static void 787brgphy_fixup_crc_bug(struct mii_softc *sc) 788{ 789 static const struct { 790 int reg; 791 uint16_t val; 792 } dspcode[] = { 793 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 794 { 0x1c, 0x8c68 }, 795 { 0x1c, 0x8d68 }, 796 { 0x1c, 0x8c68 }, 797 { 0, 0 }, 798 }; 799 int i; 800 801 for (i = 0; dspcode[i].reg != 0; i++) 802 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 803} 804 805static void 806brgphy_fixup_jitter_bug(struct mii_softc *sc) 807{ 808 static const struct { 809 int reg; 810 uint16_t val; 811 } dspcode[] = { 812 { BRGPHY_MII_AUXCTL, 0x0c00 }, 813 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 814 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 815 { BRGPHY_MII_AUXCTL, 0x0400 }, 816 { 0, 0 }, 817 }; 818 int i; 819 820 for (i = 0; dspcode[i].reg != 0; i++) 821 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 822} 823 824static void 825brgphy_fixup_disable_early_dac(struct mii_softc *sc) 826{ 827 uint32_t val; 828 829 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 830 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 831 val &= ~(1 << 8); 832 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 833 834} 835 836static void 837brgphy_ethernet_wirespeed(struct mii_softc *sc) 838{ 839 uint32_t val; 840 841 /* Enable Ethernet@WireSpeed. */ 842 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 843 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 844 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 845} 846 847static void 848brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 849{ 850 uint32_t val; 851 852 /* Set or clear jumbo frame settings in the PHY. */ 853 if (mtu > ETHER_MAX_LEN) { 854 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 855 /* BCM5401 PHY cannot read-modify-write. */ 856 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 857 } else { 858 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 859 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 860 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 861 val | BRGPHY_AUXCTL_LONG_PKT); 862 } 863 864 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 865 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 866 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 867 } else { 868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 869 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 870 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 871 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 872 873 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 874 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 875 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 876 } 877} 878 879static void 880brgphy_reset(struct mii_softc *sc) 881{ 882 struct bge_softc *bge_sc = NULL; 883 struct bce_softc *bce_sc = NULL; 884 struct ifnet *ifp; 885 int i, val; 886 887 /* 888 * Perform a reset. Note that at least some Broadcom PHYs default to 889 * being powered down as well as isolated after a reset but don't work 890 * if one or both of these bits are cleared. However, they just work 891 * fine if both bits remain set, so we don't use mii_phy_reset() here. 892 */ 893 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 894 895 /* Wait 100ms for it to complete. */ 896 for (i = 0; i < 100; i++) { 897 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 898 break; 899 DELAY(1000); 900 } 901 902 /* Handle any PHY specific procedures following the reset. */ 903 switch (sc->mii_mpd_oui) { 904 case MII_OUI_BROADCOM: 905 switch (sc->mii_mpd_model) { 906 case MII_MODEL_BROADCOM_BCM5400: 907 bcm5401_load_dspcode(sc); 908 break; 909 case MII_MODEL_BROADCOM_BCM5401: 910 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 911 bcm5401_load_dspcode(sc); 912 break; 913 case MII_MODEL_BROADCOM_BCM5411: 914 bcm5411_load_dspcode(sc); 915 break; 916 case MII_MODEL_BROADCOM_BCM54K2: 917 bcm54k2_load_dspcode(sc); 918 break; 919 } 920 break; 921 } 922 923 ifp = sc->mii_pdata->mii_ifp; 924 925 /* Find the driver associated with this PHY. */ 926 if (strcmp(ifp->if_dname, "bge") == 0) { 927 bge_sc = ifp->if_softc; 928 } else if (strcmp(ifp->if_dname, "bce") == 0) { 929 bce_sc = ifp->if_softc; 930 } 931 932 if (bge_sc) { 933 /* Fix up various bugs */ 934 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 935 brgphy_fixup_5704_a0_bug(sc); 936 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 937 brgphy_fixup_adc_bug(sc); 938 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 939 brgphy_fixup_adjust_trim(sc); 940 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 941 brgphy_fixup_ber_bug(sc); 942 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 943 brgphy_fixup_crc_bug(sc); 944 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 945 brgphy_fixup_jitter_bug(sc); 946 947 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 948 brgphy_jumbo_settings(sc, ifp->if_mtu); 949 950 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 951 brgphy_ethernet_wirespeed(sc); 952 953 /* Enable Link LED on Dell boxes */ 954 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 955 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 956 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 957 ~BRGPHY_PHY_EXTCTL_3_LED); 958 } 959 960 /* Adjust output voltage (From Linux driver) */ 961 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 962 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 963 } else if (bce_sc) { 964 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 965 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 966 967 /* Store autoneg capabilities/results in digital block (Page 0) */ 968 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 969 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 970 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 971 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 972 973 /* Enable fiber mode and autodetection */ 974 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 975 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 976 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 977 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 978 979 /* Enable parallel detection */ 980 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 981 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 982 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 983 984 /* Advertise 2.5G support through next page during autoneg */ 985 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 986 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 987 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 988 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 989 990 /* Increase TX signal amplitude */ 991 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 992 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 993 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 994 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 995 BRGPHY_5708S_TX_MISC_PG5); 996 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 997 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 998 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 999 BRGPHY_5708S_DIG_PG0); 1000 } 1001 1002 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1003 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1004 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1005 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1006 BRGPHY_5708S_TX_MISC_PG5); 1007 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1008 bce_sc->bce_port_hw_cfg & 1009 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1010 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1011 BRGPHY_5708S_DIG_PG0); 1012 } 1013 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1014 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1015 1016 /* Select the SerDes Digital block of the AN MMD. */ 1017 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1018 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1019 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1020 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1021 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1022 1023 /* Select the Over 1G block of the AN MMD. */ 1024 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1025 1026 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1027 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1028 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1029 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1030 else 1031 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1032 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1033 1034 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1035 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1036 1037 /* Enable MRBE speed autoneg. */ 1038 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1039 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1040 BRGPHY_MRBE_MSG_PG5_NP_T2; 1041 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1042 1043 /* Select the Clause 73 User B0 block of the AN MMD. */ 1044 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1045 1046 /* Enable MRBE speed autoneg. */ 1047 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1048 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1049 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1050 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1051 1052 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1053 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1054 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1055 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1056 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1057 brgphy_fixup_disable_early_dac(sc); 1058 1059 brgphy_jumbo_settings(sc, ifp->if_mtu); 1060 brgphy_ethernet_wirespeed(sc); 1061 } else { 1062 brgphy_fixup_ber_bug(sc); 1063 brgphy_jumbo_settings(sc, ifp->if_mtu); 1064 brgphy_ethernet_wirespeed(sc); 1065 } 1066 } 1067} 1068