brgphy.c revision 213364
164904Smarcel/*- 264904Smarcel * Copyright (c) 2000 364904Smarcel * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 464904Smarcel * 564904Smarcel * Redistribution and use in source and binary forms, with or without 664904Smarcel * modification, are permitted provided that the following conditions 764904Smarcel * are met: 864904Smarcel * 1. Redistributions of source code must retain the above copyright 964904Smarcel * notice, this list of conditions and the following disclaimer. 1064904Smarcel * 2. Redistributions in binary form must reproduce the above copyright 1164904Smarcel * notice, this list of conditions and the following disclaimer in the 1264904Smarcel * documentation and/or other materials provided with the distribution. 1364904Smarcel * 3. All advertising materials mentioning features or use of this software 1464904Smarcel * must display the following acknowledgement: 1565067Smarcel * This product includes software developed by Bill Paul. 1664904Smarcel * 4. Neither the name of the author nor the names of any co-contributors 1764904Smarcel * may be used to endorse or promote products derived from this software 1864904Smarcel * without specific prior written permission. 1964904Smarcel * 2064904Smarcel * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2164904Smarcel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2264904Smarcel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2364904Smarcel * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2464904Smarcel * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2564904Smarcel * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2664904Smarcel * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2764904Smarcel * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2864904Smarcel * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2964904Smarcel * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3064904Smarcel * THE POSSIBILITY OF SUCH DAMAGE. 3164904Smarcel */ 3264904Smarcel 3364904Smarcel#include <sys/cdefs.h> 3468201Sobrien__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 213364 2010-10-02 18:53:12Z marius $"); 3564904Smarcel 3668214Sgallatin/* 3768214Sgallatin * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 3868214Sgallatin */ 3968214Sgallatin 4064904Smarcel#include <sys/param.h> 4168214Sgallatin#include <sys/systm.h> 4268214Sgallatin#include <sys/kernel.h> 4368214Sgallatin#include <sys/module.h> 4464904Smarcel#include <sys/socket.h> 4568214Sgallatin#include <sys/bus.h> 4668214Sgallatin 4768214Sgallatin#include <net/if.h> 4868214Sgallatin#include <net/ethernet.h> 4968214Sgallatin#include <net/if_media.h> 5068214Sgallatin 5168214Sgallatin#include <dev/mii/mii.h> 5268214Sgallatin#include <dev/mii/miivar.h> 5368214Sgallatin#include "miidevs.h" 5468214Sgallatin 5568214Sgallatin#include <dev/mii/brgphyreg.h> 5668214Sgallatin#include <net/if_arp.h> 5768214Sgallatin#include <machine/bus.h> 5868214Sgallatin#include <dev/bge/if_bgereg.h> 5968214Sgallatin#include <dev/bce/if_bcereg.h> 6068214Sgallatin 6168214Sgallatin#include <dev/pci/pcireg.h> 6268214Sgallatin#include <dev/pci/pcivar.h> 6368214Sgallatin 6468214Sgallatin#include "miibus_if.h" 6564904Smarcel 66static int brgphy_probe(device_t); 67static int brgphy_attach(device_t); 68 69struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_oui; 72 int mii_model; 73 int mii_rev; 74 int serdes_flags; /* Keeps track of the serdes type used */ 75#define BRGPHY_5706S 0x0001 76#define BRGPHY_5708S 0x0002 77#define BRGPHY_NOANWAIT 0x0004 78#define BRGPHY_5709S 0x0008 79 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 80}; 81 82static device_method_t brgphy_methods[] = { 83 /* device interface */ 84 DEVMETHOD(device_probe, brgphy_probe), 85 DEVMETHOD(device_attach, brgphy_attach), 86 DEVMETHOD(device_detach, mii_phy_detach), 87 DEVMETHOD(device_shutdown, bus_generic_shutdown), 88 { 0, 0 } 89}; 90 91static devclass_t brgphy_devclass; 92 93static driver_t brgphy_driver = { 94 "brgphy", 95 brgphy_methods, 96 sizeof(struct brgphy_softc) 97}; 98 99DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 100 101static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102static void brgphy_setmedia(struct mii_softc *, int, int); 103static void brgphy_status(struct mii_softc *); 104static void brgphy_mii_phy_auto(struct mii_softc *); 105static void brgphy_reset(struct mii_softc *); 106static void brgphy_enable_loopback(struct mii_softc *); 107static void bcm5401_load_dspcode(struct mii_softc *); 108static void bcm5411_load_dspcode(struct mii_softc *); 109static void bcm54k2_load_dspcode(struct mii_softc *); 110static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 111static void brgphy_fixup_adc_bug(struct mii_softc *); 112static void brgphy_fixup_adjust_trim(struct mii_softc *); 113static void brgphy_fixup_ber_bug(struct mii_softc *); 114static void brgphy_fixup_crc_bug(struct mii_softc *); 115static void brgphy_fixup_jitter_bug(struct mii_softc *); 116static void brgphy_ethernet_wirespeed(struct mii_softc *); 117static void brgphy_jumbo_settings(struct mii_softc *, u_long); 118 119static const struct mii_phydesc brgphys[] = { 120 MII_PHY_DESC(xxBROADCOM, BCM5400), 121 MII_PHY_DESC(xxBROADCOM, BCM5401), 122 MII_PHY_DESC(xxBROADCOM, BCM5411), 123 MII_PHY_DESC(xxBROADCOM, BCM54K2), 124 MII_PHY_DESC(xxBROADCOM, BCM5701), 125 MII_PHY_DESC(xxBROADCOM, BCM5703), 126 MII_PHY_DESC(xxBROADCOM, BCM5704), 127 MII_PHY_DESC(xxBROADCOM, BCM5705), 128 MII_PHY_DESC(xxBROADCOM, BCM5706), 129 MII_PHY_DESC(xxBROADCOM, BCM5714), 130 MII_PHY_DESC(xxBROADCOM, BCM5750), 131 MII_PHY_DESC(xxBROADCOM, BCM5752), 132 MII_PHY_DESC(xxBROADCOM, BCM5754), 133 MII_PHY_DESC(xxBROADCOM, BCM5780), 134 MII_PHY_DESC(xxBROADCOM, BCM5708C), 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), 141 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 142 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), 143 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), 144 MII_PHY_DESC(BROADCOM2, BCM5906), 145 MII_PHY_END 146}; 147 148#define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 149#define HS21_BCM_CHIPID 0x57081021 150 151static int 152detect_hs21(struct bce_softc *bce_sc) 153{ 154 char *sysenv; 155 156 if (bce_sc->bce_chipid != HS21_BCM_CHIPID) 157 return (0); 158 sysenv = getenv("smbios.system.product"); 159 if (sysenv == NULL) 160 return (0); 161 if (strncmp(sysenv, HS21_PRODUCT_ID, strlen(HS21_PRODUCT_ID)) != 0) 162 return (0); 163 return (1); 164} 165 166/* Search for our PHY in the list of known PHYs */ 167static int 168brgphy_probe(device_t dev) 169{ 170 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 171} 172 173/* Attach the PHY to the MII bus */ 174static int 175brgphy_attach(device_t dev) 176{ 177 struct brgphy_softc *bsc; 178 struct bge_softc *bge_sc = NULL; 179 struct bce_softc *bce_sc = NULL; 180 struct mii_softc *sc; 181 struct mii_attach_args *ma; 182 struct mii_data *mii; 183 struct ifnet *ifp; 184 int fast_ether; 185 186 bsc = device_get_softc(dev); 187 sc = &bsc->mii_sc; 188 ma = device_get_ivars(dev); 189 sc->mii_dev = device_get_parent(dev); 190 mii = ma->mii_data; 191 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 192 193 /* Initialize mii_softc structure */ 194 sc->mii_inst = mii->mii_instance++; 195 sc->mii_phy = ma->mii_phyno; 196 sc->mii_service = brgphy_service; 197 sc->mii_pdata = mii; 198 199 /* 200 * At least some variants wedge when isolating, at least some also 201 * don't support loopback. 202 */ 203 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 204 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 205 206 /* Initialize brgphy_softc structure */ 207 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 208 bsc->mii_model = MII_MODEL(ma->mii_id2); 209 bsc->mii_rev = MII_REV(ma->mii_id2); 210 bsc->serdes_flags = 0; 211 212 fast_ether = 0; 213 214 if (bootverbose) 215 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 216 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 217 218 /* Handle any special cases based on the PHY ID */ 219 switch (bsc->mii_oui) { 220 case MII_OUI_BROADCOM: 221 case MII_OUI_BROADCOM2: 222 break; 223 case MII_OUI_xxBROADCOM: 224 switch (bsc->mii_model) { 225 case MII_MODEL_xxBROADCOM_BCM5706: 226 case MII_MODEL_xxBROADCOM_BCM5714: 227 /* 228 * The 5464 PHY used in the 5706 supports both copper 229 * and fiber interfaces over GMII. Need to check the 230 * shadow registers to see which mode is actually 231 * in effect, and therefore whether we have 5706C or 232 * 5706S. 233 */ 234 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 235 BRGPHY_SHADOW_1C_MODE_CTRL); 236 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 237 BRGPHY_SHADOW_1C_ENA_1000X) { 238 bsc->serdes_flags |= BRGPHY_5706S; 239 sc->mii_flags |= MIIF_HAVEFIBER; 240 } 241 break; 242 } break; 243 case MII_OUI_xxBROADCOM_ALT1: 244 switch (bsc->mii_model) { 245 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 246 bsc->serdes_flags |= BRGPHY_5708S; 247 sc->mii_flags |= MIIF_HAVEFIBER; 248 break; 249 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: 250 bsc->serdes_flags |= BRGPHY_5709S; 251 sc->mii_flags |= MIIF_HAVEFIBER; 252 break; 253 } 254 break; 255 default: 256 device_printf(dev, "Unrecognized OUI for PHY!\n"); 257 } 258 259 ifp = sc->mii_pdata->mii_ifp; 260 261 /* Find the MAC driver associated with this PHY. */ 262 if (strcmp(ifp->if_dname, "bge") == 0) { 263 bge_sc = ifp->if_softc; 264 } else if (strcmp(ifp->if_dname, "bce") == 0) { 265 bce_sc = ifp->if_softc; 266 } 267 268 /* Todo: Need to add additional controllers such as 5906 & 5787F */ 269 /* The 590x chips are 10/100 only. */ 270 if (bge_sc && 271 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 272 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 273 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 || 274 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 || 275 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) { 276 fast_ether = 1; 277 sc->mii_anegticks = MII_ANEGTICKS; 278 } 279 280 brgphy_reset(sc); 281 282 /* Read the PHY's capabilities. */ 283 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 284 if (sc->mii_capabilities & BMSR_EXTSTAT) 285 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 286 device_printf(dev, " "); 287 288#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 289 290 /* Add the supported media types */ 291 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 292 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), 293 BRGPHY_S10); 294 printf("10baseT, "); 295 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), 296 BRGPHY_S10 | BRGPHY_BMCR_FDX); 297 printf("10baseT-FDX, "); 298 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), 299 BRGPHY_S100); 300 printf("100baseTX, "); 301 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), 302 BRGPHY_S100 | BRGPHY_BMCR_FDX); 303 printf("100baseTX-FDX, "); 304 if (fast_ether == 0) { 305 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 306 BRGPHY_S1000); 307 printf("1000baseT, "); 308 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 309 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 310 printf("1000baseT-FDX, "); 311 } 312 } else { 313 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 314 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 315 printf("1000baseSX-FDX, "); 316 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 317 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 318 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 319 printf("2500baseSX-FDX, "); 320 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 321 (detect_hs21(bce_sc) != 0)) { 322 /* 323 * There appears to be certain silicon revision 324 * in IBM HS21 blades that is having issues with 325 * this driver wating for the auto-negotiation to 326 * complete. This happens with a specific chip id 327 * only and when the 1000baseSX-FDX is the only 328 * mode. Workaround this issue since it's unlikely 329 * to be ever addressed. 330 */ 331 printf("auto-neg workaround, "); 332 bsc->serdes_flags |= BRGPHY_NOANWAIT; 333 } 334 } 335 336 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 337 printf("auto\n"); 338 339#undef ADD 340 MIIBUS_MEDIAINIT(sc->mii_dev); 341 return (0); 342} 343 344static int 345brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 346{ 347 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 348 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 349 int val; 350 351 switch (cmd) { 352 case MII_POLLSTAT: 353 break; 354 case MII_MEDIACHG: 355 /* If the interface is not up, don't do anything. */ 356 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 357 break; 358 359 /* Todo: Why is this here? Is it really needed? */ 360 brgphy_reset(sc); /* XXX hardware bug work-around */ 361 362 switch (IFM_SUBTYPE(ife->ifm_media)) { 363 case IFM_AUTO: 364 brgphy_mii_phy_auto(sc); 365 break; 366 case IFM_2500_SX: 367 case IFM_1000_SX: 368 case IFM_1000_T: 369 case IFM_100_TX: 370 case IFM_10_T: 371 brgphy_setmedia(sc, ife->ifm_media, 372 mii->mii_ifp->if_flags & IFF_LINK0); 373 break; 374 default: 375 return (EINVAL); 376 } 377 break; 378 case MII_TICK: 379 /* Bail if the interface isn't up. */ 380 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 381 return (0); 382 383 384 /* Bail if autoneg isn't in process. */ 385 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 386 sc->mii_ticks = 0; 387 break; 388 } 389 390 /* 391 * Check to see if we have link. If we do, we don't 392 * need to restart the autonegotiation process. 393 */ 394 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 395 if (val & BMSR_LINK) { 396 sc->mii_ticks = 0; /* Reset autoneg timer. */ 397 break; 398 } 399 400 /* Announce link loss right after it happens. */ 401 if (sc->mii_ticks++ == 0) 402 break; 403 404 /* Only retry autonegotiation every mii_anegticks seconds. */ 405 if (sc->mii_ticks <= sc->mii_anegticks) 406 break; 407 408 409 /* Retry autonegotiation */ 410 sc->mii_ticks = 0; 411 brgphy_mii_phy_auto(sc); 412 break; 413 } 414 415 /* Update the media status. */ 416 brgphy_status(sc); 417 418 /* 419 * Callback if something changed. Note that we need to poke 420 * the DSP on the Broadcom PHYs if the media changes. 421 */ 422 if (sc->mii_media_active != mii->mii_media_active || 423 sc->mii_media_status != mii->mii_media_status || 424 cmd == MII_MEDIACHG) { 425 switch (bsc->mii_oui) { 426 case MII_OUI_BROADCOM: 427 break; 428 case MII_OUI_xxBROADCOM: 429 switch (bsc->mii_model) { 430 case MII_MODEL_xxBROADCOM_BCM5400: 431 bcm5401_load_dspcode(sc); 432 break; 433 case MII_MODEL_xxBROADCOM_BCM5401: 434 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 435 bcm5401_load_dspcode(sc); 436 break; 437 case MII_MODEL_xxBROADCOM_BCM5411: 438 bcm5411_load_dspcode(sc); 439 break; 440 case MII_MODEL_xxBROADCOM_BCM54K2: 441 bcm54k2_load_dspcode(sc); 442 break; 443 } 444 break; 445 case MII_OUI_xxBROADCOM_ALT1: 446 break; 447 } 448 } 449 mii_phy_update(sc, cmd); 450 return (0); 451} 452 453 454/****************************************************************************/ 455/* Sets the PHY link speed. */ 456/* */ 457/* Returns: */ 458/* None */ 459/****************************************************************************/ 460static void 461brgphy_setmedia(struct mii_softc *sc, int media, int master) 462{ 463 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 464 int bmcr = 0, gig; 465 466 /* Calculate the value for the BMCR register. */ 467 switch (IFM_SUBTYPE(media)) { 468 case IFM_2500_SX: 469 break; 470 case IFM_1000_SX: 471 case IFM_1000_T: 472 bmcr = BRGPHY_S1000; 473 break; 474 case IFM_100_TX: 475 bmcr = BRGPHY_S100; 476 break; 477 case IFM_10_T: 478 default: 479 bmcr = BRGPHY_S10; 480 break; 481 } 482 483 /* Calculate duplex settings for 1000BasetT/1000BaseX. */ 484 if ((media & IFM_GMASK) == IFM_FDX) { 485 bmcr |= BRGPHY_BMCR_FDX; 486 gig = BRGPHY_1000CTL_AFD; 487 } else { 488 gig = BRGPHY_1000CTL_AHD; 489 } 490 491 /* Force loopback to disconnect PHY for Ethernet medium. */ 492 brgphy_enable_loopback(sc); 493 494 /* Disable 1000BaseT advertisements. */ 495 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 496 /* Disable 10/100 advertisements. */ 497 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 498 /* Write forced link speed. */ 499 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 500 501 /* If 10/100 only then configuration is complete. */ 502 if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX)) 503 goto brgphy_setmedia_exit; 504 505 /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */ 506 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 507 /* Restart auto-negotiation for 1000BaseT/1000BaseX. */ 508 PHY_WRITE(sc, BRGPHY_MII_BMCR, 509 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 510 511 /* If not 5701 PHY then configuration is complete. */ 512 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 513 goto brgphy_setmedia_exit; 514 515 /* 516 * When setting the link manually, one side must be the master and 517 * the other the slave. However ifmedia doesn't give us a good way 518 * to specify this, so we fake it by using one of the LINK flags. 519 * If LINK0 is set, we program the PHY to be a master, otherwise 520 * it's a slave. 521 */ 522 if (master) { 523 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 524 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 525 } else { 526 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 527 gig | BRGPHY_1000CTL_MSE); 528 } 529 530brgphy_setmedia_exit: 531 return; 532} 533 534/****************************************************************************/ 535/* Set the media status based on the PHY settings. */ 536/* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled) */ 537/* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled) */ 538/* */ 539/* Returns: */ 540/* None */ 541/****************************************************************************/ 542static void 543brgphy_status(struct mii_softc *sc) 544{ 545 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 546 struct mii_data *mii = sc->mii_pdata; 547 int aux, bmcr, bmsr, anar, anlpar, xstat, val; 548 549 550 mii->mii_media_status = IFM_AVALID; 551 mii->mii_media_active = IFM_ETHER; 552 553 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 554 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 555 anar = PHY_READ(sc, BRGPHY_MII_ANAR); 556 anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR); 557 558 /* Loopback is enabled. */ 559 if (bmcr & BRGPHY_BMCR_LOOP) { 560 561 mii->mii_media_active |= IFM_LOOP; 562 } 563 564 /* Autoneg is still in progress. */ 565 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 566 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 567 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 568 /* Erg, still trying, I guess... */ 569 mii->mii_media_active |= IFM_NONE; 570 goto brgphy_status_exit; 571 } 572 573 /* Autoneg is enabled and complete, link should be up. */ 574 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 575 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 576 577 /* If copper link is up, get the negotiated speed/duplex. */ 578 if (aux & BRGPHY_AUXSTS_LINK) { 579 mii->mii_media_status |= IFM_ACTIVE; 580 switch (aux & BRGPHY_AUXSTS_AN_RES) { 581 case BRGPHY_RES_1000FD: 582 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 583 case BRGPHY_RES_1000HD: 584 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 585 case BRGPHY_RES_100FD: 586 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 587 case BRGPHY_RES_100T4: 588 mii->mii_media_active |= IFM_100_T4; break; 589 case BRGPHY_RES_100HD: 590 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 591 case BRGPHY_RES_10FD: 592 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 593 case BRGPHY_RES_10HD: 594 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 595 default: 596 mii->mii_media_active |= IFM_NONE; break; 597 } 598 } 599 } else { 600 /* If serdes link is up, get the negotiated speed/duplex. */ 601 if (bmsr & BRGPHY_BMSR_LINK) { 602 mii->mii_media_status |= IFM_ACTIVE; 603 } 604 605 /* Check the link speed/duplex based on the PHY type. */ 606 if (bsc->serdes_flags & BRGPHY_5706S) { 607 mii->mii_media_active |= IFM_1000_SX; 608 609 /* If autoneg enabled, read negotiated duplex settings */ 610 if (bmcr & BRGPHY_BMCR_AUTOEN) { 611 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 612 if (val & BRGPHY_SERDES_ANAR_FDX) 613 mii->mii_media_active |= IFM_FDX; 614 else 615 mii->mii_media_active |= IFM_HDX; 616 } 617 618 } else if (bsc->serdes_flags & BRGPHY_5708S) { 619 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 620 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 621 622 /* Check for MRBE auto-negotiated speed results. */ 623 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 624 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 625 mii->mii_media_active |= IFM_10_FL; break; 626 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 627 mii->mii_media_active |= IFM_100_FX; break; 628 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 629 mii->mii_media_active |= IFM_1000_SX; break; 630 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 631 mii->mii_media_active |= IFM_2500_SX; break; 632 } 633 634 /* Check for MRBE auto-negotiated duplex results. */ 635 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 636 mii->mii_media_active |= IFM_FDX; 637 else 638 mii->mii_media_active |= IFM_HDX; 639 640 } else if (bsc->serdes_flags & BRGPHY_5709S) { 641 642 /* Select GP Status Block of the AN MMD, get autoneg results. */ 643 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 644 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 645 646 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 647 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 648 649 /* Check for MRBE auto-negotiated speed results. */ 650 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 651 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 652 mii->mii_media_active |= IFM_10_FL; break; 653 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 654 mii->mii_media_active |= IFM_100_FX; break; 655 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 656 mii->mii_media_active |= IFM_1000_SX; break; 657 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 658 mii->mii_media_active |= IFM_2500_SX; break; 659 } 660 661 /* Check for MRBE auto-negotiated duplex results. */ 662 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 663 mii->mii_media_active |= IFM_FDX; 664 else 665 mii->mii_media_active |= IFM_HDX; 666 } 667 668 } 669 670 /* Todo: Change bge to use these settings. */ 671 672 /* Fetch flow control settings from the copper PHY. */ 673 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 674 /* Set FLAG0 if RX is enabled and FLAG1 if TX is enabled */ 675 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) { 676 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 677 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) && 678 (anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 679 mii->mii_media_active |= IFM_FLAG1; 680 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) && 681 !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 682 mii->mii_media_active |= IFM_FLAG0; 683 } 684 } 685 686 /* Todo: Add support for fiber settings too. */ 687 688 689brgphy_status_exit: 690 return; 691} 692 693static void 694brgphy_mii_phy_auto(struct mii_softc *sc) 695{ 696 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 697 int ktcr = 0; 698 699 brgphy_reset(sc); 700 701 /* Enable flow control in the advertisement register. */ 702 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 703 /* Pause capability advertisement (pause capable & asymmetric) */ 704 PHY_WRITE(sc, BRGPHY_MII_ANAR, 705 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA | 706 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC); 707 } else { 708 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX | 709 BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE); 710 } 711 712 /* Enable speed in the 1000baseT control register */ 713 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 714 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 715 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 716 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 717 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 718 719 /* Start autonegotiation */ 720 PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 721 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 722 723} 724 725 726/* Enable loopback to force the link down. */ 727static void 728brgphy_enable_loopback(struct mii_softc *sc) 729{ 730 int i; 731 732 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 733 for (i = 0; i < 15000; i++) { 734 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 735 break; 736 DELAY(10); 737 } 738} 739 740/* Turn off tap power management on 5401. */ 741static void 742bcm5401_load_dspcode(struct mii_softc *sc) 743{ 744 static const struct { 745 int reg; 746 uint16_t val; 747 } dspcode[] = { 748 { BRGPHY_MII_AUXCTL, 0x0c20 }, 749 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 750 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 751 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 752 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 753 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 754 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 755 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 756 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 757 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 758 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 759 { 0, 0 }, 760 }; 761 int i; 762 763 for (i = 0; dspcode[i].reg != 0; i++) 764 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 765 DELAY(40); 766} 767 768static void 769bcm5411_load_dspcode(struct mii_softc *sc) 770{ 771 static const struct { 772 int reg; 773 uint16_t val; 774 } dspcode[] = { 775 { 0x1c, 0x8c23 }, 776 { 0x1c, 0x8ca3 }, 777 { 0x1c, 0x8c23 }, 778 { 0, 0 }, 779 }; 780 int i; 781 782 for (i = 0; dspcode[i].reg != 0; i++) 783 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 784} 785 786void 787bcm54k2_load_dspcode(struct mii_softc *sc) 788{ 789 static const struct { 790 int reg; 791 uint16_t val; 792 } dspcode[] = { 793 { 4, 0x01e1 }, 794 { 9, 0x0300 }, 795 { 0, 0 }, 796 }; 797 int i; 798 799 for (i = 0; dspcode[i].reg != 0; i++) 800 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 801 802} 803 804static void 805brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 806{ 807 static const struct { 808 int reg; 809 uint16_t val; 810 } dspcode[] = { 811 { 0x1c, 0x8d68 }, 812 { 0x1c, 0x8d68 }, 813 { 0, 0 }, 814 }; 815 int i; 816 817 for (i = 0; dspcode[i].reg != 0; i++) 818 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 819} 820 821static void 822brgphy_fixup_adc_bug(struct mii_softc *sc) 823{ 824 static const struct { 825 int reg; 826 uint16_t val; 827 } dspcode[] = { 828 { BRGPHY_MII_AUXCTL, 0x0c00 }, 829 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 830 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 831 { 0, 0 }, 832 }; 833 int i; 834 835 for (i = 0; dspcode[i].reg != 0; i++) 836 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 837} 838 839static void 840brgphy_fixup_adjust_trim(struct mii_softc *sc) 841{ 842 static const struct { 843 int reg; 844 uint16_t val; 845 } dspcode[] = { 846 { BRGPHY_MII_AUXCTL, 0x0c00 }, 847 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 848 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 849 { BRGPHY_MII_TEST1, 0x0014 }, 850 { BRGPHY_MII_AUXCTL, 0x0400 }, 851 { 0, 0 }, 852 }; 853 int i; 854 855 for (i = 0; dspcode[i].reg != 0; i++) 856 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 857} 858 859static void 860brgphy_fixup_ber_bug(struct mii_softc *sc) 861{ 862 static const struct { 863 int reg; 864 uint16_t val; 865 } dspcode[] = { 866 { BRGPHY_MII_AUXCTL, 0x0c00 }, 867 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 868 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 869 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 870 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 871 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 872 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 873 { BRGPHY_MII_AUXCTL, 0x0400 }, 874 { 0, 0 }, 875 }; 876 int i; 877 878 for (i = 0; dspcode[i].reg != 0; i++) 879 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 880} 881 882static void 883brgphy_fixup_crc_bug(struct mii_softc *sc) 884{ 885 static const struct { 886 int reg; 887 uint16_t val; 888 } dspcode[] = { 889 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 890 { 0x1c, 0x8c68 }, 891 { 0x1c, 0x8d68 }, 892 { 0x1c, 0x8c68 }, 893 { 0, 0 }, 894 }; 895 int i; 896 897 for (i = 0; dspcode[i].reg != 0; i++) 898 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 899} 900 901static void 902brgphy_fixup_jitter_bug(struct mii_softc *sc) 903{ 904 static const struct { 905 int reg; 906 uint16_t val; 907 } dspcode[] = { 908 { BRGPHY_MII_AUXCTL, 0x0c00 }, 909 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 910 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 911 { BRGPHY_MII_AUXCTL, 0x0400 }, 912 { 0, 0 }, 913 }; 914 int i; 915 916 for (i = 0; dspcode[i].reg != 0; i++) 917 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 918} 919 920 921static void 922brgphy_fixup_disable_early_dac(struct mii_softc *sc) 923{ 924 uint32_t val; 925 926 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 927 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 928 val &= ~(1 << 8); 929 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 930 931} 932 933 934static void 935brgphy_ethernet_wirespeed(struct mii_softc *sc) 936{ 937 uint32_t val; 938 939 /* Enable Ethernet@WireSpeed. */ 940 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 941 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 942 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 943} 944 945 946static void 947brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 948{ 949 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 950 uint32_t val; 951 952 /* Set or clear jumbo frame settings in the PHY. */ 953 if (mtu > ETHER_MAX_LEN) { 954 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 955 /* BCM5401 PHY cannot read-modify-write. */ 956 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 957 } else { 958 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 959 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 960 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 961 val | BRGPHY_AUXCTL_LONG_PKT); 962 } 963 964 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 965 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 966 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 967 } else { 968 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 969 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 970 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 971 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 972 973 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 974 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 975 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 976 } 977} 978 979static void 980brgphy_reset(struct mii_softc *sc) 981{ 982 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 983 struct bge_softc *bge_sc = NULL; 984 struct bce_softc *bce_sc = NULL; 985 struct ifnet *ifp; 986 int val; 987 988 /* Perform a standard PHY reset. */ 989 mii_phy_reset(sc); 990 991 /* Handle any PHY specific procedures following the reset. */ 992 switch (bsc->mii_oui) { 993 case MII_OUI_BROADCOM: 994 break; 995 case MII_OUI_xxBROADCOM: 996 switch (bsc->mii_model) { 997 case MII_MODEL_xxBROADCOM_BCM5400: 998 bcm5401_load_dspcode(sc); 999 break; 1000 case MII_MODEL_xxBROADCOM_BCM5401: 1001 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 1002 bcm5401_load_dspcode(sc); 1003 break; 1004 case MII_MODEL_xxBROADCOM_BCM5411: 1005 bcm5411_load_dspcode(sc); 1006 break; 1007 case MII_MODEL_xxBROADCOM_BCM54K2: 1008 bcm54k2_load_dspcode(sc); 1009 break; 1010 } 1011 break; 1012 case MII_OUI_xxBROADCOM_ALT1: 1013 break; 1014 } 1015 1016 ifp = sc->mii_pdata->mii_ifp; 1017 1018 /* Find the driver associated with this PHY. */ 1019 if (strcmp(ifp->if_dname, "bge") == 0) { 1020 bge_sc = ifp->if_softc; 1021 } else if (strcmp(ifp->if_dname, "bce") == 0) { 1022 bce_sc = ifp->if_softc; 1023 } 1024 1025 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 1026 if (bge_sc) { 1027 /* Fix up various bugs */ 1028 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 1029 brgphy_fixup_5704_a0_bug(sc); 1030 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 1031 brgphy_fixup_adc_bug(sc); 1032 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) 1033 brgphy_fixup_adjust_trim(sc); 1034 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) 1035 brgphy_fixup_ber_bug(sc); 1036 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 1037 brgphy_fixup_crc_bug(sc); 1038 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) 1039 brgphy_fixup_jitter_bug(sc); 1040 1041 brgphy_jumbo_settings(sc, ifp->if_mtu); 1042 1043 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED) 1044 brgphy_ethernet_wirespeed(sc); 1045 1046 /* Enable Link LED on Dell boxes */ 1047 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 1048 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1049 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 1050 ~BRGPHY_PHY_EXTCTL_3_LED); 1051 } 1052 1053 /* Adjust output voltage (From Linux driver) */ 1054 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 1055 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 1056 1057 /* Handle any bce (NetXtreme II) workarounds. */ 1058 } else if (bce_sc) { 1059 1060 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1061 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1062 1063 /* Store autoneg capabilities/results in digital block (Page 0) */ 1064 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1065 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1066 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1067 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1068 1069 /* Enable fiber mode and autodetection */ 1070 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1071 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1072 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1073 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1074 1075 /* Enable parallel detection */ 1076 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1077 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1078 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1079 1080 /* Advertise 2.5G support through next page during autoneg */ 1081 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1082 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1083 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1084 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1085 1086 /* Increase TX signal amplitude */ 1087 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1088 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1089 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1090 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1091 BRGPHY_5708S_TX_MISC_PG5); 1092 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1093 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1094 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1095 BRGPHY_5708S_DIG_PG0); 1096 } 1097 1098 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1099 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1100 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1101 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1102 BRGPHY_5708S_TX_MISC_PG5); 1103 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1104 bce_sc->bce_port_hw_cfg & 1105 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1106 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1107 BRGPHY_5708S_DIG_PG0); 1108 } 1109 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1110 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1111 1112 /* Select the SerDes Digital block of the AN MMD. */ 1113 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1114 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1115 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1116 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1117 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1118 1119 /* Select the Over 1G block of the AN MMD. */ 1120 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1121 1122 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1123 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1124 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1125 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1126 else 1127 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1128 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1129 1130 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1131 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1132 1133 /* Enable MRBE speed autoneg. */ 1134 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1135 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1136 BRGPHY_MRBE_MSG_PG5_NP_T2; 1137 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1138 1139 /* Select the Clause 73 User B0 block of the AN MMD. */ 1140 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1141 1142 /* Enable MRBE speed autoneg. */ 1143 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1144 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1145 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1146 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1147 1148 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1149 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1150 1151 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1152 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1153 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1154 brgphy_fixup_disable_early_dac(sc); 1155 1156 brgphy_jumbo_settings(sc, ifp->if_mtu); 1157 brgphy_ethernet_wirespeed(sc); 1158 } else { 1159 brgphy_fixup_ber_bug(sc); 1160 brgphy_jumbo_settings(sc, ifp->if_mtu); 1161 brgphy_ethernet_wirespeed(sc); 1162 } 1163 1164 } 1165} 1166