brgphy.c revision 207391
1207753Smm/*- 2207753Smm * Copyright (c) 2000 3207753Smm * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4207753Smm * 5207753Smm * Redistribution and use in source and binary forms, with or without 6207753Smm * modification, are permitted provided that the following conditions 7207753Smm * are met: 8207753Smm * 1. Redistributions of source code must retain the above copyright 9207753Smm * notice, this list of conditions and the following disclaimer. 10207753Smm * 2. Redistributions in binary form must reproduce the above copyright 11207753Smm * notice, this list of conditions and the following disclaimer in the 12207753Smm * documentation and/or other materials provided with the distribution. 13207753Smm * 3. All advertising materials mentioning features or use of this software 14207753Smm * must display the following acknowledgement: 15207753Smm * This product includes software developed by Bill Paul. 16207753Smm * 4. Neither the name of the author nor the names of any co-contributors 17207753Smm * may be used to endorse or promote products derived from this software 18207753Smm * without specific prior written permission. 19207753Smm * 20207753Smm * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21207753Smm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22207753Smm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23207753Smm * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24207753Smm * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25207753Smm * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26207753Smm * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27207753Smm * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28207753Smm * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29207753Smm * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30207753Smm * THE POSSIBILITY OF SUCH DAMAGE. 31207753Smm */ 32207753Smm 33207753Smm#include <sys/cdefs.h> 34207753Smm__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 207391 2010-04-29 22:00:57Z davidch $"); 35207753Smm 36207753Smm/* 37207753Smm * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38207753Smm */ 39207753Smm 40207753Smm#include <sys/param.h> 41207753Smm#include <sys/systm.h> 42207753Smm#include <sys/kernel.h> 43207753Smm#include <sys/module.h> 44207753Smm#include <sys/socket.h> 45207753Smm#include <sys/bus.h> 46207753Smm 47207753Smm#include <net/if.h> 48207753Smm#include <net/ethernet.h> 49207753Smm#include <net/if_media.h> 50207753Smm 51207753Smm#include <dev/mii/mii.h> 52207753Smm#include <dev/mii/miivar.h> 53207753Smm#include "miidevs.h" 54207753Smm 55207753Smm#include <dev/mii/brgphyreg.h> 56207753Smm#include <net/if_arp.h> 57207753Smm#include <machine/bus.h> 58207753Smm#include <dev/bge/if_bgereg.h> 59207753Smm#include <dev/bce/if_bcereg.h> 60207753Smm 61207753Smm#include <dev/pci/pcireg.h> 62207753Smm#include <dev/pci/pcivar.h> 63207753Smm 64207753Smm#include "miibus_if.h" 65207753Smm 66207753Smmstatic int brgphy_probe(device_t); 67207753Smmstatic int brgphy_attach(device_t); 68207753Smm 69207753Smmstruct brgphy_softc { 70207753Smm struct mii_softc mii_sc; 71207753Smm int mii_oui; 72207753Smm int mii_model; 73207753Smm int mii_rev; 74207753Smm int serdes_flags; /* Keeps track of the serdes type used */ 75207753Smm#define BRGPHY_5706S 0x0001 76207753Smm#define BRGPHY_5708S 0x0002 77207753Smm#define BRGPHY_NOANWAIT 0x0004 78207753Smm#define BRGPHY_5709S 0x0008 79207753Smm int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 80207753Smm}; 81207753Smm 82207753Smmstatic device_method_t brgphy_methods[] = { 83207753Smm /* device interface */ 84207753Smm DEVMETHOD(device_probe, brgphy_probe), 85207753Smm DEVMETHOD(device_attach, brgphy_attach), 86207753Smm DEVMETHOD(device_detach, mii_phy_detach), 87207753Smm DEVMETHOD(device_shutdown, bus_generic_shutdown), 88207753Smm { 0, 0 } 89}; 90 91static devclass_t brgphy_devclass; 92 93static driver_t brgphy_driver = { 94 "brgphy", 95 brgphy_methods, 96 sizeof(struct brgphy_softc) 97}; 98 99DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 100 101static int brgphy_service(struct mii_softc *, struct mii_data *, int); 102static void brgphy_setmedia(struct mii_softc *, int, int); 103static void brgphy_status(struct mii_softc *); 104static void brgphy_mii_phy_auto(struct mii_softc *); 105static void brgphy_reset(struct mii_softc *); 106static void brgphy_enable_loopback(struct mii_softc *); 107static void bcm5401_load_dspcode(struct mii_softc *); 108static void bcm5411_load_dspcode(struct mii_softc *); 109static void bcm54k2_load_dspcode(struct mii_softc *); 110static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 111static void brgphy_fixup_adc_bug(struct mii_softc *); 112static void brgphy_fixup_adjust_trim(struct mii_softc *); 113static void brgphy_fixup_ber_bug(struct mii_softc *); 114static void brgphy_fixup_crc_bug(struct mii_softc *); 115static void brgphy_fixup_jitter_bug(struct mii_softc *); 116static void brgphy_ethernet_wirespeed(struct mii_softc *); 117static void brgphy_jumbo_settings(struct mii_softc *, u_long); 118 119static const struct mii_phydesc brgphys[] = { 120 MII_PHY_DESC(xxBROADCOM, BCM5400), 121 MII_PHY_DESC(xxBROADCOM, BCM5401), 122 MII_PHY_DESC(xxBROADCOM, BCM5411), 123 MII_PHY_DESC(xxBROADCOM, BCM54K2), 124 MII_PHY_DESC(xxBROADCOM, BCM5701), 125 MII_PHY_DESC(xxBROADCOM, BCM5703), 126 MII_PHY_DESC(xxBROADCOM, BCM5704), 127 MII_PHY_DESC(xxBROADCOM, BCM5705), 128 MII_PHY_DESC(xxBROADCOM, BCM5706), 129 MII_PHY_DESC(xxBROADCOM, BCM5714), 130 MII_PHY_DESC(xxBROADCOM, BCM5750), 131 MII_PHY_DESC(xxBROADCOM, BCM5752), 132 MII_PHY_DESC(xxBROADCOM, BCM5754), 133 MII_PHY_DESC(xxBROADCOM, BCM5780), 134 MII_PHY_DESC(xxBROADCOM, BCM5708C), 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), 141 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 142 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), 143 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), 144 MII_PHY_DESC(BROADCOM2, BCM5906), 145 MII_PHY_END 146}; 147 148#define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 149#define HS21_BCM_CHIPID 0x57081021 150 151static int 152detect_hs21(struct bce_softc *bce_sc) 153{ 154 char *sysenv; 155 156 if (bce_sc->bce_chipid != HS21_BCM_CHIPID) 157 return (0); 158 sysenv = getenv("smbios.system.product"); 159 if (sysenv == NULL) 160 return (0); 161 if (strncmp(sysenv, HS21_PRODUCT_ID, strlen(HS21_PRODUCT_ID)) != 0) 162 return (0); 163 return (1); 164} 165 166/* Search for our PHY in the list of known PHYs */ 167static int 168brgphy_probe(device_t dev) 169{ 170 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 171} 172 173/* Attach the PHY to the MII bus */ 174static int 175brgphy_attach(device_t dev) 176{ 177 struct brgphy_softc *bsc; 178 struct bge_softc *bge_sc = NULL; 179 struct bce_softc *bce_sc = NULL; 180 struct mii_softc *sc; 181 struct mii_attach_args *ma; 182 struct mii_data *mii; 183 struct ifnet *ifp; 184 int fast_ether; 185 186 bsc = device_get_softc(dev); 187 sc = &bsc->mii_sc; 188 ma = device_get_ivars(dev); 189 sc->mii_dev = device_get_parent(dev); 190 mii = device_get_softc(sc->mii_dev); 191 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 192 193 /* Initialize mii_softc structure */ 194 sc->mii_inst = mii->mii_instance; 195 sc->mii_phy = ma->mii_phyno; 196 sc->mii_service = brgphy_service; 197 sc->mii_pdata = mii; 198 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 199 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 200 mii->mii_instance++; 201 202 /* Initialize brgphy_softc structure */ 203 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 204 bsc->mii_model = MII_MODEL(ma->mii_id2); 205 bsc->mii_rev = MII_REV(ma->mii_id2); 206 bsc->serdes_flags = 0; 207 208 fast_ether = 0; 209 210 if (bootverbose) 211 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 212 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 213 214 /* Handle any special cases based on the PHY ID */ 215 switch (bsc->mii_oui) { 216 case MII_OUI_BROADCOM: 217 case MII_OUI_BROADCOM2: 218 break; 219 case MII_OUI_xxBROADCOM: 220 switch (bsc->mii_model) { 221 case MII_MODEL_xxBROADCOM_BCM5706: 222 case MII_MODEL_xxBROADCOM_BCM5714: 223 /* 224 * The 5464 PHY used in the 5706 supports both copper 225 * and fiber interfaces over GMII. Need to check the 226 * shadow registers to see which mode is actually 227 * in effect, and therefore whether we have 5706C or 228 * 5706S. 229 */ 230 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 231 BRGPHY_SHADOW_1C_MODE_CTRL); 232 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 233 BRGPHY_SHADOW_1C_ENA_1000X) { 234 bsc->serdes_flags |= BRGPHY_5706S; 235 sc->mii_flags |= MIIF_HAVEFIBER; 236 } 237 break; 238 } break; 239 case MII_OUI_xxBROADCOM_ALT1: 240 switch (bsc->mii_model) { 241 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 242 bsc->serdes_flags |= BRGPHY_5708S; 243 sc->mii_flags |= MIIF_HAVEFIBER; 244 break; 245 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: 246 bsc->serdes_flags |= BRGPHY_5709S; 247 sc->mii_flags |= MIIF_HAVEFIBER; 248 break; 249 } break; 250 default: 251 device_printf(dev, "Unrecognized OUI for PHY!\n"); 252 } 253 254 ifp = sc->mii_pdata->mii_ifp; 255 256 /* Find the MAC driver associated with this PHY. */ 257 if (strcmp(ifp->if_dname, "bge") == 0) { 258 bge_sc = ifp->if_softc; 259 } else if (strcmp(ifp->if_dname, "bce") == 0) { 260 bce_sc = ifp->if_softc; 261 } 262 263 /* Todo: Need to add additional controllers such as 5906 & 5787F */ 264 /* The 590x chips are 10/100 only. */ 265 if (bge_sc && 266 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 267 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 268 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 || 269 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 || 270 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) { 271 fast_ether = 1; 272 sc->mii_anegticks = MII_ANEGTICKS; 273 } 274 275 brgphy_reset(sc); 276 277 /* Read the PHY's capabilities. */ 278 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 279 if (sc->mii_capabilities & BMSR_EXTSTAT) 280 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 281 device_printf(dev, " "); 282 283#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 284 285 /* Create an instance of Ethernet media. */ 286 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO); 287 288 /* Add the supported media types */ 289 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 290 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), 291 BRGPHY_S10); 292 printf("10baseT, "); 293 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), 294 BRGPHY_S10 | BRGPHY_BMCR_FDX); 295 printf("10baseT-FDX, "); 296 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), 297 BRGPHY_S100); 298 printf("100baseTX, "); 299 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), 300 BRGPHY_S100 | BRGPHY_BMCR_FDX); 301 printf("100baseTX-FDX, "); 302 if (fast_ether == 0) { 303 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 304 BRGPHY_S1000); 305 printf("1000baseT, "); 306 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 307 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 308 printf("1000baseT-FDX, "); 309 } 310 } else { 311 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 312 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 313 printf("1000baseSX-FDX, "); 314 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 315 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 316 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 317 printf("2500baseSX-FDX, "); 318 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 319 (detect_hs21(bce_sc) != 0)) { 320 /* 321 * There appears to be certain silicon revision 322 * in IBM HS21 blades that is having issues with 323 * this driver wating for the auto-negotiation to 324 * complete. This happens with a specific chip id 325 * only and when the 1000baseSX-FDX is the only 326 * mode. Workaround this issue since it's unlikely 327 * to be ever addressed. 328 */ 329 printf("auto-neg workaround, "); 330 bsc->serdes_flags |= BRGPHY_NOANWAIT; 331 } 332 } 333 334 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 335 printf("auto\n"); 336 337#undef ADD 338 MIIBUS_MEDIAINIT(sc->mii_dev); 339 return (0); 340} 341 342static int 343brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 344{ 345 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 346 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 347 int error = 0; 348 int val; 349 350 switch (cmd) { 351 case MII_POLLSTAT: 352 /* If we're not polling our PHY instance, just return. */ 353 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 354 goto brgphy_service_exit; 355 break; 356 case MII_MEDIACHG: 357 /* 358 * If the media indicates a different PHY instance, 359 * isolate ourselves. 360 */ 361 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 362 PHY_WRITE(sc, MII_BMCR, 363 PHY_READ(sc, MII_BMCR) | BMCR_ISO); 364 goto brgphy_service_exit; 365 } 366 367 /* If the interface is not up, don't do anything. */ 368 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 369 break; 370 371 /* Todo: Why is this here? Is it really needed? */ 372 brgphy_reset(sc); /* XXX hardware bug work-around */ 373 374 switch (IFM_SUBTYPE(ife->ifm_media)) { 375 case IFM_AUTO: 376 brgphy_mii_phy_auto(sc); 377 break; 378 case IFM_2500_SX: 379 case IFM_1000_SX: 380 case IFM_1000_T: 381 case IFM_100_TX: 382 case IFM_10_T: 383 brgphy_setmedia(sc, ife->ifm_media, 384 mii->mii_ifp->if_flags & IFF_LINK0); 385 break; 386 default: 387 error = EINVAL; 388 goto brgphy_service_exit; 389 } 390 break; 391 case MII_TICK: 392 /* Bail if we're not currently selected. */ 393 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 394 goto brgphy_service_exit; 395 396 /* Bail if the interface isn't up. */ 397 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 398 goto brgphy_service_exit; 399 400 401 /* Bail if autoneg isn't in process. */ 402 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 403 sc->mii_ticks = 0; 404 break; 405 } 406 407 /* 408 * Check to see if we have link. If we do, we don't 409 * need to restart the autonegotiation process. 410 */ 411 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 412 if (val & BMSR_LINK) { 413 sc->mii_ticks = 0; /* Reset autoneg timer. */ 414 break; 415 } 416 417 /* Announce link loss right after it happens. */ 418 if (sc->mii_ticks++ == 0) 419 break; 420 421 /* Only retry autonegotiation every mii_anegticks seconds. */ 422 if (sc->mii_ticks <= sc->mii_anegticks) 423 break; 424 425 426 /* Retry autonegotiation */ 427 sc->mii_ticks = 0; 428 brgphy_mii_phy_auto(sc); 429 break; 430 } 431 432 /* Update the media status. */ 433 brgphy_status(sc); 434 435 /* 436 * Callback if something changed. Note that we need to poke 437 * the DSP on the Broadcom PHYs if the media changes. 438 */ 439 if (sc->mii_media_active != mii->mii_media_active || 440 sc->mii_media_status != mii->mii_media_status || 441 cmd == MII_MEDIACHG) { 442 switch (bsc->mii_oui) { 443 case MII_OUI_BROADCOM: 444 break; 445 case MII_OUI_xxBROADCOM: 446 switch (bsc->mii_model) { 447 case MII_MODEL_xxBROADCOM_BCM5400: 448 bcm5401_load_dspcode(sc); 449 break; 450 case MII_MODEL_xxBROADCOM_BCM5401: 451 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 452 bcm5401_load_dspcode(sc); 453 break; 454 case MII_MODEL_xxBROADCOM_BCM5411: 455 bcm5411_load_dspcode(sc); 456 break; 457 case MII_MODEL_xxBROADCOM_BCM54K2: 458 bcm54k2_load_dspcode(sc); 459 break; 460 } 461 break; 462 case MII_OUI_xxBROADCOM_ALT1: 463 break; 464 } 465 } 466 mii_phy_update(sc, cmd); 467brgphy_service_exit: 468 return (error); 469} 470 471 472/****************************************************************************/ 473/* Sets the PHY link speed. */ 474/* */ 475/* Returns: */ 476/* None */ 477/****************************************************************************/ 478static void 479brgphy_setmedia(struct mii_softc *sc, int media, int master) 480{ 481 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 482 int bmcr = 0, gig; 483 484 /* Calculate the value for the BMCR register. */ 485 switch (IFM_SUBTYPE(media)) { 486 case IFM_2500_SX: 487 break; 488 case IFM_1000_SX: 489 case IFM_1000_T: 490 bmcr = BRGPHY_S1000; 491 break; 492 case IFM_100_TX: 493 bmcr = BRGPHY_S100; 494 break; 495 case IFM_10_T: 496 default: 497 bmcr = BRGPHY_S10; 498 break; 499 } 500 501 /* Calculate duplex settings for 1000BasetT/1000BaseX. */ 502 if ((media & IFM_GMASK) == IFM_FDX) { 503 bmcr |= BRGPHY_BMCR_FDX; 504 gig = BRGPHY_1000CTL_AFD; 505 } else { 506 gig = BRGPHY_1000CTL_AHD; 507 } 508 509 /* Force loopback to disconnect PHY for Ethernet medium. */ 510 brgphy_enable_loopback(sc); 511 512 /* Disable 1000BaseT advertisements. */ 513 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 514 /* Disable 10/100 advertisements. */ 515 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 516 /* Write forced link speed. */ 517 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 518 519 /* If 10/100 only then configuration is complete. */ 520 if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX)) 521 goto brgphy_setmedia_exit; 522 523 /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */ 524 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 525 /* Restart auto-negotiation for 1000BaseT/1000BaseX. */ 526 PHY_WRITE(sc, BRGPHY_MII_BMCR, 527 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 528 529 /* If not 5701 PHY then configuration is complete. */ 530 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 531 goto brgphy_setmedia_exit; 532 533 /* 534 * When setting the link manually, one side must be the master and 535 * the other the slave. However ifmedia doesn't give us a good way 536 * to specify this, so we fake it by using one of the LINK flags. 537 * If LINK0 is set, we program the PHY to be a master, otherwise 538 * it's a slave. 539 */ 540 if (master) { 541 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 542 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 543 } else { 544 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 545 gig | BRGPHY_1000CTL_MSE); 546 } 547 548brgphy_setmedia_exit: 549 return; 550} 551 552/****************************************************************************/ 553/* Set the media status based on the PHY settings. */ 554/* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled) */ 555/* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled) */ 556/* */ 557/* Returns: */ 558/* None */ 559/****************************************************************************/ 560static void 561brgphy_status(struct mii_softc *sc) 562{ 563 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 564 struct mii_data *mii = sc->mii_pdata; 565 int aux, bmcr, bmsr, anar, anlpar, xstat, val; 566 567 568 mii->mii_media_status = IFM_AVALID; 569 mii->mii_media_active = IFM_ETHER; 570 571 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 572 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 573 anar = PHY_READ(sc, BRGPHY_MII_ANAR); 574 anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR); 575 576 /* Loopback is enabled. */ 577 if (bmcr & BRGPHY_BMCR_LOOP) { 578 579 mii->mii_media_active |= IFM_LOOP; 580 } 581 582 /* Autoneg is still in progress. */ 583 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 584 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 585 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 586 /* Erg, still trying, I guess... */ 587 mii->mii_media_active |= IFM_NONE; 588 goto brgphy_status_exit; 589 } 590 591 /* Autoneg is enabled and complete, link should be up. */ 592 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 593 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 594 595 /* If copper link is up, get the negotiated speed/duplex. */ 596 if (aux & BRGPHY_AUXSTS_LINK) { 597 mii->mii_media_status |= IFM_ACTIVE; 598 switch (aux & BRGPHY_AUXSTS_AN_RES) { 599 case BRGPHY_RES_1000FD: 600 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 601 case BRGPHY_RES_1000HD: 602 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 603 case BRGPHY_RES_100FD: 604 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 605 case BRGPHY_RES_100T4: 606 mii->mii_media_active |= IFM_100_T4; break; 607 case BRGPHY_RES_100HD: 608 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 609 case BRGPHY_RES_10FD: 610 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 611 case BRGPHY_RES_10HD: 612 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 613 default: 614 mii->mii_media_active |= IFM_NONE; break; 615 } 616 } 617 } else { 618 /* If serdes link is up, get the negotiated speed/duplex. */ 619 if (bmsr & BRGPHY_BMSR_LINK) { 620 mii->mii_media_status |= IFM_ACTIVE; 621 } 622 623 /* Check the link speed/duplex based on the PHY type. */ 624 if (bsc->serdes_flags & BRGPHY_5706S) { 625 mii->mii_media_active |= IFM_1000_SX; 626 627 /* If autoneg enabled, read negotiated duplex settings */ 628 if (bmcr & BRGPHY_BMCR_AUTOEN) { 629 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 630 if (val & BRGPHY_SERDES_ANAR_FDX) 631 mii->mii_media_active |= IFM_FDX; 632 else 633 mii->mii_media_active |= IFM_HDX; 634 } 635 636 } else if (bsc->serdes_flags & BRGPHY_5708S) { 637 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 638 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 639 640 /* Check for MRBE auto-negotiated speed results. */ 641 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 642 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 643 mii->mii_media_active |= IFM_10_FL; break; 644 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 645 mii->mii_media_active |= IFM_100_FX; break; 646 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 647 mii->mii_media_active |= IFM_1000_SX; break; 648 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 649 mii->mii_media_active |= IFM_2500_SX; break; 650 } 651 652 /* Check for MRBE auto-negotiated duplex results. */ 653 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 654 mii->mii_media_active |= IFM_FDX; 655 else 656 mii->mii_media_active |= IFM_HDX; 657 658 } else if (bsc->serdes_flags & BRGPHY_5709S) { 659 660 /* Select GP Status Block of the AN MMD, get autoneg results. */ 661 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 662 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 663 664 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 665 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 666 667 /* Check for MRBE auto-negotiated speed results. */ 668 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 669 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 670 mii->mii_media_active |= IFM_10_FL; break; 671 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 672 mii->mii_media_active |= IFM_100_FX; break; 673 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 674 mii->mii_media_active |= IFM_1000_SX; break; 675 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 676 mii->mii_media_active |= IFM_2500_SX; break; 677 } 678 679 /* Check for MRBE auto-negotiated duplex results. */ 680 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 681 mii->mii_media_active |= IFM_FDX; 682 else 683 mii->mii_media_active |= IFM_HDX; 684 } 685 686 } 687 688 /* Todo: Change bge to use these settings. */ 689 690 /* Fetch flow control settings from the copper PHY. */ 691 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 692 /* Set FLAG0 if RX is enabled and FLAG1 if TX is enabled */ 693 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) { 694 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 695 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) && 696 (anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 697 mii->mii_media_active |= IFM_FLAG1; 698 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) && 699 !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 700 mii->mii_media_active |= IFM_FLAG0; 701 } 702 } 703 704 /* Todo: Add support for fiber settings too. */ 705 706 707brgphy_status_exit: 708 return; 709} 710 711static void 712brgphy_mii_phy_auto(struct mii_softc *sc) 713{ 714 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 715 int ktcr = 0; 716 717 brgphy_reset(sc); 718 719 /* Enable flow control in the advertisement register. */ 720 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 721 /* Pause capability advertisement (pause capable & asymmetric) */ 722 PHY_WRITE(sc, BRGPHY_MII_ANAR, 723 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA | 724 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC); 725 } else { 726 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX | 727 BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE); 728 } 729 730 /* Enable speed in the 1000baseT control register */ 731 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 732 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 733 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 734 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 735 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 736 737 /* Start autonegotiation */ 738 PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 739 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 740 741} 742 743 744/* Enable loopback to force the link down. */ 745static void 746brgphy_enable_loopback(struct mii_softc *sc) 747{ 748 int i; 749 750 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 751 for (i = 0; i < 15000; i++) { 752 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 753 break; 754 DELAY(10); 755 } 756} 757 758/* Turn off tap power management on 5401. */ 759static void 760bcm5401_load_dspcode(struct mii_softc *sc) 761{ 762 static const struct { 763 int reg; 764 uint16_t val; 765 } dspcode[] = { 766 { BRGPHY_MII_AUXCTL, 0x0c20 }, 767 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 768 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 769 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 770 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 771 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 772 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 773 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 774 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 775 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 776 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 777 { 0, 0 }, 778 }; 779 int i; 780 781 for (i = 0; dspcode[i].reg != 0; i++) 782 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 783 DELAY(40); 784} 785 786static void 787bcm5411_load_dspcode(struct mii_softc *sc) 788{ 789 static const struct { 790 int reg; 791 uint16_t val; 792 } dspcode[] = { 793 { 0x1c, 0x8c23 }, 794 { 0x1c, 0x8ca3 }, 795 { 0x1c, 0x8c23 }, 796 { 0, 0 }, 797 }; 798 int i; 799 800 for (i = 0; dspcode[i].reg != 0; i++) 801 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 802} 803 804void 805bcm54k2_load_dspcode(struct mii_softc *sc) 806{ 807 static const struct { 808 int reg; 809 uint16_t val; 810 } dspcode[] = { 811 { 4, 0x01e1 }, 812 { 9, 0x0300 }, 813 { 0, 0 }, 814 }; 815 int i; 816 817 for (i = 0; dspcode[i].reg != 0; i++) 818 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 819 820} 821 822static void 823brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 824{ 825 static const struct { 826 int reg; 827 uint16_t val; 828 } dspcode[] = { 829 { 0x1c, 0x8d68 }, 830 { 0x1c, 0x8d68 }, 831 { 0, 0 }, 832 }; 833 int i; 834 835 for (i = 0; dspcode[i].reg != 0; i++) 836 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 837} 838 839static void 840brgphy_fixup_adc_bug(struct mii_softc *sc) 841{ 842 static const struct { 843 int reg; 844 uint16_t val; 845 } dspcode[] = { 846 { BRGPHY_MII_AUXCTL, 0x0c00 }, 847 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 848 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 849 { 0, 0 }, 850 }; 851 int i; 852 853 for (i = 0; dspcode[i].reg != 0; i++) 854 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 855} 856 857static void 858brgphy_fixup_adjust_trim(struct mii_softc *sc) 859{ 860 static const struct { 861 int reg; 862 uint16_t val; 863 } dspcode[] = { 864 { BRGPHY_MII_AUXCTL, 0x0c00 }, 865 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 866 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 867 { BRGPHY_MII_TEST1, 0x0014 }, 868 { BRGPHY_MII_AUXCTL, 0x0400 }, 869 { 0, 0 }, 870 }; 871 int i; 872 873 for (i = 0; dspcode[i].reg != 0; i++) 874 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 875} 876 877static void 878brgphy_fixup_ber_bug(struct mii_softc *sc) 879{ 880 static const struct { 881 int reg; 882 uint16_t val; 883 } dspcode[] = { 884 { BRGPHY_MII_AUXCTL, 0x0c00 }, 885 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 886 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 887 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 888 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 889 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 890 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 891 { BRGPHY_MII_AUXCTL, 0x0400 }, 892 { 0, 0 }, 893 }; 894 int i; 895 896 for (i = 0; dspcode[i].reg != 0; i++) 897 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 898} 899 900static void 901brgphy_fixup_crc_bug(struct mii_softc *sc) 902{ 903 static const struct { 904 int reg; 905 uint16_t val; 906 } dspcode[] = { 907 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 908 { 0x1c, 0x8c68 }, 909 { 0x1c, 0x8d68 }, 910 { 0x1c, 0x8c68 }, 911 { 0, 0 }, 912 }; 913 int i; 914 915 for (i = 0; dspcode[i].reg != 0; i++) 916 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 917} 918 919static void 920brgphy_fixup_jitter_bug(struct mii_softc *sc) 921{ 922 static const struct { 923 int reg; 924 uint16_t val; 925 } dspcode[] = { 926 { BRGPHY_MII_AUXCTL, 0x0c00 }, 927 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 928 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 929 { BRGPHY_MII_AUXCTL, 0x0400 }, 930 { 0, 0 }, 931 }; 932 int i; 933 934 for (i = 0; dspcode[i].reg != 0; i++) 935 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 936} 937 938 939static void 940brgphy_fixup_disable_early_dac(struct mii_softc *sc) 941{ 942 uint32_t val; 943 944 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 945 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 946 val &= ~(1 << 8); 947 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 948 949} 950 951 952static void 953brgphy_ethernet_wirespeed(struct mii_softc *sc) 954{ 955 uint32_t val; 956 957 /* Enable Ethernet@WireSpeed. */ 958 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 959 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 960 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 961} 962 963 964static void 965brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 966{ 967 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 968 uint32_t val; 969 970 /* Set or clear jumbo frame settings in the PHY. */ 971 if (mtu > ETHER_MAX_LEN) { 972 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 973 /* BCM5401 PHY cannot read-modify-write. */ 974 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 975 } else { 976 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 977 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 978 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 979 val | BRGPHY_AUXCTL_LONG_PKT); 980 } 981 982 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 983 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 984 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 985 } else { 986 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 987 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 988 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 989 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 990 991 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 992 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 993 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 994 } 995} 996 997static void 998brgphy_reset(struct mii_softc *sc) 999{ 1000 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 1001 struct bge_softc *bge_sc = NULL; 1002 struct bce_softc *bce_sc = NULL; 1003 struct ifnet *ifp; 1004 int val; 1005 1006 /* Perform a standard PHY reset. */ 1007 mii_phy_reset(sc); 1008 1009 /* Handle any PHY specific procedures following the reset. */ 1010 switch (bsc->mii_oui) { 1011 case MII_OUI_BROADCOM: 1012 break; 1013 case MII_OUI_xxBROADCOM: 1014 switch (bsc->mii_model) { 1015 case MII_MODEL_xxBROADCOM_BCM5400: 1016 bcm5401_load_dspcode(sc); 1017 break; 1018 case MII_MODEL_xxBROADCOM_BCM5401: 1019 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 1020 bcm5401_load_dspcode(sc); 1021 break; 1022 case MII_MODEL_xxBROADCOM_BCM5411: 1023 bcm5411_load_dspcode(sc); 1024 break; 1025 case MII_MODEL_xxBROADCOM_BCM54K2: 1026 bcm54k2_load_dspcode(sc); 1027 break; 1028 } 1029 break; 1030 case MII_OUI_xxBROADCOM_ALT1: 1031 break; 1032 } 1033 1034 ifp = sc->mii_pdata->mii_ifp; 1035 1036 /* Find the driver associated with this PHY. */ 1037 if (strcmp(ifp->if_dname, "bge") == 0) { 1038 bge_sc = ifp->if_softc; 1039 } else if (strcmp(ifp->if_dname, "bce") == 0) { 1040 bce_sc = ifp->if_softc; 1041 } 1042 1043 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 1044 if (bge_sc) { 1045 /* Fix up various bugs */ 1046 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 1047 brgphy_fixup_5704_a0_bug(sc); 1048 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 1049 brgphy_fixup_adc_bug(sc); 1050 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) 1051 brgphy_fixup_adjust_trim(sc); 1052 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) 1053 brgphy_fixup_ber_bug(sc); 1054 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 1055 brgphy_fixup_crc_bug(sc); 1056 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) 1057 brgphy_fixup_jitter_bug(sc); 1058 1059 brgphy_jumbo_settings(sc, ifp->if_mtu); 1060 1061 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED) 1062 brgphy_ethernet_wirespeed(sc); 1063 1064 /* Enable Link LED on Dell boxes */ 1065 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 1066 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1067 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 1068 ~BRGPHY_PHY_EXTCTL_3_LED); 1069 } 1070 1071 /* Adjust output voltage (From Linux driver) */ 1072 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 1073 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 1074 1075 /* Handle any bce (NetXtreme II) workarounds. */ 1076 } else if (bce_sc) { 1077 1078 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1079 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1080 1081 /* Store autoneg capabilities/results in digital block (Page 0) */ 1082 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1083 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1084 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1085 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1086 1087 /* Enable fiber mode and autodetection */ 1088 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1089 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1090 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1091 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1092 1093 /* Enable parallel detection */ 1094 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1095 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1096 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1097 1098 /* Advertise 2.5G support through next page during autoneg */ 1099 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1100 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1101 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1102 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1103 1104 /* Increase TX signal amplitude */ 1105 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1106 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1107 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1108 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1109 BRGPHY_5708S_TX_MISC_PG5); 1110 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1111 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1112 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1113 BRGPHY_5708S_DIG_PG0); 1114 } 1115 1116 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1117 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1118 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1119 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1120 BRGPHY_5708S_TX_MISC_PG5); 1121 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1122 bce_sc->bce_port_hw_cfg & 1123 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1124 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1125 BRGPHY_5708S_DIG_PG0); 1126 } 1127 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1128 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1129 1130 /* Select the SerDes Digital block of the AN MMD. */ 1131 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1132 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1133 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1134 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1135 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1136 1137 /* Select the Over 1G block of the AN MMD. */ 1138 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1139 1140 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1141 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1142 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1143 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1144 else 1145 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1146 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1147 1148 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1149 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1150 1151 /* Enable MRBE speed autoneg. */ 1152 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1153 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1154 BRGPHY_MRBE_MSG_PG5_NP_T2; 1155 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1156 1157 /* Select the Clause 73 User B0 block of the AN MMD. */ 1158 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1159 1160 /* Enable MRBE speed autoneg. */ 1161 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1162 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1163 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1164 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1165 1166 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1167 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1168 1169 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1170 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1171 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1172 brgphy_fixup_disable_early_dac(sc); 1173 1174 brgphy_jumbo_settings(sc, ifp->if_mtu); 1175 brgphy_ethernet_wirespeed(sc); 1176 } else { 1177 brgphy_fixup_ber_bug(sc); 1178 brgphy_jumbo_settings(sc, ifp->if_mtu); 1179 brgphy_ethernet_wirespeed(sc); 1180 } 1181 1182 } 1183} 1184 1185