brgphy.c revision 165360
1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 165360 2006-12-20 00:08:47Z jkim $"); 35 36/* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/bus.h> 46 47#include <net/if.h> 48#include <net/ethernet.h> 49#include <net/if_media.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include "miidevs.h" 54 55#include <dev/mii/brgphyreg.h> 56#include <net/if_arp.h> 57#include <machine/bus.h> 58#include <dev/bge/if_bgereg.h> 59#include <dev/bce/if_bcereg.h> 60 61#include <dev/pci/pcireg.h> 62#include <dev/pci/pcivar.h> 63 64#include "miibus_if.h" 65 66static int brgphy_probe(device_t); 67static int brgphy_attach(device_t); 68 69static device_method_t brgphy_methods[] = { 70 /* device interface */ 71 DEVMETHOD(device_probe, brgphy_probe), 72 DEVMETHOD(device_attach, brgphy_attach), 73 DEVMETHOD(device_detach, mii_phy_detach), 74 DEVMETHOD(device_shutdown, bus_generic_shutdown), 75 { 0, 0 } 76}; 77 78static devclass_t brgphy_devclass; 79 80static driver_t brgphy_driver = { 81 "brgphy", 82 brgphy_methods, 83 sizeof(struct mii_softc) 84}; 85 86DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 87 88static int brgphy_service(struct mii_softc *, struct mii_data *, int); 89static void brgphy_setmedia(struct mii_softc *, int, int); 90static void brgphy_status(struct mii_softc *); 91static int brgphy_mii_phy_auto(struct mii_softc *); 92static void brgphy_reset(struct mii_softc *); 93static void brgphy_loop(struct mii_softc *); 94static void bcm5401_load_dspcode(struct mii_softc *); 95static void bcm5411_load_dspcode(struct mii_softc *); 96static void bcm5703_load_dspcode(struct mii_softc *); 97static void bcm5750_load_dspcode(struct mii_softc *); 98static int brgphy_mii_model; 99 100static const struct mii_phydesc brgphys[] = { 101 MII_PHY_DESC(xxBROADCOM, BCM5400), 102 MII_PHY_DESC(xxBROADCOM, BCM5401), 103 MII_PHY_DESC(xxBROADCOM, BCM5411), 104 MII_PHY_DESC(xxBROADCOM, BCM5701), 105 MII_PHY_DESC(xxBROADCOM, BCM5703), 106 MII_PHY_DESC(xxBROADCOM, BCM5704), 107 MII_PHY_DESC(xxBROADCOM, BCM5705), 108 MII_PHY_DESC(xxBROADCOM, BCM5706C), 109 MII_PHY_DESC(xxBROADCOM, BCM5708C), 110 MII_PHY_DESC(xxBROADCOM, BCM5714), 111 MII_PHY_DESC(xxBROADCOM, BCM5750), 112 MII_PHY_DESC(xxBROADCOM, BCM5752), 113 MII_PHY_DESC(xxBROADCOM, BCM5754), 114 MII_PHY_DESC(xxBROADCOM, BCM5780), 115 MII_PHY_END 116}; 117 118static int 119brgphy_probe(device_t dev) 120{ 121 122 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 123} 124 125static int 126brgphy_attach(device_t dev) 127{ 128 struct mii_softc *sc; 129 struct mii_attach_args *ma; 130 struct mii_data *mii; 131 const char *sep = ""; 132 struct bge_softc *bge_sc = NULL; 133 struct bce_softc *bce_sc = NULL; 134 int fast_ether_only = FALSE; 135 136 sc = device_get_softc(dev); 137 ma = device_get_ivars(dev); 138 sc->mii_dev = device_get_parent(dev); 139 mii = device_get_softc(sc->mii_dev); 140 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 141 142 sc->mii_inst = mii->mii_instance; 143 sc->mii_phy = ma->mii_phyno; 144 sc->mii_service = brgphy_service; 145 sc->mii_pdata = mii; 146 147 sc->mii_flags |= MIIF_NOISOLATE; 148 mii->mii_instance++; 149 150#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 151#define PRINT(s) printf("%s%s", sep, s); sep = ", " 152 153 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 154 BMCR_ISO); 155#if 0 156 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 157 BMCR_LOOP|BMCR_S100); 158#endif 159 160 brgphy_mii_model = MII_MODEL(ma->mii_id2); 161 brgphy_reset(sc); 162 163 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 164 sc->mii_capabilities &= ~BMSR_ANEG; 165 device_printf(dev, " "); 166 mii_add_media(sc); 167 168 /* Find the driver associated with this PHY. */ 169 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 170 bge_sc = mii->mii_ifp->if_softc; 171 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 172 bce_sc = mii->mii_ifp->if_softc; 173 } 174 175 /* The 590x chips are 10/100 only. */ 176 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 177 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 178 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 179 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 180 fast_ether_only = TRUE; 181 182 if (fast_ether_only == FALSE) { 183 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 184 sc->mii_inst), BRGPHY_BMCR_FDX); 185 PRINT(", 1000baseTX"); 186 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 187 IFM_FDX, sc->mii_inst), 0); 188 PRINT("1000baseTX-FDX"); 189 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 190 } else 191 sc->mii_anegticks = MII_ANEGTICKS; 192 193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 194 PRINT("auto"); 195 196 printf("\n"); 197#undef ADD 198#undef PRINT 199 200 MIIBUS_MEDIAINIT(sc->mii_dev); 201 return (0); 202} 203 204static int 205brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 206{ 207 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 208 int reg; 209 210 switch (cmd) { 211 case MII_POLLSTAT: 212 /* If we're not polling our PHY instance, just return. */ 213 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 214 return (0); 215 break; 216 case MII_MEDIACHG: 217 /* 218 * If the media indicates a different PHY instance, 219 * isolate ourselves. 220 */ 221 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 222 reg = PHY_READ(sc, MII_BMCR); 223 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 224 return (0); 225 } 226 227 /* If the interface is not up, don't do anything. */ 228 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 229 break; 230 231 brgphy_reset(sc); /* XXX hardware bug work-around */ 232 233 switch (IFM_SUBTYPE(ife->ifm_media)) { 234 case IFM_AUTO: 235#ifdef foo 236 /* If we're already in auto mode, just return. */ 237 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 238 return (0); 239#endif 240 (void)brgphy_mii_phy_auto(sc); 241 break; 242 case IFM_1000_T: 243 case IFM_100_TX: 244 case IFM_10_T: 245 brgphy_setmedia(sc, ife->ifm_media, 246 mii->mii_ifp->if_flags & IFF_LINK0); 247 break; 248#ifdef foo 249 case IFM_NONE: 250 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 251 break; 252#endif 253 case IFM_100_T4: 254 default: 255 return (EINVAL); 256 } 257 break; 258 case MII_TICK: 259 /* If we're not currently selected, just return. */ 260 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 261 return (0); 262 263 /* Is the interface even up? */ 264 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 265 return (0); 266 267 /* Only used for autonegotiation. */ 268 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 269 sc->mii_ticks = 0; /* Reset autoneg timer. */ 270 break; 271 } 272 273 /* 274 * Check to see if we have link. If we do, we don't 275 * need to restart the autonegotiation process. 276 */ 277 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) { 278 sc->mii_ticks = 0; /* Reset autoneg timer. */ 279 break; 280 } 281 282 /* Announce link loss right after it happens. */ 283 if (sc->mii_ticks++ == 0) 284 break; 285 286 /* Only retry autonegotiation every mii_anegticks seconds. */ 287 if (sc->mii_ticks <= sc->mii_anegticks) 288 return (0); 289 290 sc->mii_ticks = 0; 291 (void)brgphy_mii_phy_auto(sc); 292 break; 293 } 294 295 /* Update the media status. */ 296 brgphy_status(sc); 297 298 /* 299 * Callback if something changed. Note that we need to poke 300 * the DSP on the Broadcom PHYs if the media changes. 301 */ 302 if (sc->mii_media_active != mii->mii_media_active || 303 sc->mii_media_status != mii->mii_media_status || 304 cmd == MII_MEDIACHG) { 305 switch (brgphy_mii_model) { 306 case MII_MODEL_xxBROADCOM_BCM5400: 307 case MII_MODEL_xxBROADCOM_BCM5401: 308 bcm5401_load_dspcode(sc); 309 break; 310 case MII_MODEL_xxBROADCOM_BCM5411: 311 bcm5411_load_dspcode(sc); 312 break; 313 } 314 } 315 mii_phy_update(sc, cmd); 316 return (0); 317} 318 319static void 320brgphy_setmedia(struct mii_softc *sc, int media, int master) 321{ 322 int bmcr, gig; 323 324 switch (IFM_SUBTYPE(media)) { 325 case IFM_1000_T: 326 bmcr = BRGPHY_S1000; 327 break; 328 case IFM_100_TX: 329 bmcr = BRGPHY_S100; 330 break; 331 case IFM_10_T: 332 default: 333 bmcr = BRGPHY_S10; 334 break; 335 } 336 if ((media & IFM_GMASK) == IFM_FDX) { 337 bmcr |= BRGPHY_BMCR_FDX; 338 gig = BRGPHY_1000CTL_AFD; 339 } else { 340 gig = BRGPHY_1000CTL_AHD; 341 } 342 343 brgphy_loop(sc); 344 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 345 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 346 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 347 348 if (IFM_SUBTYPE(media) != IFM_1000_T) 349 return; 350 351 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 352 PHY_WRITE(sc, BRGPHY_MII_BMCR, 353 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 354 355 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 356 return; 357 358 /* 359 * When setting the link manually, one side must be the master and 360 * the other the slave. However ifmedia doesn't give us a good way 361 * to specify this, so we fake it by using one of the LINK flags. 362 * If LINK0 is set, we program the PHY to be a master, otherwise 363 * it's a slave. 364 */ 365 if (master) { 366 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 367 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 368 } else { 369 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 370 gig | BRGPHY_1000CTL_MSE); 371 } 372} 373 374static void 375brgphy_status(struct mii_softc *sc) 376{ 377 struct mii_data *mii = sc->mii_pdata; 378 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 379 int bmcr, bmsr; 380 381 mii->mii_media_status = IFM_AVALID; 382 mii->mii_media_active = IFM_ETHER; 383 384 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 385 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 386 387 if (bmsr & BRGPHY_BMSR_LINK) 388 mii->mii_media_status |= IFM_ACTIVE; 389 390 if (bmcr & BRGPHY_BMCR_LOOP) 391 mii->mii_media_active |= IFM_LOOP; 392 393 if (bmcr & BRGPHY_BMCR_AUTOEN) { 394 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 395 /* Erg, still trying, I guess... */ 396 mii->mii_media_active |= IFM_NONE; 397 return; 398 } 399 } 400 401 if (bmsr & BRGPHY_BMSR_LINK) { 402 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 403 BRGPHY_AUXSTS_AN_RES) { 404 case BRGPHY_RES_1000FD: 405 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 406 break; 407 case BRGPHY_RES_1000HD: 408 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 409 break; 410 case BRGPHY_RES_100FD: 411 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 412 break; 413 case BRGPHY_RES_100T4: 414 mii->mii_media_active |= IFM_100_T4; 415 break; 416 case BRGPHY_RES_100HD: 417 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 418 break; 419 case BRGPHY_RES_10FD: 420 mii->mii_media_active |= IFM_10_T | IFM_FDX; 421 break; 422 case BRGPHY_RES_10HD: 423 mii->mii_media_active |= IFM_10_T | IFM_HDX; 424 break; 425 default: 426 mii->mii_media_active |= IFM_NONE; 427 break; 428 } 429 } else 430 mii->mii_media_active = ife->ifm_media; 431} 432 433static int 434brgphy_mii_phy_auto(struct mii_softc *sc) 435{ 436 int ktcr = 0; 437 438 brgphy_loop(sc); 439 brgphy_reset(sc); 440 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 441 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 442 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 443 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 444 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 445 DELAY(1000); 446 PHY_WRITE(sc, BRGPHY_MII_ANAR, 447 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 448 DELAY(1000); 449 PHY_WRITE(sc, BRGPHY_MII_BMCR, 450 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 451 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 452 return (EJUSTRETURN); 453} 454 455static void 456brgphy_loop(struct mii_softc *sc) 457{ 458 int i; 459 460 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 461 for (i = 0; i < 15000; i++) { 462 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) { 463#if 0 464 device_printf(sc->mii_dev, "looped %d\n", i); 465#endif 466 break; 467 } 468 DELAY(10); 469 } 470} 471 472/* Turn off tap power management on 5401. */ 473static void 474bcm5401_load_dspcode(struct mii_softc *sc) 475{ 476 static const struct { 477 int reg; 478 uint16_t val; 479 } dspcode[] = { 480 { BRGPHY_MII_AUXCTL, 0x0c20 }, 481 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 482 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 483 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 484 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 485 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 486 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 487 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 488 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 489 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 490 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 491 { 0, 0 }, 492 }; 493 int i; 494 495 for (i = 0; dspcode[i].reg != 0; i++) 496 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 497 DELAY(40); 498} 499 500static void 501bcm5411_load_dspcode(struct mii_softc *sc) 502{ 503 static const struct { 504 int reg; 505 uint16_t val; 506 } dspcode[] = { 507 { 0x1c, 0x8c23 }, 508 { 0x1c, 0x8ca3 }, 509 { 0x1c, 0x8c23 }, 510 { 0, 0 }, 511 }; 512 int i; 513 514 for (i = 0; dspcode[i].reg != 0; i++) 515 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 516} 517 518static void 519bcm5703_load_dspcode(struct mii_softc *sc) 520{ 521 static const struct { 522 int reg; 523 uint16_t val; 524 } dspcode[] = { 525 { BRGPHY_MII_AUXCTL, 0x0c00 }, 526 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 527 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 528 { 0, 0 }, 529 }; 530 int i; 531 532 for (i = 0; dspcode[i].reg != 0; i++) 533 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 534} 535 536static void 537bcm5704_load_dspcode(struct mii_softc *sc) 538{ 539 static const struct { 540 int reg; 541 u_int16_t val; 542 } dspcode[] = { 543 { 0x1c, 0x8d68 }, 544 { 0x1c, 0x8d68 }, 545 { 0, 0 }, 546 }; 547 int i; 548 549 for (i = 0; dspcode[i].reg != 0; i++) 550 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 551} 552 553static void 554bcm5750_load_dspcode(struct mii_softc *sc) 555{ 556 static const struct { 557 int reg; 558 u_int16_t val; 559 } dspcode[] = { 560 { 0x18, 0x0c00 }, 561 { 0x17, 0x000a }, 562 { 0x15, 0x310b }, 563 { 0x17, 0x201f }, 564 { 0x15, 0x9506 }, 565 { 0x17, 0x401f }, 566 { 0x15, 0x14e2 }, 567 { 0x18, 0x0400 }, 568 { 0, 0 }, 569 }; 570 int i; 571 572 for (i = 0; dspcode[i].reg != 0; i++) 573 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 574} 575 576static void 577brgphy_reset(struct mii_softc *sc) 578{ 579 u_int32_t val; 580 struct ifnet *ifp; 581 struct bge_softc *bge_sc = NULL; 582 struct bce_softc *bce_sc = NULL; 583 584 mii_phy_reset(sc); 585 586 switch (brgphy_mii_model) { 587 case MII_MODEL_xxBROADCOM_BCM5400: 588 case MII_MODEL_xxBROADCOM_BCM5401: 589 bcm5401_load_dspcode(sc); 590 break; 591 case MII_MODEL_xxBROADCOM_BCM5411: 592 bcm5411_load_dspcode(sc); 593 break; 594 case MII_MODEL_xxBROADCOM_BCM5703: 595 bcm5703_load_dspcode(sc); 596 break; 597 case MII_MODEL_xxBROADCOM_BCM5704: 598 bcm5704_load_dspcode(sc); 599 break; 600 case MII_MODEL_xxBROADCOM_BCM5750: 601 case MII_MODEL_xxBROADCOM_BCM5752: 602 case MII_MODEL_xxBROADCOM_BCM5714: 603 case MII_MODEL_xxBROADCOM_BCM5780: 604 case MII_MODEL_xxBROADCOM_BCM5706C: 605 case MII_MODEL_xxBROADCOM_BCM5708C: 606 bcm5750_load_dspcode(sc); 607 break; 608 } 609 610 ifp = sc->mii_pdata->mii_ifp; 611 612 /* Find the driver associated with this PHY. */ 613 if (strcmp(ifp->if_dname, "bge") == 0) { 614 bge_sc = ifp->if_softc; 615 } else if (strcmp(ifp->if_dname, "bce") == 0) { 616 bce_sc = ifp->if_softc; 617 } 618 619 /* Handle any NetXtreme/bge workarounds. */ 620 if (bge_sc) { 621 /* 622 * Don't enable Ethernet@WireSpeed for the 5700 or the 623 * 5705 A1 and A2 chips. Make sure we only do this test 624 * on "bge" NICs, since other drivers may use this same 625 * PHY subdriver. 626 */ 627 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 628 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 629 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2) 630 return; 631 632 /* Enable Ethernet@WireSpeed. */ 633 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 634 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 635 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 636 637 /* Enable Link LED on Dell boxes */ 638 if (bge_sc->bge_flags & BGE_FLAG_NO3LED) { 639 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 640 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 641 ~BRGPHY_PHY_EXTCTL_3_LED); 642 } 643 } else if (bce_sc) { 644 /* Set or clear jumbo frame settings in the PHY. */ 645 if (ifp->if_mtu > ETHER_MAX_LEN) { 646 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 647 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 648 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 649 val | BRGPHY_AUXCTL_LONG_PKT); 650 651 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 652 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 653 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 654 } else { 655 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 656 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 657 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 658 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 659 660 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 661 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 662 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 663 } 664 665 /* Enable Ethernet@Wirespeed */ 666 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 667 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 668 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 669 } 670} 671