bmtphyreg.h revision 99440
1 2/*- 3 * Copyright (c) 2001 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jason R. Thorpe. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * from NetBSD: bmtphyreg.h,v 1.1 2001/06/02 21:42:10 thorpej Exp 38 * 39 * $FreeBSD: head/sys/dev/mii/bmtphyreg.h 99440 2002-07-05 11:07:24Z benno $ 40 */ 41 42#ifndef _DEV_MII_BMTPHYREG_H_ 43#define _DEV_MII_BMTPHYREG_H_ 44 45/* 46 * BCM5201/BCM5202 registers. 47 */ 48 49#define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */ 50#define AUX_CTL_TXDIS 0x2000 /* transmitter disable */ 51#define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */ 52#define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */ 53#define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */ 54#define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */ 55#define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */ 56#define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */ 57 58 59#define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */ 60#define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */ 61#define AUX_STS_LOCKED 0x0200 /* descrambler locked */ 62#define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */ 63#define AUX_STS_REMFAULT 0x0080 /* remote fault */ 64#define AUX_STS_DISCON_STATE 0x0040 /* disconnect state */ 65#define AUX_STS_FCARDET 0x0020 /* false carrier detected */ 66#define AUX_STS_BAD_ESD 0x0010 /* bad ESD detected */ 67#define AUX_STS_RXERROR 0x0008 /* Rx error detected */ 68#define AUX_STS_TXERROR 0x0004 /* Tx error detected */ 69#define AUX_STS_LOCKERROR 0x0002 /* lock error detected */ 70#define AUX_STS_MLT3ERROR 0x0001 /* MLT3 code error detected */ 71 72 73#define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */ 74#define RXERROR_CTR_MASK 0x00ff 75 76 77#define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */ 78#define FCS_CTR_MASK 0x00ff 79 80 81#define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */ 82#define DIS_CTR_MASK 0x00ff 83 84 85#define MII_BMTPHY_PTEST 0x17 /* PTEST */ 86 87 88#define MII_BMTPHY_AUX_CSR 0x18 /* auxiliary control/status */ 89#define AUX_CSR_JABBER_DIS 0x8000 /* jabber disable */ 90#define AUX_CSR_FLINK 0x4000 /* force 10baseT link pass */ 91#define AUX_CSR_HSQ 0x0080 /* SQ high */ 92#define AUX_CSR_LSQ 0x0040 /* SQ low */ 93#define AUX_CSR_ER1 0x0020 /* edge rate 1 */ 94#define AUX_CSR_ER0 0x0010 /* edge rate 0 */ 95#define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */ 96#define AUX_CSR_F100 0x0004 /* force 100base */ 97#define AUX_CSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */ 98#define AUX_CSR_FDX 0x0001 /* full-duplex */ 99 100 101#define MII_BMTPHY_AUX_SS 0x19 /* auxiliary status summary */ 102#define AUX_SS_ACOMP 0x8000 /* auto-negotiation complete */ 103#define AUX_SS_ACOMP_ACK 0x4000 /* auto-negotiation compl. ack */ 104#define AUX_SS_AACK_DET 0x2000 /* auto-neg. ack detected */ 105#define AUX_SS_ANLPAD 0x1000 /* auto-neg. link part. ability det */ 106#define AUX_SS_ANEG_PAUSE 0x0800 /* pause operation bit */ 107#define AUX_SS_HCD 0x0700 /* highest common denominator */ 108#define AUX_SS_HCD_NONE 0x0000 /* none */ 109#define AUX_SS_HCD_10T 0x0100 /* 10baseT */ 110#define AUX_SS_HCD_10T_FDX 0x0200 /* 10baseT-FDX */ 111#define AUX_SS_HCD_100TX 0x0300 /* 100baseTX-FDX */ 112#define AUX_SS_HCD_100T4 0x0400 /* 100baseT4 */ 113#define AUX_SS_HCD_100TX_FDX 0x0500 /* 100baseTX-FDX */ 114#define AUX_SS_PDF 0x0080 /* parallel detection fault */ 115#define AUX_SS_LPRF 0x0040 /* link partner remote fault */ 116#define AUX_SS_LPPR 0x0020 /* link partner page received */ 117#define AUX_SS_LPANA 0x0010 /* link partner auto-neg able */ 118#define AUX_SS_SPEED 0x0008 /* 1 = 100, 0 = 10 */ 119#define AUX_SS_LINK 0x0004 /* link pass */ 120#define AUX_SS_ANEN 0x0002 /* auto-neg. enabled */ 121#define AUX_SS_JABBER 0x0001 /* jabber detected */ 122 123 124#define MII_BMTPHY_INTR 0x1a /* interrupt register */ 125#define INTR_FDX_LED 0x8000 /* full-duplex led enable */ 126#define INTR_INTR_EN 0x4000 /* interrupt enable */ 127#define INTR_FDX_MASK 0x0800 /* full-dupled intr mask */ 128#define INTR_SPD_MASK 0x0400 /* speed intr mask */ 129#define INTR_LINK_MASK 0x0200 /* link intr mask */ 130#define INTR_INTR_MASK 0x0100 /* master interrupt mask */ 131#define INTR_FDX_CHANGE 0x0008 /* full-duplex change */ 132#define INTR_SPD_CHANGE 0x0004 /* speed change */ 133#define INTR_LINK_CHANGE 0x0002 /* link change */ 134#define INTR_INTR_STATUS 0x0001 /* interrupt status */ 135 136 137#define MII_BMTPHY_AUX2 0x1b /* auliliary mode 2 */ 138#define AUX2_BLOCK_RXDV 0x0200 /* block RXDV mode enabled */ 139#define AUX2_ANPDQ 0x0100 /* auto-neg parallel detection Q mode */ 140#define AUX2_TRAFFIC_LED 0x0040 /* traffic meter led enable */ 141#define AUX2_FXMTRCV_LED 0x0020 /* force Tx and Rx LEDs */ 142#define AUX2_HS_TOKEN 0x0010 /* high-speed token ring mode */ 143#define AUX2_AUTO_LP 0x0008 /* auto low-power mode */ 144#define AUX2_TWOLINK_LED 0x0004 /* two link LEDs */ 145#define AUX2_SQE_DIS 0x0002 /* disable SQE pulse */ 146 147 148#define MII_BMTPHY_AUXERR 0x1c /* auxiliary error */ 149#define AUXERR_MANCHESTER 0x0400 /* Manchester code error */ 150#define AUXERR_EOF 0x0200 /* EOF detection error */ 151#define AUXERR_POLARITY 0x0100 /* polarity inversion */ 152#define AUXERR_ANEG 0x0008 /* autonegotiation enabled */ 153#define AUXERR_F100 0x0004 /* force 100base */ 154#define AUXERR_SPEED 0x0002 /* 1 = 100, 0 = 10 */ 155#define AUXERR_FDX 0x0001 /* full-duplex */ 156 157 158#define MII_BMTPHY_AUXMODE 0x1d /* auxiliary mode */ 159#define AUXMODE_ACT_LED_DIS 0x0010 /* activity LED disable */ 160#define AUXMODE_LINK_LED_DIS 0x0008 /* link LED disable */ 161#define AUXMODE_BLOCK_TXEN 0x0002 /* enable block TXEN */ 162 163 164#define MII_BMTPHY_AUXMPHY 0x1e /* auxiliary multiple phy register */ 165#define AUXMPHY_HCD_TX_FDX 0x8000 /* res. is 100baseTX-FDX */ 166#define AUXMPHY_HCD_T4 0x4000 /* res. is 100baseT4 */ 167#define AUXMPHY_HCD_TX 0x2000 /* res. is 100baseTX */ 168#define AUXMPHY_HCD_10T_FDX 0x1000 /* res. is 10baseT-FDX */ 169#define AUXMPHY_HCD_10T 0x0800 /* res. is 10baseT */ 170#define AUXMPHY_RES_ANEG 0x0100 /* restart auto-negotiation */ 171#define AUXMPHY_ANEG_COMP 0x0080 /* auto-negotiation complete */ 172#define AUXMPHY_ACK_COMP 0x0040 /* acknowledge complete */ 173#define AUXMPHY_ACK_DET 0x0020 /* acknowledge detected */ 174#define AUXMPHY_ABILITY_DET 0x0010 /* waiting for LP ability */ 175#define AUXMPHY_SUPER_ISO 0x0008 /* super-isolate mode */ 176#define AUXMPHY_10T_SERIAL 0x0002 /* 10baseT serial mode */ 177 178 179#define MII_BMTPHY_TEST 0x1d /* Broadcom test register */ 180 181 182#endif /* _DEV_MII_BMTPHYREG_H_ */ 183