1183867Sraj/*- 2183867Sraj * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3183867Sraj * All rights reserved. 4183867Sraj * 5183867Sraj * Developed by Semihalf. 6183867Sraj * 7183867Sraj * Redistribution and use in source and binary forms, with or without 8183867Sraj * modification, are permitted provided that the following conditions 9183867Sraj * are met: 10183867Sraj * 1. Redistributions of source code must retain the above copyright 11183867Sraj * notice, this list of conditions and the following disclaimer. 12183867Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183867Sraj * notice, this list of conditions and the following disclaimer in the 14183867Sraj * documentation and/or other materials provided with the distribution. 15183867Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183867Sraj * may be used to endorse or promote products derived from this software 17183867Sraj * without specific prior written permission. 18183867Sraj * 19183867Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183867Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183867Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183867Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183867Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183867Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183867Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183867Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183867Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183867Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183867Sraj * SUCH DAMAGE. 30183867Sraj * 31183867Sraj * $FreeBSD$ 32183867Sraj */ 33183867Sraj 34183867Sraj#ifndef __IF_MGE_H__ 35183867Sraj#define __IF_MGE_H__ 36183867Sraj 37183867Sraj#define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */ 38183867Sraj#define MGE_TX_DESC_NUM 256 39183867Sraj#define MGE_RX_DESC_NUM 256 40183867Sraj#define MGE_RX_QUEUE_NUM 8 41183867Sraj#define MGE_RX_DEFAULT_QUEUE 0 42183867Sraj 43183867Sraj#define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 44183867Sraj 45183867Sraj/* Interrupt Coalescing types */ 46183867Sraj#define MGE_IC_RX 0 47183867Sraj#define MGE_IC_TX 1 48183867Sraj 49183867Srajstruct mge_desc { 50183867Sraj uint32_t cmd_status; 51183867Sraj uint16_t buff_size; 52183867Sraj uint16_t byte_count; 53183867Sraj bus_addr_t buffer; 54183867Sraj bus_addr_t next_desc; 55183867Sraj}; 56183867Sraj 57183867Srajstruct mge_desc_wrapper { 58183867Sraj bus_dmamap_t desc_dmap; 59183867Sraj struct mge_desc* mge_desc; 60183867Sraj bus_addr_t mge_desc_paddr; 61183867Sraj bus_dmamap_t buffer_dmap; 62183867Sraj struct mbuf* buffer; 63183867Sraj}; 64183867Sraj 65183867Srajstruct mge_softc { 66183867Sraj struct ifnet *ifp; /* per-interface network data */ 67209131Sraj 68209131Sraj phandle_t node; 69209131Sraj 70183867Sraj device_t dev; 71183867Sraj device_t miibus; 72209131Sraj 73183867Sraj struct mii_data *mii; 74183867Sraj struct resource *res[1 + MGE_INTR_COUNT]; /* resources */ 75183867Sraj void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */ 76183867Sraj struct mtx transmit_lock; /* transmitter lock */ 77183867Sraj struct mtx receive_lock; /* receiver lock */ 78183867Sraj 79183867Sraj uint32_t mge_if_flags; 80183867Sraj uint32_t mge_media_status; 81183867Sraj 82183867Sraj struct callout wd_callout; 83183867Sraj int wd_timer; 84183867Sraj 85183867Sraj bus_dma_tag_t mge_desc_dtag; 86183867Sraj bus_dma_tag_t mge_tx_dtag; 87183867Sraj bus_dma_tag_t mge_rx_dtag; 88183867Sraj bus_addr_t tx_desc_start; 89183867Sraj bus_addr_t rx_desc_start; 90183867Sraj uint32_t tx_desc_curr; 91183867Sraj uint32_t rx_desc_curr; 92183867Sraj uint32_t tx_desc_used_idx; 93183867Sraj uint32_t tx_desc_used_count; 94183867Sraj uint32_t rx_ic_time; 95183867Sraj uint32_t tx_ic_time; 96183867Sraj struct mge_desc_wrapper mge_tx_desc[MGE_TX_DESC_NUM]; 97183867Sraj struct mge_desc_wrapper mge_rx_desc[MGE_RX_DESC_NUM]; 98186892Sraj 99186892Sraj uint32_t mge_tfut_ipg_max; /* TX FIFO Urgent Threshold */ 100186892Sraj uint32_t mge_rx_ipg_max; 101186892Sraj uint32_t mge_tx_arb_cfg; 102186892Sraj uint32_t mge_tx_tok_cfg; 103186892Sraj uint32_t mge_tx_tok_cnt; 104186892Sraj uint16_t mge_mtu; 105186892Sraj int mge_ver; 106239276Sgonzo int mge_intr_cnt; 107239276Sgonzo uint8_t mge_hw_csum; 108232518Sraj 109232518Sraj struct mge_softc *phy_sc; 110183867Sraj}; 111183867Sraj 112183867Sraj 113183867Sraj/* bus access macros */ 114183867Sraj#define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg)) 115183867Sraj#define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val)) 116183867Sraj 117183867Sraj/* Locking macros */ 118183867Sraj#define MGE_TRANSMIT_LOCK(sc) do { \ 119183867Sraj mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 120183867Sraj mtx_lock(&(sc)->transmit_lock); \ 121183867Sraj} while (0) 122183867Sraj 123183867Sraj#define MGE_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 124183867Sraj#define MGE_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 125183867Sraj 126183867Sraj#define MGE_RECEIVE_LOCK(sc) do { \ 127183867Sraj mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 128183867Sraj mtx_lock(&(sc)->receive_lock); \ 129183867Sraj} while (0) 130183867Sraj 131183867Sraj#define MGE_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 132183867Sraj#define MGE_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 133183867Sraj 134183867Sraj#define MGE_GLOBAL_LOCK(sc) do { \ 135183867Sraj if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ 136183867Sraj (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ 137183867Sraj panic("mge deadlock possibility detection!"); \ 138183867Sraj } \ 139183867Sraj mtx_lock(&(sc)->transmit_lock); \ 140183867Sraj mtx_lock(&(sc)->receive_lock); \ 141183867Sraj} while (0) 142183867Sraj 143183867Sraj#define MGE_GLOBAL_UNLOCK(sc) do { \ 144183867Sraj MGE_RECEIVE_UNLOCK(sc); \ 145183867Sraj MGE_TRANSMIT_UNLOCK(sc); \ 146183867Sraj} while (0) 147183867Sraj 148183867Sraj#define MGE_GLOBAL_LOCK_ASSERT(sc) do { \ 149183867Sraj MGE_TRANSMIT_LOCK_ASSERT(sc); \ 150183867Sraj MGE_RECEIVE_LOCK_ASSERT(sc); \ 151183867Sraj} while (0) 152183867Sraj 153183867Sraj/* SMI-related macros */ 154183867Sraj#define MGE_REG_PHYDEV 0x000 155183867Sraj#define MGE_REG_SMI 0x004 156183867Sraj#define MGE_SMI_READ (1 << 26) 157183867Sraj#define MGE_SMI_WRITE (0 << 26) 158183867Sraj#define MGE_SMI_READVALID (1 << 27) 159183867Sraj#define MGE_SMI_BUSY (1 << 28) 160183867Sraj 161183867Sraj/* TODO verify the timings and retries count w/specs */ 162183867Sraj#define MGE_SMI_READ_RETRIES 1000 163183867Sraj#define MGE_SMI_READ_DELAY 100 164183867Sraj#define MGE_SMI_WRITE_RETRIES 1000 165183867Sraj#define MGE_SMI_WRITE_DELAY 100 166183867Sraj 167183867Sraj/* MGE registers */ 168183867Sraj#define MGE_INT_CAUSE 0x080 169183867Sraj#define MGE_INT_MASK 0x084 170183867Sraj 171183867Sraj#define MGE_PORT_CONFIG 0x400 172183867Sraj#define PORT_CONFIG_UPM (1 << 0) /* promiscuous */ 173183867Sraj#define PORT_CONFIG_DFLT_RXQ(val) (((val) & 7) << 1) /* default RX queue */ 174183867Sraj#define PORT_CONFIG_ARO_RXQ(val) (((val) & 7) << 4) /* ARP RX queue */ 175183867Sraj#define PORT_CONFIG_REJECT_BCAST (1 << 7) /* reject non-ip and non-arp bcast */ 176183867Sraj#define PORT_CONFIG_REJECT_IP_BCAST (1 << 8) /* reject ip bcast */ 177183867Sraj#define PORT_CONFIG_REJECT_ARP__BCAST (1 << 9) /* reject arp bcast */ 178183867Sraj#define PORT_CONFIG_AMNoTxES (1 << 12) /* Automatic mode not updating Error Summary in Tx descriptor */ 179183867Sraj#define PORT_CONFIG_TCP_CAP (1 << 14) /* capture tcp to a different queue */ 180183867Sraj#define PORT_CONFIG_UDP_CAP (1 << 15) /* capture udp to a different queue */ 181183867Sraj#define PORT_CONFIG_TCPQ (7 << 16) /* queue to capture tcp */ 182183867Sraj#define PORT_CONFIG_UDPQ (7 << 19) /* queue to capture udp */ 183183867Sraj#define PORT_CONFIG_BPDUQ (7 << 22) /* queue to capture bpdu */ 184183867Sraj#define PORT_CONFIG_RXCS (1 << 25) /* calculation Rx TCP checksum include pseudo header */ 185183867Sraj 186183867Sraj#define MGE_PORT_EXT_CONFIG 0x404 187183867Sraj#define MGE_MAC_ADDR_L 0x414 188183867Sraj#define MGE_MAC_ADDR_H 0x418 189183867Sraj 190183867Sraj#define MGE_SDMA_CONFIG 0x41c 191183867Sraj#define MGE_SDMA_INT_ON_FRAME_BOUND (1 << 0) 192183867Sraj#define MGE_SDMA_RX_BURST_SIZE(val) (((val) & 7) << 1) 193183867Sraj#define MGE_SDMA_TX_BURST_SIZE(val) (((val) & 7) << 22) 194183867Sraj#define MGE_SDMA_BURST_1_WORD 0x0 195183867Sraj#define MGE_SDMA_BURST_2_WORD 0x1 196183867Sraj#define MGE_SDMA_BURST_4_WORD 0x2 197183867Sraj#define MGE_SDMA_BURST_8_WORD 0x3 198183867Sraj#define MGE_SDMA_BURST_16_WORD 0x4 199183867Sraj#define MGE_SDMA_RX_BYTE_SWAP (1 << 4) 200183867Sraj#define MGE_SDMA_TX_BYTE_SWAP (1 << 5) 201183867Sraj#define MGE_SDMA_DESC_SWAP_MODE (1 << 6) 202183867Sraj 203183867Sraj#define MGE_PORT_SERIAL_CTRL 0x43c 204183867Sraj#define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */ 205183867Sraj#define PORT_SERIAL_FORCE_LINKUP (1 << 1) /* force link status to up */ 206183867Sraj#define PORT_SERIAL_AUTONEG (1 << 2) /* enable autoneg for duplex mode */ 207183867Sraj#define PORT_SERIAL_AUTONEG_FC (1 << 3) /* enable autoneg for FC */ 208183867Sraj#define PORT_SERIAL_PAUSE_ADV (1 << 4) /* advertise symmetric FC in autoneg */ 209183867Sraj#define PORT_SERIAL_FORCE_FC(val) (((val) & 3) << 5) /* pause enable & disable frames conf */ 210183867Sraj#define PORT_SERIAL_NO_PAUSE_DIS 0x00 211183867Sraj#define PORT_SERIAL_PAUSE_DIS 0x01 212183867Sraj#define PORT_SERIAL_FORCE_BP(val) (((val) & 3) << 7) /* transmitting JAM configuration */ 213183867Sraj#define PORT_SERIAL_NO_JAM 0x00 214183867Sraj#define PORT_SERIAL_JAM 0x01 215183867Sraj#define PORT_SERIAL_RES_BIT9 (1 << 9) 216183867Sraj#define PORT_SERIAL_FORCE_LINK_FAIL (1 << 10) 217183867Sraj#define PORT_SERIAL_SPEED_AUTONEG (1 << 13) 218183867Sraj#define PORT_SERIAL_FORCE_DTE_ADV (1 << 14) 219183867Sraj#define PORT_SERIAL_MRU(val) (((val) & 7) << 17) 220183867Sraj#define PORT_SERIAL_MRU_1518 0x0 221183867Sraj#define PORT_SERIAL_MRU_1522 0x1 222183867Sraj#define PORT_SERIAL_MRU_1552 0x2 223183867Sraj#define PORT_SERIAL_MRU_9022 0x3 224183867Sraj#define PORT_SERIAL_MRU_9192 0x4 225183867Sraj#define PORT_SERIAL_MRU_9700 0x5 226183867Sraj#define PORT_SERIAL_FULL_DUPLEX (1 << 21) 227183867Sraj#define PORT_SERIAL_FULL_DUPLEX_FC (1 << 22) 228183867Sraj#define PORT_SERIAL_GMII_SPEED_1000 (1 << 23) 229183867Sraj#define PORT_SERIAL_MII_SPEED_100 (1 << 24) 230183867Sraj 231183867Sraj#define MGE_PORT_STATUS 0x444 232183867Sraj#define MGE_STATUS_LINKUP (1 << 1) 233183867Sraj#define MGE_STATUS_FULL_DUPLEX (1 << 2) 234183867Sraj#define MGE_STATUS_FLOW_CONTROL (1 << 3) 235183867Sraj#define MGE_STATUS_1000MB (1 << 4) 236183867Sraj#define MGE_STATUS_100MB (1 << 5) 237183867Sraj#define MGE_STATUS_TX_IN_PROG (1 << 7) 238183867Sraj#define MGE_STATUS_TX_FIFO_EMPTY (1 << 10) 239183867Sraj 240183867Sraj#define MGE_TX_QUEUE_CMD 0x448 241183867Sraj#define MGE_ENABLE_TXQ (1 << 0) 242183867Sraj#define MGE_DISABLE_TXQ (1 << 8) 243183867Sraj 244183867Sraj/* 88F6281 only */ 245183867Sraj#define MGE_PORT_SERIAL_CTRL1 0x44c 246183867Sraj#define MGE_PCS_LOOPBACK (1 << 1) 247183867Sraj#define MGE_RGMII_EN (1 << 3) 248183867Sraj#define MGE_PORT_RESET (1 << 4) 249183867Sraj#define MGE_CLK125_BYPASS (1 << 5) 250183867Sraj#define MGE_INBAND_AUTONEG (1 << 6) 251183867Sraj#define MGE_INBAND_AUTONEG_BYPASS (1 << 6) 252183867Sraj#define MGE_INBAND_AUTONEG_RESTART (1 << 7) 253183867Sraj#define MGE_1000BASEX (1 << 11) 254183867Sraj#define MGE_BP_COLLISION_COUNT (1 << 15) 255183867Sraj#define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16) 256183867Sraj#define MGE_DROP_ODD_PREAMBLE (1 << 22) 257183867Sraj 258183867Sraj#define MGE_PORT_INT_CAUSE 0x460 259183867Sraj#define MGE_PORT_INT_MASK 0x468 260183867Sraj#define MGE_PORT_INT_RX (1 << 0) 261183867Sraj#define MGE_PORT_INT_EXTEND (1 << 1) 262183867Sraj#define MGE_PORT_INT_RXQ0 (1 << 2) 263183867Sraj#define MGE_PORT_INT_RXERR (1 << 10) 264183867Sraj#define MGE_PORT_INT_RXERRQ0 (1 << 11) 265183867Sraj#define MGE_PORT_INT_SUM (1 << 31) 266183867Sraj 267183867Sraj#define MGE_PORT_INT_CAUSE_EXT 0x464 268183867Sraj#define MGE_PORT_INT_MASK_EXT 0x46C 269183867Sraj#define MGE_PORT_INT_EXT_TXBUF0 (1 << 0) 270183867Sraj#define MGE_PORT_INT_EXT_TXERR0 (1 << 8) 271183867Sraj#define MGE_PORT_INT_EXT_PHYSC (1 << 16) 272183867Sraj#define MGE_PORT_INT_EXT_RXOR (1 << 18) 273183867Sraj#define MGE_PORT_INT_EXT_TXUR (1 << 19) 274183867Sraj#define MGE_PORT_INT_EXT_LC (1 << 20) 275183867Sraj#define MGE_PORT_INT_EXT_IAR (1 << 23) 276183867Sraj#define MGE_PORT_INT_EXT_SUM (1 << 31) 277183867Sraj 278183867Sraj#define MGE_RX_FIFO_URGENT_TRSH 0x470 279183867Sraj#define MGE_TX_FIFO_URGENT_TRSH 0x474 280183867Sraj 281183867Sraj#define MGE_FIXED_PRIO_CONF 0x4dc 282183867Sraj#define MGE_FIXED_PRIO_EN(q) (1 << (q)) 283183867Sraj 284183867Sraj#define MGE_RX_CUR_DESC_PTR(q) (0x60c + ((q)<<4)) 285183867Sraj 286183867Sraj#define MGE_RX_QUEUE_CMD 0x680 287183867Sraj#define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7)) 288183867Sraj#define MGE_ENABLE_RXQ_ALL (0xff) 289183867Sraj#define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8)) 290183867Sraj#define MGE_DISABLE_RXQ_ALL (0xff00) 291183867Sraj 292183867Sraj#define MGE_TX_CUR_DESC_PTR 0x6c0 293183867Sraj 294183867Sraj#define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4)) 295183867Sraj#define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4)) 296183867Sraj#define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4)) 297183867Sraj 298183867Sraj#define MGE_MCAST_REG_NUMBER 64 299183867Sraj#define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2)) 300183867Sraj#define MGE_DA_FILTER_OTH_MCAST(i) (0x1500 + ((i) << 2)) 301183867Sraj 302183867Sraj#define MGE_UCAST_REG_NUMBER 4 303183867Sraj#define MGE_DA_FILTER_UCAST(i) (0x1600 + ((i) << 2)) 304183867Sraj 305183867Sraj 306183867Sraj/* TX descriptor bits */ 307183867Sraj#define MGE_TX_LLC_SNAP (1 << 9) 308183867Sraj#define MGE_TX_NOT_FRAGMENT (1 << 10) 309183867Sraj#define MGE_TX_VLAN_TAGGED (1 << 15) 310183867Sraj#define MGE_TX_UDP (1 << 16) 311183867Sraj#define MGE_TX_GEN_L4_CSUM (1 << 17) 312183867Sraj#define MGE_TX_GEN_IP_CSUM (1 << 18) 313183867Sraj#define MGE_TX_PADDING (1 << 19) 314183867Sraj#define MGE_TX_LAST (1 << 20) 315183867Sraj#define MGE_TX_FIRST (1 << 21) 316183867Sraj#define MGE_TX_ETH_CRC (1 << 22) 317183867Sraj#define MGE_TX_EN_INT (1 << 23) 318183867Sraj 319183867Sraj#define MGE_TX_IP_HDR_SIZE(size) ((size << 11) & 0xFFFF) 320183867Sraj 321183867Sraj/* RX descriptor bits */ 322183867Sraj#define MGE_ERR_SUMMARY (1 << 0) 323183867Sraj#define MGE_ERR_MASK (3 << 1) 324183867Sraj#define MGE_RX_L4_PROTO_MASK (3 << 21) 325183867Sraj#define MGE_RX_L4_PROTO_TCP (0 << 21) 326183867Sraj#define MGE_RX_L4_PROTO_UDP (1 << 21) 327183867Sraj#define MGE_RX_L3_IS_IP (1 << 24) 328183867Sraj#define MGE_RX_IP_OK (1 << 25) 329183867Sraj#define MGE_RX_DESC_LAST (1 << 26) 330183867Sraj#define MGE_RX_DESC_FIRST (1 << 27) 331183867Sraj#define MGE_RX_ENABLE_INT (1 << 29) 332183867Sraj#define MGE_RX_L4_CSUM_OK (1 << 30) 333183867Sraj#define MGE_DMA_OWNED (1 << 31) 334183867Sraj 335183867Sraj#define MGE_RX_IP_FRAGMENT (1 << 2) 336183867Sraj 337183867Sraj#define MGE_RX_L4_IS_TCP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 338183867Sraj == MGE_RX_L4_PROTO_TCP) 339183867Sraj 340183867Sraj#define MGE_RX_L4_IS_UDP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 341183867Sraj == MGE_RX_L4_PROTO_UDP) 342183867Sraj 343183867Sraj/* TX error codes */ 344183867Sraj#define MGE_TX_ERROR_LC (0 << 1) /* Late collision */ 345183867Sraj#define MGE_TX_ERROR_UR (1 << 1) /* Underrun error */ 346183867Sraj#define MGE_TX_ERROR_RL (2 << 1) /* Excessive collision */ 347183867Sraj 348183867Sraj/* RX error codes */ 349183867Sraj#define MGE_RX_ERROR_CE (0 << 1) /* CRC error */ 350183867Sraj#define MGE_RX_ERROR_OR (1 << 1) /* Overrun error */ 351183867Sraj#define MGE_RX_ERROR_MF (2 << 1) /* Max frame lenght error */ 352183867Sraj#define MGE_RX_ERROR_RE (3 << 1) /* Resource error */ 353183867Sraj 354183867Sraj#endif /* __IF_MGE_H__ */ 355