1157114Sscottl/*- 2157114Sscottl * Copyright (c) 2006 IronPort Systems 3157114Sscottl * All rights reserved. 4157114Sscottl * 5157114Sscottl * Redistribution and use in source and binary forms, with or without 6157114Sscottl * modification, are permitted provided that the following conditions 7157114Sscottl * are met: 8157114Sscottl * 1. Redistributions of source code must retain the above copyright 9157114Sscottl * notice, this list of conditions and the following disclaimer. 10157114Sscottl * 2. Redistributions in binary form must reproduce the above copyright 11157114Sscottl * notice, this list of conditions and the following disclaimer in the 12157114Sscottl * documentation and/or other materials provided with the distribution. 13157114Sscottl * 14157114Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15157114Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16157114Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17157114Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18157114Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19157114Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20157114Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21157114Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22157114Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23157114Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24157114Sscottl * SUCH DAMAGE. 25157114Sscottl */ 26171980Sscottl/*- 27171980Sscottl * Copyright (c) 2007 LSI Corp. 28171980Sscottl * Copyright (c) 2007 Rajesh Prabhakaran. 29171980Sscottl * All rights reserved. 30171980Sscottl * 31171980Sscottl * Redistribution and use in source and binary forms, with or without 32171980Sscottl * modification, are permitted provided that the following conditions 33171980Sscottl * are met: 34171980Sscottl * 1. Redistributions of source code must retain the above copyright 35171980Sscottl * notice, this list of conditions and the following disclaimer. 36171980Sscottl * 2. Redistributions in binary form must reproduce the above copyright 37171980Sscottl * notice, this list of conditions and the following disclaimer in the 38171980Sscottl * documentation and/or other materials provided with the distribution. 39171980Sscottl * 40171980Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41171980Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42171980Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43171980Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44171980Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45171980Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46171980Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47171980Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48171980Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49171980Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50171980Sscottl * SUCH DAMAGE. 51171980Sscottl */ 52157114Sscottl 53157114Sscottl#ifndef _MFIREG_H 54157114Sscottl#define _MFIREG_H 55157114Sscottl 56157114Sscottl#include <sys/cdefs.h> 57157114Sscottl__FBSDID("$FreeBSD$"); 58157114Sscottl 59157114Sscottl/* 60157114Sscottl * MegaRAID SAS MFI firmware definitions 61157114Sscottl * 62157114Sscottl * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63157114Sscottl * new firmware interface from the old AMI MegaRAID one, and there is no 64157114Sscottl * reason why this interface should be limited to just SAS. In any case, LSI 65157114Sscottl * seems to also call this interface 'MFI', so that will be used here. 66157114Sscottl */ 67233711Sambrisko#define MEGAMFI_FRAME_SIZE 64 68157114Sscottl/* 69157114Sscottl * Start with the register set. All registers are 32 bits wide. 70157114Sscottl * The usual Intel IOP style setup. 71157114Sscottl */ 72157114Sscottl#define MFI_IMSG0 0x10 /* Inbound message 0 */ 73157114Sscottl#define MFI_IMSG1 0x14 /* Inbound message 1 */ 74157114Sscottl#define MFI_OMSG0 0x18 /* Outbound message 0 */ 75157114Sscottl#define MFI_OMSG1 0x1c /* Outbound message 1 */ 76157114Sscottl#define MFI_IDB 0x20 /* Inbound doorbell */ 77157114Sscottl#define MFI_ISTS 0x24 /* Inbound interrupt status */ 78157114Sscottl#define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79157114Sscottl#define MFI_ODB 0x2c /* Outbound doorbell */ 80157114Sscottl#define MFI_OSTS 0x30 /* Outbound interrupt status */ 81157114Sscottl#define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82157114Sscottl#define MFI_IQP 0x40 /* Inbound queue port */ 83157114Sscottl#define MFI_OQP 0x44 /* Outbound queue port */ 84157114Sscottl 85171980Sscottl/* 86233711Sambrisko* ThunderBolt specific Register 87233711Sambrisko*/ 88233711Sambrisko 89247369Ssmh#define MFI_RFPI 0x48 /* reply_free_post_host_index */ 90233711Sambrisko#define MFI_RPI 0x6c /* reply_post_host_index */ 91233711Sambrisko#define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 92233711Sambrisko#define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 93233711Sambrisko 94233711Sambrisko/* 95171980Sscottl * 1078 specific related register 96171980Sscottl */ 97171980Sscottl#define MFI_ODR0 0x9c /* outbound doorbell register0 */ 98171980Sscottl#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 99171980Sscottl#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 100171980Sscottl#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 101233711Sambrisko#define MFI_RMI 0x2 /* reply message interrupt */ 102171980Sscottl#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 103171980Sscottl#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 104171980Sscottl 105233711Sambrisko/* OCR registers */ 106233711Sambrisko#define MFI_WSR 0x004 /* write sequence register */ 107233711Sambrisko#define MFI_HDR 0x008 /* host diagnostic register */ 108233711Sambrisko#define MFI_RSR 0x3c3 /* Reset Status Register */ 109233711Sambrisko 110184897Sambrisko/* 111184897Sambrisko * GEN2 specific changes 112184897Sambrisko */ 113184897Sambrisko#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 114184897Sambrisko#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 115184897Sambrisko 116233711Sambrisko/* 117233711Sambrisko * skinny specific changes 118233711Sambrisko */ 119233711Sambrisko#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 120233711Sambrisko#define MFI_IQPL 0x000000c0 121233711Sambrisko#define MFI_IQPH 0x000000c4 122233711Sambrisko#define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 123233711Sambrisko 124157114Sscottl/* Bits for MFI_OSTS */ 125157114Sscottl#define MFI_OSTS_INTR_VALID 0x00000002 126157114Sscottl 127233711Sambrisko/* OCR specific flags */ 128233711Sambrisko#define MFI_FIRMWARE_STATE_CHANGE 0x00000002 129233711Sambrisko#define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 130233711Sambrisko 131157114Sscottl/* 132157114Sscottl * Firmware state values. Found in OMSG0 during initialization. 133157114Sscottl */ 134157114Sscottl#define MFI_FWSTATE_MASK 0xf0000000 135157114Sscottl#define MFI_FWSTATE_UNDEFINED 0x00000000 136157114Sscottl#define MFI_FWSTATE_BB_INIT 0x10000000 137157114Sscottl#define MFI_FWSTATE_FW_INIT 0x40000000 138157114Sscottl#define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 139157114Sscottl#define MFI_FWSTATE_FW_INIT_2 0x70000000 140157114Sscottl#define MFI_FWSTATE_DEVICE_SCAN 0x80000000 141224041Sjhb#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 142157114Sscottl#define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 143157114Sscottl#define MFI_FWSTATE_READY 0xb0000000 144157114Sscottl#define MFI_FWSTATE_OPERATIONAL 0xc0000000 145157114Sscottl#define MFI_FWSTATE_FAULT 0xf0000000 146157114Sscottl#define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 147157114Sscottl#define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 148233711Sambrisko#define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 149233711Sambrisko#define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 150233711Sambrisko#define MFI_RESET_REQUIRED 0x00000001 151157114Sscottl 152233711Sambrisko/* ThunderBolt Support */ 153233711Sambrisko#define MFI_FWSTATE_TB_MASK 0xf0000000 154233711Sambrisko#define MFI_FWSTATE_TB_RESET 0x00000000 155233711Sambrisko#define MFI_FWSTATE_TB_READY 0x10000000 156233711Sambrisko#define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 157233711Sambrisko#define MFI_FWSTATE_TB_FAULT 0x40000000 158233711Sambrisko 159157114Sscottl/* 160157114Sscottl * Control bits to drive the card to ready state. These go into the IDB 161157114Sscottl * register. 162157114Sscottl */ 163157114Sscottl#define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 164157114Sscottl#define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 165157114Sscottl#define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 166157114Sscottl#define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 167224041Sjhb#define MFI_FWINIT_HOTPLUG 0x00000010 168157114Sscottl 169233711Sambrisko/* ADP reset flags */ 170233711Sambrisko#define MFI_STOP_ADP 0x00000020 171233711Sambrisko#define MFI_ADP_RESET 0x00000040 172233711Sambrisko#define DIAG_WRITE_ENABLE 0x00000080 173233711Sambrisko#define DIAG_RESET_ADAPTER 0x00000004 174233711Sambrisko 175157114Sscottl/* MFI Commands */ 176157114Sscottltypedef enum { 177157114Sscottl MFI_CMD_INIT = 0x00, 178157114Sscottl MFI_CMD_LD_READ, 179157114Sscottl MFI_CMD_LD_WRITE, 180157114Sscottl MFI_CMD_LD_SCSI_IO, 181157114Sscottl MFI_CMD_PD_SCSI_IO, 182157114Sscottl MFI_CMD_DCMD, 183157114Sscottl MFI_CMD_ABORT, 184157114Sscottl MFI_CMD_SMP, 185157114Sscottl MFI_CMD_STP 186157114Sscottl} mfi_cmd_t; 187157114Sscottl 188157114Sscottl/* Direct commands */ 189157114Sscottltypedef enum { 190157114Sscottl MFI_DCMD_CTRL_GETINFO = 0x01010000, 191233711Sambrisko MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 192163398Sscottl MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 193163398Sscottl MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 194157114Sscottl MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 195255806Ssbruno MFI_DCMD_CTRL_GET_PROPS = 0x01020100, 196255806Ssbruno MFI_DCMD_CTRL_SET_PROPS = 0x01020200, 197157114Sscottl MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 198157114Sscottl MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 199157114Sscottl MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 200157114Sscottl MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 201196200Sscottl MFI_DCMD_PR_GET_STATUS = 0x01070100, 202196200Sscottl MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 203196200Sscottl MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 204196200Sscottl MFI_DCMD_PR_START = 0x01070400, 205196200Sscottl MFI_DCMD_PR_STOP = 0x01070500, 206196200Sscottl MFI_DCMD_TIME_SECS_GET = 0x01080201, 207196200Sscottl MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 208196200Sscottl MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 209196200Sscottl MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 210196200Sscottl MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 211196200Sscottl MFI_DCMD_PD_GET_LIST = 0x02010000, 212233711Sambrisko MFI_DCMD_PD_LIST_QUERY = 0x02010100, 213196200Sscottl MFI_DCMD_PD_GET_INFO = 0x02020000, 214196200Sscottl MFI_DCMD_PD_STATE_SET = 0x02030100, 215196200Sscottl MFI_DCMD_PD_REBUILD_START = 0x02040100, 216196200Sscottl MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 217196200Sscottl MFI_DCMD_PD_CLEAR_START = 0x02050100, 218196200Sscottl MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 219196200Sscottl MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 220196200Sscottl MFI_DCMD_PD_LOCATE_START = 0x02070100, 221196200Sscottl MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 222233711Sambrisko MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 223233711Sambrisko MFI_DCMD_LD_SYNC = 0x0300e102, 224159811Sps MFI_DCMD_LD_GET_LIST = 0x03010000, 225159811Sps MFI_DCMD_LD_GET_INFO = 0x03020000, 226157114Sscottl MFI_DCMD_LD_GET_PROP = 0x03030000, 227159811Sps MFI_DCMD_LD_SET_PROP = 0x03040000, 228196200Sscottl MFI_DCMD_LD_INIT_START = 0x03060100, 229171821Sjhb MFI_DCMD_LD_DELETE = 0x03090000, 230163398Sscottl MFI_DCMD_CFG_READ = 0x04010000, 231163398Sscottl MFI_DCMD_CFG_ADD = 0x04020000, 232163398Sscottl MFI_DCMD_CFG_CLEAR = 0x04030000, 233196200Sscottl MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 234233711Sambrisko MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 235251516Ssbruno MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100, 236251516Ssbruno MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200, 237251516Ssbruno MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300, 238184897Sambrisko MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 239251516Ssbruno MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500, 240196200Sscottl MFI_DCMD_BBU_GET_STATUS = 0x05010000, 241196200Sscottl MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 242196200Sscottl MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 243249257Smarkj MFI_DCMD_BBU_START_LEARN = 0x05040000, 244249257Smarkj MFI_DCMD_BBU_GET_PROP = 0x05050100, 245249257Smarkj MFI_DCMD_BBU_SET_PROP = 0x05050200, 246157114Sscottl MFI_DCMD_CLUSTER = 0x08000000, 247157114Sscottl MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 248157114Sscottl MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 249157114Sscottl} mfi_dcmd_t; 250157114Sscottl 251157114Sscottl/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 252157114Sscottl#define MFI_FLUSHCACHE_CTRL 0x01 253157114Sscottl#define MFI_FLUSHCACHE_DISK 0x02 254157114Sscottl 255157114Sscottl/* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 256157114Sscottl#define MFI_SHUTDOWN_SPINDOWN 0x01 257157114Sscottl 258157114Sscottl/* 259158737Sambrisko * MFI Frame flags 260157114Sscottl */ 261157114Sscottl#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 262157114Sscottl#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 263157114Sscottl#define MFI_FRAME_SGL32 0x0000 264157114Sscottl#define MFI_FRAME_SGL64 0x0002 265157114Sscottl#define MFI_FRAME_SENSE32 0x0000 266157114Sscottl#define MFI_FRAME_SENSE64 0x0004 267157114Sscottl#define MFI_FRAME_DIR_NONE 0x0000 268157114Sscottl#define MFI_FRAME_DIR_WRITE 0x0008 269157114Sscottl#define MFI_FRAME_DIR_READ 0x0010 270157114Sscottl#define MFI_FRAME_DIR_BOTH 0x0018 271233711Sambrisko#define MFI_FRAME_IEEE_SGL 0x0020 272247369Ssmh#define MFI_FRAME_FMT "\20" \ 273247369Ssmh "\1NOPOST" \ 274247369Ssmh "\2SGL64" \ 275247369Ssmh "\3SENSE64" \ 276247369Ssmh "\4WRITE" \ 277247369Ssmh "\5READ" \ 278247369Ssmh "\6IEEESGL" 279157114Sscottl 280233711Sambrisko/* ThunderBolt Specific */ 281233711Sambrisko 282233711Sambrisko/* 283233711Sambrisko * Pre-TB command size and TB command size. 284233711Sambrisko * We will be checking it at the load time for the time being 285233711Sambrisko */ 286233711Sambrisko#define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 287233711Sambrisko 288233711Sambrisko#define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 289233711Sambrisko/* 290233711Sambrisko * We are defining only 128 byte message to reduce memory move over head 291233711Sambrisko * and also it will reduce the SRB extension size by 128byte compared with 292233711Sambrisko * 256 message size 293233711Sambrisko */ 294233711Sambrisko#define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 295233711Sambrisko#define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 296233711Sambrisko#define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 297233711Sambrisko#define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 298233711Sambrisko#define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 299233711Sambrisko#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 300233711Sambrisko 301233711Sambrisko#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 302233711Sambrisko#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 303233711Sambrisko 304233711Sambrisko#define MR_INTERNAL_MFI_FRAMES_SMID 1 305233711Sambrisko#define MR_CTRL_EVENT_WAIT_SMID 2 306233711Sambrisko#define MR_INTERNAL_DRIVER_RESET_SMID 3 307233711Sambrisko 308233711Sambrisko 309157114Sscottl/* MFI Status codes */ 310157114Sscottltypedef enum { 311157114Sscottl MFI_STAT_OK = 0x00, 312157114Sscottl MFI_STAT_INVALID_CMD, 313157114Sscottl MFI_STAT_INVALID_DCMD, 314157114Sscottl MFI_STAT_INVALID_PARAMETER, 315157114Sscottl MFI_STAT_INVALID_SEQUENCE_NUMBER, 316157114Sscottl MFI_STAT_ABORT_NOT_POSSIBLE, 317157114Sscottl MFI_STAT_APP_HOST_CODE_NOT_FOUND, 318157114Sscottl MFI_STAT_APP_IN_USE, 319157114Sscottl MFI_STAT_APP_NOT_INITIALIZED, 320157114Sscottl MFI_STAT_ARRAY_INDEX_INVALID, 321157114Sscottl MFI_STAT_ARRAY_ROW_NOT_EMPTY, 322157114Sscottl MFI_STAT_CONFIG_RESOURCE_CONFLICT, 323157114Sscottl MFI_STAT_DEVICE_NOT_FOUND, 324157114Sscottl MFI_STAT_DRIVE_TOO_SMALL, 325157114Sscottl MFI_STAT_FLASH_ALLOC_FAIL, 326157114Sscottl MFI_STAT_FLASH_BUSY, 327157114Sscottl MFI_STAT_FLASH_ERROR = 0x10, 328157114Sscottl MFI_STAT_FLASH_IMAGE_BAD, 329157114Sscottl MFI_STAT_FLASH_IMAGE_INCOMPLETE, 330157114Sscottl MFI_STAT_FLASH_NOT_OPEN, 331157114Sscottl MFI_STAT_FLASH_NOT_STARTED, 332157114Sscottl MFI_STAT_FLUSH_FAILED, 333157114Sscottl MFI_STAT_HOST_CODE_NOT_FOUNT, 334157114Sscottl MFI_STAT_LD_CC_IN_PROGRESS, 335157114Sscottl MFI_STAT_LD_INIT_IN_PROGRESS, 336157114Sscottl MFI_STAT_LD_LBA_OUT_OF_RANGE, 337157114Sscottl MFI_STAT_LD_MAX_CONFIGURED, 338157114Sscottl MFI_STAT_LD_NOT_OPTIMAL, 339157114Sscottl MFI_STAT_LD_RBLD_IN_PROGRESS, 340157114Sscottl MFI_STAT_LD_RECON_IN_PROGRESS, 341157114Sscottl MFI_STAT_LD_WRONG_RAID_LEVEL, 342157114Sscottl MFI_STAT_MAX_SPARES_EXCEEDED, 343157114Sscottl MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 344157114Sscottl MFI_STAT_MFC_HW_ERROR, 345157114Sscottl MFI_STAT_NO_HW_PRESENT, 346157114Sscottl MFI_STAT_NOT_FOUND, 347157114Sscottl MFI_STAT_NOT_IN_ENCL, 348157114Sscottl MFI_STAT_PD_CLEAR_IN_PROGRESS, 349157114Sscottl MFI_STAT_PD_TYPE_WRONG, 350157114Sscottl MFI_STAT_PR_DISABLED, 351157114Sscottl MFI_STAT_ROW_INDEX_INVALID, 352157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_ACTION, 353157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_DATA, 354157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_PAGE, 355157114Sscottl MFI_STAT_SAS_CONFIG_INVALID_TYPE, 356157114Sscottl MFI_STAT_SCSI_DONE_WITH_ERROR, 357157114Sscottl MFI_STAT_SCSI_IO_FAILED, 358157114Sscottl MFI_STAT_SCSI_RESERVATION_CONFLICT, 359157114Sscottl MFI_STAT_SHUTDOWN_FAILED = 0x30, 360157114Sscottl MFI_STAT_TIME_NOT_SET, 361157114Sscottl MFI_STAT_WRONG_STATE, 362157114Sscottl MFI_STAT_LD_OFFLINE, 363157114Sscottl MFI_STAT_PEER_NOTIFICATION_REJECTED, 364157114Sscottl MFI_STAT_PEER_NOTIFICATION_FAILED, 365157114Sscottl MFI_STAT_RESERVATION_IN_PROGRESS, 366157114Sscottl MFI_STAT_I2C_ERRORS_DETECTED, 367157114Sscottl MFI_STAT_PCI_ERRORS_DETECTED, 368196200Sscottl MFI_STAT_DIAG_FAILED, 369196200Sscottl MFI_STAT_BOOT_MSG_PENDING, 370196200Sscottl MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 371157114Sscottl MFI_STAT_INVALID_STATUS = 0xFF 372157114Sscottl} mfi_status_t; 373157114Sscottl 374157114Sscottltypedef enum { 375157114Sscottl MFI_EVT_CLASS_DEBUG = -2, 376157114Sscottl MFI_EVT_CLASS_PROGRESS = -1, 377157114Sscottl MFI_EVT_CLASS_INFO = 0, 378157114Sscottl MFI_EVT_CLASS_WARNING = 1, 379157114Sscottl MFI_EVT_CLASS_CRITICAL = 2, 380157114Sscottl MFI_EVT_CLASS_FATAL = 3, 381157114Sscottl MFI_EVT_CLASS_DEAD = 4 382157114Sscottl} mfi_evt_class_t; 383157114Sscottl 384157114Sscottltypedef enum { 385157114Sscottl MFI_EVT_LOCALE_LD = 0x0001, 386157114Sscottl MFI_EVT_LOCALE_PD = 0x0002, 387157114Sscottl MFI_EVT_LOCALE_ENCL = 0x0004, 388157114Sscottl MFI_EVT_LOCALE_BBU = 0x0008, 389157114Sscottl MFI_EVT_LOCALE_SAS = 0x0010, 390157114Sscottl MFI_EVT_LOCALE_CTRL = 0x0020, 391157114Sscottl MFI_EVT_LOCALE_CONFIG = 0x0040, 392157114Sscottl MFI_EVT_LOCALE_CLUSTER = 0x0080, 393157114Sscottl MFI_EVT_LOCALE_ALL = 0xffff 394157114Sscottl} mfi_evt_locale_t; 395157114Sscottl 396157114Sscottltypedef enum { 397158737Sambrisko MR_EVT_ARGS_NONE = 0x00, 398158737Sambrisko MR_EVT_ARGS_CDB_SENSE, 399158737Sambrisko MR_EVT_ARGS_LD, 400158737Sambrisko MR_EVT_ARGS_LD_COUNT, 401158737Sambrisko MR_EVT_ARGS_LD_LBA, 402158737Sambrisko MR_EVT_ARGS_LD_OWNER, 403158737Sambrisko MR_EVT_ARGS_LD_LBA_PD_LBA, 404158737Sambrisko MR_EVT_ARGS_LD_PROG, 405158737Sambrisko MR_EVT_ARGS_LD_STATE, 406158737Sambrisko MR_EVT_ARGS_LD_STRIP, 407158737Sambrisko MR_EVT_ARGS_PD, 408158737Sambrisko MR_EVT_ARGS_PD_ERR, 409158737Sambrisko MR_EVT_ARGS_PD_LBA, 410158737Sambrisko MR_EVT_ARGS_PD_LBA_LD, 411158737Sambrisko MR_EVT_ARGS_PD_PROG, 412158737Sambrisko MR_EVT_ARGS_PD_STATE, 413158737Sambrisko MR_EVT_ARGS_PCI, 414158737Sambrisko MR_EVT_ARGS_RATE, 415158737Sambrisko MR_EVT_ARGS_STR, 416158737Sambrisko MR_EVT_ARGS_TIME, 417158737Sambrisko MR_EVT_ARGS_ECC 418157114Sscottl} mfi_evt_args; 419157114Sscottl 420233711Sambrisko#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 421233711Sambrisko#define MR_EVT_PD_REMOVED 0x0070 422233711Sambrisko#define MR_EVT_PD_INSERTED 0x005b 423235014Sambrisko#define MR_EVT_LD_CHANGE 0x0051 424233711Sambrisko 425163398Sscottltypedef enum { 426163398Sscottl MR_LD_CACHE_WRITE_BACK = 0x01, 427163398Sscottl MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 428163398Sscottl MR_LD_CACHE_READ_AHEAD = 0x04, 429163398Sscottl MR_LD_CACHE_READ_ADAPTIVE = 0x08, 430163398Sscottl MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 431163398Sscottl MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 432163398Sscottl MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 433163398Sscottl} mfi_ld_cache; 434196200Sscottl#define MR_LD_CACHE_MASK 0x7f 435163398Sscottl 436196200Sscottl#define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 437196200Sscottl#define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 438196200Sscottl#define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 439196200Sscottl (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 440196200Sscottl#define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 441196200Sscottl#define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 442196200Sscottl#define MR_LD_CACHE_POLICY_IO_CACHED \ 443196200Sscottl (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 444196200Sscottl#define MR_LD_CACHE_POLICY_IO_DIRECT 0 445196200Sscottl 446163398Sscottltypedef enum { 447163398Sscottl MR_PD_CACHE_UNCHANGED = 0, 448163398Sscottl MR_PD_CACHE_ENABLE = 1, 449163398Sscottl MR_PD_CACHE_DISABLE = 2 450163398Sscottl} mfi_pd_cache; 451163398Sscottl 452233711Sambriskotypedef enum { 453233711Sambrisko MR_PD_QUERY_TYPE_ALL = 0, 454233711Sambrisko MR_PD_QUERY_TYPE_STATE = 1, 455233711Sambrisko MR_PD_QUERY_TYPE_POWER_STATE = 2, 456233711Sambrisko MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 457233711Sambrisko MR_PD_QUERY_TYPE_SPEED = 4, 458233711Sambrisko MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 459233711Sambrisko} mfi_pd_query_type; 460233711Sambrisko 461157114Sscottl/* 462157114Sscottl * Other propertities and definitions 463157114Sscottl */ 464157114Sscottl#define MFI_MAX_PD_CHANNELS 2 465157114Sscottl#define MFI_MAX_LD_CHANNELS 2 466157114Sscottl#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 467157114Sscottl#define MFI_MAX_CHANNEL_DEVS 128 468157114Sscottl#define MFI_DEFAULT_ID -1 469157114Sscottl#define MFI_MAX_LUN 8 470157114Sscottl#define MFI_MAX_LD 64 471196200Sscottl#define MFI_MAX_PD 256 472157114Sscottl 473157114Sscottl#define MFI_FRAME_SIZE 64 474157114Sscottl#define MFI_MBOX_SIZE 12 475157114Sscottl 476247369Ssmh/* Firmware flashing can take 50+ seconds */ 477247369Ssmh#define MFI_POLL_TIMEOUT_SECS 60 478157114Sscottl 479157114Sscottl/* Allow for speedier math calculations */ 480157114Sscottl#define MFI_SECTOR_LEN 512 481157114Sscottl 482157114Sscottl/* Scatter Gather elements */ 483157114Sscottlstruct mfi_sg32 { 484157114Sscottl uint32_t addr; 485157114Sscottl uint32_t len; 486157114Sscottl} __packed; 487157114Sscottl 488157114Sscottlstruct mfi_sg64 { 489157114Sscottl uint64_t addr; 490157114Sscottl uint32_t len; 491157114Sscottl} __packed; 492157114Sscottl 493233711Sambriskostruct mfi_sg_skinny { 494233711Sambrisko uint64_t addr; 495233711Sambrisko uint32_t len; 496233711Sambrisko uint32_t flag; 497233711Sambrisko} __packed; 498233711Sambrisko 499157114Sscottlunion mfi_sgl { 500233711Sambrisko struct mfi_sg32 sg32[1]; 501233711Sambrisko struct mfi_sg64 sg64[1]; 502233711Sambrisko struct mfi_sg_skinny sg_skinny[1]; 503157114Sscottl} __packed; 504157114Sscottl 505157114Sscottl/* Message frames. All messages have a common header */ 506157114Sscottlstruct mfi_frame_header { 507157114Sscottl uint8_t cmd; 508157114Sscottl uint8_t sense_len; 509157114Sscottl uint8_t cmd_status; 510157114Sscottl uint8_t scsi_status; 511157114Sscottl uint8_t target_id; 512157114Sscottl uint8_t lun_id; 513157114Sscottl uint8_t cdb_len; 514157114Sscottl uint8_t sg_count; 515157114Sscottl uint32_t context; 516233711Sambrisko /* 517233711Sambrisko * pad0 is MSI Specific. Not used by Driver. Zero the value before 518233711Sambrisko * sending the command to f/w. 519233711Sambrisko */ 520157114Sscottl uint32_t pad0; 521157114Sscottl uint16_t flags; 522175897Sambrisko#define MFI_FRAME_DATAOUT 0x08 523175897Sambrisko#define MFI_FRAME_DATAIN 0x10 524157114Sscottl uint16_t timeout; 525157114Sscottl uint32_t data_len; 526157114Sscottl} __packed; 527157114Sscottl 528157114Sscottlstruct mfi_init_frame { 529157114Sscottl struct mfi_frame_header header; 530157114Sscottl uint32_t qinfo_new_addr_lo; 531157114Sscottl uint32_t qinfo_new_addr_hi; 532157114Sscottl uint32_t qinfo_old_addr_lo; 533157114Sscottl uint32_t qinfo_old_addr_hi; 534233711Sambrisko // Start LSIP200113393 535233711Sambrisko uint32_t driver_ver_lo; /*28h */ 536233711Sambrisko uint32_t driver_ver_hi; /*2Ch */ 537233711Sambrisko 538233711Sambrisko uint32_t reserved[4]; 539233711Sambrisko // End LSIP200113393 540157114Sscottl} __packed; 541157114Sscottl 542233711Sambrisko/* 543233711Sambrisko * Define MFI Address Context union. 544233711Sambrisko */ 545233711Sambrisko#ifdef MFI_ADDRESS_IS_uint64_t 546233711Sambrisko typedef uint64_t MFI_ADDRESS; 547233711Sambrisko#else 548233711Sambrisko typedef union _MFI_ADDRESS { 549233711Sambrisko struct { 550233711Sambrisko uint32_t addressLow; 551233711Sambrisko uint32_t addressHigh; 552233711Sambrisko } u; 553233711Sambrisko uint64_t address; 554233711Sambrisko } MFI_ADDRESS, *PMFI_ADDRESS; 555233711Sambrisko#endif 556233711Sambrisko 557157114Sscottl#define MFI_IO_FRAME_SIZE 40 558157114Sscottlstruct mfi_io_frame { 559157114Sscottl struct mfi_frame_header header; 560157114Sscottl uint32_t sense_addr_lo; 561157114Sscottl uint32_t sense_addr_hi; 562157114Sscottl uint32_t lba_lo; 563157114Sscottl uint32_t lba_hi; 564157114Sscottl union mfi_sgl sgl; 565157114Sscottl} __packed; 566157114Sscottl 567157114Sscottl#define MFI_PASS_FRAME_SIZE 48 568157114Sscottlstruct mfi_pass_frame { 569157114Sscottl struct mfi_frame_header header; 570157114Sscottl uint32_t sense_addr_lo; 571157114Sscottl uint32_t sense_addr_hi; 572157114Sscottl uint8_t cdb[16]; 573157114Sscottl union mfi_sgl sgl; 574157114Sscottl} __packed; 575157114Sscottl 576157114Sscottl#define MFI_DCMD_FRAME_SIZE 40 577157114Sscottlstruct mfi_dcmd_frame { 578157114Sscottl struct mfi_frame_header header; 579157114Sscottl uint32_t opcode; 580157114Sscottl uint8_t mbox[MFI_MBOX_SIZE]; 581157114Sscottl union mfi_sgl sgl; 582157114Sscottl} __packed; 583157114Sscottl 584157114Sscottlstruct mfi_abort_frame { 585157114Sscottl struct mfi_frame_header header; 586157114Sscottl uint32_t abort_context; 587233711Sambrisko /* pad is changed to reserved.*/ 588233711Sambrisko uint32_t reserved0; 589157114Sscottl uint32_t abort_mfi_addr_lo; 590157114Sscottl uint32_t abort_mfi_addr_hi; 591233711Sambrisko uint32_t reserved1[6]; 592157114Sscottl} __packed; 593157114Sscottl 594157114Sscottlstruct mfi_smp_frame { 595157114Sscottl struct mfi_frame_header header; 596157114Sscottl uint64_t sas_addr; 597157114Sscottl union { 598157114Sscottl struct mfi_sg32 sg32[2]; 599157114Sscottl struct mfi_sg64 sg64[2]; 600157114Sscottl } sgl; 601157114Sscottl} __packed; 602157114Sscottl 603157114Sscottlstruct mfi_stp_frame { 604157114Sscottl struct mfi_frame_header header; 605157114Sscottl uint16_t fis[10]; 606157114Sscottl uint32_t stp_flags; 607157114Sscottl union { 608157114Sscottl struct mfi_sg32 sg32[2]; 609157114Sscottl struct mfi_sg64 sg64[2]; 610157114Sscottl } sgl; 611157114Sscottl} __packed; 612157114Sscottl 613157114Sscottlunion mfi_frame { 614157114Sscottl struct mfi_frame_header header; 615157114Sscottl struct mfi_init_frame init; 616233711Sambrisko /* ThunderBolt Initialization */ 617157114Sscottl struct mfi_io_frame io; 618157114Sscottl struct mfi_pass_frame pass; 619157114Sscottl struct mfi_dcmd_frame dcmd; 620157114Sscottl struct mfi_abort_frame abort; 621157114Sscottl struct mfi_smp_frame smp; 622157114Sscottl struct mfi_stp_frame stp; 623157114Sscottl uint8_t bytes[MFI_FRAME_SIZE]; 624157114Sscottl}; 625157114Sscottl 626157114Sscottl#define MFI_SENSE_LEN 128 627157114Sscottlstruct mfi_sense { 628157114Sscottl uint8_t data[MFI_SENSE_LEN]; 629157114Sscottl}; 630157114Sscottl 631157114Sscottl/* The queue init structure that is passed with the init message */ 632157114Sscottlstruct mfi_init_qinfo { 633157114Sscottl uint32_t flags; 634157114Sscottl uint32_t rq_entries; 635157114Sscottl uint32_t rq_addr_lo; 636157114Sscottl uint32_t rq_addr_hi; 637157114Sscottl uint32_t pi_addr_lo; 638157114Sscottl uint32_t pi_addr_hi; 639157114Sscottl uint32_t ci_addr_lo; 640157114Sscottl uint32_t ci_addr_hi; 641157114Sscottl} __packed; 642157114Sscottl 643157114Sscottl/* SAS (?) controller properties, part of mfi_ctrl_info */ 644157114Sscottlstruct mfi_ctrl_props { 645157114Sscottl uint16_t seq_num; 646157114Sscottl uint16_t pred_fail_poll_interval; 647157114Sscottl uint16_t intr_throttle_cnt; 648157114Sscottl uint16_t intr_throttle_timeout; 649157114Sscottl uint8_t rebuild_rate; 650157114Sscottl uint8_t patrol_read_rate; 651157114Sscottl uint8_t bgi_rate; 652157114Sscottl uint8_t cc_rate; 653157114Sscottl uint8_t recon_rate; 654157114Sscottl uint8_t cache_flush_interval; 655157114Sscottl uint8_t spinup_drv_cnt; 656157114Sscottl uint8_t spinup_delay; 657157114Sscottl uint8_t cluster_enable; 658157114Sscottl uint8_t coercion_mode; 659157114Sscottl uint8_t alarm_enable; 660157114Sscottl uint8_t disable_auto_rebuild; 661157114Sscottl uint8_t disable_battery_warn; 662157114Sscottl uint8_t ecc_bucket_size; 663157114Sscottl uint16_t ecc_bucket_leak_rate; 664157114Sscottl uint8_t restore_hotspare_on_insertion; 665157114Sscottl uint8_t expose_encl_devices; 666233711Sambrisko uint8_t maintainPdFailHistory; 667233711Sambrisko uint8_t disallowHostRequestReordering; 668233711Sambrisko /* set TRUE to abort CC on detecting an inconsistency */ 669233711Sambrisko uint8_t abortCCOnError; 670233711Sambrisko /* load balance mode (MR_LOAD_BALANCE_MODE) */ 671233711Sambrisko uint8_t loadBalanceMode; 672233711Sambrisko /* 673233711Sambrisko * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 674233711Sambrisko * h/w mechansim like GPIO pins 675233711Sambrisko * 1 - disable auto detect SGPIO, 676233711Sambrisko * 2 - disable i2c SEP auto detect 677233711Sambrisko * 3 - disable both auto detect 678233711Sambrisko */ 679233711Sambrisko uint8_t disableAutoDetectBackplane; 680233711Sambrisko /* 681233711Sambrisko * % of source LD to be reserved for a VDs snapshot in snapshot 682233711Sambrisko * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 683233711Sambrisko */ 684233711Sambrisko uint8_t snapVDSpace; 685233711Sambrisko 686233711Sambrisko /* 687233711Sambrisko * Add properties that can be controlled by a bit in the following 688233711Sambrisko * structure. 689233711Sambrisko */ 690233711Sambrisko struct { 691233711Sambrisko /* set TRUE to disable copyBack (0=copback enabled) */ 692233711Sambrisko uint32_t copyBackDisabled :1; 693233711Sambrisko uint32_t SMARTerEnabled :1; 694233711Sambrisko uint32_t prCorrectUnconfiguredAreas :1; 695233711Sambrisko uint32_t useFdeOnly :1; 696233711Sambrisko uint32_t disableNCQ :1; 697233711Sambrisko uint32_t SSDSMARTerEnabled :1; 698233711Sambrisko uint32_t SSDPatrolReadEnabled :1; 699233711Sambrisko uint32_t enableSpinDownUnconfigured :1; 700233711Sambrisko uint32_t autoEnhancedImport :1; 701233711Sambrisko uint32_t enableSecretKeyControl :1; 702233711Sambrisko uint32_t disableOnlineCtrlReset :1; 703233711Sambrisko uint32_t allowBootWithPinnedCache :1; 704233711Sambrisko uint32_t disableSpinDownHS :1; 705233711Sambrisko uint32_t enableJBOD :1; 706233711Sambrisko uint32_t reserved :18; 707233711Sambrisko } OnOffProperties; 708233711Sambrisko /* 709233711Sambrisko * % of source LD to be reserved for auto snapshot in snapshot 710233711Sambrisko * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 711233711Sambrisko */ 712233711Sambrisko uint8_t autoSnapVDSpace; 713233711Sambrisko /* 714233711Sambrisko * Snapshot writeable VIEWs capacity as a % of source LD capacity: 715233711Sambrisko * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 716233711Sambrisko */ 717233711Sambrisko uint8_t viewSpace; 718233711Sambrisko /* # of idle minutes before device is spun down (0=use FW defaults) */ 719233711Sambrisko uint16_t spinDownTime; 720233711Sambrisko uint8_t reserved[24]; 721157114Sscottl} __packed; 722157114Sscottl 723157114Sscottl/* PCI information about the card. */ 724157114Sscottlstruct mfi_info_pci { 725157114Sscottl uint16_t vendor; 726157114Sscottl uint16_t device; 727157114Sscottl uint16_t subvendor; 728157114Sscottl uint16_t subdevice; 729157114Sscottl uint8_t reserved[24]; 730157114Sscottl} __packed; 731157114Sscottl 732157114Sscottl/* Host (front end) interface information */ 733157114Sscottlstruct mfi_info_host { 734157114Sscottl uint8_t type; 735157114Sscottl#define MFI_INFO_HOST_PCIX 0x01 736157114Sscottl#define MFI_INFO_HOST_PCIE 0x02 737157114Sscottl#define MFI_INFO_HOST_ISCSI 0x04 738157114Sscottl#define MFI_INFO_HOST_SAS3G 0x08 739157114Sscottl uint8_t reserved[6]; 740157114Sscottl uint8_t port_count; 741157114Sscottl uint64_t port_addr[8]; 742157114Sscottl} __packed; 743157114Sscottl 744157114Sscottl/* Device (back end) interface information */ 745157114Sscottlstruct mfi_info_device { 746157114Sscottl uint8_t type; 747157114Sscottl#define MFI_INFO_DEV_SPI 0x01 748157114Sscottl#define MFI_INFO_DEV_SAS3G 0x02 749157114Sscottl#define MFI_INFO_DEV_SATA1 0x04 750157114Sscottl#define MFI_INFO_DEV_SATA3G 0x08 751157114Sscottl uint8_t reserved[6]; 752157114Sscottl uint8_t port_count; 753157114Sscottl uint64_t port_addr[8]; 754157114Sscottl} __packed; 755157114Sscottl 756157114Sscottl/* Firmware component information */ 757157114Sscottlstruct mfi_info_component { 758157114Sscottl char name[8]; 759157114Sscottl char version[32]; 760157114Sscottl char build_date[16]; 761157114Sscottl char build_time[16]; 762157114Sscottl} __packed; 763157114Sscottl 764163398Sscottl/* Controller default settings */ 765163398Sscottlstruct mfi_defaults { 766163398Sscottl uint64_t sas_addr; 767163398Sscottl uint8_t phy_polarity; 768163398Sscottl uint8_t background_rate; 769163398Sscottl uint8_t stripe_size; 770163398Sscottl uint8_t flush_time; 771163398Sscottl uint8_t write_back; 772163398Sscottl uint8_t read_ahead; 773163398Sscottl uint8_t cache_when_bbu_bad; 774163398Sscottl uint8_t cached_io; 775163398Sscottl uint8_t smart_mode; 776163398Sscottl uint8_t alarm_disable; 777163398Sscottl uint8_t coercion; 778163398Sscottl uint8_t zrc_config; 779163398Sscottl uint8_t dirty_led_shows_drive_activity; 780163398Sscottl uint8_t bios_continue_on_error; 781163398Sscottl uint8_t spindown_mode; 782163398Sscottl uint8_t allowed_device_types; 783163398Sscottl uint8_t allow_mix_in_enclosure; 784163398Sscottl uint8_t allow_mix_in_ld; 785163398Sscottl uint8_t allow_sata_in_cluster; 786163398Sscottl uint8_t max_chained_enclosures; 787163398Sscottl uint8_t disable_ctrl_r; 788163398Sscottl uint8_t enabel_web_bios; 789163398Sscottl uint8_t phy_polarity_split; 790163398Sscottl uint8_t direct_pd_mapping; 791163398Sscottl uint8_t bios_enumerate_lds; 792163398Sscottl uint8_t restored_hot_spare_on_insertion; 793163398Sscottl uint8_t expose_enclosure_devices; 794163398Sscottl uint8_t maintain_pd_fail_history; 795163398Sscottl uint8_t resv[28]; 796163398Sscottl} __packed; 797157114Sscottl 798163398Sscottl/* Controller default settings */ 799163398Sscottlstruct mfi_bios_data { 800163398Sscottl uint16_t boot_target_id; 801163398Sscottl uint8_t do_not_int_13; 802163398Sscottl uint8_t continue_on_error; 803163398Sscottl uint8_t verbose; 804163398Sscottl uint8_t geometry; 805163398Sscottl uint8_t expose_all_drives; 806163398Sscottl uint8_t reserved[56]; 807163398Sscottl uint8_t check_sum; 808163398Sscottl} __packed; 809163398Sscottl 810157114Sscottl/* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 811157114Sscottlstruct mfi_ctrl_info { 812157114Sscottl struct mfi_info_pci pci; 813157114Sscottl struct mfi_info_host host; 814157114Sscottl struct mfi_info_device device; 815157114Sscottl 816157114Sscottl /* Firmware components that are present and active. */ 817157114Sscottl uint32_t image_check_word; 818157114Sscottl uint32_t image_component_count; 819157114Sscottl struct mfi_info_component image_component[8]; 820157114Sscottl 821157114Sscottl /* Firmware components that have been flashed but are inactive */ 822157114Sscottl uint32_t pending_image_component_count; 823157114Sscottl struct mfi_info_component pending_image_component[8]; 824157114Sscottl 825157114Sscottl uint8_t max_arms; 826157114Sscottl uint8_t max_spans; 827157114Sscottl uint8_t max_arrays; 828157114Sscottl uint8_t max_lds; 829157114Sscottl char product_name[80]; 830157114Sscottl char serial_number[32]; 831157114Sscottl uint32_t hw_present; 832157114Sscottl#define MFI_INFO_HW_BBU 0x01 833157114Sscottl#define MFI_INFO_HW_ALARM 0x02 834157114Sscottl#define MFI_INFO_HW_NVRAM 0x04 835157114Sscottl#define MFI_INFO_HW_UART 0x08 836157114Sscottl uint32_t current_fw_time; 837157114Sscottl uint16_t max_cmds; 838157114Sscottl uint16_t max_sg_elements; 839157114Sscottl uint32_t max_request_size; 840157114Sscottl uint16_t lds_present; 841157114Sscottl uint16_t lds_degraded; 842157114Sscottl uint16_t lds_offline; 843157114Sscottl uint16_t pd_present; 844157114Sscottl uint16_t pd_disks_present; 845157114Sscottl uint16_t pd_disks_pred_failure; 846157114Sscottl uint16_t pd_disks_failed; 847157114Sscottl uint16_t nvram_size; 848157114Sscottl uint16_t memory_size; 849157114Sscottl uint16_t flash_size; 850157114Sscottl uint16_t ram_correctable_errors; 851157114Sscottl uint16_t ram_uncorrectable_errors; 852157114Sscottl uint8_t cluster_allowed; 853157114Sscottl uint8_t cluster_active; 854157114Sscottl uint16_t max_strips_per_io; 855157114Sscottl 856157114Sscottl uint32_t raid_levels; 857157114Sscottl#define MFI_INFO_RAID_0 0x01 858157114Sscottl#define MFI_INFO_RAID_1 0x02 859157114Sscottl#define MFI_INFO_RAID_5 0x04 860157114Sscottl#define MFI_INFO_RAID_1E 0x08 861157114Sscottl#define MFI_INFO_RAID_6 0x10 862157114Sscottl 863157114Sscottl uint32_t adapter_ops; 864158737Sambrisko#define MFI_INFO_AOPS_RBLD_RATE 0x0001 865157114Sscottl#define MFI_INFO_AOPS_CC_RATE 0x0002 866157114Sscottl#define MFI_INFO_AOPS_BGI_RATE 0x0004 867157114Sscottl#define MFI_INFO_AOPS_RECON_RATE 0x0008 868157114Sscottl#define MFI_INFO_AOPS_PATROL_RATE 0x0010 869157114Sscottl#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 870157114Sscottl#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 871157114Sscottl#define MFI_INFO_AOPS_BBU 0x0080 872157114Sscottl#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 873157114Sscottl#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 874157114Sscottl#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 875157114Sscottl#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 876157114Sscottl#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 877157114Sscottl#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 878157114Sscottl#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 879157114Sscottl 880157114Sscottl uint32_t ld_ops; 881157114Sscottl#define MFI_INFO_LDOPS_READ_POLICY 0x01 882157114Sscottl#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 883157114Sscottl#define MFI_INFO_LDOPS_IO_POLICY 0x04 884157114Sscottl#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 885157114Sscottl#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 886157114Sscottl 887157114Sscottl struct { 888157114Sscottl uint8_t min; 889157114Sscottl uint8_t max; 890157114Sscottl uint8_t reserved[2]; 891157114Sscottl } __packed stripe_sz_ops; 892157114Sscottl 893157114Sscottl uint32_t pd_ops; 894157114Sscottl#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 895157114Sscottl#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 896157114Sscottl#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 897157114Sscottl 898157114Sscottl uint32_t pd_mix_support; 899157114Sscottl#define MFI_INFO_PDMIX_SAS 0x01 900157114Sscottl#define MFI_INFO_PDMIX_SATA 0x02 901157114Sscottl#define MFI_INFO_PDMIX_ENCL 0x04 902157114Sscottl#define MFI_INFO_PDMIX_LD 0x08 903157114Sscottl#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 904157114Sscottl 905157114Sscottl uint8_t ecc_bucket_count; 906157114Sscottl uint8_t reserved2[11]; 907157114Sscottl struct mfi_ctrl_props properties; 908157114Sscottl char package_version[0x60]; 909157114Sscottl uint8_t pad[0x800 - 0x6a0]; 910157114Sscottl} __packed; 911157114Sscottl 912158737Sambrisko/* keep track of an event. */ 913158737Sambriskounion mfi_evt { 914158737Sambrisko struct { 915158737Sambrisko uint16_t locale; 916158737Sambrisko uint8_t reserved; 917222589Semaste int8_t evt_class; 918158737Sambrisko } members; 919158737Sambrisko uint32_t word; 920158737Sambrisko} __packed; 921158737Sambrisko 922158737Sambrisko/* event log state. */ 923158737Sambriskostruct mfi_evt_log_state { 924158737Sambrisko uint32_t newest_seq_num; 925158737Sambrisko uint32_t oldest_seq_num; 926158737Sambrisko uint32_t clear_seq_num; 927158737Sambrisko uint32_t shutdown_seq_num; 928158737Sambrisko uint32_t boot_seq_num; 929158737Sambrisko} __packed; 930158737Sambrisko 931158737Sambriskostruct mfi_progress { 932158737Sambrisko uint16_t progress; 933158737Sambrisko uint16_t elapsed_seconds; 934158737Sambrisko} __packed; 935158737Sambrisko 936158737Sambriskostruct mfi_evt_ld { 937158737Sambrisko uint16_t target_id; 938158737Sambrisko uint8_t ld_index; 939158737Sambrisko uint8_t reserved; 940158737Sambrisko} __packed; 941158737Sambrisko 942158737Sambriskostruct mfi_evt_pd { 943158737Sambrisko uint16_t device_id; 944158737Sambrisko uint8_t enclosure_index; 945158737Sambrisko uint8_t slot_number; 946158737Sambrisko} __packed; 947158737Sambrisko 948158737Sambrisko/* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 949158737Sambriskostruct mfi_evt_detail { 950158737Sambrisko uint32_t seq; 951158737Sambrisko uint32_t time; 952158737Sambrisko uint32_t code; 953222589Semaste union mfi_evt evt_class; 954158737Sambrisko uint8_t arg_type; 955158737Sambrisko uint8_t reserved1[15]; 956158737Sambrisko 957158737Sambrisko union { 958158737Sambrisko struct { 959158737Sambrisko struct mfi_evt_pd pd; 960158737Sambrisko uint8_t cdb_len; 961158737Sambrisko uint8_t sense_len; 962158737Sambrisko uint8_t reserved[2]; 963158737Sambrisko uint8_t cdb[16]; 964158737Sambrisko uint8_t sense[64]; 965158737Sambrisko } cdb_sense; 966158737Sambrisko 967158737Sambrisko struct mfi_evt_ld ld; 968158737Sambrisko 969158737Sambrisko struct { 970158737Sambrisko struct mfi_evt_ld ld; 971158737Sambrisko uint64_t count; 972158737Sambrisko } ld_count; 973158737Sambrisko 974158737Sambrisko struct { 975158737Sambrisko uint64_t lba; 976158737Sambrisko struct mfi_evt_ld ld; 977158737Sambrisko } ld_lba; 978158737Sambrisko 979158737Sambrisko struct { 980158737Sambrisko struct mfi_evt_ld ld; 981158737Sambrisko uint32_t pre_owner; 982158737Sambrisko uint32_t new_owner; 983158737Sambrisko } ld_owner; 984158737Sambrisko 985158737Sambrisko struct { 986158737Sambrisko uint64_t ld_lba; 987158737Sambrisko uint64_t pd_lba; 988158737Sambrisko struct mfi_evt_ld ld; 989158737Sambrisko struct mfi_evt_pd pd; 990158737Sambrisko } ld_lba_pd_lba; 991158737Sambrisko 992158737Sambrisko struct { 993158737Sambrisko struct mfi_evt_ld ld; 994158737Sambrisko struct mfi_progress prog; 995158737Sambrisko } ld_prog; 996158737Sambrisko 997158737Sambrisko struct { 998158737Sambrisko struct mfi_evt_ld ld; 999158737Sambrisko uint32_t prev_state; 1000158737Sambrisko uint32_t new_state; 1001158737Sambrisko } ld_state; 1002158737Sambrisko 1003158737Sambrisko struct { 1004158737Sambrisko uint64_t strip; 1005158737Sambrisko struct mfi_evt_ld ld; 1006158737Sambrisko } ld_strip; 1007158737Sambrisko 1008158737Sambrisko struct mfi_evt_pd pd; 1009158737Sambrisko 1010158737Sambrisko struct { 1011158737Sambrisko struct mfi_evt_pd pd; 1012158737Sambrisko uint32_t err; 1013158737Sambrisko } pd_err; 1014158737Sambrisko 1015158737Sambrisko struct { 1016158737Sambrisko uint64_t lba; 1017158737Sambrisko struct mfi_evt_pd pd; 1018158737Sambrisko } pd_lba; 1019158737Sambrisko 1020158737Sambrisko struct { 1021158737Sambrisko uint64_t lba; 1022158737Sambrisko struct mfi_evt_pd pd; 1023158737Sambrisko struct mfi_evt_ld ld; 1024158737Sambrisko } pd_lba_ld; 1025158737Sambrisko 1026158737Sambrisko struct { 1027158737Sambrisko struct mfi_evt_pd pd; 1028158737Sambrisko struct mfi_progress prog; 1029158737Sambrisko } pd_prog; 1030158737Sambrisko 1031158737Sambrisko struct { 1032158737Sambrisko struct mfi_evt_pd ld; 1033158737Sambrisko uint32_t prev_state; 1034158737Sambrisko uint32_t new_state; 1035158737Sambrisko } pd_state; 1036158737Sambrisko 1037158737Sambrisko struct { 1038158737Sambrisko uint16_t venderId; 1039158737Sambrisko uint16_t deviceId; 1040158737Sambrisko uint16_t subVenderId; 1041158737Sambrisko uint16_t subDeviceId; 1042158737Sambrisko } pci; 1043158737Sambrisko 1044158737Sambrisko uint32_t rate; 1045158737Sambrisko 1046158737Sambrisko char str[96]; 1047158737Sambrisko 1048158737Sambrisko struct { 1049158737Sambrisko uint32_t rtc; 1050158737Sambrisko uint16_t elapsedSeconds; 1051158737Sambrisko } time; 1052158737Sambrisko 1053158737Sambrisko struct { 1054158737Sambrisko uint32_t ecar; 1055158737Sambrisko uint32_t elog; 1056158737Sambrisko char str[64]; 1057158737Sambrisko } ecc; 1058158737Sambrisko 1059158737Sambrisko uint8_t b[96]; 1060158737Sambrisko uint16_t s[48]; 1061158737Sambrisko uint32_t w[24]; 1062158737Sambrisko uint64_t d[12]; 1063158737Sambrisko } args; 1064158737Sambrisko 1065158737Sambrisko char description[128]; 1066158737Sambrisko} __packed; 1067158737Sambrisko 1068162118Sambriskostruct mfi_evt_list { 1069162118Sambrisko uint32_t count; 1070162118Sambrisko uint32_t reserved; 1071162118Sambrisko struct mfi_evt_detail event[1]; 1072158737Sambrisko} __packed; 1073158737Sambrisko 1074163398Sscottlunion mfi_pd_ref { 1075163398Sscottl struct { 1076163398Sscottl uint16_t device_id; 1077163398Sscottl uint16_t seq_num; 1078163398Sscottl } v; 1079163398Sscottl uint32_t ref; 1080159811Sps} __packed; 1081159811Sps 1082163398Sscottlunion mfi_pd_ddf_type { 1083163398Sscottl struct { 1084163398Sscottl union { 1085163398Sscottl struct { 1086163398Sscottl uint16_t forced_pd_guid : 1; 1087163398Sscottl uint16_t in_vd : 1; 1088163398Sscottl uint16_t is_global_spare : 1; 1089163398Sscottl uint16_t is_spare : 1; 1090163398Sscottl uint16_t is_foreign : 1; 1091163398Sscottl uint16_t reserved : 7; 1092163398Sscottl uint16_t intf : 4; 1093163398Sscottl } pd_type; 1094163398Sscottl uint16_t type; 1095163398Sscottl } v; 1096163398Sscottl uint16_t reserved; 1097163398Sscottl } ddf; 1098163398Sscottl struct { 1099163398Sscottl uint32_t reserved; 1100163398Sscottl } non_disk; 1101163398Sscottl uint32_t type; 1102163398Sscottl} __packed; 1103163398Sscottl 1104163398Sscottlstruct mfi_pd_progress { 1105196200Sscottl uint32_t active; 1106196200Sscottl#define MFI_PD_PROGRESS_REBUILD (1<<0) 1107196200Sscottl#define MFI_PD_PROGRESS_PATROL (1<<1) 1108196200Sscottl#define MFI_PD_PROGRESS_CLEAR (1<<2) 1109163398Sscottl struct mfi_progress rbld; 1110163398Sscottl struct mfi_progress patrol; 1111163398Sscottl struct mfi_progress clear; 1112163398Sscottl struct mfi_progress reserved[4]; 1113163398Sscottl} __packed; 1114163398Sscottl 1115163398Sscottlstruct mfi_pd_info { 1116163398Sscottl union mfi_pd_ref ref; 1117163398Sscottl uint8_t inquiry_data[96]; 1118163398Sscottl uint8_t vpd_page83[64]; 1119163398Sscottl uint8_t not_supported; 1120163398Sscottl uint8_t scsi_dev_type; 1121163398Sscottl uint8_t connected_port_bitmap; 1122163398Sscottl uint8_t device_speed; 1123163398Sscottl uint32_t media_err_count; 1124163398Sscottl uint32_t other_err_count; 1125163398Sscottl uint32_t pred_fail_count; 1126163398Sscottl uint32_t last_pred_fail_event_seq_num; 1127196200Sscottl uint16_t fw_state; /* MFI_PD_STATE_* */ 1128196200Sscottl uint8_t disabled_for_removal; 1129163398Sscottl uint8_t link_speed; 1130163398Sscottl union mfi_pd_ddf_type state; 1131163398Sscottl struct { 1132163398Sscottl uint8_t count; 1133163398Sscottl uint8_t is_path_broken; 1134163398Sscottl uint8_t reserved[6]; 1135163398Sscottl uint64_t sas_addr[4]; 1136163398Sscottl } path_info; 1137163398Sscottl uint64_t raw_size; 1138163398Sscottl uint64_t non_coerced_size; 1139163398Sscottl uint64_t coerced_size; 1140163398Sscottl uint16_t encl_device_id; 1141163398Sscottl uint8_t encl_index; 1142163398Sscottl uint8_t slot_number; 1143163398Sscottl struct mfi_pd_progress prog_info; 1144163398Sscottl uint8_t bad_block_table_full; 1145163398Sscottl uint8_t unusable_in_current_config; 1146163398Sscottl uint8_t vpd_page83_ext[64]; 1147163398Sscottl uint8_t reserved[512-358]; 1148163398Sscottl} __packed; 1149163398Sscottl 1150163398Sscottlstruct mfi_pd_address { 1151163398Sscottl uint16_t device_id; 1152163398Sscottl uint16_t encl_device_id; 1153163398Sscottl uint8_t encl_index; 1154163398Sscottl uint8_t slot_number; 1155196200Sscottl uint8_t scsi_dev_type; /* 0 = disk */ 1156163398Sscottl uint8_t connect_port_bitmap; 1157163398Sscottl uint64_t sas_addr[2]; 1158163398Sscottl} __packed; 1159163398Sscottl 1160233711Sambrisko#define MAX_SYS_PDS 240 1161163398Sscottlstruct mfi_pd_list { 1162163398Sscottl uint32_t size; 1163163398Sscottl uint32_t count; 1164233711Sambrisko struct mfi_pd_address addr[MAX_SYS_PDS]; 1165163398Sscottl} __packed; 1166163398Sscottl 1167196200Sscottlenum mfi_pd_state { 1168196200Sscottl MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1169196200Sscottl MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1170196200Sscottl MFI_PD_STATE_HOT_SPARE = 0x02, 1171196200Sscottl MFI_PD_STATE_OFFLINE = 0x10, 1172196200Sscottl MFI_PD_STATE_FAILED = 0x11, 1173196200Sscottl MFI_PD_STATE_REBUILD = 0x14, 1174214130Spluknet MFI_PD_STATE_ONLINE = 0x18, 1175214130Spluknet MFI_PD_STATE_COPYBACK = 0x20, 1176214130Spluknet MFI_PD_STATE_SYSTEM = 0x40 1177196200Sscottl}; 1178196200Sscottl 1179233711Sambrisko/* 1180233711Sambrisko * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1181233711Sambrisko * Adding a #define to denote this. 1182233711Sambrisko */ 1183233711Sambrisko#define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1184233711Sambrisko 1185163398Sscottlunion mfi_ld_ref { 1186163398Sscottl struct { 1187163398Sscottl uint8_t target_id; 1188163398Sscottl uint8_t reserved; 1189163398Sscottl uint16_t seq; 1190163398Sscottl } v; 1191163398Sscottl uint32_t ref; 1192163398Sscottl} __packed; 1193163398Sscottl 1194159811Spsstruct mfi_ld_list { 1195159811Sps uint32_t ld_count; 1196159811Sps uint32_t reserved1; 1197159811Sps struct { 1198163398Sscottl union mfi_ld_ref ld; 1199159811Sps uint8_t state; 1200159811Sps uint8_t reserved2[3]; 1201159811Sps uint64_t size; 1202159811Sps } ld_list[MFI_MAX_LD]; 1203159811Sps} __packed; 1204159811Sps 1205159811Spsenum mfi_ld_access { 1206159811Sps MFI_LD_ACCESS_RW = 0, 1207159811Sps MFI_LD_ACCSSS_RO = 2, 1208159811Sps MFI_LD_ACCESS_BLOCKED = 3, 1209159811Sps}; 1210159811Sps#define MFI_LD_ACCESS_MASK 3 1211159811Sps 1212159811Spsenum mfi_ld_state { 1213159811Sps MFI_LD_STATE_OFFLINE = 0, 1214159811Sps MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1215159811Sps MFI_LD_STATE_DEGRADED = 2, 1216159811Sps MFI_LD_STATE_OPTIMAL = 3 1217159811Sps}; 1218159811Sps 1219159811Spsstruct mfi_ld_props { 1220163398Sscottl union mfi_ld_ref ld; 1221159811Sps char name[16]; 1222159811Sps uint8_t default_cache_policy; 1223159811Sps uint8_t access_policy; 1224159811Sps uint8_t disk_cache_policy; 1225159811Sps uint8_t current_cache_policy; 1226159811Sps uint8_t no_bgi; 1227159811Sps uint8_t reserved[7]; 1228159811Sps} __packed; 1229159811Sps 1230159811Spsstruct mfi_ld_params { 1231159811Sps uint8_t primary_raid_level; 1232159811Sps uint8_t raid_level_qualifier; 1233159811Sps uint8_t secondary_raid_level; 1234159811Sps uint8_t stripe_size; 1235159811Sps uint8_t num_drives; 1236159811Sps uint8_t span_depth; 1237159811Sps uint8_t state; 1238159811Sps uint8_t init_state; 1239196200Sscottl#define MFI_LD_PARAMS_INIT_NO 0 1240196200Sscottl#define MFI_LD_PARAMS_INIT_QUICK 1 1241196200Sscottl#define MFI_LD_PARAMS_INIT_FULL 2 1242159811Sps uint8_t is_consistent; 1243233711Sambrisko uint8_t reserved1[6]; 1244233711Sambrisko uint8_t isSSCD; 1245233711Sambrisko uint8_t reserved2[16]; 1246159811Sps} __packed; 1247159811Sps 1248159811Spsstruct mfi_ld_progress { 1249159811Sps uint32_t active; 1250159811Sps#define MFI_LD_PROGRESS_CC (1<<0) 1251159811Sps#define MFI_LD_PROGRESS_BGI (1<<1) 1252159811Sps#define MFI_LD_PROGRESS_FGI (1<<2) 1253196200Sscottl#define MFI_LD_PROGRESS_RECON (1<<3) 1254159811Sps struct mfi_progress cc; 1255159811Sps struct mfi_progress bgi; 1256159811Sps struct mfi_progress fgi; 1257159811Sps struct mfi_progress recon; 1258159811Sps struct mfi_progress reserved[4]; 1259159811Sps} __packed; 1260159811Sps 1261159811Spsstruct mfi_span { 1262159811Sps uint64_t start_block; 1263159811Sps uint64_t num_blocks; 1264159811Sps uint16_t array_ref; 1265159811Sps uint8_t reserved[6]; 1266159811Sps} __packed; 1267159811Sps 1268159811Sps#define MFI_MAX_SPAN_DEPTH 8 1269159811Spsstruct mfi_ld_config { 1270159811Sps struct mfi_ld_props properties; 1271159811Sps struct mfi_ld_params params; 1272159811Sps struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1273159811Sps} __packed; 1274159811Sps 1275159811Spsstruct mfi_ld_info { 1276159811Sps struct mfi_ld_config ld_config; 1277159811Sps uint64_t size; 1278159811Sps struct mfi_ld_progress progress; 1279159811Sps uint16_t cluster_owner; 1280159811Sps uint8_t reconstruct_active; 1281159811Sps uint8_t reserved1[1]; 1282159811Sps uint8_t vpd_page83[64]; 1283159811Sps uint8_t reserved2[16]; 1284159811Sps} __packed; 1285159811Sps 1286233711Sambrisko#define MFI_MAX_ARRAYS 16 1287163398Sscottlstruct mfi_spare { 1288163398Sscottl union mfi_pd_ref ref; 1289196200Sscottl uint8_t spare_type; 1290196200Sscottl#define MFI_SPARE_DEDICATED (1 << 0) 1291196200Sscottl#define MFI_SPARE_REVERTIBLE (1 << 1) 1292196200Sscottl#define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1293163398Sscottl uint8_t reserved[2]; 1294163398Sscottl uint8_t array_count; 1295233711Sambrisko uint16_t array_ref[MFI_MAX_ARRAYS]; 1296163398Sscottl} __packed; 1297163398Sscottl 1298233711Sambrisko#define MFI_MAX_ROW_SIZE 32 1299163398Sscottlstruct mfi_array { 1300163398Sscottl uint64_t size; 1301163398Sscottl uint8_t num_drives; 1302163398Sscottl uint8_t reserved; 1303163398Sscottl uint16_t array_ref; 1304163398Sscottl uint8_t pad[20]; 1305163398Sscottl struct { 1306196200Sscottl union mfi_pd_ref ref; /* 0xffff == missing drive */ 1307196200Sscottl uint16_t fw_state; /* MFI_PD_STATE_* */ 1308163398Sscottl struct { 1309163398Sscottl uint8_t pd; 1310163398Sscottl uint8_t slot; 1311163398Sscottl } encl; 1312233711Sambrisko } pd[MFI_MAX_ROW_SIZE]; 1313163398Sscottl} __packed; 1314163398Sscottl 1315163398Sscottlstruct mfi_config_data { 1316163398Sscottl uint32_t size; 1317163398Sscottl uint16_t array_count; 1318163398Sscottl uint16_t array_size; 1319163398Sscottl uint16_t log_drv_count; 1320163398Sscottl uint16_t log_drv_size; 1321163398Sscottl uint16_t spares_count; 1322163398Sscottl uint16_t spares_size; 1323163398Sscottl uint8_t reserved[16]; 1324196200Sscottl struct mfi_array array[0]; 1325196200Sscottl struct mfi_ld_config ld[0]; 1326196200Sscottl struct mfi_spare spare[0]; 1327163398Sscottl} __packed; 1328163398Sscottl 1329196200Sscottlstruct mfi_bbu_capacity_info { 1330196200Sscottl uint16_t relative_charge; 1331196200Sscottl uint16_t absolute_charge; 1332196200Sscottl uint16_t remaining_capacity; 1333196200Sscottl uint16_t full_charge_capacity; 1334196200Sscottl uint16_t run_time_to_empty; 1335196200Sscottl uint16_t average_time_to_empty; 1336196200Sscottl uint16_t average_time_to_full; 1337196200Sscottl uint16_t cycle_count; 1338196200Sscottl uint16_t max_error; 1339196200Sscottl uint16_t remaining_capacity_alarm; 1340196200Sscottl uint16_t remaining_time_alarm; 1341196200Sscottl uint8_t reserved[26]; 1342196200Sscottl} __packed; 1343196200Sscottl 1344196200Sscottlstruct mfi_bbu_design_info { 1345196200Sscottl uint32_t mfg_date; 1346196200Sscottl uint16_t design_capacity; 1347196200Sscottl uint16_t design_voltage; 1348196200Sscottl uint16_t spec_info; 1349196200Sscottl uint16_t serial_number; 1350196200Sscottl uint16_t pack_stat_config; 1351196200Sscottl uint8_t mfg_name[12]; 1352196200Sscottl uint8_t device_name[8]; 1353196200Sscottl uint8_t device_chemistry[8]; 1354196200Sscottl uint8_t mfg_data[8]; 1355196200Sscottl uint8_t reserved[17]; 1356196200Sscottl} __packed; 1357196200Sscottl 1358196200Sscottlstruct mfi_ibbu_state { 1359196200Sscottl uint16_t gas_guage_status; 1360196200Sscottl uint16_t relative_charge; 1361196200Sscottl uint16_t charger_system_state; 1362196200Sscottl uint16_t charger_system_ctrl; 1363196200Sscottl uint16_t charging_current; 1364196200Sscottl uint16_t absolute_charge; 1365196200Sscottl uint16_t max_error; 1366196200Sscottl uint8_t reserved[18]; 1367196200Sscottl} __packed; 1368196200Sscottl 1369196200Sscottlstruct mfi_bbu_state { 1370196200Sscottl uint16_t gas_guage_status; 1371196200Sscottl uint16_t relative_charge; 1372196200Sscottl uint16_t charger_status; 1373196200Sscottl uint16_t remaining_capacity; 1374196200Sscottl uint16_t full_charge_capacity; 1375196200Sscottl uint8_t is_SOH_good; 1376196200Sscottl uint8_t reserved[21]; 1377196200Sscottl} __packed; 1378196200Sscottl 1379249257Smarkjstruct mfi_bbu_properties { 1380249257Smarkj uint32_t auto_learn_period; 1381249257Smarkj uint32_t next_learn_time; 1382249257Smarkj uint8_t learn_delay_interval; 1383249257Smarkj uint8_t auto_learn_mode; 1384249257Smarkj uint8_t bbu_mode; 1385249257Smarkj uint8_t reserved[21]; 1386249257Smarkj} __packed; 1387249257Smarkj 1388196200Sscottlunion mfi_bbu_status_detail { 1389196200Sscottl struct mfi_ibbu_state ibbu; 1390196200Sscottl struct mfi_bbu_state bbu; 1391196200Sscottl}; 1392196200Sscottl 1393196200Sscottlstruct mfi_bbu_status { 1394196200Sscottl uint8_t battery_type; 1395196200Sscottl#define MFI_BBU_TYPE_NONE 0 1396196200Sscottl#define MFI_BBU_TYPE_IBBU 1 1397233711Sambrisko#define MFI_BBU_TYPE_BBU 2 1398196200Sscottl uint8_t reserved; 1399196200Sscottl uint16_t voltage; 1400196200Sscottl int16_t current; 1401196200Sscottl uint16_t temperature; 1402196200Sscottl uint32_t fw_status; 1403196200Sscottl#define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1404196200Sscottl#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1405196200Sscottl#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1406235634Ssbruno#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1407235634Ssbruno#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1408235634Ssbruno#define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1409235634Ssbruno#define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1410235634Ssbruno#define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1411235634Ssbruno#define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1412235634Ssbruno#define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1413196200Sscottl uint8_t pad[20]; 1414196200Sscottl union mfi_bbu_status_detail detail; 1415196200Sscottl} __packed; 1416196200Sscottl 1417196200Sscottlenum mfi_pr_state { 1418196200Sscottl MFI_PR_STATE_STOPPED = 0, 1419196200Sscottl MFI_PR_STATE_READY = 1, 1420196200Sscottl MFI_PR_STATE_ACTIVE = 2, 1421196200Sscottl MFI_PR_STATE_ABORTED = 0xff 1422196200Sscottl}; 1423196200Sscottl 1424196200Sscottlstruct mfi_pr_status { 1425196200Sscottl uint32_t num_iteration; 1426196200Sscottl uint8_t state; 1427196200Sscottl uint8_t num_pd_done; 1428196200Sscottl uint8_t reserved[10]; 1429196200Sscottl}; 1430196200Sscottl 1431196200Sscottlenum mfi_pr_opmode { 1432196200Sscottl MFI_PR_OPMODE_AUTO = 0, 1433196200Sscottl MFI_PR_OPMODE_MANUAL = 1, 1434196200Sscottl MFI_PR_OPMODE_DISABLED = 2 1435196200Sscottl}; 1436196200Sscottl 1437196200Sscottlstruct mfi_pr_properties { 1438196200Sscottl uint8_t op_mode; 1439196200Sscottl uint8_t max_pd; 1440196200Sscottl uint8_t reserved; 1441196200Sscottl uint8_t exclude_ld_count; 1442196200Sscottl uint16_t excluded_ld[MFI_MAX_LD]; 1443196200Sscottl uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1444196200Sscottl uint8_t last_pd_map[MFI_MAX_PD / 8]; 1445196200Sscottl uint32_t next_exec; 1446196200Sscottl uint32_t exec_freq; 1447196200Sscottl uint32_t clear_freq; 1448196200Sscottl}; 1449196200Sscottl 1450233711Sambrisko/* ThunderBolt support */ 1451233711Sambrisko 1452233711Sambrisko/* 1453233711Sambrisko * Raid Context structure which describes MegaRAID specific IO Paramenters 1454233711Sambrisko * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1455233711Sambrisko */ 1456233711Sambriskotypedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1457233711Sambrisko uint16_t resvd0; /* 0x00 - 0x01 */ 1458233711Sambrisko uint16_t timeoutValue; /* 0x02 - 0x03 */ 1459233711Sambrisko uint8_t regLockFlags; 1460233711Sambrisko uint8_t armId; 1461233711Sambrisko uint16_t TargetID; /* 0x06 - 0x07 */ 1462233711Sambrisko 1463233711Sambrisko uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1464233711Sambrisko 1465233711Sambrisko uint32_t RegLockLength; /* 0x10 - 0x13 */ 1466233711Sambrisko 1467233711Sambrisko uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1468233711Sambrisko uint8_t exStatus; /* 0x16 */ 1469233711Sambrisko uint8_t Status; /* 0x17 status */ 1470233711Sambrisko 1471233711Sambrisko uint8_t RAIDFlags; /* 0x18 */ 1472233711Sambrisko uint8_t numSGE; /* 0x19 numSge */ 1473233711Sambrisko uint16_t configSeqNum; /* 0x1A - 0x1B */ 1474233711Sambrisko uint8_t spanArm; /* 0x1C */ 1475233711Sambrisko uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1476233711Sambrisko} MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1477233711Sambrisko 1478233711Sambrisko/***************************************************************************** 1479233711Sambrisko* 1480233711Sambrisko* Message Functions 1481233711Sambrisko* 1482233711Sambrisko*****************************************************************************/ 1483233711Sambrisko 1484233711Sambrisko#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1485233711Sambrisko#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1486233711Sambrisko#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1487233711Sambrisko#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1488233711Sambrisko#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1489233711Sambrisko#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1490233711Sambrisko#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1491233711Sambrisko#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1492233711Sambrisko#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1493233711Sambrisko#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1494233711Sambrisko#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1495233711Sambrisko#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1496233711Sambrisko#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1497233711Sambrisko#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1498233711Sambrisko#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1499233711Sambrisko#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1500233711Sambrisko#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1501233711Sambrisko#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1502233711Sambrisko#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1503233711Sambrisko#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1504233711Sambrisko#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1505233711Sambrisko#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1506233711Sambrisko#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1507233711Sambrisko#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1508233711Sambrisko#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1509233711Sambrisko#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1510233711Sambrisko#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1511233711Sambrisko#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1512233711Sambrisko#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1513233711Sambrisko#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1514233711Sambrisko 1515233711Sambrisko/* Doorbell functions */ 1516233711Sambrisko#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1517233711Sambrisko#define MPI2_FUNCTION_HANDSHAKE (0x42) 1518233711Sambrisko 1519233711Sambrisko/***************************************************************************** 1520233711Sambrisko* 1521233711Sambrisko* MPI Version Definitions 1522233711Sambrisko* 1523233711Sambrisko*****************************************************************************/ 1524233711Sambrisko 1525233711Sambrisko#define MPI2_VERSION_MAJOR (0x02) 1526233711Sambrisko#define MPI2_VERSION_MINOR (0x00) 1527233711Sambrisko#define MPI2_VERSION_MAJOR_MASK (0xFF00) 1528233711Sambrisko#define MPI2_VERSION_MAJOR_SHIFT (8) 1529233711Sambrisko#define MPI2_VERSION_MINOR_MASK (0x00FF) 1530233711Sambrisko#define MPI2_VERSION_MINOR_SHIFT (0) 1531233711Sambrisko#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1532233711Sambrisko MPI2_VERSION_MINOR) 1533233711Sambrisko 1534233711Sambrisko#define MPI2_VERSION_02_00 (0x0200) 1535233711Sambrisko 1536233711Sambrisko/* versioning for this MPI header set */ 1537233711Sambrisko#define MPI2_HEADER_VERSION_UNIT (0x10) 1538233711Sambrisko#define MPI2_HEADER_VERSION_DEV (0x00) 1539233711Sambrisko#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1540233711Sambrisko#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1541233711Sambrisko#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1542233711Sambrisko#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1543233711Sambrisko#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1544233711Sambrisko MPI2_HEADER_VERSION_DEV) 1545233711Sambrisko 1546233711Sambrisko 1547233711Sambrisko/* IOCInit Request message */ 1548233711Sambriskostruct MPI2_IOC_INIT_REQUEST { 1549233711Sambrisko uint8_t WhoInit; /* 0x00 */ 1550233711Sambrisko uint8_t Reserved1; /* 0x01 */ 1551233711Sambrisko uint8_t ChainOffset; /* 0x02 */ 1552233711Sambrisko uint8_t Function; /* 0x03 */ 1553233711Sambrisko uint16_t Reserved2; /* 0x04 */ 1554233711Sambrisko uint8_t Reserved3; /* 0x06 */ 1555233711Sambrisko uint8_t MsgFlags; /* 0x07 */ 1556233711Sambrisko uint8_t VP_ID; /* 0x08 */ 1557233711Sambrisko uint8_t VF_ID; /* 0x09 */ 1558233711Sambrisko uint16_t Reserved4; /* 0x0A */ 1559233711Sambrisko uint16_t MsgVersion; /* 0x0C */ 1560233711Sambrisko uint16_t HeaderVersion; /* 0x0E */ 1561233711Sambrisko uint32_t Reserved5; /* 0x10 */ 1562233711Sambrisko uint16_t Reserved6; /* 0x14 */ 1563233711Sambrisko uint8_t Reserved7; /* 0x16 */ 1564233711Sambrisko uint8_t HostMSIxVectors; /* 0x17 */ 1565233711Sambrisko uint16_t Reserved8; /* 0x18 */ 1566233711Sambrisko uint16_t SystemRequestFrameSize; /* 0x1A */ 1567233711Sambrisko uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1568233711Sambrisko uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1569233711Sambrisko uint32_t SenseBufferAddressHigh; /* 0x20 */ 1570233711Sambrisko uint32_t SystemReplyAddressHigh; /* 0x24 */ 1571233711Sambrisko uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1572233711Sambrisko uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1573233711Sambrisko uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1574233711Sambrisko uint64_t TimeStamp; /* 0x40 */ 1575233711Sambrisko}; 1576233711Sambrisko 1577233711Sambrisko/* WhoInit values */ 1578233711Sambrisko#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1579233711Sambrisko#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1580233711Sambrisko#define MPI2_WHOINIT_ROM_BIOS (0x02) 1581233711Sambrisko#define MPI2_WHOINIT_PCI_PEER (0x03) 1582233711Sambrisko#define MPI2_WHOINIT_HOST_DRIVER (0x04) 1583233711Sambrisko#define MPI2_WHOINIT_MANUFACTURER (0x05) 1584233711Sambrisko 1585233711Sambriskostruct MPI2_SGE_CHAIN_UNION { 1586233711Sambrisko uint16_t Length; 1587233711Sambrisko uint8_t NextChainOffset; 1588233711Sambrisko uint8_t Flags; 1589233711Sambrisko union { 1590233711Sambrisko uint32_t Address32; 1591233711Sambrisko uint64_t Address64; 1592233711Sambrisko } u; 1593233711Sambrisko}; 1594233711Sambrisko 1595233711Sambriskostruct MPI2_IEEE_SGE_SIMPLE32 { 1596233711Sambrisko uint32_t Address; 1597233711Sambrisko uint32_t FlagsLength; 1598233711Sambrisko}; 1599233711Sambrisko 1600233711Sambriskostruct MPI2_IEEE_SGE_SIMPLE64 { 1601233711Sambrisko uint64_t Address; 1602233711Sambrisko uint32_t Length; 1603233711Sambrisko uint16_t Reserved1; 1604233711Sambrisko uint8_t Reserved2; 1605233711Sambrisko uint8_t Flags; 1606233711Sambrisko}; 1607233711Sambrisko 1608233711Sambriskotypedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1609233711Sambrisko struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1610233711Sambrisko struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1611233711Sambrisko} MPI2_IEEE_SGE_SIMPLE_UNION; 1612233711Sambrisko 1613233711Sambriskotypedef struct _MPI2_SGE_SIMPLE_UNION { 1614233711Sambrisko uint32_t FlagsLength; 1615233711Sambrisko union { 1616233711Sambrisko uint32_t Address32; 1617233711Sambrisko uint64_t Address64; 1618233711Sambrisko } u; 1619233711Sambrisko} MPI2_SGE_SIMPLE_UNION; 1620233711Sambrisko 1621233711Sambrisko/**************************************************************************** 1622233711Sambrisko* IEEE SGE field definitions and masks 1623233711Sambrisko****************************************************************************/ 1624233711Sambrisko 1625233711Sambrisko/* Flags field bit definitions */ 1626233711Sambrisko 1627233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1628233711Sambrisko 1629233711Sambrisko#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1630233711Sambrisko 1631233711Sambrisko#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1632233711Sambrisko 1633233711Sambrisko/* Element Type */ 1634233711Sambrisko 1635233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1636233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1637233711Sambrisko 1638233711Sambrisko/* Data Location Address Space */ 1639233711Sambrisko 1640233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1641233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1642233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1643233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1644233711Sambrisko#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1645233711Sambrisko 1646233711Sambrisko/* Address Size */ 1647233711Sambrisko 1648233711Sambrisko#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1649233711Sambrisko#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1650233711Sambrisko 1651233711Sambrisko/*******************/ 1652233711Sambrisko/* SCSI IO Control bits */ 1653233711Sambrisko#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1654233711Sambrisko#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1655233711Sambrisko 1656233711Sambrisko#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1657233711Sambrisko#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1658233711Sambrisko#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1659233711Sambrisko#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1660233711Sambrisko#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1661233711Sambrisko 1662233711Sambrisko#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1663233711Sambrisko#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1664233711Sambrisko 1665233711Sambrisko#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1666233711Sambrisko#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1667233711Sambrisko#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1668233711Sambrisko#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1669233711Sambrisko#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1670233711Sambrisko 1671233711Sambrisko#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1672233711Sambrisko#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1673233711Sambrisko#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1674233711Sambrisko#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1675233711Sambrisko 1676233711Sambrisko/*******************/ 1677233711Sambrisko 1678233711Sambriskotypedef struct { 1679233711Sambrisko uint8_t CDB[20]; /* 0x00 */ 1680233711Sambrisko uint32_t PrimaryReferenceTag; /* 0x14 */ 1681233711Sambrisko uint16_t PrimaryApplicationTag; /* 0x18 */ 1682233711Sambrisko uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1683233711Sambrisko uint32_t TransferLength; /* 0x1C */ 1684233711Sambrisko} MPI2_SCSI_IO_CDB_EEDP32; 1685233711Sambrisko 1686233711Sambrisko 1687233711Sambriskotypedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1688233711Sambrisko struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1689233711Sambrisko struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1690233711Sambrisko} MPI2_IEEE_SGE_CHAIN_UNION; 1691233711Sambrisko 1692233711Sambriskotypedef union _MPI2_SIMPLE_SGE_UNION { 1693233711Sambrisko MPI2_SGE_SIMPLE_UNION MpiSimple; 1694233711Sambrisko MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1695233711Sambrisko} MPI2_SIMPLE_SGE_UNION; 1696233711Sambrisko 1697233711Sambriskotypedef union _MPI2_SGE_IO_UNION { 1698233711Sambrisko MPI2_SGE_SIMPLE_UNION MpiSimple; 1699233711Sambrisko struct MPI2_SGE_CHAIN_UNION MpiChain; 1700233711Sambrisko MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1701233711Sambrisko MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1702233711Sambrisko} MPI2_SGE_IO_UNION; 1703233711Sambrisko 1704233711Sambriskotypedef union { 1705233711Sambrisko uint8_t CDB32[32]; 1706233711Sambrisko MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1707233711Sambrisko MPI2_SGE_SIMPLE_UNION SGE; 1708233711Sambrisko} MPI2_SCSI_IO_CDB_UNION; 1709233711Sambrisko 1710233711Sambrisko 1711233711Sambrisko/* MPI 2.5 SGLs */ 1712233711Sambrisko 1713233711Sambrisko#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1714233711Sambrisko 1715233711Sambriskotypedef struct _MPI25_IEEE_SGE_CHAIN64 { 1716233711Sambrisko uint64_t Address; 1717233711Sambrisko uint32_t Length; 1718233711Sambrisko uint16_t Reserved1; 1719233711Sambrisko uint8_t NextChainOffset; 1720233711Sambrisko uint8_t Flags; 1721233711Sambrisko} MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1722233711Sambrisko 1723233711Sambrisko/* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1724233711Sambrisko 1725233711Sambrisko 1726233711Sambrisko/********/ 1727233711Sambrisko 1728233711Sambrisko/* 1729233711Sambrisko * RAID SCSI IO Request Message 1730233711Sambrisko * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1731233711Sambrisko */ 1732233711Sambriskostruct mfi_mpi2_request_raid_scsi_io { 1733233711Sambrisko uint16_t DevHandle; /* 0x00 */ 1734233711Sambrisko uint8_t ChainOffset; /* 0x02 */ 1735233711Sambrisko uint8_t Function; /* 0x03 */ 1736233711Sambrisko uint16_t Reserved1; /* 0x04 */ 1737233711Sambrisko uint8_t Reserved2; /* 0x06 */ 1738233711Sambrisko uint8_t MsgFlags; /* 0x07 */ 1739233711Sambrisko uint8_t VP_ID; /* 0x08 */ 1740233711Sambrisko uint8_t VF_ID; /* 0x09 */ 1741233711Sambrisko uint16_t Reserved3; /* 0x0A */ 1742233711Sambrisko uint32_t SenseBufferLowAddress; /* 0x0C */ 1743233711Sambrisko uint16_t SGLFlags; /* 0x10 */ 1744233711Sambrisko uint8_t SenseBufferLength; /* 0x12 */ 1745233711Sambrisko uint8_t Reserved4; /* 0x13 */ 1746233711Sambrisko uint8_t SGLOffset0; /* 0x14 */ 1747233711Sambrisko uint8_t SGLOffset1; /* 0x15 */ 1748233711Sambrisko uint8_t SGLOffset2; /* 0x16 */ 1749233711Sambrisko uint8_t SGLOffset3; /* 0x17 */ 1750233711Sambrisko uint32_t SkipCount; /* 0x18 */ 1751233711Sambrisko uint32_t DataLength; /* 0x1C */ 1752233711Sambrisko uint32_t BidirectionalDataLength; /* 0x20 */ 1753233711Sambrisko uint16_t IoFlags; /* 0x24 */ 1754233711Sambrisko uint16_t EEDPFlags; /* 0x26 */ 1755233711Sambrisko uint32_t EEDPBlockSize; /* 0x28 */ 1756233711Sambrisko uint32_t SecondaryReferenceTag; /* 0x2C */ 1757233711Sambrisko uint16_t SecondaryApplicationTag; /* 0x30 */ 1758233711Sambrisko uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1759233711Sambrisko uint8_t LUN[8]; /* 0x34 */ 1760233711Sambrisko uint32_t Control; /* 0x3C */ 1761233711Sambrisko MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1762233711Sambrisko MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1763233711Sambrisko MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1764233711Sambrisko} __packed; 1765233711Sambrisko 1766233711Sambrisko/* 1767233711Sambrisko * MPT RAID MFA IO Descriptor. 1768233711Sambrisko */ 1769233711Sambriskotypedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1770233711Sambrisko uint32_t RequestFlags : 8; 1771233711Sambrisko uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1772233711Sambrisko uint32_t MessageAddress2; /* bits 61:32 */ 1773233711Sambrisko} MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1774233711Sambrisko 1775233711Sambriskostruct mfi_mpi2_request_header { 1776233711Sambrisko uint8_t RequestFlags; /* 0x00 */ 1777233711Sambrisko uint8_t MSIxIndex; /* 0x01 */ 1778233711Sambrisko uint16_t SMID; /* 0x02 */ 1779233711Sambrisko uint16_t LMID; /* 0x04 */ 1780233711Sambrisko}; 1781233711Sambrisko 1782233711Sambrisko/* defines for the RequestFlags field */ 1783233711Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1784233711Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1785233711Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1786233711Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1787233711Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1788233711Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1789233711Sambrisko 1790233711Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1791233711Sambrisko 1792233711Sambriskostruct mfi_mpi2_request_high_priority { 1793233711Sambrisko struct mfi_mpi2_request_header header; 1794233711Sambrisko uint16_t reserved; 1795233711Sambrisko}; 1796233711Sambrisko 1797233711Sambriskostruct mfi_mpi2_request_scsi_io { 1798233711Sambrisko struct mfi_mpi2_request_header header; 1799233711Sambrisko uint16_t scsi_io_dev_handle; 1800233711Sambrisko}; 1801233711Sambrisko 1802233711Sambriskostruct mfi_mpi2_request_scsi_target { 1803233711Sambrisko struct mfi_mpi2_request_header header; 1804233711Sambrisko uint16_t scsi_target_io_index; 1805233711Sambrisko}; 1806233711Sambrisko 1807233711Sambrisko/* Request Descriptors */ 1808233711Sambriskounion mfi_mpi2_request_descriptor { 1809233711Sambrisko struct mfi_mpi2_request_header header; 1810233711Sambrisko struct mfi_mpi2_request_high_priority high_priority; 1811233711Sambrisko struct mfi_mpi2_request_scsi_io scsi_io; 1812233711Sambrisko struct mfi_mpi2_request_scsi_target scsi_target; 1813233711Sambrisko uint64_t words; 1814233711Sambrisko}; 1815233711Sambrisko 1816233711Sambrisko 1817233711Sambriskostruct mfi_mpi2_reply_header { 1818233711Sambrisko uint8_t ReplyFlags; /* 0x00 */ 1819233711Sambrisko uint8_t MSIxIndex; /* 0x01 */ 1820233711Sambrisko uint16_t SMID; /* 0x02 */ 1821233711Sambrisko}; 1822233711Sambrisko 1823233711Sambrisko/* defines for the ReplyFlags field */ 1824233711Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1825233711Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1826233711Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1827233711Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1828233711Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1829233711Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1830233711Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1831233711Sambrisko 1832233711Sambrisko/* values for marking a reply descriptor as unused */ 1833233711Sambrisko#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1834233711Sambrisko#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1835233711Sambrisko 1836233711Sambriskostruct mfi_mpi2_reply_default { 1837233711Sambrisko struct mfi_mpi2_reply_header header; 1838233711Sambrisko uint32_t DescriptorTypeDependent2; 1839233711Sambrisko}; 1840233711Sambrisko 1841233711Sambriskostruct mfi_mpi2_reply_address { 1842233711Sambrisko struct mfi_mpi2_reply_header header; 1843233711Sambrisko uint32_t ReplyFrameAddress; 1844233711Sambrisko}; 1845233711Sambrisko 1846233711Sambriskostruct mfi_mpi2_reply_scsi_io { 1847233711Sambrisko struct mfi_mpi2_reply_header header; 1848233711Sambrisko uint16_t TaskTag; /* 0x04 */ 1849233711Sambrisko uint16_t Reserved1; /* 0x06 */ 1850233711Sambrisko}; 1851233711Sambrisko 1852233711Sambriskostruct mfi_mpi2_reply_target_assist { 1853233711Sambrisko struct mfi_mpi2_reply_header header; 1854233711Sambrisko uint8_t SequenceNumber; /* 0x04 */ 1855233711Sambrisko uint8_t Reserved1; /* 0x04 */ 1856233711Sambrisko uint16_t IoIndex; /* 0x06 */ 1857233711Sambrisko}; 1858233711Sambrisko 1859233711Sambriskostruct mfi_mpi2_reply_target_cmd_buffer { 1860233711Sambrisko struct mfi_mpi2_reply_header header; 1861233711Sambrisko uint8_t SequenceNumber; /* 0x04 */ 1862233711Sambrisko uint8_t Flags; /* 0x04 */ 1863233711Sambrisko uint16_t InitiatorDevHandle; /* 0x06 */ 1864233711Sambrisko uint16_t IoIndex; /* 0x06 */ 1865233711Sambrisko}; 1866233711Sambrisko 1867233711Sambriskostruct mfi_mpi2_reply_raid_accel { 1868233711Sambrisko struct mfi_mpi2_reply_header header; 1869233711Sambrisko uint8_t SequenceNumber; /* 0x04 */ 1870233711Sambrisko uint32_t Reserved; /* 0x04 */ 1871233711Sambrisko}; 1872233711Sambrisko 1873233711Sambrisko/* union of Reply Descriptors */ 1874233711Sambriskounion mfi_mpi2_reply_descriptor { 1875233711Sambrisko struct mfi_mpi2_reply_header header; 1876233711Sambrisko struct mfi_mpi2_reply_scsi_io scsi_io; 1877233711Sambrisko struct mfi_mpi2_reply_target_assist target_assist; 1878233711Sambrisko struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1879233711Sambrisko struct mfi_mpi2_reply_raid_accel raid_accel; 1880233711Sambrisko struct mfi_mpi2_reply_default reply_default; 1881233711Sambrisko uint64_t words; 1882233711Sambrisko}; 1883233711Sambrisko 1884233711Sambriskostruct IO_REQUEST_INFO { 1885233711Sambrisko uint64_t ldStartBlock; 1886233711Sambrisko uint32_t numBlocks; 1887233711Sambrisko uint16_t ldTgtId; 1888233711Sambrisko uint8_t isRead; 1889233711Sambrisko uint16_t devHandle; 1890233711Sambrisko uint64_t pdBlock; 1891233711Sambrisko uint8_t fpOkForIo; 1892233711Sambrisko}; 1893233711Sambrisko 1894169611Sscottl#define MFI_SCSI_MAX_TARGETS 128 1895169611Sscottl#define MFI_SCSI_MAX_LUNS 8 1896169611Sscottl#define MFI_SCSI_INITIATOR_ID 255 1897169611Sscottl#define MFI_SCSI_MAX_CMDS 8 1898169611Sscottl#define MFI_SCSI_MAX_CDB_LEN 16 1899169611Sscottl 1900157114Sscottl#endif /* _MFIREG_H */ 1901